1 /* Declarations for Intel 80386 opcode table 2 Copyright 2007, 2008, 2009, 2010, 2012 3 Free Software Foundation, Inc. 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to the Free 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 20 02110-1301, USA. */ 21 22 #include "opcode/i386.h" 23 #ifdef HAVE_LIMITS_H 24 #include <limits.h> 25 #endif 26 27 #ifndef CHAR_BIT 28 #define CHAR_BIT 8 29 #endif 30 31 /* Position of cpu flags bitfiled. */ 32 33 enum 34 { 35 /* i186 or better required */ 36 Cpu186 = 0, 37 /* i286 or better required */ 38 Cpu286, 39 /* i386 or better required */ 40 Cpu386, 41 /* i486 or better required */ 42 Cpu486, 43 /* i585 or better required */ 44 Cpu586, 45 /* i686 or better required */ 46 Cpu686, 47 /* CLFLUSH Instruction support required */ 48 CpuClflush, 49 /* NOP Instruction support required */ 50 CpuNop, 51 /* SYSCALL Instructions support required */ 52 CpuSYSCALL, 53 /* Floating point support required */ 54 Cpu8087, 55 /* i287 support required */ 56 Cpu287, 57 /* i387 support required */ 58 Cpu387, 59 /* i686 and floating point support required */ 60 Cpu687, 61 /* SSE3 and floating point support required */ 62 CpuFISTTP, 63 /* MMX support required */ 64 CpuMMX, 65 /* SSE support required */ 66 CpuSSE, 67 /* SSE2 support required */ 68 CpuSSE2, 69 /* 3dnow! support required */ 70 Cpu3dnow, 71 /* 3dnow! Extensions support required */ 72 Cpu3dnowA, 73 /* SSE3 support required */ 74 CpuSSE3, 75 /* VIA PadLock required */ 76 CpuPadLock, 77 /* AMD Secure Virtual Machine Ext-s required */ 78 CpuSVME, 79 /* VMX Instructions required */ 80 CpuVMX, 81 /* SMX Instructions required */ 82 CpuSMX, 83 /* SSSE3 support required */ 84 CpuSSSE3, 85 /* SSE4a support required */ 86 CpuSSE4a, 87 /* ABM New Instructions required */ 88 CpuABM, 89 /* SSE4.1 support required */ 90 CpuSSE4_1, 91 /* SSE4.2 support required */ 92 CpuSSE4_2, 93 /* AVX support required */ 94 CpuAVX, 95 /* AVX2 support required */ 96 CpuAVX2, 97 /* Intel L1OM support required */ 98 CpuL1OM, 99 /* Intel K1OM support required */ 100 CpuK1OM, 101 /* Xsave/xrstor New Instructions support required */ 102 CpuXsave, 103 /* Xsaveopt New Instructions support required */ 104 CpuXsaveopt, 105 /* AES support required */ 106 CpuAES, 107 /* PCLMUL support required */ 108 CpuPCLMUL, 109 /* FMA support required */ 110 CpuFMA, 111 /* FMA4 support required */ 112 CpuFMA4, 113 /* XOP support required */ 114 CpuXOP, 115 /* LWP support required */ 116 CpuLWP, 117 /* BMI support required */ 118 CpuBMI, 119 /* TBM support required */ 120 CpuTBM, 121 /* MOVBE Instruction support required */ 122 CpuMovbe, 123 /* CMPXCHG16B instruction support required. */ 124 CpuCX16, 125 /* EPT Instructions required */ 126 CpuEPT, 127 /* RDTSCP Instruction support required */ 128 CpuRdtscp, 129 /* FSGSBASE Instructions required */ 130 CpuFSGSBase, 131 /* RDRND Instructions required */ 132 CpuRdRnd, 133 /* F16C Instructions required */ 134 CpuF16C, 135 /* Intel BMI2 support required */ 136 CpuBMI2, 137 /* LZCNT support required */ 138 CpuLZCNT, 139 /* HLE support required */ 140 CpuHLE, 141 /* RTM support required */ 142 CpuRTM, 143 /* INVPCID Instructions required */ 144 CpuINVPCID, 145 /* VMFUNC Instruction required */ 146 CpuVMFUNC, 147 /* 64bit support available, used by -march= in assembler. */ 148 CpuLM, 149 /* RDRSEED instruction required. */ 150 CpuRDSEED, 151 /* Multi-presisionn add-carry instructions are required. */ 152 CpuADX, 153 /* Supports prefetchw and prefetch instructions. */ 154 CpuPRFCHW, 155 /* SMAP instructions required. */ 156 CpuSMAP, 157 /* 64bit support required */ 158 Cpu64, 159 /* Not supported in the 64bit mode */ 160 CpuNo64, 161 /* The last bitfield in i386_cpu_flags. */ 162 CpuMax = CpuNo64 163 }; 164 165 #define CpuNumOfUints \ 166 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) 167 #define CpuNumOfBits \ 168 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) 169 170 /* If you get a compiler error for zero width of the unused field, 171 comment it out. */ 172 #define CpuUnused (CpuMax + 1) 173 174 /* We can check if an instruction is available with array instead 175 of bitfield. */ 176 typedef union i386_cpu_flags 177 { 178 struct 179 { 180 unsigned int cpui186:1; 181 unsigned int cpui286:1; 182 unsigned int cpui386:1; 183 unsigned int cpui486:1; 184 unsigned int cpui586:1; 185 unsigned int cpui686:1; 186 unsigned int cpuclflush:1; 187 unsigned int cpunop:1; 188 unsigned int cpusyscall:1; 189 unsigned int cpu8087:1; 190 unsigned int cpu287:1; 191 unsigned int cpu387:1; 192 unsigned int cpu687:1; 193 unsigned int cpufisttp:1; 194 unsigned int cpummx:1; 195 unsigned int cpusse:1; 196 unsigned int cpusse2:1; 197 unsigned int cpua3dnow:1; 198 unsigned int cpua3dnowa:1; 199 unsigned int cpusse3:1; 200 unsigned int cpupadlock:1; 201 unsigned int cpusvme:1; 202 unsigned int cpuvmx:1; 203 unsigned int cpusmx:1; 204 unsigned int cpussse3:1; 205 unsigned int cpusse4a:1; 206 unsigned int cpuabm:1; 207 unsigned int cpusse4_1:1; 208 unsigned int cpusse4_2:1; 209 unsigned int cpuavx:1; 210 unsigned int cpuavx2:1; 211 unsigned int cpul1om:1; 212 unsigned int cpuk1om:1; 213 unsigned int cpuxsave:1; 214 unsigned int cpuxsaveopt:1; 215 unsigned int cpuaes:1; 216 unsigned int cpupclmul:1; 217 unsigned int cpufma:1; 218 unsigned int cpufma4:1; 219 unsigned int cpuxop:1; 220 unsigned int cpulwp:1; 221 unsigned int cpubmi:1; 222 unsigned int cputbm:1; 223 unsigned int cpumovbe:1; 224 unsigned int cpucx16:1; 225 unsigned int cpuept:1; 226 unsigned int cpurdtscp:1; 227 unsigned int cpufsgsbase:1; 228 unsigned int cpurdrnd:1; 229 unsigned int cpuf16c:1; 230 unsigned int cpubmi2:1; 231 unsigned int cpulzcnt:1; 232 unsigned int cpuhle:1; 233 unsigned int cpurtm:1; 234 unsigned int cpuinvpcid:1; 235 unsigned int cpuvmfunc:1; 236 unsigned int cpulm:1; 237 unsigned int cpurdseed:1; 238 unsigned int cpuadx:1; 239 unsigned int cpuprfchw:1; 240 unsigned int cpusmap:1; 241 unsigned int cpu64:1; 242 unsigned int cpuno64:1; 243 #ifdef CpuUnused 244 unsigned int unused:(CpuNumOfBits - CpuUnused); 245 #endif 246 } bitfield; 247 unsigned int array[CpuNumOfUints]; 248 } i386_cpu_flags; 249 250 /* Position of opcode_modifier bits. */ 251 252 enum 253 { 254 /* has direction bit. */ 255 D = 0, 256 /* set if operands can be words or dwords encoded the canonical way */ 257 W, 258 /* Skip the current insn and use the next insn in i386-opc.tbl to swap 259 operand in encoding. */ 260 S, 261 /* insn has a modrm byte. */ 262 Modrm, 263 /* register is in low 3 bits of opcode */ 264 ShortForm, 265 /* special case for jump insns. */ 266 Jump, 267 /* call and jump */ 268 JumpDword, 269 /* loop and jecxz */ 270 JumpByte, 271 /* special case for intersegment leaps/calls */ 272 JumpInterSegment, 273 /* FP insn memory format bit, sized by 0x4 */ 274 FloatMF, 275 /* src/dest swap for floats. */ 276 FloatR, 277 /* has float insn direction bit. */ 278 FloatD, 279 /* needs size prefix if in 32-bit mode */ 280 Size16, 281 /* needs size prefix if in 16-bit mode */ 282 Size32, 283 /* needs size prefix if in 64-bit mode */ 284 Size64, 285 /* check register size. */ 286 CheckRegSize, 287 /* instruction ignores operand size prefix and in Intel mode ignores 288 mnemonic size suffix check. */ 289 IgnoreSize, 290 /* default insn size depends on mode */ 291 DefaultSize, 292 /* b suffix on instruction illegal */ 293 No_bSuf, 294 /* w suffix on instruction illegal */ 295 No_wSuf, 296 /* l suffix on instruction illegal */ 297 No_lSuf, 298 /* s suffix on instruction illegal */ 299 No_sSuf, 300 /* q suffix on instruction illegal */ 301 No_qSuf, 302 /* long double suffix on instruction illegal */ 303 No_ldSuf, 304 /* instruction needs FWAIT */ 305 FWait, 306 /* quick test for string instructions */ 307 IsString, 308 /* quick test for lockable instructions */ 309 IsLockable, 310 /* fake an extra reg operand for clr, imul and special register 311 processing for some instructions. */ 312 RegKludge, 313 /* The first operand must be xmm0 */ 314 FirstXmm0, 315 /* An implicit xmm0 as the first operand */ 316 Implicit1stXmm0, 317 /* The HLE prefix is OK: 318 1. With a LOCK prefix. 319 2. With or without a LOCK prefix. 320 3. With a RELEASE (0xf3) prefix. 321 */ 322 #define HLEPrefixNone 0 323 #define HLEPrefixLock 1 324 #define HLEPrefixAny 2 325 #define HLEPrefixRelease 3 326 HLEPrefixOk, 327 /* An instruction on which a "rep" prefix is acceptable. */ 328 RepPrefixOk, 329 /* Convert to DWORD */ 330 ToDword, 331 /* Convert to QWORD */ 332 ToQword, 333 /* Address prefix changes operand 0 */ 334 AddrPrefixOp0, 335 /* opcode is a prefix */ 336 IsPrefix, 337 /* instruction has extension in 8 bit imm */ 338 ImmExt, 339 /* instruction don't need Rex64 prefix. */ 340 NoRex64, 341 /* instruction require Rex64 prefix. */ 342 Rex64, 343 /* deprecated fp insn, gets a warning */ 344 Ugh, 345 /* insn has VEX prefix: 346 1: 128bit VEX prefix. 347 2: 256bit VEX prefix. 348 3: Scalar VEX prefix. 349 */ 350 #define VEX128 1 351 #define VEX256 2 352 #define VEXScalar 3 353 Vex, 354 /* How to encode VEX.vvvv: 355 0: VEX.vvvv must be 1111b. 356 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where 357 the content of source registers will be preserved. 358 VEX.DDS. The second register operand is encoded in VEX.vvvv 359 where the content of first source register will be overwritten 360 by the result. 361 VEX.NDD2. The second destination register operand is encoded in 362 VEX.vvvv for instructions with 2 destination register operands. 363 For assembler, there are no difference between VEX.NDS, VEX.DDS 364 and VEX.NDD2. 365 2. VEX.NDD. Register destination is encoded in VEX.vvvv for 366 instructions with 1 destination register operand. 367 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one 368 of the operands can access a memory location. 369 */ 370 #define VEXXDS 1 371 #define VEXNDD 2 372 #define VEXLWP 3 373 VexVVVV, 374 /* How the VEX.W bit is used: 375 0: Set by the REX.W bit. 376 1: VEX.W0. Should always be 0. 377 2: VEX.W1. Should always be 1. 378 */ 379 #define VEXW0 1 380 #define VEXW1 2 381 VexW, 382 /* VEX opcode prefix: 383 0: VEX 0x0F opcode prefix. 384 1: VEX 0x0F38 opcode prefix. 385 2: VEX 0x0F3A opcode prefix 386 3: XOP 0x08 opcode prefix. 387 4: XOP 0x09 opcode prefix 388 5: XOP 0x0A opcode prefix. 389 */ 390 #define VEX0F 0 391 #define VEX0F38 1 392 #define VEX0F3A 2 393 #define XOP08 3 394 #define XOP09 4 395 #define XOP0A 5 396 VexOpcode, 397 /* number of VEX source operands: 398 0: <= 2 source operands. 399 1: 2 XOP source operands. 400 2: 3 source operands. 401 */ 402 #define XOP2SOURCES 1 403 #define VEX3SOURCES 2 404 VexSources, 405 /* instruction has VEX 8 bit imm */ 406 VexImmExt, 407 /* Instruction with vector SIB byte: 408 1: 128bit vector register. 409 2: 256bit vector register. 410 */ 411 #define VecSIB128 1 412 #define VecSIB256 2 413 VecSIB, 414 /* SSE to AVX support required */ 415 SSE2AVX, 416 /* No AVX equivalent */ 417 NoAVX, 418 /* Compatible with old (<= 2.8.1) versions of gcc */ 419 OldGcc, 420 /* AT&T mnemonic. */ 421 ATTMnemonic, 422 /* AT&T syntax. */ 423 ATTSyntax, 424 /* Intel syntax. */ 425 IntelSyntax, 426 /* The last bitfield in i386_opcode_modifier. */ 427 Opcode_Modifier_Max 428 }; 429 430 typedef struct i386_opcode_modifier 431 { 432 unsigned int d:1; 433 unsigned int w:1; 434 unsigned int s:1; 435 unsigned int modrm:1; 436 unsigned int shortform:1; 437 unsigned int jump:1; 438 unsigned int jumpdword:1; 439 unsigned int jumpbyte:1; 440 unsigned int jumpintersegment:1; 441 unsigned int floatmf:1; 442 unsigned int floatr:1; 443 unsigned int floatd:1; 444 unsigned int size16:1; 445 unsigned int size32:1; 446 unsigned int size64:1; 447 unsigned int checkregsize:1; 448 unsigned int ignoresize:1; 449 unsigned int defaultsize:1; 450 unsigned int no_bsuf:1; 451 unsigned int no_wsuf:1; 452 unsigned int no_lsuf:1; 453 unsigned int no_ssuf:1; 454 unsigned int no_qsuf:1; 455 unsigned int no_ldsuf:1; 456 unsigned int fwait:1; 457 unsigned int isstring:1; 458 unsigned int islockable:1; 459 unsigned int regkludge:1; 460 unsigned int firstxmm0:1; 461 unsigned int implicit1stxmm0:1; 462 unsigned int hleprefixok:2; 463 unsigned int repprefixok:1; 464 unsigned int todword:1; 465 unsigned int toqword:1; 466 unsigned int addrprefixop0:1; 467 unsigned int isprefix:1; 468 unsigned int immext:1; 469 unsigned int norex64:1; 470 unsigned int rex64:1; 471 unsigned int ugh:1; 472 unsigned int vex:2; 473 unsigned int vexvvvv:2; 474 unsigned int vexw:2; 475 unsigned int vexopcode:3; 476 unsigned int vexsources:2; 477 unsigned int veximmext:1; 478 unsigned int vecsib:2; 479 unsigned int sse2avx:1; 480 unsigned int noavx:1; 481 unsigned int oldgcc:1; 482 unsigned int attmnemonic:1; 483 unsigned int attsyntax:1; 484 unsigned int intelsyntax:1; 485 } i386_opcode_modifier; 486 487 /* Position of operand_type bits. */ 488 489 enum 490 { 491 /* 8bit register */ 492 Reg8 = 0, 493 /* 16bit register */ 494 Reg16, 495 /* 32bit register */ 496 Reg32, 497 /* 64bit register */ 498 Reg64, 499 /* Floating pointer stack register */ 500 FloatReg, 501 /* MMX register */ 502 RegMMX, 503 /* SSE register */ 504 RegXMM, 505 /* AVX registers */ 506 RegYMM, 507 /* Control register */ 508 Control, 509 /* Debug register */ 510 Debug, 511 /* Test register */ 512 Test, 513 /* 2 bit segment register */ 514 SReg2, 515 /* 3 bit segment register */ 516 SReg3, 517 /* 1 bit immediate */ 518 Imm1, 519 /* 8 bit immediate */ 520 Imm8, 521 /* 8 bit immediate sign extended */ 522 Imm8S, 523 /* 16 bit immediate */ 524 Imm16, 525 /* 32 bit immediate */ 526 Imm32, 527 /* 32 bit immediate sign extended */ 528 Imm32S, 529 /* 64 bit immediate */ 530 Imm64, 531 /* 8bit/16bit/32bit displacements are used in different ways, 532 depending on the instruction. For jumps, they specify the 533 size of the PC relative displacement, for instructions with 534 memory operand, they specify the size of the offset relative 535 to the base register, and for instructions with memory offset 536 such as `mov 1234,%al' they specify the size of the offset 537 relative to the segment base. */ 538 /* 8 bit displacement */ 539 Disp8, 540 /* 16 bit displacement */ 541 Disp16, 542 /* 32 bit displacement */ 543 Disp32, 544 /* 32 bit signed displacement */ 545 Disp32S, 546 /* 64 bit displacement */ 547 Disp64, 548 /* Accumulator %al/%ax/%eax/%rax */ 549 Acc, 550 /* Floating pointer top stack register %st(0) */ 551 FloatAcc, 552 /* Register which can be used for base or index in memory operand. */ 553 BaseIndex, 554 /* Register to hold in/out port addr = dx */ 555 InOutPortReg, 556 /* Register to hold shift count = cl */ 557 ShiftCount, 558 /* Absolute address for jump. */ 559 JumpAbsolute, 560 /* String insn operand with fixed es segment */ 561 EsSeg, 562 /* RegMem is for instructions with a modrm byte where the register 563 destination operand should be encoded in the mod and regmem fields. 564 Normally, it will be encoded in the reg field. We add a RegMem 565 flag to the destination register operand to indicate that it should 566 be encoded in the regmem field. */ 567 RegMem, 568 /* Memory. */ 569 Mem, 570 /* BYTE memory. */ 571 Byte, 572 /* WORD memory. 2 byte */ 573 Word, 574 /* DWORD memory. 4 byte */ 575 Dword, 576 /* FWORD memory. 6 byte */ 577 Fword, 578 /* QWORD memory. 8 byte */ 579 Qword, 580 /* TBYTE memory. 10 byte */ 581 Tbyte, 582 /* XMMWORD memory. */ 583 Xmmword, 584 /* YMMWORD memory. */ 585 Ymmword, 586 /* Unspecified memory size. */ 587 Unspecified, 588 /* Any memory size. */ 589 Anysize, 590 591 /* Vector 4 bit immediate. */ 592 Vec_Imm4, 593 594 /* The last bitfield in i386_operand_type. */ 595 OTMax 596 }; 597 598 #define OTNumOfUints \ 599 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) 600 #define OTNumOfBits \ 601 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) 602 603 /* If you get a compiler error for zero width of the unused field, 604 comment it out. */ 605 #define OTUnused (OTMax + 1) 606 607 typedef union i386_operand_type 608 { 609 struct 610 { 611 unsigned int reg8:1; 612 unsigned int reg16:1; 613 unsigned int reg32:1; 614 unsigned int reg64:1; 615 unsigned int floatreg:1; 616 unsigned int regmmx:1; 617 unsigned int regxmm:1; 618 unsigned int regymm:1; 619 unsigned int control:1; 620 unsigned int debug:1; 621 unsigned int test:1; 622 unsigned int sreg2:1; 623 unsigned int sreg3:1; 624 unsigned int imm1:1; 625 unsigned int imm8:1; 626 unsigned int imm8s:1; 627 unsigned int imm16:1; 628 unsigned int imm32:1; 629 unsigned int imm32s:1; 630 unsigned int imm64:1; 631 unsigned int disp8:1; 632 unsigned int disp16:1; 633 unsigned int disp32:1; 634 unsigned int disp32s:1; 635 unsigned int disp64:1; 636 unsigned int acc:1; 637 unsigned int floatacc:1; 638 unsigned int baseindex:1; 639 unsigned int inoutportreg:1; 640 unsigned int shiftcount:1; 641 unsigned int jumpabsolute:1; 642 unsigned int esseg:1; 643 unsigned int regmem:1; 644 unsigned int mem:1; 645 unsigned int byte:1; 646 unsigned int word:1; 647 unsigned int dword:1; 648 unsigned int fword:1; 649 unsigned int qword:1; 650 unsigned int tbyte:1; 651 unsigned int xmmword:1; 652 unsigned int ymmword:1; 653 unsigned int unspecified:1; 654 unsigned int anysize:1; 655 unsigned int vec_imm4:1; 656 #ifdef OTUnused 657 unsigned int unused:(OTNumOfBits - OTUnused); 658 #endif 659 } bitfield; 660 unsigned int array[OTNumOfUints]; 661 } i386_operand_type; 662 663 typedef struct insn_template 664 { 665 /* instruction name sans width suffix ("mov" for movl insns) */ 666 char *name; 667 668 /* how many operands */ 669 unsigned int operands; 670 671 /* base_opcode is the fundamental opcode byte without optional 672 prefix(es). */ 673 unsigned int base_opcode; 674 #define Opcode_D 0x2 /* Direction bit: 675 set if Reg --> Regmem; 676 unset if Regmem --> Reg. */ 677 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ 678 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ 679 680 /* extension_opcode is the 3 bit extension for group <n> insns. 681 This field is also used to store the 8-bit opcode suffix for the 682 AMD 3DNow! instructions. 683 If this template has no extension opcode (the usual case) use None 684 Instructions */ 685 unsigned int extension_opcode; 686 #define None 0xffff /* If no extension_opcode is possible. */ 687 688 /* Opcode length. */ 689 unsigned char opcode_length; 690 691 /* cpu feature flags */ 692 i386_cpu_flags cpu_flags; 693 694 /* the bits in opcode_modifier are used to generate the final opcode from 695 the base_opcode. These bits also are used to detect alternate forms of 696 the same instruction */ 697 i386_opcode_modifier opcode_modifier; 698 699 /* operand_types[i] describes the type of operand i. This is made 700 by OR'ing together all of the possible type masks. (e.g. 701 'operand_types[i] = Reg|Imm' specifies that operand i can be 702 either a register or an immediate operand. */ 703 i386_operand_type operand_types[MAX_OPERANDS]; 704 } 705 insn_template; 706 707 extern const insn_template i386_optab[]; 708 709 /* these are for register name --> number & type hash lookup */ 710 typedef struct 711 { 712 char *reg_name; 713 i386_operand_type reg_type; 714 unsigned char reg_flags; 715 #define RegRex 0x1 /* Extended register. */ 716 #define RegRex64 0x2 /* Extended 8 bit register. */ 717 unsigned char reg_num; 718 #define RegRip ((unsigned char ) ~0) 719 #define RegEip (RegRip - 1) 720 /* EIZ and RIZ are fake index registers. */ 721 #define RegEiz (RegEip - 1) 722 #define RegRiz (RegEiz - 1) 723 /* FLAT is a fake segment register (Intel mode). */ 724 #define RegFlat ((unsigned char) ~0) 725 signed char dw2_regnum[2]; 726 #define Dw2Inval (-1) 727 } 728 reg_entry; 729 730 /* Entries in i386_regtab. */ 731 #define REGNAM_AL 1 732 #define REGNAM_AX 25 733 #define REGNAM_EAX 41 734 735 extern const reg_entry i386_regtab[]; 736 extern const unsigned int i386_regtab_size; 737 738 typedef struct 739 { 740 char *seg_name; 741 unsigned int seg_prefix; 742 } 743 seg_entry; 744 745 extern const seg_entry cs; 746 extern const seg_entry ds; 747 extern const seg_entry ss; 748 extern const seg_entry es; 749 extern const seg_entry fs; 750 extern const seg_entry gs; 751