1#include "x86_arch.h" 2 3.hidden OPENSSL_cpuid_setup 4.section .init 5 call OPENSSL_cpuid_setup 6 7 8.hidden OPENSSL_ia32cap_P 9 10.text 11 12.globl OPENSSL_atomic_add 13.type OPENSSL_atomic_add,@function 14.align 16 15OPENSSL_atomic_add: 16 movl (%rdi),%eax 17.Lspin: leaq (%rsi,%rax,1),%r8 18.byte 0xf0 19 cmpxchgl %r8d,(%rdi) 20 jne .Lspin 21 movl %r8d,%eax 22.byte 0x48,0x98 23 retq 24.size OPENSSL_atomic_add,.-OPENSSL_atomic_add 25 26.globl OPENSSL_ia32_cpuid 27.type OPENSSL_ia32_cpuid,@function 28.align 16 29OPENSSL_ia32_cpuid: 30 movq %rbx,%r8 31 32 xorl %eax,%eax 33 cpuid 34 movl %eax,%r11d 35 36 xorl %eax,%eax 37 cmpl $1970169159,%ebx 38 setne %al 39 movl %eax,%r9d 40 cmpl $1231384169,%edx 41 setne %al 42 orl %eax,%r9d 43 cmpl $1818588270,%ecx 44 setne %al 45 orl %eax,%r9d 46 jz .Lintel 47 48 cmpl $1752462657,%ebx 49 setne %al 50 movl %eax,%r10d 51 cmpl $1769238117,%edx 52 setne %al 53 orl %eax,%r10d 54 cmpl $1145913699,%ecx 55 setne %al 56 orl %eax,%r10d 57 jnz .Lintel 58 59 60 movl $2147483648,%eax 61 cpuid 62 cmpl $2147483649,%eax 63 jb .Lintel 64 movl %eax,%r10d 65 movl $2147483649,%eax 66 cpuid 67 andl $IA32CAP_MASK1_AMD_XOP,%r9d 68 orl $1,%r9d 69 70 cmpl $2147483656,%r10d 71 jb .Lintel 72 73 movl $2147483656,%eax 74 cpuid 75 movzbq %cl,%r10 76 incq %r10 77 78 movl $1,%eax 79 cpuid 80 btl $IA32CAP_BIT0_HT,%edx 81 jnc .Lgeneric 82 shrl $16,%ebx 83 cmpb %r10b,%bl 84 ja .Lgeneric 85 xorl $IA32CAP_MASK0_HT,%edx 86 jmp .Lgeneric 87 88.Lintel: 89 cmpl $4,%r11d 90 movl $-1,%r10d 91 jb .Lnocacheinfo 92 93 movl $4,%eax 94 movl $0,%ecx 95 cpuid 96 movl %eax,%r10d 97 shrl $14,%r10d 98 andl $4095,%r10d 99 100.Lnocacheinfo: 101 movl $1,%eax 102 cpuid 103 104 andl $(~(IA32CAP_MASK0_INTELP4 | IA32CAP_MASK0_INTEL)),%edx 105 cmpl $0,%r9d 106 jne .Lnotintel 107 108 orl $IA32CAP_MASK0_INTEL,%edx 109 andb $15,%ah 110 cmpb $15,%ah 111 jne .Lnotintel 112 113 orl $IA32CAP_MASK0_INTELP4,%edx 114.Lnotintel: 115 btl $IA32CAP_BIT0_HT,%edx 116 jnc .Lgeneric 117 xorl $IA32CAP_MASK0_HT,%edx 118 cmpl $0,%r10d 119 je .Lgeneric 120 121 orl $IA32CAP_MASK0_HT,%edx 122 shrl $16,%ebx 123 cmpb $1,%bl 124 ja .Lgeneric 125 xorl $IA32CAP_MASK0_HT,%edx 126 127.Lgeneric: 128 andl $IA32CAP_MASK1_AMD_XOP,%r9d 129 andl $(~IA32CAP_MASK1_AMD_XOP),%ecx 130 orl %ecx,%r9d 131 132 movl %edx,%r10d 133 btl $IA32CAP_BIT1_OSXSAVE,%r9d 134 jnc .Lclear_avx 135 xorl %ecx,%ecx 136.byte 0x0f,0x01,0xd0 137 andl $6,%eax 138 cmpl $6,%eax 139 je .Ldone 140.Lclear_avx: 141 movl $(~(IA32CAP_MASK1_AVX | IA32CAP_MASK1_FMA3 | IA32CAP_MASK1_AMD_XOP)),%eax 142 andl %eax,%r9d 143.Ldone: 144 shlq $32,%r9 145 movl %r10d,%eax 146 movq %r8,%rbx 147 orq %r9,%rax 148 retq 149.size OPENSSL_ia32_cpuid,.-OPENSSL_ia32_cpuid 150.globl OPENSSL_wipe_cpu 151.type OPENSSL_wipe_cpu,@function 152.align 16 153OPENSSL_wipe_cpu: 154 pxor %xmm0,%xmm0 155 pxor %xmm1,%xmm1 156 pxor %xmm2,%xmm2 157 pxor %xmm3,%xmm3 158 pxor %xmm4,%xmm4 159 pxor %xmm5,%xmm5 160 pxor %xmm6,%xmm6 161 pxor %xmm7,%xmm7 162 pxor %xmm8,%xmm8 163 pxor %xmm9,%xmm9 164 pxor %xmm10,%xmm10 165 pxor %xmm11,%xmm11 166 pxor %xmm12,%xmm12 167 pxor %xmm13,%xmm13 168 pxor %xmm14,%xmm14 169 pxor %xmm15,%xmm15 170 xorq %rcx,%rcx 171 xorq %rdx,%rdx 172 xorq %rsi,%rsi 173 xorq %rdi,%rdi 174 xorq %r8,%r8 175 xorq %r9,%r9 176 xorq %r10,%r10 177 xorq %r11,%r11 178 leaq 8(%rsp),%rax 179 retq 180.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu 181#if defined(HAVE_GNU_STACK) 182.section .note.GNU-stack,"",%progbits 183#endif 184