1 /* $OpenBSD: x86_arch.h,v 1.1 2016/11/04 17:30:30 miod Exp $ */ 2 /* 3 * Copyright (c) 2016 Miodrag Vallat. 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 /* 19 * The knowledge of the layout of OPENSSL_ia32cap_P is internal to libcrypto 20 * (and, to some extent, to libssl), and may change in the future without 21 * notice. 22 */ 23 24 /* 25 * OPENSSL_ia32cap_P is computed at runtime by OPENSSL_ia32_cpuid(). 26 * 27 * On processors which lack the cpuid instruction, the value is always 28 * zero (this only matters on 32-bit processors, of course). 29 * 30 * On processors which support the cpuid instruction, after running 31 * "cpuid 1", the value of %edx is written to the low word of OPENSSL_ia32cap_P, 32 * and the value of %ecx is written to its high word. 33 * 34 * Further processing is done to set or clear specific bits, depending 35 * upon the exact processor type. 36 * 37 * Assembly routines usually address OPENSSL_ia32cap_P as two 32-bit words, 38 * hence two sets of bit numbers and masks. OPENSSL_cpu_caps() returns the 39 * complete 64-bit word. 40 */ 41 42 /* bit numbers for the low word */ 43 #define IA32CAP_BIT0_FPU 0 44 #define IA32CAP_BIT0_MMX 23 45 #define IA32CAP_BIT0_FXSR 24 46 #define IA32CAP_BIT0_SSE 25 47 #define IA32CAP_BIT0_SSE2 26 48 #define IA32CAP_BIT0_HT 28 49 50 /* the following bits are not obtained from cpuid */ 51 #define IA32CAP_BIT0_INTELP4 20 52 #define IA32CAP_BIT0_INTEL 30 53 54 /* bit numbers for the high word */ 55 #define IA32CAP_BIT1_PCLMUL 1 56 #define IA32CAP_BIT1_SSSE3 9 57 #define IA32CAP_BIT1_FMA3 12 58 #define IA32CAP_BIT1_AESNI 25 59 #define IA32CAP_BIT1_OSXSAVE 27 60 #define IA32CAP_BIT1_AVX 28 61 62 #define IA32CAP_BIT1_AMD_XOP 11 63 64 /* bit masks for the low word */ 65 #define IA32CAP_MASK0_MMX (1 << IA32CAP_BIT0_MMX) 66 #define IA32CAP_MASK0_FXSR (1 << IA32CAP_BIT0_FXSR) 67 #define IA32CAP_MASK0_SSE (1 << IA32CAP_BIT0_SSE) 68 #define IA32CAP_MASK0_SSE2 (1 << IA32CAP_BIT0_SSE2) 69 #define IA32CAP_MASK0_HT (1 << IA32CAP_BIT0_HT) 70 71 #define IA32CAP_MASK0_INTELP4 (1 << IA32CAP_BIT0_INTELP4) 72 #define IA32CAP_MASK0_INTEL (1 << IA32CAP_BIT0_INTEL) 73 74 /* bit masks for the high word */ 75 #define IA32CAP_MASK1_PCLMUL (1 << IA32CAP_BIT1_PCLMUL) 76 #define IA32CAP_MASK1_SSSE3 (1 << IA32CAP_BIT1_SSSE3) 77 #define IA32CAP_MASK1_FMA3 (1 << IA32CAP_BIT1_FMA3) 78 #define IA32CAP_MASK1_AESNI (1 << IA32CAP_BIT1_AESNI) 79 #define IA32CAP_MASK1_AVX (1 << IA32CAP_BIT1_AVX) 80 81 #define IA32CAP_MASK1_AMD_XOP (1 << IA32CAP_BIT1_AMD_XOP) 82 83 /* bit masks for OPENSSL_cpu_caps() */ 84 #define CPUCAP_MASK_MMX IA32CAP_MASK0_MMX 85 #define CPUCAP_MASK_FXSR IA32CAP_MASK0_FXSR 86 #define CPUCAP_MASK_SSE IA32CAP_MASK0_SSE 87 #define CPUCAP_MASK_INTELP4 IA32CAP_MASK0_INTELP4 88 #define CPUCAP_MASK_PCLMUL (1ULL << (32 + IA32CAP_BIT1_PCLMUL)) 89 #define CPUCAP_MASK_SSSE3 (1ULL << (32 + IA32CAP_BIT1_SSSE3)) 90 #define CPUCAP_MASK_AESNI (1ULL << (32 + IA32CAP_BIT1_AESNI)) 91