1.\" Copyright (c) 1998, 1999, Nicolas Souchu 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD: src/share/man/man4/ppc.4,v 1.13.4.4 2001/08/17 13:08:39 ru Exp $ 26.\" $DragonFly: src/share/man/man4/ppc.4,v 1.4 2007/05/27 23:06:33 swildner Exp $ 27.\" 28.Dd March 5, 1998 29.Dt PPC 4 30.Os 31.Sh NAME 32.Nm ppc 33.Nd Parallel Port Chipset driver 34.Sh SYNOPSIS 35.Cd "device ppc0 at isa? port? flags 0xXX irq 7" 36.Pp 37For one or more PPBUS busses: 38.Cd "device ppbus at ppc0" 39.Sh DESCRIPTION 40The 41.Nm 42driver provides low level support to various parallel port chipsets for the 43.Xr ppbus 4 44system. 45.Pp 46During the probe phase, 47.Nm 48detects parallel port chipsets and initializes 49private data according to their operating mode: COMPATIBLE, 50NIBBLE, PS/2, EPP, ECP and other mixed modes. 51If a mode is provided at startup through the 52.Va flags 53variable of the boot 54interface, the operating mode of the chipset is forced according to 55.Va flags 56and the hardware supported modes. 57.Pp 58During the attach phase, 59.Nm 60allocates a ppbus structure, initializes it and calls the ppbus 61attach function. 62.Ss Supported flags 63.Bl -item -offset indent 64.It 65bits 0-3: chipset forced mode(s) 66.Bd -literal 67PPB_COMPATIBLE 0x0 /* Centronics compatible mode */ 68PPB_NIBBLE 0x1 /* reverse 4 bit mode */ 69PPB_PS2 0x2 /* PS/2 byte mode */ 70PPB_EPP 0x4 /* EPP mode, 32 bit */ 71PPB_ECP 0x8 /* ECP mode */ 72.Ed 73.Pp 74And any mixed values. 75.It 76bit 4: EPP protocol (0 EPP 1.9, 1 EPP 1.7) 77.It 78bit 5: activate IRQ (1 IRQ disabled, 0 IRQ enabled) 79.It 80bit 6: disable chipset specific detection 81.It 82bit 7: disable FIFO detection 83.El 84.Ss Supported chipsets 85Some parallel port chipsets are explicitly supported: 86detection and initialisation code has been written according to 87their datasheets. 88.Bl -bullet -offset indent 89.It 90SMC FDC37C665GT and FDC37C666GT chipsets 91.It 92Natsemi PC873xx-family (PC87332 and PC87306) 93.It 94Winbond W83877xx-family (W83877F and W83877AF) 95.It 96SMC-like chipsets with mixed modes (see 97.Xr ppbus 4 ) 98.El 99.Ss Adding support to a new chipset 100You may want to add support for the newest chipset your motherboard was 101sold with. 102For the ISA bus, just retrieve the specs of the chipset and write the 103corresponding 104.Fn ppc_mychipset_detect 105function. 106Then add an entry to the general purpose 107.Fn ppc_detect 108function. 109.Pp 110Your 111.Fn ppc_mychipset_detect 112function should ensure that if the mode field of the 113.Va flags 114boot variable is not null, then the operating 115mode is forced to the given mode and no other mode is available and 116ppb->ppb_avm field contains the available modes of the chipset. 117.Sh SEE ALSO 118.Xr ppbus 4 , 119.Xr ppi 4 120.Sh HISTORY 121The 122.Nm 123manual page first appeared in 124.Fx 3.0 . 125.Sh AUTHORS 126This manual page was written by 127.An Nicolas Souchu . 128.Sh BUGS 129The chipset detection process may corrupt your chipset configuration. 130You may 131disable chipset specific detection by using the above flags. 132