1 /** @file 2 EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration, 3 and DMA interfaces that a driver uses to access its PCI controller. 4 5 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef __PCI_IO_H__ 11 #define __PCI_IO_H__ 12 13 /// 14 /// Global ID for the PCI I/O Protocol 15 /// 16 #define EFI_PCI_IO_PROTOCOL_GUID \ 17 { \ 18 0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \ 19 } 20 21 typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL; 22 23 /// 24 /// ******************************************************* 25 /// EFI_PCI_IO_PROTOCOL_WIDTH 26 /// ******************************************************* 27 /// 28 typedef enum { 29 EfiPciIoWidthUint8 = 0, 30 EfiPciIoWidthUint16, 31 EfiPciIoWidthUint32, 32 EfiPciIoWidthUint64, 33 EfiPciIoWidthFifoUint8, 34 EfiPciIoWidthFifoUint16, 35 EfiPciIoWidthFifoUint32, 36 EfiPciIoWidthFifoUint64, 37 EfiPciIoWidthFillUint8, 38 EfiPciIoWidthFillUint16, 39 EfiPciIoWidthFillUint32, 40 EfiPciIoWidthFillUint64, 41 EfiPciIoWidthMaximum 42 } EFI_PCI_IO_PROTOCOL_WIDTH; 43 44 // 45 // Complete PCI address generater 46 // 47 #define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged 48 #define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles 49 #define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode) 50 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode) 51 #define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode) 52 #define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode) 53 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode) 54 #define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode) 55 #define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode) 56 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined 57 #define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header 58 #define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header 59 #define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header 60 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached 61 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range 62 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device 63 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR 64 #define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC 65 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode) 66 #define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode) 67 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode) 68 69 #define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) 70 #define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO) 71 72 /// 73 /// ******************************************************* 74 /// EFI_PCI_IO_PROTOCOL_OPERATION 75 /// ******************************************************* 76 /// 77 typedef enum { 78 /// 79 /// A read operation from system memory by a bus master. 80 /// 81 EfiPciIoOperationBusMasterRead, 82 /// 83 /// A write operation from system memory by a bus master. 84 /// 85 EfiPciIoOperationBusMasterWrite, 86 /// 87 /// Provides both read and write access to system memory by both the processor and a 88 /// bus master. The buffer is coherent from both the processor's and the bus master's point of view. 89 /// 90 EfiPciIoOperationBusMasterCommonBuffer, 91 EfiPciIoOperationMaximum 92 } EFI_PCI_IO_PROTOCOL_OPERATION; 93 94 /// 95 /// ******************************************************* 96 /// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION 97 /// ******************************************************* 98 /// 99 typedef enum { 100 /// 101 /// Retrieve the PCI controller's current attributes, and return them in Result. 102 /// 103 EfiPciIoAttributeOperationGet, 104 /// 105 /// Set the PCI controller's current attributes to Attributes. 106 /// 107 EfiPciIoAttributeOperationSet, 108 /// 109 /// Enable the attributes specified by the bits that are set in Attributes for this PCI controller. 110 /// 111 EfiPciIoAttributeOperationEnable, 112 /// 113 /// Disable the attributes specified by the bits that are set in Attributes for this PCI controller. 114 /// 115 EfiPciIoAttributeOperationDisable, 116 /// 117 /// Retrieve the PCI controller's supported attributes, and return them in Result. 118 /// 119 EfiPciIoAttributeOperationSupported, 120 EfiPciIoAttributeOperationMaximum 121 } EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION; 122 123 /** 124 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is 125 satisfied or after a defined duration. 126 127 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 128 @param Width Signifies the width of the memory or I/O operations. 129 @param BarIndex The BAR index of the standard PCI Configuration header to use as the 130 base address for the memory operation to perform. 131 @param Offset The offset within the selected BAR to start the memory operation. 132 @param Mask Mask used for the polling criteria. 133 @param Value The comparison value used for the polling exit criteria. 134 @param Delay The number of 100 ns units to poll. 135 @param Result Pointer to the last value read from the memory location. 136 137 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. 138 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. 139 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller. 140 @retval EFI_TIMEOUT Delay expired before a match occurred. 141 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 142 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 143 144 **/ 145 typedef 146 EFI_STATUS 147 (EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM)( 148 IN EFI_PCI_IO_PROTOCOL *This, 149 IN EFI_PCI_IO_PROTOCOL_WIDTH Width, 150 IN UINT8 BarIndex, 151 IN UINT64 Offset, 152 IN UINT64 Mask, 153 IN UINT64 Value, 154 IN UINT64 Delay, 155 OUT UINT64 *Result 156 ); 157 158 /** 159 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space. 160 161 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 162 @param Width Signifies the width of the memory or I/O operations. 163 @param BarIndex The BAR index of the standard PCI Configuration header to use as the 164 base address for the memory or I/O operation to perform. 165 @param Offset The offset within the selected BAR to start the memory or I/O operation. 166 @param Count The number of memory or I/O operations to perform. 167 @param Buffer For read operations, the destination buffer to store the results. For write 168 operations, the source buffer to write data from. 169 170 @retval EFI_SUCCESS The data was read from or written to the PCI controller. 171 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. 172 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not 173 valid for the PCI BAR specified by BarIndex. 174 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 175 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 176 177 **/ 178 typedef 179 EFI_STATUS 180 (EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM)( 181 IN EFI_PCI_IO_PROTOCOL *This, 182 IN EFI_PCI_IO_PROTOCOL_WIDTH Width, 183 IN UINT8 BarIndex, 184 IN UINT64 Offset, 185 IN UINTN Count, 186 IN OUT VOID *Buffer 187 ); 188 189 typedef struct { 190 /// 191 /// Read PCI controller registers in the PCI memory or I/O space. 192 /// 193 EFI_PCI_IO_PROTOCOL_IO_MEM Read; 194 /// 195 /// Write PCI controller registers in the PCI memory or I/O space. 196 /// 197 EFI_PCI_IO_PROTOCOL_IO_MEM Write; 198 } EFI_PCI_IO_PROTOCOL_ACCESS; 199 200 /** 201 Enable a PCI driver to access PCI controller registers in PCI configuration space. 202 203 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 204 @param Width Signifies the width of the memory operations. 205 @param Offset The offset within the PCI configuration space for the PCI controller. 206 @param Count The number of PCI configuration operations to perform. 207 @param Buffer For read operations, the destination buffer to store the results. For write 208 operations, the source buffer to write data from. 209 210 211 @retval EFI_SUCCESS The data was read from or written to the PCI controller. 212 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not 213 valid for the PCI configuration header of the PCI controller. 214 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 215 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. 216 217 **/ 218 typedef 219 EFI_STATUS 220 (EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG)( 221 IN EFI_PCI_IO_PROTOCOL *This, 222 IN EFI_PCI_IO_PROTOCOL_WIDTH Width, 223 IN UINT32 Offset, 224 IN UINTN Count, 225 IN OUT VOID *Buffer 226 ); 227 228 typedef struct { 229 /// 230 /// Read PCI controller registers in PCI configuration space. 231 /// 232 EFI_PCI_IO_PROTOCOL_CONFIG Read; 233 /// 234 /// Write PCI controller registers in PCI configuration space. 235 /// 236 EFI_PCI_IO_PROTOCOL_CONFIG Write; 237 } EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS; 238 239 /** 240 Enables a PCI driver to copy one region of PCI memory space to another region of PCI 241 memory space. 242 243 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 244 @param Width Signifies the width of the memory operations. 245 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the 246 base address for the memory operation to perform. 247 @param DestOffset The destination offset within the BAR specified by DestBarIndex to 248 start the memory writes for the copy operation. 249 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the 250 base address for the memory operation to perform. 251 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start 252 the memory reads for the copy operation. 253 @param Count The number of memory operations to perform. Bytes moved is Width 254 size * Count, starting at DestOffset and SrcOffset. 255 256 @retval EFI_SUCCESS The data was copied from one memory region to another memory region. 257 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller. 258 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller. 259 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count 260 is not valid for the PCI BAR specified by DestBarIndex. 261 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is 262 not valid for the PCI BAR specified by SrcBarIndex. 263 @retval EFI_INVALID_PARAMETER Width is invalid. 264 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 265 266 **/ 267 typedef 268 EFI_STATUS 269 (EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM)( 270 IN EFI_PCI_IO_PROTOCOL *This, 271 IN EFI_PCI_IO_PROTOCOL_WIDTH Width, 272 IN UINT8 DestBarIndex, 273 IN UINT64 DestOffset, 274 IN UINT8 SrcBarIndex, 275 IN UINT64 SrcOffset, 276 IN UINTN Count 277 ); 278 279 /** 280 Provides the PCI controller-specific addresses needed to access system memory. 281 282 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 283 @param Operation Indicates if the bus master is going to read or write to system memory. 284 @param HostAddress The system memory address to map to the PCI controller. 285 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes 286 that were mapped. 287 @param DeviceAddress The resulting map address for the bus master PCI controller to use to 288 access the hosts HostAddress. 289 @param Mapping A resulting value to pass to Unmap(). 290 291 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. 292 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. 293 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 294 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 295 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address. 296 297 **/ 298 typedef 299 EFI_STATUS 300 (EFIAPI *EFI_PCI_IO_PROTOCOL_MAP)( 301 IN EFI_PCI_IO_PROTOCOL *This, 302 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation, 303 IN VOID *HostAddress, 304 IN OUT UINTN *NumberOfBytes, 305 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, 306 OUT VOID **Mapping 307 ); 308 309 /** 310 Completes the Map() operation and releases any corresponding resources. 311 312 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 313 @param Mapping The mapping value returned from Map(). 314 315 @retval EFI_SUCCESS The range was unmapped. 316 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory. 317 318 **/ 319 typedef 320 EFI_STATUS 321 (EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP)( 322 IN EFI_PCI_IO_PROTOCOL *This, 323 IN VOID *Mapping 324 ); 325 326 /** 327 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer 328 or EfiPciOperationBusMasterCommonBuffer64 mapping. 329 330 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 331 @param Type This parameter is not used and must be ignored. 332 @param MemoryType The type of memory to allocate, EfiBootServicesData or 333 EfiRuntimeServicesData. 334 @param Pages The number of pages to allocate. 335 @param HostAddress A pointer to store the base system memory address of the 336 allocated range. 337 @param Attributes The requested bit mask of attributes for the allocated range. 338 339 @retval EFI_SUCCESS The requested memory pages were allocated. 340 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are 341 MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE. 342 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 343 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. 344 345 **/ 346 typedef 347 EFI_STATUS 348 (EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER)( 349 IN EFI_PCI_IO_PROTOCOL *This, 350 IN EFI_ALLOCATE_TYPE Type, 351 IN EFI_MEMORY_TYPE MemoryType, 352 IN UINTN Pages, 353 OUT VOID **HostAddress, 354 IN UINT64 Attributes 355 ); 356 357 /** 358 Frees memory that was allocated with AllocateBuffer(). 359 360 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 361 @param Pages The number of pages to free. 362 @param HostAddress The base system memory address of the allocated range. 363 364 @retval EFI_SUCCESS The requested memory pages were freed. 365 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages 366 was not allocated with AllocateBuffer(). 367 368 **/ 369 typedef 370 EFI_STATUS 371 (EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER)( 372 IN EFI_PCI_IO_PROTOCOL *This, 373 IN UINTN Pages, 374 IN VOID *HostAddress 375 ); 376 377 /** 378 Flushes all PCI posted write transactions from a PCI host bridge to system memory. 379 380 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 381 382 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host 383 bridge to system memory. 384 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI 385 host bridge due to a hardware error. 386 387 **/ 388 typedef 389 EFI_STATUS 390 (EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH)( 391 IN EFI_PCI_IO_PROTOCOL *This 392 ); 393 394 /** 395 Retrieves this PCI controller's current PCI bus number, device number, and function number. 396 397 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 398 @param SegmentNumber The PCI controller's current PCI segment number. 399 @param BusNumber The PCI controller's current PCI bus number. 400 @param DeviceNumber The PCI controller's current PCI device number. 401 @param FunctionNumber The PCI controller's current PCI function number. 402 403 @retval EFI_SUCCESS The PCI controller location was returned. 404 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 405 406 **/ 407 typedef 408 EFI_STATUS 409 (EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION)( 410 IN EFI_PCI_IO_PROTOCOL *This, 411 OUT UINTN *SegmentNumber, 412 OUT UINTN *BusNumber, 413 OUT UINTN *DeviceNumber, 414 OUT UINTN *FunctionNumber 415 ); 416 417 /** 418 Performs an operation on the attributes that this PCI controller supports. The operations include 419 getting the set of supported attributes, retrieving the current attributes, setting the current 420 attributes, enabling attributes, and disabling attributes. 421 422 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 423 @param Operation The operation to perform on the attributes for this PCI controller. 424 @param Attributes The mask of attributes that are used for Set, Enable, and Disable 425 operations. 426 @param Result A pointer to the result mask of attributes that are returned for the Get 427 and Supported operations. 428 429 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed. 430 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 431 @retval EFI_UNSUPPORTED one or more of the bits set in 432 Attributes are not supported by this PCI controller or one of 433 its parent bridges when Operation is Set, Enable or Disable. 434 435 **/ 436 typedef 437 EFI_STATUS 438 (EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES)( 439 IN EFI_PCI_IO_PROTOCOL *This, 440 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation, 441 IN UINT64 Attributes, 442 OUT UINT64 *Result OPTIONAL 443 ); 444 445 /** 446 Gets the attributes that this PCI controller supports setting on a BAR using 447 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR. 448 449 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 450 @param BarIndex The BAR index of the standard PCI Configuration header to use as the 451 base address for resource range. The legal range for this field is 0..5. 452 @param Supports A pointer to the mask of attributes that this PCI controller supports 453 setting for this BAR with SetBarAttributes(). 454 @param Resources A pointer to the resource descriptors that describe the current 455 configuration of this BAR of the PCI controller. 456 457 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI 458 controller supports are returned in Supports. If Resources 459 is not NULL, then the resource descriptors that the PCI 460 controller is currently using are returned in Resources. 461 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. 462 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. 463 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate 464 Resources. 465 **/ 466 typedef 467 EFI_STATUS 468 (EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES)( 469 IN EFI_PCI_IO_PROTOCOL *This, 470 IN UINT8 BarIndex, 471 OUT UINT64 *Supports OPTIONAL, 472 OUT VOID **Resources OPTIONAL 473 ); 474 475 /** 476 Sets the attributes for a range of a BAR on a PCI controller. 477 478 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 479 @param Attributes The mask of attributes to set for the resource range specified by 480 BarIndex, Offset, and Length. 481 @param BarIndex The BAR index of the standard PCI Configuration header to use as the 482 base address for resource range. The legal range for this field is 0..5. 483 @param Offset A pointer to the BAR relative base address of the resource range to be 484 modified by the attributes specified by Attributes. 485 @param Length A pointer to the length of the resource range to be modified by the 486 attributes specified by Attributes. 487 488 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource 489 range specified by BarIndex, Offset, and Length were 490 set on the PCI controller, and the actual resource range is returned 491 in Offset and Length. 492 @retval EFI_INVALID_PARAMETER Offset or Length is NULL. 493 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. 494 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the 495 resource range specified by BarIndex, Offset, and 496 Length. 497 498 **/ 499 typedef 500 EFI_STATUS 501 (EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES)( 502 IN EFI_PCI_IO_PROTOCOL *This, 503 IN UINT64 Attributes, 504 IN UINT8 BarIndex, 505 IN OUT UINT64 *Offset, 506 IN OUT UINT64 *Length 507 ); 508 509 /// 510 /// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration, 511 /// and DMA interfaces used to abstract accesses to PCI controllers. 512 /// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus. 513 /// A device driver that wishes to manage a PCI controller in a system will have to 514 /// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller. 515 /// 516 struct _EFI_PCI_IO_PROTOCOL { 517 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem; 518 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo; 519 EFI_PCI_IO_PROTOCOL_ACCESS Mem; 520 EFI_PCI_IO_PROTOCOL_ACCESS Io; 521 EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci; 522 EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem; 523 EFI_PCI_IO_PROTOCOL_MAP Map; 524 EFI_PCI_IO_PROTOCOL_UNMAP Unmap; 525 EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer; 526 EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer; 527 EFI_PCI_IO_PROTOCOL_FLUSH Flush; 528 EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation; 529 EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes; 530 EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes; 531 EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes; 532 533 /// 534 /// The size, in bytes, of the ROM image. 535 /// 536 UINT64 RomSize; 537 538 /// 539 /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible 540 /// for allocating memory for the ROM image, and copying the contents of the ROM to memory. 541 /// The contents of this buffer are either from the PCI option ROM that can be accessed 542 /// through the ROM BAR of the PCI controller, or it is from a platform-specific location. 543 /// The Attributes() function can be used to determine from which of these two sources 544 /// the RomImage buffer was initialized. 545 /// 546 VOID *RomImage; 547 }; 548 549 extern EFI_GUID gEfiPciIoProtocolGuid; 550 551 #endif 552