1*1370a723SSascha Wildner /** @file
2*1370a723SSascha Wildner   This header file contains all of the PXE type definitions,
3*1370a723SSascha Wildner   structure prototypes, global variables and constants that
4*1370a723SSascha Wildner   are needed for porting PXE to EFI.
5*1370a723SSascha Wildner 
6*1370a723SSascha Wildner Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
7*1370a723SSascha Wildner SPDX-License-Identifier: BSD-2-Clause-Patent
8*1370a723SSascha Wildner 
9*1370a723SSascha Wildner   @par Revision Reference:
10*1370a723SSascha Wildner   32/64-bit PXE specification:
11*1370a723SSascha Wildner   alpha-4, 99-Dec-17.
12*1370a723SSascha Wildner 
13*1370a723SSascha Wildner **/
14*1370a723SSascha Wildner 
15*1370a723SSascha Wildner #ifndef __EFI_PXE_H__
16*1370a723SSascha Wildner #define __EFI_PXE_H__
17*1370a723SSascha Wildner 
18*1370a723SSascha Wildner #pragma pack(1)
19*1370a723SSascha Wildner 
20*1370a723SSascha Wildner #define PXE_BUSTYPE(a, b, c, d) \
21*1370a723SSascha Wildner     ( \
22*1370a723SSascha Wildner       (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \
23*1370a723SSascha Wildner         ((PXE_UINT32) (a) & 0xFF) \
24*1370a723SSascha Wildner     )
25*1370a723SSascha Wildner 
26*1370a723SSascha Wildner ///
27*1370a723SSascha Wildner /// UNDI ROM ID and devive ID signature.
28*1370a723SSascha Wildner ///
29*1370a723SSascha Wildner #define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')
30*1370a723SSascha Wildner 
31*1370a723SSascha Wildner ///
32*1370a723SSascha Wildner /// BUS ROM ID signatures.
33*1370a723SSascha Wildner ///
34*1370a723SSascha Wildner #define PXE_BUSTYPE_PCI     PXE_BUSTYPE ('P', 'C', 'I', 'R')
35*1370a723SSascha Wildner #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')
36*1370a723SSascha Wildner #define PXE_BUSTYPE_USB     PXE_BUSTYPE ('U', 'S', 'B', 'R')
37*1370a723SSascha Wildner #define PXE_BUSTYPE_1394    PXE_BUSTYPE ('1', '3', '9', '4')
38*1370a723SSascha Wildner 
39*1370a723SSascha Wildner #define PXE_SWAP_UINT16(n)  ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8))
40*1370a723SSascha Wildner 
41*1370a723SSascha Wildner #define PXE_SWAP_UINT32(n) \
42*1370a723SSascha Wildner   ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \
43*1370a723SSascha Wildner    (((PXE_UINT32)(n) & 0x0000FF00) << 8)  | \
44*1370a723SSascha Wildner    (((PXE_UINT32)(n) & 0x00FF0000) >> 8)  | \
45*1370a723SSascha Wildner    (((PXE_UINT32)(n) & 0xFF000000) >> 24))
46*1370a723SSascha Wildner 
47*1370a723SSascha Wildner #define PXE_SWAP_UINT64(n) \
48*1370a723SSascha Wildner   ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \
49*1370a723SSascha Wildner    (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \
50*1370a723SSascha Wildner    (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \
51*1370a723SSascha Wildner    (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8)  | \
52*1370a723SSascha Wildner    (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8)  | \
53*1370a723SSascha Wildner    (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \
54*1370a723SSascha Wildner    (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \
55*1370a723SSascha Wildner    (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56))
56*1370a723SSascha Wildner 
57*1370a723SSascha Wildner #define PXE_CPBSIZE_NOT_USED  0               ///< zero
58*1370a723SSascha Wildner #define PXE_DBSIZE_NOT_USED   0               ///< zero
59*1370a723SSascha Wildner #define PXE_CPBADDR_NOT_USED  (PXE_UINT64) 0  ///< zero
60*1370a723SSascha Wildner #define PXE_DBADDR_NOT_USED   (PXE_UINT64) 0  ///< zero
61*1370a723SSascha Wildner #define PXE_CONST             CONST
62*1370a723SSascha Wildner 
63*1370a723SSascha Wildner #define PXE_VOLATILE          volatile
64*1370a723SSascha Wildner 
65*1370a723SSascha Wildner typedef VOID           PXE_VOID;
66*1370a723SSascha Wildner typedef UINT8          PXE_UINT8;
67*1370a723SSascha Wildner typedef UINT16         PXE_UINT16;
68*1370a723SSascha Wildner typedef UINT32         PXE_UINT32;
69*1370a723SSascha Wildner typedef UINTN          PXE_UINTN;
70*1370a723SSascha Wildner 
71*1370a723SSascha Wildner ///
72*1370a723SSascha Wildner /// Typedef unsigned long PXE_UINT64.
73*1370a723SSascha Wildner ///
74*1370a723SSascha Wildner typedef UINT64      PXE_UINT64;
75*1370a723SSascha Wildner 
76*1370a723SSascha Wildner typedef PXE_UINT8 PXE_BOOL;
77*1370a723SSascha Wildner #define PXE_FALSE 0            ///< zero
78*1370a723SSascha Wildner #define PXE_TRUE  (!PXE_FALSE)
79*1370a723SSascha Wildner 
80*1370a723SSascha Wildner typedef PXE_UINT16      PXE_OPCODE;
81*1370a723SSascha Wildner 
82*1370a723SSascha Wildner ///
83*1370a723SSascha Wildner /// Return UNDI operational state.
84*1370a723SSascha Wildner ///
85*1370a723SSascha Wildner #define PXE_OPCODE_GET_STATE  0x0000
86*1370a723SSascha Wildner 
87*1370a723SSascha Wildner ///
88*1370a723SSascha Wildner /// Change UNDI operational state from Stopped to Started.
89*1370a723SSascha Wildner ///
90*1370a723SSascha Wildner #define PXE_OPCODE_START  0x0001
91*1370a723SSascha Wildner 
92*1370a723SSascha Wildner ///
93*1370a723SSascha Wildner /// Change UNDI operational state from Started to Stopped.
94*1370a723SSascha Wildner ///
95*1370a723SSascha Wildner #define PXE_OPCODE_STOP 0x0002
96*1370a723SSascha Wildner 
97*1370a723SSascha Wildner ///
98*1370a723SSascha Wildner /// Get UNDI initialization information.
99*1370a723SSascha Wildner ///
100*1370a723SSascha Wildner #define PXE_OPCODE_GET_INIT_INFO  0x0003
101*1370a723SSascha Wildner 
102*1370a723SSascha Wildner ///
103*1370a723SSascha Wildner /// Get NIC configuration information.
104*1370a723SSascha Wildner ///
105*1370a723SSascha Wildner #define PXE_OPCODE_GET_CONFIG_INFO  0x0004
106*1370a723SSascha Wildner 
107*1370a723SSascha Wildner ///
108*1370a723SSascha Wildner /// Changed UNDI operational state from Started to Initialized.
109*1370a723SSascha Wildner ///
110*1370a723SSascha Wildner #define PXE_OPCODE_INITIALIZE 0x0005
111*1370a723SSascha Wildner 
112*1370a723SSascha Wildner ///
113*1370a723SSascha Wildner /// Re-initialize the NIC H/W.
114*1370a723SSascha Wildner ///
115*1370a723SSascha Wildner #define PXE_OPCODE_RESET  0x0006
116*1370a723SSascha Wildner 
117*1370a723SSascha Wildner ///
118*1370a723SSascha Wildner /// Change the UNDI operational state from Initialized to Started.
119*1370a723SSascha Wildner ///
120*1370a723SSascha Wildner #define PXE_OPCODE_SHUTDOWN 0x0007
121*1370a723SSascha Wildner 
122*1370a723SSascha Wildner ///
123*1370a723SSascha Wildner /// Read & change state of external interrupt enables.
124*1370a723SSascha Wildner ///
125*1370a723SSascha Wildner #define PXE_OPCODE_INTERRUPT_ENABLES  0x0008
126*1370a723SSascha Wildner 
127*1370a723SSascha Wildner ///
128*1370a723SSascha Wildner /// Read & change state of packet receive filters.
129*1370a723SSascha Wildner ///
130*1370a723SSascha Wildner #define PXE_OPCODE_RECEIVE_FILTERS  0x0009
131*1370a723SSascha Wildner 
132*1370a723SSascha Wildner ///
133*1370a723SSascha Wildner /// Read & change station MAC address.
134*1370a723SSascha Wildner ///
135*1370a723SSascha Wildner #define PXE_OPCODE_STATION_ADDRESS  0x000A
136*1370a723SSascha Wildner 
137*1370a723SSascha Wildner ///
138*1370a723SSascha Wildner /// Read traffic statistics.
139*1370a723SSascha Wildner ///
140*1370a723SSascha Wildner #define PXE_OPCODE_STATISTICS 0x000B
141*1370a723SSascha Wildner 
142*1370a723SSascha Wildner ///
143*1370a723SSascha Wildner /// Convert multicast IP address to multicast MAC address.
144*1370a723SSascha Wildner ///
145*1370a723SSascha Wildner #define PXE_OPCODE_MCAST_IP_TO_MAC  0x000C
146*1370a723SSascha Wildner 
147*1370a723SSascha Wildner ///
148*1370a723SSascha Wildner /// Read or change non-volatile storage on the NIC.
149*1370a723SSascha Wildner ///
150*1370a723SSascha Wildner #define PXE_OPCODE_NVDATA 0x000D
151*1370a723SSascha Wildner 
152*1370a723SSascha Wildner ///
153*1370a723SSascha Wildner /// Get & clear interrupt status.
154*1370a723SSascha Wildner ///
155*1370a723SSascha Wildner #define PXE_OPCODE_GET_STATUS 0x000E
156*1370a723SSascha Wildner 
157*1370a723SSascha Wildner ///
158*1370a723SSascha Wildner /// Fill media header in packet for transmit.
159*1370a723SSascha Wildner ///
160*1370a723SSascha Wildner #define PXE_OPCODE_FILL_HEADER  0x000F
161*1370a723SSascha Wildner 
162*1370a723SSascha Wildner ///
163*1370a723SSascha Wildner /// Transmit packet(s).
164*1370a723SSascha Wildner ///
165*1370a723SSascha Wildner #define PXE_OPCODE_TRANSMIT 0x0010
166*1370a723SSascha Wildner 
167*1370a723SSascha Wildner ///
168*1370a723SSascha Wildner /// Receive packet.
169*1370a723SSascha Wildner ///
170*1370a723SSascha Wildner #define PXE_OPCODE_RECEIVE  0x0011
171*1370a723SSascha Wildner 
172*1370a723SSascha Wildner ///
173*1370a723SSascha Wildner /// Last valid PXE UNDI OpCode number.
174*1370a723SSascha Wildner ///
175*1370a723SSascha Wildner #define PXE_OPCODE_LAST_VALID 0x0011
176*1370a723SSascha Wildner 
177*1370a723SSascha Wildner typedef PXE_UINT16  PXE_OPFLAGS;
178*1370a723SSascha Wildner 
179*1370a723SSascha Wildner #define PXE_OPFLAGS_NOT_USED  0x0000
180*1370a723SSascha Wildner 
181*1370a723SSascha Wildner //
182*1370a723SSascha Wildner // //////////////////////////////////////
183*1370a723SSascha Wildner // UNDI Get State
184*1370a723SSascha Wildner //
185*1370a723SSascha Wildner // No OpFlags
186*1370a723SSascha Wildner 
187*1370a723SSascha Wildner ////////////////////////////////////////
188*1370a723SSascha Wildner // UNDI Start
189*1370a723SSascha Wildner //
190*1370a723SSascha Wildner // No OpFlags
191*1370a723SSascha Wildner 
192*1370a723SSascha Wildner ////////////////////////////////////////
193*1370a723SSascha Wildner // UNDI Stop
194*1370a723SSascha Wildner //
195*1370a723SSascha Wildner // No OpFlags
196*1370a723SSascha Wildner 
197*1370a723SSascha Wildner ////////////////////////////////////////
198*1370a723SSascha Wildner // UNDI Get Init Info
199*1370a723SSascha Wildner //
200*1370a723SSascha Wildner // No Opflags
201*1370a723SSascha Wildner 
202*1370a723SSascha Wildner ////////////////////////////////////////
203*1370a723SSascha Wildner // UNDI Get Config Info
204*1370a723SSascha Wildner //
205*1370a723SSascha Wildner // No Opflags
206*1370a723SSascha Wildner 
207*1370a723SSascha Wildner ///
208*1370a723SSascha Wildner /// UNDI Initialize
209*1370a723SSascha Wildner ///
210*1370a723SSascha Wildner #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK    0x0001
211*1370a723SSascha Wildner #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE         0x0000
212*1370a723SSascha Wildner #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE  0x0001
213*1370a723SSascha Wildner 
214*1370a723SSascha Wildner ///
215*1370a723SSascha Wildner ///
216*1370a723SSascha Wildner /// UNDI Reset
217*1370a723SSascha Wildner ///
218*1370a723SSascha Wildner #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS  0x0001
219*1370a723SSascha Wildner #define PXE_OPFLAGS_RESET_DISABLE_FILTERS     0x0002
220*1370a723SSascha Wildner 
221*1370a723SSascha Wildner ///
222*1370a723SSascha Wildner /// UNDI Shutdown.
223*1370a723SSascha Wildner ///
224*1370a723SSascha Wildner /// No OpFlags.
225*1370a723SSascha Wildner 
226*1370a723SSascha Wildner ///
227*1370a723SSascha Wildner /// UNDI Interrupt Enables.
228*1370a723SSascha Wildner ///
229*1370a723SSascha Wildner ///
230*1370a723SSascha Wildner /// Select whether to enable or disable external interrupt signals.
231*1370a723SSascha Wildner /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.
232*1370a723SSascha Wildner ///
233*1370a723SSascha Wildner #define PXE_OPFLAGS_INTERRUPT_OPMASK  0xC000
234*1370a723SSascha Wildner #define PXE_OPFLAGS_INTERRUPT_ENABLE  0x8000
235*1370a723SSascha Wildner #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000
236*1370a723SSascha Wildner #define PXE_OPFLAGS_INTERRUPT_READ    0x0000
237*1370a723SSascha Wildner 
238*1370a723SSascha Wildner ///
239*1370a723SSascha Wildner /// Enable receive interrupts.  An external interrupt will be generated
240*1370a723SSascha Wildner /// after a complete non-error packet has been received.
241*1370a723SSascha Wildner ///
242*1370a723SSascha Wildner #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001
243*1370a723SSascha Wildner 
244*1370a723SSascha Wildner ///
245*1370a723SSascha Wildner /// Enable transmit interrupts.  An external interrupt will be generated
246*1370a723SSascha Wildner /// after a complete non-error packet has been transmitted.
247*1370a723SSascha Wildner ///
248*1370a723SSascha Wildner #define PXE_OPFLAGS_INTERRUPT_TRANSMIT  0x0002
249*1370a723SSascha Wildner 
250*1370a723SSascha Wildner ///
251*1370a723SSascha Wildner /// Enable command interrupts.  An external interrupt will be generated
252*1370a723SSascha Wildner /// when command execution stops.
253*1370a723SSascha Wildner ///
254*1370a723SSascha Wildner #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004
255*1370a723SSascha Wildner 
256*1370a723SSascha Wildner ///
257*1370a723SSascha Wildner /// Generate software interrupt.  Setting this bit generates an external
258*1370a723SSascha Wildner /// interrupt, if it is supported by the hardware.
259*1370a723SSascha Wildner ///
260*1370a723SSascha Wildner #define PXE_OPFLAGS_INTERRUPT_SOFTWARE  0x0008
261*1370a723SSascha Wildner 
262*1370a723SSascha Wildner ///
263*1370a723SSascha Wildner /// UNDI Receive Filters.
264*1370a723SSascha Wildner ///
265*1370a723SSascha Wildner ///
266*1370a723SSascha Wildner /// Select whether to enable or disable receive filters.
267*1370a723SSascha Wildner /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.
268*1370a723SSascha Wildner ///
269*1370a723SSascha Wildner #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK   0xC000
270*1370a723SSascha Wildner #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE   0x8000
271*1370a723SSascha Wildner #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE  0x4000
272*1370a723SSascha Wildner #define PXE_OPFLAGS_RECEIVE_FILTER_READ     0x0000
273*1370a723SSascha Wildner 
274*1370a723SSascha Wildner ///
275*1370a723SSascha Wildner /// To reset the contents of the multicast MAC address filter list,
276*1370a723SSascha Wildner /// set this OpFlag:
277*1370a723SSascha Wildner ///
278*1370a723SSascha Wildner #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000
279*1370a723SSascha Wildner 
280*1370a723SSascha Wildner ///
281*1370a723SSascha Wildner /// Enable unicast packet receiving.  Packets sent to the current station
282*1370a723SSascha Wildner /// MAC address will be received.
283*1370a723SSascha Wildner ///
284*1370a723SSascha Wildner #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST  0x0001
285*1370a723SSascha Wildner 
286*1370a723SSascha Wildner ///
287*1370a723SSascha Wildner /// Enable broadcast packet receiving.  Packets sent to the broadcast
288*1370a723SSascha Wildner /// MAC address will be received.
289*1370a723SSascha Wildner ///
290*1370a723SSascha Wildner #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST  0x0002
291*1370a723SSascha Wildner 
292*1370a723SSascha Wildner ///
293*1370a723SSascha Wildner /// Enable filtered multicast packet receiving.  Packets sent to any
294*1370a723SSascha Wildner /// of the multicast MAC addresses in the multicast MAC address filter
295*1370a723SSascha Wildner /// list will be received.  If the filter list is empty, no multicast
296*1370a723SSascha Wildner ///
297*1370a723SSascha Wildner #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
298*1370a723SSascha Wildner 
299*1370a723SSascha Wildner ///
300*1370a723SSascha Wildner /// Enable promiscuous packet receiving.  All packets will be received.
301*1370a723SSascha Wildner ///
302*1370a723SSascha Wildner #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS  0x0008
303*1370a723SSascha Wildner 
304*1370a723SSascha Wildner ///
305*1370a723SSascha Wildner /// Enable promiscuous multicast packet receiving.  All multicast
306*1370a723SSascha Wildner /// packets will be received.
307*1370a723SSascha Wildner ///
308*1370a723SSascha Wildner #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST  0x0010
309*1370a723SSascha Wildner 
310*1370a723SSascha Wildner ///
311*1370a723SSascha Wildner /// UNDI Station Address.
312*1370a723SSascha Wildner ///
313*1370a723SSascha Wildner #define PXE_OPFLAGS_STATION_ADDRESS_READ   0x0000
314*1370a723SSascha Wildner #define PXE_OPFLAGS_STATION_ADDRESS_WRITE  0x0000
315*1370a723SSascha Wildner #define PXE_OPFLAGS_STATION_ADDRESS_RESET  0x0001
316*1370a723SSascha Wildner 
317*1370a723SSascha Wildner ///
318*1370a723SSascha Wildner /// UNDI Statistics.
319*1370a723SSascha Wildner ///
320*1370a723SSascha Wildner #define PXE_OPFLAGS_STATISTICS_READ   0x0000
321*1370a723SSascha Wildner #define PXE_OPFLAGS_STATISTICS_RESET  0x0001
322*1370a723SSascha Wildner 
323*1370a723SSascha Wildner ///
324*1370a723SSascha Wildner /// UNDI MCast IP to MAC.
325*1370a723SSascha Wildner ///
326*1370a723SSascha Wildner ///
327*1370a723SSascha Wildner /// Identify the type of IP address in the CPB.
328*1370a723SSascha Wildner ///
329*1370a723SSascha Wildner #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK  0x0003
330*1370a723SSascha Wildner #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC       0x0000
331*1370a723SSascha Wildner #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC       0x0001
332*1370a723SSascha Wildner 
333*1370a723SSascha Wildner ///
334*1370a723SSascha Wildner /// UNDI NvData.
335*1370a723SSascha Wildner ///
336*1370a723SSascha Wildner ///
337*1370a723SSascha Wildner /// Select the type of non-volatile data operation.
338*1370a723SSascha Wildner ///
339*1370a723SSascha Wildner #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001
340*1370a723SSascha Wildner #define PXE_OPFLAGS_NVDATA_READ   0x0000
341*1370a723SSascha Wildner #define PXE_OPFLAGS_NVDATA_WRITE  0x0001
342*1370a723SSascha Wildner 
343*1370a723SSascha Wildner ///
344*1370a723SSascha Wildner /// UNDI Get Status.
345*1370a723SSascha Wildner ///
346*1370a723SSascha Wildner ///
347*1370a723SSascha Wildner /// Return current interrupt status.  This will also clear any interrupts
348*1370a723SSascha Wildner /// that are currently set.  This can be used in a polling routine.  The
349*1370a723SSascha Wildner /// interrupt flags are still set and cleared even when the interrupts
350*1370a723SSascha Wildner /// are disabled.
351*1370a723SSascha Wildner ///
352*1370a723SSascha Wildner #define PXE_OPFLAGS_GET_INTERRUPT_STATUS  0x0001
353*1370a723SSascha Wildner 
354*1370a723SSascha Wildner ///
355*1370a723SSascha Wildner /// Return list of transmitted buffers for recycling.  Transmit buffers
356*1370a723SSascha Wildner /// must not be changed or unallocated until they have recycled.  After
357*1370a723SSascha Wildner /// issuing a transmit command, wait for a transmit complete interrupt.
358*1370a723SSascha Wildner /// When a transmit complete interrupt is received, read the transmitted
359*1370a723SSascha Wildner /// buffers.  Do not plan on getting one buffer per interrupt.  Some
360*1370a723SSascha Wildner /// NICs and UNDIs may transmit multiple buffers per interrupt.
361*1370a723SSascha Wildner ///
362*1370a723SSascha Wildner #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002
363*1370a723SSascha Wildner 
364*1370a723SSascha Wildner ///
365*1370a723SSascha Wildner /// Return current media status.
366*1370a723SSascha Wildner ///
367*1370a723SSascha Wildner #define PXE_OPFLAGS_GET_MEDIA_STATUS    0x0004
368*1370a723SSascha Wildner 
369*1370a723SSascha Wildner ///
370*1370a723SSascha Wildner /// UNDI Fill Header.
371*1370a723SSascha Wildner ///
372*1370a723SSascha Wildner #define PXE_OPFLAGS_FILL_HEADER_OPMASK      0x0001
373*1370a723SSascha Wildner #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED  0x0001
374*1370a723SSascha Wildner #define PXE_OPFLAGS_FILL_HEADER_WHOLE       0x0000
375*1370a723SSascha Wildner 
376*1370a723SSascha Wildner ///
377*1370a723SSascha Wildner /// UNDI Transmit.
378*1370a723SSascha Wildner ///
379*1370a723SSascha Wildner ///
380*1370a723SSascha Wildner /// S/W UNDI only.  Return after the packet has been transmitted.  A
381*1370a723SSascha Wildner /// transmit complete interrupt will still be generated and the transmit
382*1370a723SSascha Wildner /// buffer will have to be recycled.
383*1370a723SSascha Wildner ///
384*1370a723SSascha Wildner #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK  0x0001
385*1370a723SSascha Wildner #define PXE_OPFLAGS_TRANSMIT_BLOCK          0x0001
386*1370a723SSascha Wildner #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK     0x0000
387*1370a723SSascha Wildner 
388*1370a723SSascha Wildner #define PXE_OPFLAGS_TRANSMIT_OPMASK     0x0002
389*1370a723SSascha Wildner #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002
390*1370a723SSascha Wildner #define PXE_OPFLAGS_TRANSMIT_WHOLE      0x0000
391*1370a723SSascha Wildner 
392*1370a723SSascha Wildner ///
393*1370a723SSascha Wildner /// UNDI Receive.
394*1370a723SSascha Wildner ///
395*1370a723SSascha Wildner /// No OpFlags.
396*1370a723SSascha Wildner ///
397*1370a723SSascha Wildner 
398*1370a723SSascha Wildner ///
399*1370a723SSascha Wildner /// PXE STATFLAGS.
400*1370a723SSascha Wildner ///
401*1370a723SSascha Wildner typedef PXE_UINT16  PXE_STATFLAGS;
402*1370a723SSascha Wildner 
403*1370a723SSascha Wildner #define PXE_STATFLAGS_INITIALIZE  0x0000
404*1370a723SSascha Wildner 
405*1370a723SSascha Wildner ///
406*1370a723SSascha Wildner /// Common StatFlags that can be returned by all commands.
407*1370a723SSascha Wildner ///
408*1370a723SSascha Wildner ///
409*1370a723SSascha Wildner /// The COMMAND_COMPLETE and COMMAND_FAILED status flags must be
410*1370a723SSascha Wildner /// implemented by all UNDIs.  COMMAND_QUEUED is only needed by UNDIs
411*1370a723SSascha Wildner /// that support command queuing.
412*1370a723SSascha Wildner ///
413*1370a723SSascha Wildner #define PXE_STATFLAGS_STATUS_MASK       0xC000
414*1370a723SSascha Wildner #define PXE_STATFLAGS_COMMAND_COMPLETE  0xC000
415*1370a723SSascha Wildner #define PXE_STATFLAGS_COMMAND_FAILED    0x8000
416*1370a723SSascha Wildner #define PXE_STATFLAGS_COMMAND_QUEUED    0x4000
417*1370a723SSascha Wildner 
418*1370a723SSascha Wildner ///
419*1370a723SSascha Wildner /// UNDI Get State.
420*1370a723SSascha Wildner ///
421*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATE_MASK        0x0003
422*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002
423*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATE_STARTED     0x0001
424*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATE_STOPPED     0x0000
425*1370a723SSascha Wildner 
426*1370a723SSascha Wildner ///
427*1370a723SSascha Wildner /// UNDI Start.
428*1370a723SSascha Wildner ///
429*1370a723SSascha Wildner /// No additional StatFlags.
430*1370a723SSascha Wildner ///
431*1370a723SSascha Wildner 
432*1370a723SSascha Wildner ///
433*1370a723SSascha Wildner /// UNDI Get Init Info.
434*1370a723SSascha Wildner ///
435*1370a723SSascha Wildner #define PXE_STATFLAGS_CABLE_DETECT_MASK           0x0001
436*1370a723SSascha Wildner #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED  0x0000
437*1370a723SSascha Wildner #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED      0x0001
438*1370a723SSascha Wildner 
439*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_MASK           0x0002
440*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_NOT_SUPPORTED  0x0000
441*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_SUPPORTED      0x0002
442*1370a723SSascha Wildner 
443*1370a723SSascha Wildner ///
444*1370a723SSascha Wildner /// UNDI Initialize.
445*1370a723SSascha Wildner ///
446*1370a723SSascha Wildner #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA  0x0001
447*1370a723SSascha Wildner 
448*1370a723SSascha Wildner ///
449*1370a723SSascha Wildner /// UNDI Reset.
450*1370a723SSascha Wildner ///
451*1370a723SSascha Wildner #define PXE_STATFLAGS_RESET_NO_MEDIA  0x0001
452*1370a723SSascha Wildner 
453*1370a723SSascha Wildner ///
454*1370a723SSascha Wildner /// UNDI Shutdown.
455*1370a723SSascha Wildner ///
456*1370a723SSascha Wildner /// No additional StatFlags.
457*1370a723SSascha Wildner 
458*1370a723SSascha Wildner ///
459*1370a723SSascha Wildner /// UNDI Interrupt Enables.
460*1370a723SSascha Wildner ///
461*1370a723SSascha Wildner ///
462*1370a723SSascha Wildner /// If set, receive interrupts are enabled.
463*1370a723SSascha Wildner ///
464*1370a723SSascha Wildner #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001
465*1370a723SSascha Wildner 
466*1370a723SSascha Wildner ///
467*1370a723SSascha Wildner /// If set, transmit interrupts are enabled.
468*1370a723SSascha Wildner ///
469*1370a723SSascha Wildner #define PXE_STATFLAGS_INTERRUPT_TRANSMIT  0x0002
470*1370a723SSascha Wildner 
471*1370a723SSascha Wildner ///
472*1370a723SSascha Wildner /// If set, command interrupts are enabled.
473*1370a723SSascha Wildner ///
474*1370a723SSascha Wildner #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004
475*1370a723SSascha Wildner 
476*1370a723SSascha Wildner ///
477*1370a723SSascha Wildner /// UNDI Receive Filters.
478*1370a723SSascha Wildner ///
479*1370a723SSascha Wildner 
480*1370a723SSascha Wildner ///
481*1370a723SSascha Wildner /// If set, unicast packets will be received.
482*1370a723SSascha Wildner ///
483*1370a723SSascha Wildner #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST  0x0001
484*1370a723SSascha Wildner 
485*1370a723SSascha Wildner ///
486*1370a723SSascha Wildner /// If set, broadcast packets will be received.
487*1370a723SSascha Wildner ///
488*1370a723SSascha Wildner #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST  0x0002
489*1370a723SSascha Wildner 
490*1370a723SSascha Wildner ///
491*1370a723SSascha Wildner /// If set, multicast packets that match up with the multicast address
492*1370a723SSascha Wildner /// filter list will be received.
493*1370a723SSascha Wildner ///
494*1370a723SSascha Wildner #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
495*1370a723SSascha Wildner 
496*1370a723SSascha Wildner ///
497*1370a723SSascha Wildner /// If set, all packets will be received.
498*1370a723SSascha Wildner ///
499*1370a723SSascha Wildner #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS  0x0008
500*1370a723SSascha Wildner 
501*1370a723SSascha Wildner ///
502*1370a723SSascha Wildner /// If set, all multicast packets will be received.
503*1370a723SSascha Wildner ///
504*1370a723SSascha Wildner #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST  0x0010
505*1370a723SSascha Wildner 
506*1370a723SSascha Wildner ///
507*1370a723SSascha Wildner /// UNDI Station Address.
508*1370a723SSascha Wildner ///
509*1370a723SSascha Wildner /// No additional StatFlags.
510*1370a723SSascha Wildner ///
511*1370a723SSascha Wildner 
512*1370a723SSascha Wildner ///
513*1370a723SSascha Wildner /// UNDI Statistics.
514*1370a723SSascha Wildner ///
515*1370a723SSascha Wildner /// No additional StatFlags.
516*1370a723SSascha Wildner ///
517*1370a723SSascha Wildner 
518*1370a723SSascha Wildner ///
519*1370a723SSascha Wildner //// UNDI MCast IP to MAC.
520*1370a723SSascha Wildner ////
521*1370a723SSascha Wildner //// No additional StatFlags.
522*1370a723SSascha Wildner 
523*1370a723SSascha Wildner ///
524*1370a723SSascha Wildner /// UNDI NvData.
525*1370a723SSascha Wildner ///
526*1370a723SSascha Wildner /// No additional StatFlags.
527*1370a723SSascha Wildner ///
528*1370a723SSascha Wildner 
529*1370a723SSascha Wildner ///
530*1370a723SSascha Wildner /// UNDI Get Status.
531*1370a723SSascha Wildner ///
532*1370a723SSascha Wildner 
533*1370a723SSascha Wildner ///
534*1370a723SSascha Wildner /// Use to determine if an interrupt has occurred.
535*1370a723SSascha Wildner ///
536*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F
537*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS  0x0000
538*1370a723SSascha Wildner 
539*1370a723SSascha Wildner ///
540*1370a723SSascha Wildner /// If set, at least one receive interrupt occurred.
541*1370a723SSascha Wildner ///
542*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATUS_RECEIVE  0x0001
543*1370a723SSascha Wildner 
544*1370a723SSascha Wildner ///
545*1370a723SSascha Wildner /// If set, at least one transmit interrupt occurred.
546*1370a723SSascha Wildner ///
547*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002
548*1370a723SSascha Wildner 
549*1370a723SSascha Wildner ///
550*1370a723SSascha Wildner /// If set, at least one command interrupt occurred.
551*1370a723SSascha Wildner ///
552*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATUS_COMMAND  0x0004
553*1370a723SSascha Wildner 
554*1370a723SSascha Wildner ///
555*1370a723SSascha Wildner /// If set, at least one software interrupt occurred.
556*1370a723SSascha Wildner ///
557*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008
558*1370a723SSascha Wildner 
559*1370a723SSascha Wildner ///
560*1370a723SSascha Wildner /// This flag is set if the transmitted buffer queue is empty.  This flag
561*1370a723SSascha Wildner /// will be set if all transmitted buffer addresses get written into the DB.
562*1370a723SSascha Wildner ///
563*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY  0x0010
564*1370a723SSascha Wildner 
565*1370a723SSascha Wildner ///
566*1370a723SSascha Wildner /// This flag is set if no transmitted buffer addresses were written
567*1370a723SSascha Wildner /// into the DB.  (This could be because DBsize was too small.)
568*1370a723SSascha Wildner ///
569*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN  0x0020
570*1370a723SSascha Wildner 
571*1370a723SSascha Wildner ///
572*1370a723SSascha Wildner /// This flag is set if there is no media detected.
573*1370a723SSascha Wildner ///
574*1370a723SSascha Wildner #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA  0x0040
575*1370a723SSascha Wildner 
576*1370a723SSascha Wildner ///
577*1370a723SSascha Wildner /// UNDI Fill Header.
578*1370a723SSascha Wildner ///
579*1370a723SSascha Wildner /// No additional StatFlags.
580*1370a723SSascha Wildner ///
581*1370a723SSascha Wildner 
582*1370a723SSascha Wildner ///
583*1370a723SSascha Wildner /// UNDI Transmit.
584*1370a723SSascha Wildner ///
585*1370a723SSascha Wildner /// No additional StatFlags.
586*1370a723SSascha Wildner 
587*1370a723SSascha Wildner ///
588*1370a723SSascha Wildner /// UNDI Receive
589*1370a723SSascha Wildner ///.
590*1370a723SSascha Wildner 
591*1370a723SSascha Wildner ///
592*1370a723SSascha Wildner /// No additional StatFlags.
593*1370a723SSascha Wildner ///
594*1370a723SSascha Wildner typedef PXE_UINT16  PXE_STATCODE;
595*1370a723SSascha Wildner 
596*1370a723SSascha Wildner #define PXE_STATCODE_INITIALIZE 0x0000
597*1370a723SSascha Wildner 
598*1370a723SSascha Wildner ///
599*1370a723SSascha Wildner /// Common StatCodes returned by all UNDI commands, UNDI protocol functions
600*1370a723SSascha Wildner /// and BC protocol functions.
601*1370a723SSascha Wildner ///
602*1370a723SSascha Wildner #define PXE_STATCODE_SUCCESS              0x0000
603*1370a723SSascha Wildner 
604*1370a723SSascha Wildner #define PXE_STATCODE_INVALID_CDB          0x0001
605*1370a723SSascha Wildner #define PXE_STATCODE_INVALID_CPB          0x0002
606*1370a723SSascha Wildner #define PXE_STATCODE_BUSY                 0x0003
607*1370a723SSascha Wildner #define PXE_STATCODE_QUEUE_FULL           0x0004
608*1370a723SSascha Wildner #define PXE_STATCODE_ALREADY_STARTED      0x0005
609*1370a723SSascha Wildner #define PXE_STATCODE_NOT_STARTED          0x0006
610*1370a723SSascha Wildner #define PXE_STATCODE_NOT_SHUTDOWN         0x0007
611*1370a723SSascha Wildner #define PXE_STATCODE_ALREADY_INITIALIZED  0x0008
612*1370a723SSascha Wildner #define PXE_STATCODE_NOT_INITIALIZED      0x0009
613*1370a723SSascha Wildner #define PXE_STATCODE_DEVICE_FAILURE       0x000A
614*1370a723SSascha Wildner #define PXE_STATCODE_NVDATA_FAILURE       0x000B
615*1370a723SSascha Wildner #define PXE_STATCODE_UNSUPPORTED          0x000C
616*1370a723SSascha Wildner #define PXE_STATCODE_BUFFER_FULL          0x000D
617*1370a723SSascha Wildner #define PXE_STATCODE_INVALID_PARAMETER    0x000E
618*1370a723SSascha Wildner #define PXE_STATCODE_INVALID_UNDI         0x000F
619*1370a723SSascha Wildner #define PXE_STATCODE_IPV4_NOT_SUPPORTED   0x0010
620*1370a723SSascha Wildner #define PXE_STATCODE_IPV6_NOT_SUPPORTED   0x0011
621*1370a723SSascha Wildner #define PXE_STATCODE_NOT_ENOUGH_MEMORY    0x0012
622*1370a723SSascha Wildner #define PXE_STATCODE_NO_DATA              0x0013
623*1370a723SSascha Wildner 
624*1370a723SSascha Wildner typedef PXE_UINT16  PXE_IFNUM;
625*1370a723SSascha Wildner 
626*1370a723SSascha Wildner ///
627*1370a723SSascha Wildner /// This interface number must be passed to the S/W UNDI Start command.
628*1370a723SSascha Wildner ///
629*1370a723SSascha Wildner #define PXE_IFNUM_START 0x0000
630*1370a723SSascha Wildner 
631*1370a723SSascha Wildner ///
632*1370a723SSascha Wildner /// This interface number is returned by the S/W UNDI Get State and
633*1370a723SSascha Wildner /// Start commands if information in the CDB, CPB or DB is invalid.
634*1370a723SSascha Wildner ///
635*1370a723SSascha Wildner #define PXE_IFNUM_INVALID 0x0000
636*1370a723SSascha Wildner 
637*1370a723SSascha Wildner typedef PXE_UINT16  PXE_CONTROL;
638*1370a723SSascha Wildner 
639*1370a723SSascha Wildner ///
640*1370a723SSascha Wildner /// Setting this flag directs the UNDI to queue this command for later
641*1370a723SSascha Wildner /// execution if the UNDI is busy and it supports command queuing.
642*1370a723SSascha Wildner /// If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error
643*1370a723SSascha Wildner /// is returned.  If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL
644*1370a723SSascha Wildner /// error is returned.
645*1370a723SSascha Wildner ///
646*1370a723SSascha Wildner #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002
647*1370a723SSascha Wildner 
648*1370a723SSascha Wildner ///
649*1370a723SSascha Wildner /// These two bit values are used to determine if there are more UNDI
650*1370a723SSascha Wildner /// CDB structures following this one.  If the link bit is set, there
651*1370a723SSascha Wildner /// must be a CDB structure following this one.  Execution will start
652*1370a723SSascha Wildner /// on the next CDB structure as soon as this one completes successfully.
653*1370a723SSascha Wildner /// If an error is generated by this command, execution will stop.
654*1370a723SSascha Wildner ///
655*1370a723SSascha Wildner #define PXE_CONTROL_LINK              0x0001
656*1370a723SSascha Wildner #define PXE_CONTROL_LAST_CDB_IN_LIST  0x0000
657*1370a723SSascha Wildner 
658*1370a723SSascha Wildner typedef PXE_UINT8   PXE_FRAME_TYPE;
659*1370a723SSascha Wildner 
660*1370a723SSascha Wildner #define PXE_FRAME_TYPE_NONE                     0x00
661*1370a723SSascha Wildner #define PXE_FRAME_TYPE_UNICAST                  0x01
662*1370a723SSascha Wildner #define PXE_FRAME_TYPE_BROADCAST                0x02
663*1370a723SSascha Wildner #define PXE_FRAME_TYPE_FILTERED_MULTICAST       0x03
664*1370a723SSascha Wildner #define PXE_FRAME_TYPE_PROMISCUOUS              0x04
665*1370a723SSascha Wildner #define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST    0x05
666*1370a723SSascha Wildner 
667*1370a723SSascha Wildner #define PXE_FRAME_TYPE_MULTICAST                PXE_FRAME_TYPE_FILTERED_MULTICAST
668*1370a723SSascha Wildner 
669*1370a723SSascha Wildner typedef PXE_UINT32  PXE_IPV4;
670*1370a723SSascha Wildner 
671*1370a723SSascha Wildner typedef PXE_UINT32  PXE_IPV6[4];
672*1370a723SSascha Wildner #define PXE_MAC_LENGTH  32
673*1370a723SSascha Wildner 
674*1370a723SSascha Wildner typedef PXE_UINT8   PXE_MAC_ADDR[PXE_MAC_LENGTH];
675*1370a723SSascha Wildner 
676*1370a723SSascha Wildner typedef PXE_UINT8   PXE_IFTYPE;
677*1370a723SSascha Wildner typedef UINT16      PXE_MEDIA_PROTOCOL;
678*1370a723SSascha Wildner 
679*1370a723SSascha Wildner ///
680*1370a723SSascha Wildner /// This information is from the ARP section of RFC 1700.
681*1370a723SSascha Wildner ///
682*1370a723SSascha Wildner ///     1 Ethernet (10Mb)                                    [JBP]
683*1370a723SSascha Wildner ///     2 Experimental Ethernet (3Mb)                        [JBP]
684*1370a723SSascha Wildner ///     3 Amateur Radio AX.25                                [PXK]
685*1370a723SSascha Wildner ///     4 Proteon ProNET Token Ring                          [JBP]
686*1370a723SSascha Wildner ///     5 Chaos                                              [GXP]
687*1370a723SSascha Wildner ///     6 IEEE 802 Networks                                  [JBP]
688*1370a723SSascha Wildner ///     7 ARCNET                                             [JBP]
689*1370a723SSascha Wildner ///     8 Hyperchannel                                       [JBP]
690*1370a723SSascha Wildner ///     9 Lanstar                                             [TU]
691*1370a723SSascha Wildner ///    10 Autonet Short Address                             [MXB1]
692*1370a723SSascha Wildner ///    11 LocalTalk                                         [JKR1]
693*1370a723SSascha Wildner ///    12 LocalNet (IBM* PCNet or SYTEK* LocalNET)           [JXM]
694*1370a723SSascha Wildner ///    13 Ultra link                                        [RXD2]
695*1370a723SSascha Wildner ///    14 SMDS                                              [GXC1]
696*1370a723SSascha Wildner ///    15 Frame Relay                                        [AGM]
697*1370a723SSascha Wildner ///    16 Asynchronous Transmission Mode (ATM)              [JXB2]
698*1370a723SSascha Wildner ///    17 HDLC                                               [JBP]
699*1370a723SSascha Wildner ///    18 Fibre Channel                            [Yakov Rekhter]
700*1370a723SSascha Wildner ///    19 Asynchronous Transmission Mode (ATM)      [Mark Laubach]
701*1370a723SSascha Wildner ///    20 Serial Line                                        [JBP]
702*1370a723SSascha Wildner ///    21 Asynchronous Transmission Mode (ATM)              [MXB1]
703*1370a723SSascha Wildner ///
704*1370a723SSascha Wildner /// * Other names and brands may be claimed as the property of others.
705*1370a723SSascha Wildner ///
706*1370a723SSascha Wildner #define PXE_IFTYPE_ETHERNET       0x01
707*1370a723SSascha Wildner #define PXE_IFTYPE_TOKENRING      0x04
708*1370a723SSascha Wildner #define PXE_IFTYPE_FIBRE_CHANNEL  0x12
709*1370a723SSascha Wildner 
710*1370a723SSascha Wildner typedef struct s_pxe_hw_undi {
711*1370a723SSascha Wildner   PXE_UINT32  Signature;      ///< PXE_ROMID_SIGNATURE.
712*1370a723SSascha Wildner   PXE_UINT8   Len;            ///< sizeof(PXE_HW_UNDI).
713*1370a723SSascha Wildner   PXE_UINT8   Fudge;          ///< makes 8-bit cksum equal zero.
714*1370a723SSascha Wildner   PXE_UINT8   Rev;            ///< PXE_ROMID_REV.
715*1370a723SSascha Wildner   PXE_UINT8   IFcnt;          ///< physical connector count lower byte.
716*1370a723SSascha Wildner   PXE_UINT8   MajorVer;       ///< PXE_ROMID_MAJORVER.
717*1370a723SSascha Wildner   PXE_UINT8   MinorVer;       ///< PXE_ROMID_MINORVER.
718*1370a723SSascha Wildner   PXE_UINT8   IFcntExt;       ///< physical connector count upper byte.
719*1370a723SSascha Wildner   PXE_UINT8   reserved;       ///< zero, not used.
720*1370a723SSascha Wildner   PXE_UINT32  Implementation; ///< implementation flags.
721*1370a723SSascha Wildner   ///< reserved             ///< vendor use.
722*1370a723SSascha Wildner   ///< UINT32 Status;       ///< status port.
723*1370a723SSascha Wildner   ///< UINT32 Command;      ///< command port.
724*1370a723SSascha Wildner   ///< UINT64 CDBaddr;      ///< CDB address port.
725*1370a723SSascha Wildner   ///<
726*1370a723SSascha Wildner } PXE_HW_UNDI;
727*1370a723SSascha Wildner 
728*1370a723SSascha Wildner ///
729*1370a723SSascha Wildner /// Status port bit definitions.
730*1370a723SSascha Wildner ///
731*1370a723SSascha Wildner 
732*1370a723SSascha Wildner ///
733*1370a723SSascha Wildner /// UNDI operation state.
734*1370a723SSascha Wildner ///
735*1370a723SSascha Wildner #define PXE_HWSTAT_STATE_MASK   0xC0000000
736*1370a723SSascha Wildner #define PXE_HWSTAT_BUSY         0xC0000000
737*1370a723SSascha Wildner #define PXE_HWSTAT_INITIALIZED  0x80000000
738*1370a723SSascha Wildner #define PXE_HWSTAT_STARTED      0x40000000
739*1370a723SSascha Wildner #define PXE_HWSTAT_STOPPED      0x00000000
740*1370a723SSascha Wildner 
741*1370a723SSascha Wildner ///
742*1370a723SSascha Wildner /// If set, last command failed.
743*1370a723SSascha Wildner ///
744*1370a723SSascha Wildner #define PXE_HWSTAT_COMMAND_FAILED 0x20000000
745*1370a723SSascha Wildner 
746*1370a723SSascha Wildner ///
747*1370a723SSascha Wildner /// If set, identifies enabled receive filters.
748*1370a723SSascha Wildner ///
749*1370a723SSascha Wildner #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000
750*1370a723SSascha Wildner #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED           0x00000800
751*1370a723SSascha Wildner #define PXE_HWSTAT_BROADCAST_RX_ENABLED             0x00000400
752*1370a723SSascha Wildner #define PXE_HWSTAT_MULTICAST_RX_ENABLED             0x00000200
753*1370a723SSascha Wildner #define PXE_HWSTAT_UNICAST_RX_ENABLED               0x00000100
754*1370a723SSascha Wildner 
755*1370a723SSascha Wildner ///
756*1370a723SSascha Wildner /// If set, identifies enabled external interrupts.
757*1370a723SSascha Wildner ///
758*1370a723SSascha Wildner #define PXE_HWSTAT_SOFTWARE_INT_ENABLED     0x00000080
759*1370a723SSascha Wildner #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED  0x00000040
760*1370a723SSascha Wildner #define PXE_HWSTAT_PACKET_RX_INT_ENABLED    0x00000020
761*1370a723SSascha Wildner #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010
762*1370a723SSascha Wildner 
763*1370a723SSascha Wildner ///
764*1370a723SSascha Wildner /// If set, identifies pending interrupts.
765*1370a723SSascha Wildner ///
766*1370a723SSascha Wildner #define PXE_HWSTAT_SOFTWARE_INT_PENDING     0x00000008
767*1370a723SSascha Wildner #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING  0x00000004
768*1370a723SSascha Wildner #define PXE_HWSTAT_PACKET_RX_INT_PENDING    0x00000002
769*1370a723SSascha Wildner #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001
770*1370a723SSascha Wildner 
771*1370a723SSascha Wildner ///
772*1370a723SSascha Wildner /// Command port definitions.
773*1370a723SSascha Wildner ///
774*1370a723SSascha Wildner 
775*1370a723SSascha Wildner ///
776*1370a723SSascha Wildner /// If set, CDB identified in CDBaddr port is given to UNDI.
777*1370a723SSascha Wildner /// If not set, other bits in this word will be processed.
778*1370a723SSascha Wildner ///
779*1370a723SSascha Wildner #define PXE_HWCMD_ISSUE_COMMAND   0x80000000
780*1370a723SSascha Wildner #define PXE_HWCMD_INTS_AND_FILTS  0x00000000
781*1370a723SSascha Wildner 
782*1370a723SSascha Wildner ///
783*1370a723SSascha Wildner /// Use these to enable/disable receive filters.
784*1370a723SSascha Wildner ///
785*1370a723SSascha Wildner #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000
786*1370a723SSascha Wildner #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE           0x00000800
787*1370a723SSascha Wildner #define PXE_HWCMD_BROADCAST_RX_ENABLE             0x00000400
788*1370a723SSascha Wildner #define PXE_HWCMD_MULTICAST_RX_ENABLE             0x00000200
789*1370a723SSascha Wildner #define PXE_HWCMD_UNICAST_RX_ENABLE               0x00000100
790*1370a723SSascha Wildner 
791*1370a723SSascha Wildner ///
792*1370a723SSascha Wildner /// Use these to enable/disable external interrupts.
793*1370a723SSascha Wildner ///
794*1370a723SSascha Wildner #define PXE_HWCMD_SOFTWARE_INT_ENABLE     0x00000080
795*1370a723SSascha Wildner #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE  0x00000040
796*1370a723SSascha Wildner #define PXE_HWCMD_PACKET_RX_INT_ENABLE    0x00000020
797*1370a723SSascha Wildner #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010
798*1370a723SSascha Wildner 
799*1370a723SSascha Wildner ///
800*1370a723SSascha Wildner /// Use these to clear pending external interrupts.
801*1370a723SSascha Wildner ///
802*1370a723SSascha Wildner #define PXE_HWCMD_CLEAR_SOFTWARE_INT      0x00000008
803*1370a723SSascha Wildner #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT   0x00000004
804*1370a723SSascha Wildner #define PXE_HWCMD_CLEAR_PACKET_RX_INT     0x00000002
805*1370a723SSascha Wildner #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT  0x00000001
806*1370a723SSascha Wildner 
807*1370a723SSascha Wildner typedef struct s_pxe_sw_undi {
808*1370a723SSascha Wildner   PXE_UINT32  Signature;      ///< PXE_ROMID_SIGNATURE.
809*1370a723SSascha Wildner   PXE_UINT8   Len;            ///< sizeof(PXE_SW_UNDI).
810*1370a723SSascha Wildner   PXE_UINT8   Fudge;          ///< makes 8-bit cksum zero.
811*1370a723SSascha Wildner   PXE_UINT8   Rev;            ///< PXE_ROMID_REV.
812*1370a723SSascha Wildner   PXE_UINT8   IFcnt;          ///< physical connector count lower byte.
813*1370a723SSascha Wildner   PXE_UINT8   MajorVer;       ///< PXE_ROMID_MAJORVER.
814*1370a723SSascha Wildner   PXE_UINT8   MinorVer;       ///< PXE_ROMID_MINORVER.
815*1370a723SSascha Wildner   PXE_UINT8   IFcntExt;       ///< physical connector count upper byte.
816*1370a723SSascha Wildner   PXE_UINT8   reserved1;      ///< zero, not used.
817*1370a723SSascha Wildner   PXE_UINT32  Implementation; ///< Implementation flags.
818*1370a723SSascha Wildner   PXE_UINT64  EntryPoint;     ///< API entry point.
819*1370a723SSascha Wildner   PXE_UINT8   reserved2[3];   ///< zero, not used.
820*1370a723SSascha Wildner   PXE_UINT8   BusCnt;         ///< number of bustypes supported.
821*1370a723SSascha Wildner   PXE_UINT32  BusType[1];     ///< list of supported bustypes.
822*1370a723SSascha Wildner } PXE_SW_UNDI;
823*1370a723SSascha Wildner 
824*1370a723SSascha Wildner typedef union u_pxe_undi {
825*1370a723SSascha Wildner   PXE_HW_UNDI hw;
826*1370a723SSascha Wildner   PXE_SW_UNDI sw;
827*1370a723SSascha Wildner } PXE_UNDI;
828*1370a723SSascha Wildner 
829*1370a723SSascha Wildner ///
830*1370a723SSascha Wildner /// Signature of !PXE structure.
831*1370a723SSascha Wildner ///
832*1370a723SSascha Wildner #define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')
833*1370a723SSascha Wildner 
834*1370a723SSascha Wildner ///
835*1370a723SSascha Wildner /// !PXE structure format revision
836*1370a723SSascha Wildner ///.
837*1370a723SSascha Wildner #define PXE_ROMID_REV 0x02
838*1370a723SSascha Wildner 
839*1370a723SSascha Wildner ///
840*1370a723SSascha Wildner /// UNDI command interface revision.  These are the values that get sent
841*1370a723SSascha Wildner /// in option 94 (Client Network Interface Identifier) in the DHCP Discover
842*1370a723SSascha Wildner /// and PXE Boot Server Request packets.
843*1370a723SSascha Wildner ///
844*1370a723SSascha Wildner #define PXE_ROMID_MAJORVER    0x03
845*1370a723SSascha Wildner #define PXE_ROMID_MINORVER    0x01
846*1370a723SSascha Wildner 
847*1370a723SSascha Wildner ///
848*1370a723SSascha Wildner /// Implementation flags.
849*1370a723SSascha Wildner ///
850*1370a723SSascha Wildner #define PXE_ROMID_IMP_HW_UNDI                             0x80000000
851*1370a723SSascha Wildner #define PXE_ROMID_IMP_SW_VIRT_ADDR                        0x40000000
852*1370a723SSascha Wildner #define PXE_ROMID_IMP_64BIT_DEVICE                        0x00010000
853*1370a723SSascha Wildner #define PXE_ROMID_IMP_FRAG_SUPPORTED                      0x00008000
854*1370a723SSascha Wildner #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED                  0x00004000
855*1370a723SSascha Wildner #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED                 0x00002000
856*1370a723SSascha Wildner #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED               0x00001000
857*1370a723SSascha Wildner #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK                 0x00000C00
858*1370a723SSascha Wildner #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE                0x00000C00
859*1370a723SSascha Wildner #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE              0x00000800
860*1370a723SSascha Wildner #define PXE_ROMID_IMP_NVDATA_READ_ONLY                    0x00000400
861*1370a723SSascha Wildner #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE                0x00000000
862*1370a723SSascha Wildner #define PXE_ROMID_IMP_STATISTICS_SUPPORTED                0x00000200
863*1370a723SSascha Wildner #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE               0x00000100
864*1370a723SSascha Wildner #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED  0x00000080
865*1370a723SSascha Wildner #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED            0x00000040
866*1370a723SSascha Wildner #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED              0x00000020
867*1370a723SSascha Wildner #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED     0x00000010
868*1370a723SSascha Wildner #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED              0x00000008
869*1370a723SSascha Wildner #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED           0x00000004
870*1370a723SSascha Wildner #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED             0x00000002
871*1370a723SSascha Wildner #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED          0x00000001
872*1370a723SSascha Wildner 
873*1370a723SSascha Wildner typedef struct s_pxe_cdb {
874*1370a723SSascha Wildner   PXE_OPCODE    OpCode;
875*1370a723SSascha Wildner   PXE_OPFLAGS   OpFlags;
876*1370a723SSascha Wildner   PXE_UINT16    CPBsize;
877*1370a723SSascha Wildner   PXE_UINT16    DBsize;
878*1370a723SSascha Wildner   PXE_UINT64    CPBaddr;
879*1370a723SSascha Wildner   PXE_UINT64    DBaddr;
880*1370a723SSascha Wildner   PXE_STATCODE  StatCode;
881*1370a723SSascha Wildner   PXE_STATFLAGS StatFlags;
882*1370a723SSascha Wildner   PXE_UINT16    IFnum;
883*1370a723SSascha Wildner   PXE_CONTROL   Control;
884*1370a723SSascha Wildner } PXE_CDB;
885*1370a723SSascha Wildner 
886*1370a723SSascha Wildner typedef union u_pxe_ip_addr {
887*1370a723SSascha Wildner   PXE_IPV6  IPv6;
888*1370a723SSascha Wildner   PXE_IPV4  IPv4;
889*1370a723SSascha Wildner } PXE_IP_ADDR;
890*1370a723SSascha Wildner 
891*1370a723SSascha Wildner typedef union pxe_device {
892*1370a723SSascha Wildner   ///
893*1370a723SSascha Wildner   /// PCI and PC Card NICs are both identified using bus, device
894*1370a723SSascha Wildner   /// and function numbers.  For PC Card, this may require PC
895*1370a723SSascha Wildner   /// Card services to be loaded in the BIOS or preboot
896*1370a723SSascha Wildner   /// environment.
897*1370a723SSascha Wildner   ///
898*1370a723SSascha Wildner   struct {
899*1370a723SSascha Wildner     ///
900*1370a723SSascha Wildner     /// See S/W UNDI ROMID structure definition for PCI and
901*1370a723SSascha Wildner     /// PCC BusType definitions.
902*1370a723SSascha Wildner     ///
903*1370a723SSascha Wildner     PXE_UINT32  BusType;
904*1370a723SSascha Wildner 
905*1370a723SSascha Wildner     ///
906*1370a723SSascha Wildner     /// Bus, device & function numbers that locate this device.
907*1370a723SSascha Wildner     ///
908*1370a723SSascha Wildner     PXE_UINT16  Bus;
909*1370a723SSascha Wildner     PXE_UINT8   Device;
910*1370a723SSascha Wildner     PXE_UINT8   Function;
911*1370a723SSascha Wildner   } PCI, PCC;
912*1370a723SSascha Wildner } PXE_DEVICE;
913*1370a723SSascha Wildner 
914*1370a723SSascha Wildner ///
915*1370a723SSascha Wildner /// cpb and db definitions
916*1370a723SSascha Wildner ///
917*1370a723SSascha Wildner #define MAX_PCI_CONFIG_LEN    64  ///< # of dwords.
918*1370a723SSascha Wildner #define MAX_EEPROM_LEN        128 ///< # of dwords.
919*1370a723SSascha Wildner #define MAX_XMIT_BUFFERS      32  ///< recycling Q length for xmit_done.
920*1370a723SSascha Wildner #define MAX_MCAST_ADDRESS_CNT 8
921*1370a723SSascha Wildner 
922*1370a723SSascha Wildner typedef struct s_pxe_cpb_start_30 {
923*1370a723SSascha Wildner   ///
924*1370a723SSascha Wildner   /// PXE_VOID Delay(UINTN microseconds);
925*1370a723SSascha Wildner   ///
926*1370a723SSascha Wildner   /// UNDI will never request a delay smaller than 10 microseconds
927*1370a723SSascha Wildner   /// and will always request delays in increments of 10 microseconds.
928*1370a723SSascha Wildner   /// The Delay() CallBack routine must delay between n and n + 10
929*1370a723SSascha Wildner   /// microseconds before returning control to the UNDI.
930*1370a723SSascha Wildner   ///
931*1370a723SSascha Wildner   /// This field cannot be set to zero.
932*1370a723SSascha Wildner   ///
933*1370a723SSascha Wildner   UINT64  Delay;
934*1370a723SSascha Wildner 
935*1370a723SSascha Wildner   ///
936*1370a723SSascha Wildner   /// PXE_VOID Block(UINT32 enable);
937*1370a723SSascha Wildner   ///
938*1370a723SSascha Wildner   /// UNDI may need to block multi-threaded/multi-processor access to
939*1370a723SSascha Wildner   /// critical code sections when programming or accessing the network
940*1370a723SSascha Wildner   /// device.  To this end, a blocking service is needed by the UNDI.
941*1370a723SSascha Wildner   /// When UNDI needs a block, it will call Block() passing a non-zero
942*1370a723SSascha Wildner   /// value.  When UNDI no longer needs a block, it will call Block()
943*1370a723SSascha Wildner   /// with a zero value.  When called, if the Block() is already enabled,
944*1370a723SSascha Wildner   /// do not return control to the UNDI until the previous Block() is
945*1370a723SSascha Wildner   /// disabled.
946*1370a723SSascha Wildner   ///
947*1370a723SSascha Wildner   /// This field cannot be set to zero.
948*1370a723SSascha Wildner   ///
949*1370a723SSascha Wildner   UINT64  Block;
950*1370a723SSascha Wildner 
951*1370a723SSascha Wildner   ///
952*1370a723SSascha Wildner   /// PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);
953*1370a723SSascha Wildner   ///
954*1370a723SSascha Wildner   /// UNDI will pass the virtual address of a buffer and the virtual
955*1370a723SSascha Wildner   /// address of a 64-bit physical buffer.  Convert the virtual address
956*1370a723SSascha Wildner   /// to a physical address and write the result to the physical address
957*1370a723SSascha Wildner   /// buffer.  If virtual and physical addresses are the same, just
958*1370a723SSascha Wildner   /// copy the virtual address to the physical address buffer.
959*1370a723SSascha Wildner   ///
960*1370a723SSascha Wildner   /// This field can be set to zero if virtual and physical addresses
961*1370a723SSascha Wildner   /// are equal.
962*1370a723SSascha Wildner   ///
963*1370a723SSascha Wildner   UINT64  Virt2Phys;
964*1370a723SSascha Wildner   ///
965*1370a723SSascha Wildner   /// PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,
966*1370a723SSascha Wildner   ///              UINT64 buf_addr);
967*1370a723SSascha Wildner   ///
968*1370a723SSascha Wildner   /// UNDI will read or write the device io space using this call back
969*1370a723SSascha Wildner   /// function. It passes the number of bytes as the len parameter and it
970*1370a723SSascha Wildner   /// will be either 1,2,4 or 8.
971*1370a723SSascha Wildner   ///
972*1370a723SSascha Wildner   /// This field can not be set to zero.
973*1370a723SSascha Wildner   ///
974*1370a723SSascha Wildner   UINT64  Mem_IO;
975*1370a723SSascha Wildner } PXE_CPB_START_30;
976*1370a723SSascha Wildner 
977*1370a723SSascha Wildner typedef struct s_pxe_cpb_start_31 {
978*1370a723SSascha Wildner   ///
979*1370a723SSascha Wildner   /// PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);
980*1370a723SSascha Wildner   ///
981*1370a723SSascha Wildner   /// UNDI will never request a delay smaller than 10 microseconds
982*1370a723SSascha Wildner   /// and will always request delays in increments of 10 microseconds.
983*1370a723SSascha Wildner   /// The Delay() CallBack routine must delay between n and n + 10
984*1370a723SSascha Wildner   /// microseconds before returning control to the UNDI.
985*1370a723SSascha Wildner   ///
986*1370a723SSascha Wildner   /// This field cannot be set to zero.
987*1370a723SSascha Wildner   ///
988*1370a723SSascha Wildner   UINT64  Delay;
989*1370a723SSascha Wildner 
990*1370a723SSascha Wildner   ///
991*1370a723SSascha Wildner   /// PXE_VOID Block(UINT64 unq_id, UINT32 enable);
992*1370a723SSascha Wildner   ///
993*1370a723SSascha Wildner   /// UNDI may need to block multi-threaded/multi-processor access to
994*1370a723SSascha Wildner   /// critical code sections when programming or accessing the network
995*1370a723SSascha Wildner   /// device.  To this end, a blocking service is needed by the UNDI.
996*1370a723SSascha Wildner   /// When UNDI needs a block, it will call Block() passing a non-zero
997*1370a723SSascha Wildner   /// value.  When UNDI no longer needs a block, it will call Block()
998*1370a723SSascha Wildner   /// with a zero value.  When called, if the Block() is already enabled,
999*1370a723SSascha Wildner   /// do not return control to the UNDI until the previous Block() is
1000*1370a723SSascha Wildner   /// disabled.
1001*1370a723SSascha Wildner   ///
1002*1370a723SSascha Wildner   /// This field cannot be set to zero.
1003*1370a723SSascha Wildner   ///
1004*1370a723SSascha Wildner   UINT64  Block;
1005*1370a723SSascha Wildner 
1006*1370a723SSascha Wildner   ///
1007*1370a723SSascha Wildner   /// PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);
1008*1370a723SSascha Wildner   ///
1009*1370a723SSascha Wildner   /// UNDI will pass the virtual address of a buffer and the virtual
1010*1370a723SSascha Wildner   /// address of a 64-bit physical buffer.  Convert the virtual address
1011*1370a723SSascha Wildner   /// to a physical address and write the result to the physical address
1012*1370a723SSascha Wildner   /// buffer.  If virtual and physical addresses are the same, just
1013*1370a723SSascha Wildner   /// copy the virtual address to the physical address buffer.
1014*1370a723SSascha Wildner   ///
1015*1370a723SSascha Wildner   /// This field can be set to zero if virtual and physical addresses
1016*1370a723SSascha Wildner   /// are equal.
1017*1370a723SSascha Wildner   ///
1018*1370a723SSascha Wildner   UINT64  Virt2Phys;
1019*1370a723SSascha Wildner   ///
1020*1370a723SSascha Wildner   /// PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,
1021*1370a723SSascha Wildner   ///              UINT64 buf_addr);
1022*1370a723SSascha Wildner   ///
1023*1370a723SSascha Wildner   /// UNDI will read or write the device io space using this call back
1024*1370a723SSascha Wildner   /// function. It passes the number of bytes as the len parameter and it
1025*1370a723SSascha Wildner   /// will be either 1,2,4 or 8.
1026*1370a723SSascha Wildner   ///
1027*1370a723SSascha Wildner   /// This field can not be set to zero.
1028*1370a723SSascha Wildner   ///
1029*1370a723SSascha Wildner   UINT64  Mem_IO;
1030*1370a723SSascha Wildner   ///
1031*1370a723SSascha Wildner   /// PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1032*1370a723SSascha Wildner   ///                 UINT32 Direction, UINT64 mapped_addr);
1033*1370a723SSascha Wildner   ///
1034*1370a723SSascha Wildner   /// UNDI will pass the virtual address of a buffer, direction of the data
1035*1370a723SSascha Wildner   /// flow from/to the mapped buffer (the constants are defined below)
1036*1370a723SSascha Wildner   /// and a place holder (pointer) for the mapped address.
1037*1370a723SSascha Wildner   /// This call will Map the given address to a physical DMA address and write
1038*1370a723SSascha Wildner   /// the result to the mapped_addr pointer.  If there is no need to
1039*1370a723SSascha Wildner   /// map the given address to a lower address (i.e. the given address is
1040*1370a723SSascha Wildner   /// associated with a physical address that is already compatible to be
1041*1370a723SSascha Wildner   /// used with the DMA, it converts the given virtual address to it's
1042*1370a723SSascha Wildner   /// physical address and write that in the mapped address pointer.
1043*1370a723SSascha Wildner   ///
1044*1370a723SSascha Wildner   /// This field can be set to zero if there is no mapping service available.
1045*1370a723SSascha Wildner   ///
1046*1370a723SSascha Wildner   UINT64  Map_Mem;
1047*1370a723SSascha Wildner 
1048*1370a723SSascha Wildner   ///
1049*1370a723SSascha Wildner   /// PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1050*1370a723SSascha Wildner   ///            UINT32 Direction, UINT64 mapped_addr);
1051*1370a723SSascha Wildner   ///
1052*1370a723SSascha Wildner   /// UNDI will pass the virtual and mapped addresses of a buffer.
1053*1370a723SSascha Wildner   /// This call will un map the given address.
1054*1370a723SSascha Wildner   ///
1055*1370a723SSascha Wildner   /// This field can be set to zero if there is no unmapping service available.
1056*1370a723SSascha Wildner   ///
1057*1370a723SSascha Wildner   UINT64  UnMap_Mem;
1058*1370a723SSascha Wildner 
1059*1370a723SSascha Wildner   ///
1060*1370a723SSascha Wildner   /// PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,
1061*1370a723SSascha Wildner   ///            UINT32 size, UINT32 Direction, UINT64 mapped_addr);
1062*1370a723SSascha Wildner   ///
1063*1370a723SSascha Wildner   /// UNDI will pass the virtual and mapped addresses of a buffer.
1064*1370a723SSascha Wildner   /// This call will synchronize the contents of both the virtual and mapped.
1065*1370a723SSascha Wildner   /// buffers for the given Direction.
1066*1370a723SSascha Wildner   ///
1067*1370a723SSascha Wildner   /// This field can be set to zero if there is no service available.
1068*1370a723SSascha Wildner   ///
1069*1370a723SSascha Wildner   UINT64  Sync_Mem;
1070*1370a723SSascha Wildner 
1071*1370a723SSascha Wildner   ///
1072*1370a723SSascha Wildner   /// protocol driver can provide anything for this Unique_ID, UNDI remembers
1073*1370a723SSascha Wildner   /// that as just a 64bit value associated to the interface specified by
1074*1370a723SSascha Wildner   /// the ifnum and gives it back as a parameter to all the call-back routines
1075*1370a723SSascha Wildner   /// when calling for that interface!
1076*1370a723SSascha Wildner   ///
1077*1370a723SSascha Wildner   UINT64  Unique_ID;
1078*1370a723SSascha Wildner } PXE_CPB_START_31;
1079*1370a723SSascha Wildner 
1080*1370a723SSascha Wildner #define TO_AND_FROM_DEVICE    0
1081*1370a723SSascha Wildner #define FROM_DEVICE           1
1082*1370a723SSascha Wildner #define TO_DEVICE             2
1083*1370a723SSascha Wildner 
1084*1370a723SSascha Wildner #define PXE_DELAY_MILLISECOND 1000
1085*1370a723SSascha Wildner #define PXE_DELAY_SECOND      1000000
1086*1370a723SSascha Wildner #define PXE_IO_READ           0
1087*1370a723SSascha Wildner #define PXE_IO_WRITE          1
1088*1370a723SSascha Wildner #define PXE_MEM_READ          2
1089*1370a723SSascha Wildner #define PXE_MEM_WRITE         4
1090*1370a723SSascha Wildner 
1091*1370a723SSascha Wildner typedef struct s_pxe_db_get_init_info {
1092*1370a723SSascha Wildner   ///
1093*1370a723SSascha Wildner   /// Minimum length of locked memory buffer that must be given to
1094*1370a723SSascha Wildner   /// the Initialize command. Giving UNDI more memory will generally
1095*1370a723SSascha Wildner   /// give better performance.
1096*1370a723SSascha Wildner   ///
1097*1370a723SSascha Wildner   /// If MemoryRequired is zero, the UNDI does not need and will not
1098*1370a723SSascha Wildner   /// use system memory to receive and transmit packets.
1099*1370a723SSascha Wildner   ///
1100*1370a723SSascha Wildner   PXE_UINT32  MemoryRequired;
1101*1370a723SSascha Wildner 
1102*1370a723SSascha Wildner   ///
1103*1370a723SSascha Wildner   /// Maximum frame data length for Tx/Rx excluding the media header.
1104*1370a723SSascha Wildner   ///
1105*1370a723SSascha Wildner   PXE_UINT32  FrameDataLen;
1106*1370a723SSascha Wildner 
1107*1370a723SSascha Wildner   ///
1108*1370a723SSascha Wildner   /// Supported link speeds are in units of mega bits.  Common ethernet
1109*1370a723SSascha Wildner   /// values are 10, 100 and 1000.  Unused LinkSpeeds[] entries are zero
1110*1370a723SSascha Wildner   /// filled.
1111*1370a723SSascha Wildner   ///
1112*1370a723SSascha Wildner   PXE_UINT32  LinkSpeeds[4];
1113*1370a723SSascha Wildner 
1114*1370a723SSascha Wildner   ///
1115*1370a723SSascha Wildner   /// Number of non-volatile storage items.
1116*1370a723SSascha Wildner   ///
1117*1370a723SSascha Wildner   PXE_UINT32  NvCount;
1118*1370a723SSascha Wildner 
1119*1370a723SSascha Wildner   ///
1120*1370a723SSascha Wildner   /// Width of non-volatile storage item in bytes.  0, 1, 2 or 4
1121*1370a723SSascha Wildner   ///
1122*1370a723SSascha Wildner   PXE_UINT16  NvWidth;
1123*1370a723SSascha Wildner 
1124*1370a723SSascha Wildner   ///
1125*1370a723SSascha Wildner   /// Media header length.  This is the typical media header length for
1126*1370a723SSascha Wildner   /// this UNDI.  This information is needed when allocating receive
1127*1370a723SSascha Wildner   /// and transmit buffers.
1128*1370a723SSascha Wildner   ///
1129*1370a723SSascha Wildner   PXE_UINT16  MediaHeaderLen;
1130*1370a723SSascha Wildner 
1131*1370a723SSascha Wildner   ///
1132*1370a723SSascha Wildner   /// Number of bytes in the NIC hardware (MAC) address.
1133*1370a723SSascha Wildner   ///
1134*1370a723SSascha Wildner   PXE_UINT16  HWaddrLen;
1135*1370a723SSascha Wildner 
1136*1370a723SSascha Wildner   ///
1137*1370a723SSascha Wildner   /// Maximum number of multicast MAC addresses in the multicast
1138*1370a723SSascha Wildner   /// MAC address filter list.
1139*1370a723SSascha Wildner   ///
1140*1370a723SSascha Wildner   PXE_UINT16  MCastFilterCnt;
1141*1370a723SSascha Wildner 
1142*1370a723SSascha Wildner   ///
1143*1370a723SSascha Wildner   /// Default number and size of transmit and receive buffers that will
1144*1370a723SSascha Wildner   /// be allocated by the UNDI.  If MemoryRequired is non-zero, this
1145*1370a723SSascha Wildner   /// allocation will come out of the memory buffer given to the Initialize
1146*1370a723SSascha Wildner   /// command.  If MemoryRequired is zero, this allocation will come out of
1147*1370a723SSascha Wildner   /// memory on the NIC.
1148*1370a723SSascha Wildner   ///
1149*1370a723SSascha Wildner   PXE_UINT16  TxBufCnt;
1150*1370a723SSascha Wildner   PXE_UINT16  TxBufSize;
1151*1370a723SSascha Wildner   PXE_UINT16  RxBufCnt;
1152*1370a723SSascha Wildner   PXE_UINT16  RxBufSize;
1153*1370a723SSascha Wildner 
1154*1370a723SSascha Wildner   ///
1155*1370a723SSascha Wildner   /// Hardware interface types defined in the Assigned Numbers RFC
1156*1370a723SSascha Wildner   /// and used in DHCP and ARP packets.
1157*1370a723SSascha Wildner   /// See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.
1158*1370a723SSascha Wildner   ///
1159*1370a723SSascha Wildner   PXE_UINT8   IFtype;
1160*1370a723SSascha Wildner 
1161*1370a723SSascha Wildner   ///
1162*1370a723SSascha Wildner   /// Supported duplex.  See PXE_DUPLEX_xxxxx #defines below.
1163*1370a723SSascha Wildner   ///
1164*1370a723SSascha Wildner   PXE_UINT8   SupportedDuplexModes;
1165*1370a723SSascha Wildner 
1166*1370a723SSascha Wildner   ///
1167*1370a723SSascha Wildner   /// Supported loopback options.  See PXE_LOOPBACK_xxxxx #defines below.
1168*1370a723SSascha Wildner   ///
1169*1370a723SSascha Wildner   PXE_UINT8   SupportedLoopBackModes;
1170*1370a723SSascha Wildner } PXE_DB_GET_INIT_INFO;
1171*1370a723SSascha Wildner 
1172*1370a723SSascha Wildner #define PXE_MAX_TXRX_UNIT_ETHER           1500
1173*1370a723SSascha Wildner 
1174*1370a723SSascha Wildner #define PXE_HWADDR_LEN_ETHER              0x0006
1175*1370a723SSascha Wildner #define PXE_MAC_HEADER_LEN_ETHER          0x000E
1176*1370a723SSascha Wildner 
1177*1370a723SSascha Wildner #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED  1
1178*1370a723SSascha Wildner #define PXE_DUPLEX_FORCE_FULL_SUPPORTED   2
1179*1370a723SSascha Wildner 
1180*1370a723SSascha Wildner #define PXE_LOOPBACK_INTERNAL_SUPPORTED   1
1181*1370a723SSascha Wildner #define PXE_LOOPBACK_EXTERNAL_SUPPORTED   2
1182*1370a723SSascha Wildner 
1183*1370a723SSascha Wildner typedef struct s_pxe_pci_config_info {
1184*1370a723SSascha Wildner   ///
1185*1370a723SSascha Wildner   /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1186*1370a723SSascha Wildner   /// For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.
1187*1370a723SSascha Wildner   ///
1188*1370a723SSascha Wildner   UINT32  BusType;
1189*1370a723SSascha Wildner 
1190*1370a723SSascha Wildner   ///
1191*1370a723SSascha Wildner   /// This identifies the PCI network device that this UNDI interface.
1192*1370a723SSascha Wildner   /// is bound to.
1193*1370a723SSascha Wildner   ///
1194*1370a723SSascha Wildner   UINT16  Bus;
1195*1370a723SSascha Wildner   UINT8   Device;
1196*1370a723SSascha Wildner   UINT8   Function;
1197*1370a723SSascha Wildner 
1198*1370a723SSascha Wildner   ///
1199*1370a723SSascha Wildner   /// This is a copy of the PCI configuration space for this
1200*1370a723SSascha Wildner   /// network device.
1201*1370a723SSascha Wildner   ///
1202*1370a723SSascha Wildner   union {
1203*1370a723SSascha Wildner     UINT8   Byte[256];
1204*1370a723SSascha Wildner     UINT16  Word[128];
1205*1370a723SSascha Wildner     UINT32  Dword[64];
1206*1370a723SSascha Wildner   } Config;
1207*1370a723SSascha Wildner } PXE_PCI_CONFIG_INFO;
1208*1370a723SSascha Wildner 
1209*1370a723SSascha Wildner typedef struct s_pxe_pcc_config_info {
1210*1370a723SSascha Wildner   ///
1211*1370a723SSascha Wildner   /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1212*1370a723SSascha Wildner   /// For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.
1213*1370a723SSascha Wildner   ///
1214*1370a723SSascha Wildner   PXE_UINT32  BusType;
1215*1370a723SSascha Wildner 
1216*1370a723SSascha Wildner   ///
1217*1370a723SSascha Wildner   /// This identifies the PCC network device that this UNDI interface
1218*1370a723SSascha Wildner   /// is bound to.
1219*1370a723SSascha Wildner   ///
1220*1370a723SSascha Wildner   PXE_UINT16  Bus;
1221*1370a723SSascha Wildner   PXE_UINT8   Device;
1222*1370a723SSascha Wildner   PXE_UINT8   Function;
1223*1370a723SSascha Wildner 
1224*1370a723SSascha Wildner   ///
1225*1370a723SSascha Wildner   /// This is a copy of the PCC configuration space for this
1226*1370a723SSascha Wildner   /// network device.
1227*1370a723SSascha Wildner   ///
1228*1370a723SSascha Wildner   union {
1229*1370a723SSascha Wildner     PXE_UINT8   Byte[256];
1230*1370a723SSascha Wildner     PXE_UINT16  Word[128];
1231*1370a723SSascha Wildner     PXE_UINT32  Dword[64];
1232*1370a723SSascha Wildner   } Config;
1233*1370a723SSascha Wildner } PXE_PCC_CONFIG_INFO;
1234*1370a723SSascha Wildner 
1235*1370a723SSascha Wildner typedef union u_pxe_db_get_config_info {
1236*1370a723SSascha Wildner   PXE_PCI_CONFIG_INFO   pci;
1237*1370a723SSascha Wildner   PXE_PCC_CONFIG_INFO   pcc;
1238*1370a723SSascha Wildner } PXE_DB_GET_CONFIG_INFO;
1239*1370a723SSascha Wildner 
1240*1370a723SSascha Wildner typedef struct s_pxe_cpb_initialize {
1241*1370a723SSascha Wildner   ///
1242*1370a723SSascha Wildner   /// Address of first (lowest) byte of the memory buffer.  This buffer must
1243*1370a723SSascha Wildner   /// be in contiguous physical memory and cannot be swapped out.  The UNDI
1244*1370a723SSascha Wildner   /// will be using this for transmit and receive buffering.
1245*1370a723SSascha Wildner   ///
1246*1370a723SSascha Wildner   PXE_UINT64  MemoryAddr;
1247*1370a723SSascha Wildner 
1248*1370a723SSascha Wildner   ///
1249*1370a723SSascha Wildner   /// MemoryLength must be greater than or equal to MemoryRequired
1250*1370a723SSascha Wildner   /// returned by the Get Init Info command.
1251*1370a723SSascha Wildner   ///
1252*1370a723SSascha Wildner   PXE_UINT32  MemoryLength;
1253*1370a723SSascha Wildner 
1254*1370a723SSascha Wildner   ///
1255*1370a723SSascha Wildner   /// Desired link speed in Mbit/sec.  Common ethernet values are 10, 100
1256*1370a723SSascha Wildner   /// and 1000.  Setting a value of zero will auto-detect and/or use the
1257*1370a723SSascha Wildner   /// default link speed (operation depends on UNDI/NIC functionality).
1258*1370a723SSascha Wildner   ///
1259*1370a723SSascha Wildner   PXE_UINT32  LinkSpeed;
1260*1370a723SSascha Wildner 
1261*1370a723SSascha Wildner   ///
1262*1370a723SSascha Wildner   /// Suggested number and size of receive and transmit buffers to
1263*1370a723SSascha Wildner   /// allocate.  If MemoryAddr and MemoryLength are non-zero, this
1264*1370a723SSascha Wildner   /// allocation comes out of the supplied memory buffer.  If MemoryAddr
1265*1370a723SSascha Wildner   /// and MemoryLength are zero, this allocation comes out of memory
1266*1370a723SSascha Wildner   /// on the NIC.
1267*1370a723SSascha Wildner   ///
1268*1370a723SSascha Wildner   /// If these fields are set to zero, the UNDI will allocate buffer
1269*1370a723SSascha Wildner   /// counts and sizes as it sees fit.
1270*1370a723SSascha Wildner   ///
1271*1370a723SSascha Wildner   PXE_UINT16  TxBufCnt;
1272*1370a723SSascha Wildner   PXE_UINT16  TxBufSize;
1273*1370a723SSascha Wildner   PXE_UINT16  RxBufCnt;
1274*1370a723SSascha Wildner   PXE_UINT16  RxBufSize;
1275*1370a723SSascha Wildner 
1276*1370a723SSascha Wildner   ///
1277*1370a723SSascha Wildner   /// The following configuration parameters are optional and must be zero
1278*1370a723SSascha Wildner   /// to use the default values.
1279*1370a723SSascha Wildner   ///
1280*1370a723SSascha Wildner   PXE_UINT8   DuplexMode;
1281*1370a723SSascha Wildner 
1282*1370a723SSascha Wildner   PXE_UINT8   LoopBackMode;
1283*1370a723SSascha Wildner } PXE_CPB_INITIALIZE;
1284*1370a723SSascha Wildner 
1285*1370a723SSascha Wildner #define PXE_DUPLEX_DEFAULT      0x00
1286*1370a723SSascha Wildner #define PXE_FORCE_FULL_DUPLEX   0x01
1287*1370a723SSascha Wildner #define PXE_ENABLE_FULL_DUPLEX  0x02
1288*1370a723SSascha Wildner #define PXE_FORCE_HALF_DUPLEX   0x04
1289*1370a723SSascha Wildner #define PXE_DISABLE_FULL_DUPLEX 0x08
1290*1370a723SSascha Wildner 
1291*1370a723SSascha Wildner #define LOOPBACK_NORMAL         0
1292*1370a723SSascha Wildner #define LOOPBACK_INTERNAL       1
1293*1370a723SSascha Wildner #define LOOPBACK_EXTERNAL       2
1294*1370a723SSascha Wildner 
1295*1370a723SSascha Wildner typedef struct s_pxe_db_initialize {
1296*1370a723SSascha Wildner   ///
1297*1370a723SSascha Wildner   /// Actual amount of memory used from the supplied memory buffer.  This
1298*1370a723SSascha Wildner   /// may be less that the amount of memory suppllied and may be zero if
1299*1370a723SSascha Wildner   /// the UNDI and network device do not use external memory buffers.
1300*1370a723SSascha Wildner   ///
1301*1370a723SSascha Wildner   /// Memory used by the UNDI and network device is allocated from the
1302*1370a723SSascha Wildner   /// lowest memory buffer address.
1303*1370a723SSascha Wildner   ///
1304*1370a723SSascha Wildner   PXE_UINT32  MemoryUsed;
1305*1370a723SSascha Wildner 
1306*1370a723SSascha Wildner   ///
1307*1370a723SSascha Wildner   /// Actual number and size of receive and transmit buffers that were
1308*1370a723SSascha Wildner   /// allocated.
1309*1370a723SSascha Wildner   ///
1310*1370a723SSascha Wildner   PXE_UINT16  TxBufCnt;
1311*1370a723SSascha Wildner   PXE_UINT16  TxBufSize;
1312*1370a723SSascha Wildner   PXE_UINT16  RxBufCnt;
1313*1370a723SSascha Wildner   PXE_UINT16  RxBufSize;
1314*1370a723SSascha Wildner } PXE_DB_INITIALIZE;
1315*1370a723SSascha Wildner 
1316*1370a723SSascha Wildner typedef struct s_pxe_cpb_receive_filters {
1317*1370a723SSascha Wildner   ///
1318*1370a723SSascha Wildner   /// List of multicast MAC addresses.  This list, if present, will
1319*1370a723SSascha Wildner   /// replace the existing multicast MAC address filter list.
1320*1370a723SSascha Wildner   ///
1321*1370a723SSascha Wildner   PXE_MAC_ADDR  MCastList[MAX_MCAST_ADDRESS_CNT];
1322*1370a723SSascha Wildner } PXE_CPB_RECEIVE_FILTERS;
1323*1370a723SSascha Wildner 
1324*1370a723SSascha Wildner typedef struct s_pxe_db_receive_filters {
1325*1370a723SSascha Wildner   ///
1326*1370a723SSascha Wildner   /// Filtered multicast MAC address list.
1327*1370a723SSascha Wildner   ///
1328*1370a723SSascha Wildner   PXE_MAC_ADDR  MCastList[MAX_MCAST_ADDRESS_CNT];
1329*1370a723SSascha Wildner } PXE_DB_RECEIVE_FILTERS;
1330*1370a723SSascha Wildner 
1331*1370a723SSascha Wildner typedef struct s_pxe_cpb_station_address {
1332*1370a723SSascha Wildner   ///
1333*1370a723SSascha Wildner   /// If supplied and supported, the current station MAC address
1334*1370a723SSascha Wildner   /// will be changed.
1335*1370a723SSascha Wildner   ///
1336*1370a723SSascha Wildner   PXE_MAC_ADDR  StationAddr;
1337*1370a723SSascha Wildner } PXE_CPB_STATION_ADDRESS;
1338*1370a723SSascha Wildner 
1339*1370a723SSascha Wildner typedef struct s_pxe_dpb_station_address {
1340*1370a723SSascha Wildner   ///
1341*1370a723SSascha Wildner   /// Current station MAC address.
1342*1370a723SSascha Wildner   ///
1343*1370a723SSascha Wildner   PXE_MAC_ADDR  StationAddr;
1344*1370a723SSascha Wildner 
1345*1370a723SSascha Wildner   ///
1346*1370a723SSascha Wildner   /// Station broadcast MAC address.
1347*1370a723SSascha Wildner   ///
1348*1370a723SSascha Wildner   PXE_MAC_ADDR  BroadcastAddr;
1349*1370a723SSascha Wildner 
1350*1370a723SSascha Wildner   ///
1351*1370a723SSascha Wildner   /// Permanent station MAC address.
1352*1370a723SSascha Wildner   ///
1353*1370a723SSascha Wildner   PXE_MAC_ADDR  PermanentAddr;
1354*1370a723SSascha Wildner } PXE_DB_STATION_ADDRESS;
1355*1370a723SSascha Wildner 
1356*1370a723SSascha Wildner typedef struct s_pxe_db_statistics {
1357*1370a723SSascha Wildner   ///
1358*1370a723SSascha Wildner   /// Bit field identifying what statistic data is collected by the
1359*1370a723SSascha Wildner   /// UNDI/NIC.
1360*1370a723SSascha Wildner   /// If bit 0x00 is set, Data[0x00] is collected.
1361*1370a723SSascha Wildner   /// If bit 0x01 is set, Data[0x01] is collected.
1362*1370a723SSascha Wildner   /// If bit 0x20 is set, Data[0x20] is collected.
1363*1370a723SSascha Wildner   /// If bit 0x21 is set, Data[0x21] is collected.
1364*1370a723SSascha Wildner   /// Etc.
1365*1370a723SSascha Wildner   ///
1366*1370a723SSascha Wildner   PXE_UINT64  Supported;
1367*1370a723SSascha Wildner 
1368*1370a723SSascha Wildner   ///
1369*1370a723SSascha Wildner   /// Statistic data.
1370*1370a723SSascha Wildner   ///
1371*1370a723SSascha Wildner   PXE_UINT64  Data[64];
1372*1370a723SSascha Wildner } PXE_DB_STATISTICS;
1373*1370a723SSascha Wildner 
1374*1370a723SSascha Wildner ///
1375*1370a723SSascha Wildner /// Total number of frames received.  Includes frames with errors and
1376*1370a723SSascha Wildner /// dropped frames.
1377*1370a723SSascha Wildner ///
1378*1370a723SSascha Wildner #define PXE_STATISTICS_RX_TOTAL_FRAMES  0x00
1379*1370a723SSascha Wildner 
1380*1370a723SSascha Wildner ///
1381*1370a723SSascha Wildner /// Number of valid frames received and copied into receive buffers.
1382*1370a723SSascha Wildner ///
1383*1370a723SSascha Wildner #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01
1384*1370a723SSascha Wildner 
1385*1370a723SSascha Wildner ///
1386*1370a723SSascha Wildner /// Number of frames below the minimum length for the media.
1387*1370a723SSascha Wildner /// This would be <64 for ethernet.
1388*1370a723SSascha Wildner ///
1389*1370a723SSascha Wildner #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES  0x02
1390*1370a723SSascha Wildner 
1391*1370a723SSascha Wildner ///
1392*1370a723SSascha Wildner /// Number of frames longer than the maxminum length for the
1393*1370a723SSascha Wildner /// media.  This would be >1500 for ethernet.
1394*1370a723SSascha Wildner ///
1395*1370a723SSascha Wildner #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03
1396*1370a723SSascha Wildner 
1397*1370a723SSascha Wildner ///
1398*1370a723SSascha Wildner /// Valid frames that were dropped because receive buffers were full.
1399*1370a723SSascha Wildner ///
1400*1370a723SSascha Wildner #define PXE_STATISTICS_RX_DROPPED_FRAMES  0x04
1401*1370a723SSascha Wildner 
1402*1370a723SSascha Wildner ///
1403*1370a723SSascha Wildner /// Number of valid unicast frames received and not dropped.
1404*1370a723SSascha Wildner ///
1405*1370a723SSascha Wildner #define PXE_STATISTICS_RX_UNICAST_FRAMES  0x05
1406*1370a723SSascha Wildner 
1407*1370a723SSascha Wildner ///
1408*1370a723SSascha Wildner /// Number of valid broadcast frames received and not dropped.
1409*1370a723SSascha Wildner ///
1410*1370a723SSascha Wildner #define PXE_STATISTICS_RX_BROADCAST_FRAMES  0x06
1411*1370a723SSascha Wildner 
1412*1370a723SSascha Wildner ///
1413*1370a723SSascha Wildner /// Number of valid mutlicast frames received and not dropped.
1414*1370a723SSascha Wildner ///
1415*1370a723SSascha Wildner #define PXE_STATISTICS_RX_MULTICAST_FRAMES  0x07
1416*1370a723SSascha Wildner 
1417*1370a723SSascha Wildner ///
1418*1370a723SSascha Wildner /// Number of frames w/ CRC or alignment errors.
1419*1370a723SSascha Wildner ///
1420*1370a723SSascha Wildner #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES  0x08
1421*1370a723SSascha Wildner 
1422*1370a723SSascha Wildner ///
1423*1370a723SSascha Wildner /// Total number of bytes received.  Includes frames with errors
1424*1370a723SSascha Wildner /// and dropped frames.
1425*1370a723SSascha Wildner ///
1426*1370a723SSascha Wildner #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09
1427*1370a723SSascha Wildner 
1428*1370a723SSascha Wildner ///
1429*1370a723SSascha Wildner /// Transmit statistics.
1430*1370a723SSascha Wildner ///
1431*1370a723SSascha Wildner #define PXE_STATISTICS_TX_TOTAL_FRAMES      0x0A
1432*1370a723SSascha Wildner #define PXE_STATISTICS_TX_GOOD_FRAMES       0x0B
1433*1370a723SSascha Wildner #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES  0x0C
1434*1370a723SSascha Wildner #define PXE_STATISTICS_TX_OVERSIZE_FRAMES   0x0D
1435*1370a723SSascha Wildner #define PXE_STATISTICS_TX_DROPPED_FRAMES    0x0E
1436*1370a723SSascha Wildner #define PXE_STATISTICS_TX_UNICAST_FRAMES    0x0F
1437*1370a723SSascha Wildner #define PXE_STATISTICS_TX_BROADCAST_FRAMES  0x10
1438*1370a723SSascha Wildner #define PXE_STATISTICS_TX_MULTICAST_FRAMES  0x11
1439*1370a723SSascha Wildner #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES  0x12
1440*1370a723SSascha Wildner #define PXE_STATISTICS_TX_TOTAL_BYTES       0x13
1441*1370a723SSascha Wildner 
1442*1370a723SSascha Wildner ///
1443*1370a723SSascha Wildner /// Number of collisions detection on this subnet.
1444*1370a723SSascha Wildner ///
1445*1370a723SSascha Wildner #define PXE_STATISTICS_COLLISIONS 0x14
1446*1370a723SSascha Wildner 
1447*1370a723SSascha Wildner ///
1448*1370a723SSascha Wildner /// Number of frames destined for unsupported protocol.
1449*1370a723SSascha Wildner ///
1450*1370a723SSascha Wildner #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15
1451*1370a723SSascha Wildner 
1452*1370a723SSascha Wildner ///
1453*1370a723SSascha Wildner /// Number of valid frames received that were duplicated.
1454*1370a723SSascha Wildner ///
1455*1370a723SSascha Wildner #define PXE_STATISTICS_RX_DUPLICATED_FRAMES 0x16
1456*1370a723SSascha Wildner 
1457*1370a723SSascha Wildner ///
1458*1370a723SSascha Wildner /// Number of encrypted frames received that failed to decrypt.
1459*1370a723SSascha Wildner ///
1460*1370a723SSascha Wildner #define PXE_STATISTICS_RX_DECRYPT_ERROR_FRAMES 0x17
1461*1370a723SSascha Wildner 
1462*1370a723SSascha Wildner ///
1463*1370a723SSascha Wildner /// Number of frames that failed to transmit after exceeding the retry limit.
1464*1370a723SSascha Wildner ///
1465*1370a723SSascha Wildner #define PXE_STATISTICS_TX_ERROR_FRAMES 0x18
1466*1370a723SSascha Wildner 
1467*1370a723SSascha Wildner ///
1468*1370a723SSascha Wildner /// Number of frames transmitted successfully after more than one attempt.
1469*1370a723SSascha Wildner ///
1470*1370a723SSascha Wildner #define PXE_STATISTICS_TX_RETRY_FRAMES 0x19
1471*1370a723SSascha Wildner 
1472*1370a723SSascha Wildner typedef struct s_pxe_cpb_mcast_ip_to_mac {
1473*1370a723SSascha Wildner   ///
1474*1370a723SSascha Wildner   /// Multicast IP address to be converted to multicast MAC address.
1475*1370a723SSascha Wildner   ///
1476*1370a723SSascha Wildner   PXE_IP_ADDR IP;
1477*1370a723SSascha Wildner } PXE_CPB_MCAST_IP_TO_MAC;
1478*1370a723SSascha Wildner 
1479*1370a723SSascha Wildner typedef struct s_pxe_db_mcast_ip_to_mac {
1480*1370a723SSascha Wildner   ///
1481*1370a723SSascha Wildner   /// Multicast MAC address.
1482*1370a723SSascha Wildner   ///
1483*1370a723SSascha Wildner   PXE_MAC_ADDR  MAC;
1484*1370a723SSascha Wildner } PXE_DB_MCAST_IP_TO_MAC;
1485*1370a723SSascha Wildner 
1486*1370a723SSascha Wildner typedef struct s_pxe_cpb_nvdata_sparse {
1487*1370a723SSascha Wildner   ///
1488*1370a723SSascha Wildner   /// NvData item list.  Only items in this list will be updated.
1489*1370a723SSascha Wildner   ///
1490*1370a723SSascha Wildner   struct {
1491*1370a723SSascha Wildner     ///
1492*1370a723SSascha Wildner     ///  Non-volatile storage address to be changed.
1493*1370a723SSascha Wildner     ///
1494*1370a723SSascha Wildner     PXE_UINT32  Addr;
1495*1370a723SSascha Wildner 
1496*1370a723SSascha Wildner     ///
1497*1370a723SSascha Wildner     /// Data item to write into above storage address.
1498*1370a723SSascha Wildner     ///
1499*1370a723SSascha Wildner     union {
1500*1370a723SSascha Wildner       PXE_UINT8   Byte;
1501*1370a723SSascha Wildner       PXE_UINT16  Word;
1502*1370a723SSascha Wildner       PXE_UINT32  Dword;
1503*1370a723SSascha Wildner     } Data;
1504*1370a723SSascha Wildner   } Item[MAX_EEPROM_LEN];
1505*1370a723SSascha Wildner } PXE_CPB_NVDATA_SPARSE;
1506*1370a723SSascha Wildner 
1507*1370a723SSascha Wildner ///
1508*1370a723SSascha Wildner /// When using bulk update, the size of the CPB structure must be
1509*1370a723SSascha Wildner /// the same size as the non-volatile NIC storage.
1510*1370a723SSascha Wildner ///
1511*1370a723SSascha Wildner typedef union u_pxe_cpb_nvdata_bulk {
1512*1370a723SSascha Wildner   ///
1513*1370a723SSascha Wildner   /// Array of byte-wide data items.
1514*1370a723SSascha Wildner   ///
1515*1370a723SSascha Wildner   PXE_UINT8   Byte[MAX_EEPROM_LEN << 2];
1516*1370a723SSascha Wildner 
1517*1370a723SSascha Wildner   ///
1518*1370a723SSascha Wildner   /// Array of word-wide data items.
1519*1370a723SSascha Wildner   ///
1520*1370a723SSascha Wildner   PXE_UINT16  Word[MAX_EEPROM_LEN << 1];
1521*1370a723SSascha Wildner 
1522*1370a723SSascha Wildner   ///
1523*1370a723SSascha Wildner   /// Array of dword-wide data items.
1524*1370a723SSascha Wildner   ///
1525*1370a723SSascha Wildner   PXE_UINT32  Dword[MAX_EEPROM_LEN];
1526*1370a723SSascha Wildner } PXE_CPB_NVDATA_BULK;
1527*1370a723SSascha Wildner 
1528*1370a723SSascha Wildner typedef struct s_pxe_db_nvdata {
1529*1370a723SSascha Wildner   ///
1530*1370a723SSascha Wildner   /// Arrays of data items from non-volatile storage.
1531*1370a723SSascha Wildner   ///
1532*1370a723SSascha Wildner   union {
1533*1370a723SSascha Wildner     ///
1534*1370a723SSascha Wildner     /// Array of byte-wide data items.
1535*1370a723SSascha Wildner     ///
1536*1370a723SSascha Wildner     PXE_UINT8   Byte[MAX_EEPROM_LEN << 2];
1537*1370a723SSascha Wildner 
1538*1370a723SSascha Wildner     ///
1539*1370a723SSascha Wildner     /// Array of word-wide data items.
1540*1370a723SSascha Wildner     ///
1541*1370a723SSascha Wildner     PXE_UINT16  Word[MAX_EEPROM_LEN << 1];
1542*1370a723SSascha Wildner 
1543*1370a723SSascha Wildner     ///
1544*1370a723SSascha Wildner     /// Array of dword-wide data items.
1545*1370a723SSascha Wildner     ///
1546*1370a723SSascha Wildner     PXE_UINT32  Dword[MAX_EEPROM_LEN];
1547*1370a723SSascha Wildner   } Data;
1548*1370a723SSascha Wildner } PXE_DB_NVDATA;
1549*1370a723SSascha Wildner 
1550*1370a723SSascha Wildner typedef struct s_pxe_db_get_status {
1551*1370a723SSascha Wildner   ///
1552*1370a723SSascha Wildner   /// Length of next receive frame (header + data).  If this is zero,
1553*1370a723SSascha Wildner   /// there is no next receive frame available.
1554*1370a723SSascha Wildner   ///
1555*1370a723SSascha Wildner   PXE_UINT32  RxFrameLen;
1556*1370a723SSascha Wildner 
1557*1370a723SSascha Wildner   ///
1558*1370a723SSascha Wildner   /// Reserved, set to zero.
1559*1370a723SSascha Wildner   ///
1560*1370a723SSascha Wildner   PXE_UINT32  reserved;
1561*1370a723SSascha Wildner 
1562*1370a723SSascha Wildner   ///
1563*1370a723SSascha Wildner   ///  Addresses of transmitted buffers that need to be recycled.
1564*1370a723SSascha Wildner   ///
1565*1370a723SSascha Wildner   PXE_UINT64  TxBuffer[MAX_XMIT_BUFFERS];
1566*1370a723SSascha Wildner } PXE_DB_GET_STATUS;
1567*1370a723SSascha Wildner 
1568*1370a723SSascha Wildner typedef struct s_pxe_cpb_fill_header {
1569*1370a723SSascha Wildner   ///
1570*1370a723SSascha Wildner   /// Source and destination MAC addresses.  These will be copied into
1571*1370a723SSascha Wildner   /// the media header without doing byte swapping.
1572*1370a723SSascha Wildner   ///
1573*1370a723SSascha Wildner   PXE_MAC_ADDR  SrcAddr;
1574*1370a723SSascha Wildner   PXE_MAC_ADDR  DestAddr;
1575*1370a723SSascha Wildner 
1576*1370a723SSascha Wildner   ///
1577*1370a723SSascha Wildner   /// Address of first byte of media header.  The first byte of packet data
1578*1370a723SSascha Wildner   /// follows the last byte of the media header.
1579*1370a723SSascha Wildner   ///
1580*1370a723SSascha Wildner   PXE_UINT64        MediaHeader;
1581*1370a723SSascha Wildner 
1582*1370a723SSascha Wildner   ///
1583*1370a723SSascha Wildner   /// Length of packet data in bytes (not including the media header).
1584*1370a723SSascha Wildner   ///
1585*1370a723SSascha Wildner   PXE_UINT32        PacketLen;
1586*1370a723SSascha Wildner 
1587*1370a723SSascha Wildner   ///
1588*1370a723SSascha Wildner   /// Protocol type.  This will be copied into the media header without
1589*1370a723SSascha Wildner   /// doing byte swapping.  Protocol type numbers can be obtained from
1590*1370a723SSascha Wildner   /// the Assigned Numbers RFC 1700.
1591*1370a723SSascha Wildner   ///
1592*1370a723SSascha Wildner   PXE_UINT16        Protocol;
1593*1370a723SSascha Wildner 
1594*1370a723SSascha Wildner   ///
1595*1370a723SSascha Wildner   /// Length of the media header in bytes.
1596*1370a723SSascha Wildner   ///
1597*1370a723SSascha Wildner   PXE_UINT16        MediaHeaderLen;
1598*1370a723SSascha Wildner } PXE_CPB_FILL_HEADER;
1599*1370a723SSascha Wildner 
1600*1370a723SSascha Wildner #define PXE_PROTOCOL_ETHERNET_IP  0x0800
1601*1370a723SSascha Wildner #define PXE_PROTOCOL_ETHERNET_ARP 0x0806
1602*1370a723SSascha Wildner #define MAX_XMIT_FRAGMENTS        16
1603*1370a723SSascha Wildner 
1604*1370a723SSascha Wildner typedef struct s_pxe_cpb_fill_header_fragmented {
1605*1370a723SSascha Wildner   ///
1606*1370a723SSascha Wildner   /// Source and destination MAC addresses.  These will be copied into
1607*1370a723SSascha Wildner   /// the media header without doing byte swapping.
1608*1370a723SSascha Wildner   ///
1609*1370a723SSascha Wildner   PXE_MAC_ADDR        SrcAddr;
1610*1370a723SSascha Wildner   PXE_MAC_ADDR        DestAddr;
1611*1370a723SSascha Wildner 
1612*1370a723SSascha Wildner   ///
1613*1370a723SSascha Wildner   /// Length of packet data in bytes (not including the media header).
1614*1370a723SSascha Wildner   ///
1615*1370a723SSascha Wildner   PXE_UINT32          PacketLen;
1616*1370a723SSascha Wildner 
1617*1370a723SSascha Wildner   ///
1618*1370a723SSascha Wildner   /// Protocol type.  This will be copied into the media header without
1619*1370a723SSascha Wildner   /// doing byte swapping.  Protocol type numbers can be obtained from
1620*1370a723SSascha Wildner   /// the Assigned Numbers RFC 1700.
1621*1370a723SSascha Wildner   ///
1622*1370a723SSascha Wildner   PXE_MEDIA_PROTOCOL  Protocol;
1623*1370a723SSascha Wildner 
1624*1370a723SSascha Wildner   ///
1625*1370a723SSascha Wildner   /// Length of the media header in bytes.
1626*1370a723SSascha Wildner   ///
1627*1370a723SSascha Wildner   PXE_UINT16          MediaHeaderLen;
1628*1370a723SSascha Wildner 
1629*1370a723SSascha Wildner   ///
1630*1370a723SSascha Wildner   /// Number of packet fragment descriptors.
1631*1370a723SSascha Wildner   ///
1632*1370a723SSascha Wildner   PXE_UINT16          FragCnt;
1633*1370a723SSascha Wildner 
1634*1370a723SSascha Wildner   ///
1635*1370a723SSascha Wildner   /// Reserved, must be set to zero.
1636*1370a723SSascha Wildner   ///
1637*1370a723SSascha Wildner   PXE_UINT16          reserved;
1638*1370a723SSascha Wildner 
1639*1370a723SSascha Wildner   ///
1640*1370a723SSascha Wildner   /// Array of packet fragment descriptors.  The first byte of the media
1641*1370a723SSascha Wildner   /// header is the first byte of the first fragment.
1642*1370a723SSascha Wildner   ///
1643*1370a723SSascha Wildner   struct {
1644*1370a723SSascha Wildner     ///
1645*1370a723SSascha Wildner     /// Address of this packet fragment.
1646*1370a723SSascha Wildner     ///
1647*1370a723SSascha Wildner     PXE_UINT64  FragAddr;
1648*1370a723SSascha Wildner 
1649*1370a723SSascha Wildner     ///
1650*1370a723SSascha Wildner     /// Length of this packet fragment.
1651*1370a723SSascha Wildner     ///
1652*1370a723SSascha Wildner     PXE_UINT32  FragLen;
1653*1370a723SSascha Wildner 
1654*1370a723SSascha Wildner     ///
1655*1370a723SSascha Wildner     /// Reserved, must be set to zero.
1656*1370a723SSascha Wildner     ///
1657*1370a723SSascha Wildner     PXE_UINT32  reserved;
1658*1370a723SSascha Wildner   } FragDesc[MAX_XMIT_FRAGMENTS];
1659*1370a723SSascha Wildner } PXE_CPB_FILL_HEADER_FRAGMENTED;
1660*1370a723SSascha Wildner 
1661*1370a723SSascha Wildner typedef struct s_pxe_cpb_transmit {
1662*1370a723SSascha Wildner   ///
1663*1370a723SSascha Wildner   /// Address of first byte of frame buffer.  This is also the first byte
1664*1370a723SSascha Wildner   /// of the media header.
1665*1370a723SSascha Wildner   ///
1666*1370a723SSascha Wildner   PXE_UINT64  FrameAddr;
1667*1370a723SSascha Wildner 
1668*1370a723SSascha Wildner   ///
1669*1370a723SSascha Wildner   /// Length of the data portion of the frame buffer in bytes.  Do not
1670*1370a723SSascha Wildner   /// include the length of the media header.
1671*1370a723SSascha Wildner   ///
1672*1370a723SSascha Wildner   PXE_UINT32  DataLen;
1673*1370a723SSascha Wildner 
1674*1370a723SSascha Wildner   ///
1675*1370a723SSascha Wildner   /// Length of the media header in bytes.
1676*1370a723SSascha Wildner   ///
1677*1370a723SSascha Wildner   PXE_UINT16  MediaheaderLen;
1678*1370a723SSascha Wildner 
1679*1370a723SSascha Wildner   ///
1680*1370a723SSascha Wildner   /// Reserved, must be zero.
1681*1370a723SSascha Wildner   ///
1682*1370a723SSascha Wildner   PXE_UINT16  reserved;
1683*1370a723SSascha Wildner } PXE_CPB_TRANSMIT;
1684*1370a723SSascha Wildner 
1685*1370a723SSascha Wildner typedef struct s_pxe_cpb_transmit_fragments {
1686*1370a723SSascha Wildner   ///
1687*1370a723SSascha Wildner   /// Length of packet data in bytes (not including the media header).
1688*1370a723SSascha Wildner   ///
1689*1370a723SSascha Wildner   PXE_UINT32  FrameLen;
1690*1370a723SSascha Wildner 
1691*1370a723SSascha Wildner   ///
1692*1370a723SSascha Wildner   /// Length of the media header in bytes.
1693*1370a723SSascha Wildner   ///
1694*1370a723SSascha Wildner   PXE_UINT16  MediaheaderLen;
1695*1370a723SSascha Wildner 
1696*1370a723SSascha Wildner   ///
1697*1370a723SSascha Wildner   /// Number of packet fragment descriptors.
1698*1370a723SSascha Wildner   ///
1699*1370a723SSascha Wildner   PXE_UINT16  FragCnt;
1700*1370a723SSascha Wildner 
1701*1370a723SSascha Wildner   ///
1702*1370a723SSascha Wildner   /// Array of frame fragment descriptors.  The first byte of the first
1703*1370a723SSascha Wildner   /// fragment is also the first byte of the media header.
1704*1370a723SSascha Wildner   ///
1705*1370a723SSascha Wildner   struct {
1706*1370a723SSascha Wildner     ///
1707*1370a723SSascha Wildner     /// Address of this frame fragment.
1708*1370a723SSascha Wildner     ///
1709*1370a723SSascha Wildner     PXE_UINT64  FragAddr;
1710*1370a723SSascha Wildner 
1711*1370a723SSascha Wildner     ///
1712*1370a723SSascha Wildner     /// Length of this frame fragment.
1713*1370a723SSascha Wildner     ///
1714*1370a723SSascha Wildner     PXE_UINT32  FragLen;
1715*1370a723SSascha Wildner 
1716*1370a723SSascha Wildner     ///
1717*1370a723SSascha Wildner     /// Reserved, must be set to zero.
1718*1370a723SSascha Wildner     ///
1719*1370a723SSascha Wildner     PXE_UINT32  reserved;
1720*1370a723SSascha Wildner   } FragDesc[MAX_XMIT_FRAGMENTS];
1721*1370a723SSascha Wildner } PXE_CPB_TRANSMIT_FRAGMENTS;
1722*1370a723SSascha Wildner 
1723*1370a723SSascha Wildner typedef struct s_pxe_cpb_receive {
1724*1370a723SSascha Wildner   ///
1725*1370a723SSascha Wildner   /// Address of first byte of receive buffer.  This is also the first byte
1726*1370a723SSascha Wildner   /// of the frame header.
1727*1370a723SSascha Wildner   ///
1728*1370a723SSascha Wildner   PXE_UINT64  BufferAddr;
1729*1370a723SSascha Wildner 
1730*1370a723SSascha Wildner   ///
1731*1370a723SSascha Wildner   /// Length of receive buffer.  This must be large enough to hold the
1732*1370a723SSascha Wildner   /// received frame (media header + data).  If the length of smaller than
1733*1370a723SSascha Wildner   /// the received frame, data will be lost.
1734*1370a723SSascha Wildner   ///
1735*1370a723SSascha Wildner   PXE_UINT32  BufferLen;
1736*1370a723SSascha Wildner 
1737*1370a723SSascha Wildner   ///
1738*1370a723SSascha Wildner   /// Reserved, must be set to zero.
1739*1370a723SSascha Wildner   ///
1740*1370a723SSascha Wildner   PXE_UINT32  reserved;
1741*1370a723SSascha Wildner } PXE_CPB_RECEIVE;
1742*1370a723SSascha Wildner 
1743*1370a723SSascha Wildner typedef struct s_pxe_db_receive {
1744*1370a723SSascha Wildner   ///
1745*1370a723SSascha Wildner   /// Source and destination MAC addresses from media header.
1746*1370a723SSascha Wildner   ///
1747*1370a723SSascha Wildner   PXE_MAC_ADDR        SrcAddr;
1748*1370a723SSascha Wildner   PXE_MAC_ADDR        DestAddr;
1749*1370a723SSascha Wildner 
1750*1370a723SSascha Wildner   ///
1751*1370a723SSascha Wildner   /// Length of received frame.  May be larger than receive buffer size.
1752*1370a723SSascha Wildner   /// The receive buffer will not be overwritten.  This is how to tell
1753*1370a723SSascha Wildner   /// if data was lost because the receive buffer was too small.
1754*1370a723SSascha Wildner   ///
1755*1370a723SSascha Wildner   PXE_UINT32          FrameLen;
1756*1370a723SSascha Wildner 
1757*1370a723SSascha Wildner   ///
1758*1370a723SSascha Wildner   /// Protocol type from media header.
1759*1370a723SSascha Wildner   ///
1760*1370a723SSascha Wildner   PXE_MEDIA_PROTOCOL  Protocol;
1761*1370a723SSascha Wildner 
1762*1370a723SSascha Wildner   ///
1763*1370a723SSascha Wildner   /// Length of media header in received frame.
1764*1370a723SSascha Wildner   ///
1765*1370a723SSascha Wildner   PXE_UINT16          MediaHeaderLen;
1766*1370a723SSascha Wildner 
1767*1370a723SSascha Wildner   ///
1768*1370a723SSascha Wildner   /// Type of receive frame.
1769*1370a723SSascha Wildner   ///
1770*1370a723SSascha Wildner   PXE_FRAME_TYPE      Type;
1771*1370a723SSascha Wildner 
1772*1370a723SSascha Wildner   ///
1773*1370a723SSascha Wildner   /// Reserved, must be zero.
1774*1370a723SSascha Wildner   ///
1775*1370a723SSascha Wildner   PXE_UINT8           reserved[7];
1776*1370a723SSascha Wildner } PXE_DB_RECEIVE;
1777*1370a723SSascha Wildner 
1778*1370a723SSascha Wildner #pragma pack()
1779*1370a723SSascha Wildner 
1780*1370a723SSascha Wildner #endif
1781