1 /* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/firewire/firewire.h,v 1.17 2003/11/07 09:01:41 simokawa Exp $ 35 * $DragonFly: src/sys/bus/firewire/firewire.h,v 1.5 2004/05/19 22:52:38 dillon Exp $ 36 * 37 */ 38 39 #ifndef _FIREWIRE_H 40 #define _FIREWIRE_H 1 41 42 #include <sys/ioccom.h> 43 44 #define DEV_DEF 0 45 #define DEV_DV 2 46 47 struct fw_isochreq { 48 unsigned char ch:6, 49 tag:2; 50 }; 51 52 struct fw_isobufreq { 53 struct fw_bufspec { 54 unsigned int nchunk; 55 unsigned int npacket; 56 unsigned int psize; 57 } tx, rx; 58 }; 59 60 struct fw_addr { 61 unsigned long hi; 62 unsigned long lo; 63 }; 64 65 struct fw_asybindreq { 66 struct fw_addr start; 67 unsigned long len; 68 }; 69 70 struct fw_reg_req_t { 71 unsigned long addr; 72 unsigned long data; 73 }; 74 75 #define MAXREC(x) (2 << (x)) 76 #define FWPMAX_S400 (2048 + 20) /* MAXREC plus space for control data */ 77 #define FWMAXQUEUE 128 78 79 #define FWLOCALBUS 0xffc0 80 81 #define FWTCODE_WREQQ 0 82 #define FWTCODE_WREQB 1 83 #define FWTCODE_WRES 2 84 #define FWTCODE_RREQQ 4 85 #define FWTCODE_RREQB 5 86 #define FWTCODE_RRESQ 6 87 #define FWTCODE_RRESB 7 88 #define FWTCODE_CYCS 8 89 #define FWTCODE_LREQ 9 90 #define FWTCODE_STREAM 0xa 91 #define FWTCODE_LRES 0xb 92 #define FWTCODE_PHY 0xe 93 94 #define FWRETRY_1 0 95 #define FWRETRY_X 1 96 #define FWRETRY_A 2 97 #define FWRETRY_B 3 98 99 #define FWRCODE_COMPLETE 0 100 #define FWRCODE_ER_CONFL 4 101 #define FWRCODE_ER_DATA 5 102 #define FWRCODE_ER_TYPE 6 103 #define FWRCODE_ER_ADDR 7 104 105 #define FWSPD_S100 0 106 #define FWSPD_S200 1 107 #define FWSPD_S400 2 108 109 #define FWP_TL_VALID (1 << 7) 110 111 struct fw_isohdr { 112 u_int32_t hdr[1]; 113 }; 114 115 struct fw_asyhdr { 116 u_int32_t hdr[4]; 117 }; 118 119 #if BYTE_ORDER == BIG_ENDIAN 120 #define BIT4x2(x,y) u_int8_t x:4, y:4 121 #define BIT16x2(x,y) u_int32_t x:16, y:16 122 #else 123 #define BIT4x2(x,y) u_int8_t y:4, x:4 124 #define BIT16x2(x,y) u_int32_t y:16, x:16 125 #endif 126 127 128 #if BYTE_ORDER == BIG_ENDIAN 129 #define COMMON_HDR(a,b,c,d) u_int32_t a:16,b:8,c:4,d:4 130 #define COMMON_RES(a,b,c,d) u_int32_t a:16,b:4,c:4,d:8 131 #else 132 #define COMMON_HDR(a,b,c,d) u_int32_t d:4,c:4,b:8,a:16 133 #define COMMON_RES(a,b,c,d) u_int32_t d:8,c:4,b:4,a:16 134 #endif 135 136 struct fw_pkt { 137 union { 138 u_int32_t ld[0]; 139 struct { 140 COMMON_HDR(, , tcode, ); 141 } common; 142 struct { 143 COMMON_HDR(len, chtag, tcode, sy); 144 u_int32_t payload[0]; 145 } stream; 146 struct { 147 COMMON_HDR(dst, tlrt, tcode, pri); 148 BIT16x2(src, ); 149 } hdr; 150 struct { 151 COMMON_HDR(dst, tlrt, tcode, pri); 152 BIT16x2(src, dest_hi); 153 u_int32_t dest_lo; 154 } rreqq; 155 struct { 156 COMMON_HDR(dst, tlrt, tcode, pri); 157 COMMON_RES(src, rtcode, , ); 158 u_int32_t :32; 159 } wres; 160 struct { 161 COMMON_HDR(dst, tlrt, tcode, pri); 162 BIT16x2(src, dest_hi); 163 u_int32_t dest_lo; 164 BIT16x2(len, extcode); 165 } rreqb; 166 struct { 167 COMMON_HDR(dst, tlrt, tcode, pri); 168 BIT16x2(src, dest_hi); 169 u_int32_t dest_lo; 170 u_int32_t data; 171 } wreqq; 172 struct { 173 COMMON_HDR(dst, tlrt, tcode, pri); 174 BIT16x2(src, dest_hi); 175 u_int32_t dest_lo; 176 u_int32_t data; 177 } cyc; 178 struct { 179 COMMON_HDR(dst, tlrt, tcode, pri); 180 COMMON_RES(src, rtcode, , ); 181 u_int32_t :32; 182 u_int32_t data; 183 } rresq; 184 struct { 185 COMMON_HDR(dst, tlrt, tcode, pri); 186 BIT16x2(src, dest_hi); 187 u_int32_t dest_lo; 188 BIT16x2(len, extcode); 189 u_int32_t payload[0]; 190 } wreqb; 191 struct { 192 COMMON_HDR(dst, tlrt, tcode, pri); 193 BIT16x2(src, dest_hi); 194 u_int32_t dest_lo; 195 BIT16x2(len, extcode); 196 u_int32_t payload[0]; 197 } lreq; 198 struct { 199 COMMON_HDR(dst, tlrt, tcode, pri); 200 COMMON_RES(src, rtcode, , ); 201 u_int32_t :32; 202 BIT16x2(len, extcode); 203 u_int32_t payload[0]; 204 } rresb; 205 struct { 206 COMMON_HDR(dst, tlrt, tcode, pri); 207 COMMON_RES(src, rtcode, , ); 208 u_int32_t :32; 209 BIT16x2(len, extcode); 210 u_int32_t payload[0]; 211 } lres; 212 } mode; 213 }; 214 215 /* 216 * Response code (rtcode) 217 */ 218 /* The node has successfully completed the command. */ 219 #define RESP_CMP 0 220 /* A resource conflict was detected. The request may be retried. */ 221 #define RESP_CONFLICT_ERROR 4 222 /* Hardware error, data is unavailable. */ 223 #define RESP_DATA_ERROR 5 224 /* A field in the request packet header was set to an unsupported or incorrect 225 * value, or an invalid transaction was attempted (e.g., a write to a read-only 226 * address). */ 227 #define RESP_TYPE_ERROR 6 228 /* The destination offset field in the request was set to an address not 229 * accessible in the destination node. */ 230 #define RESP_ADDRESS_ERROR 7 231 232 /* 233 * Extended transaction code (extcode) 234 */ 235 #define EXTCODE_MASK_SWAP 1 236 #define EXTCODE_CMP_SWAP 2 237 #define EXTCODE_FETCH_ADD 3 238 #define EXTCODE_LITTLE_ADD 4 239 #define EXTCODE_BOUNDED_ADD 5 240 #define EXTCODE_WRAP_ADD 6 241 242 struct fw_eui64 { 243 u_int32_t hi, lo; 244 }; 245 #define FW_EUI64_BYTE(eui, x) \ 246 ((((x)<4)? \ 247 ((eui)->hi >> (8*(3-(x)))): \ 248 ((eui)->lo >> (8*(7-(x)))) \ 249 ) & 0xff) 250 #define FW_EUI64_EQUAL(x, y) \ 251 ((x).hi == (y).hi && (x).lo == (y).lo) 252 253 struct fw_asyreq { 254 struct fw_asyreq_t{ 255 unsigned char sped; 256 unsigned int type; 257 #define FWASREQNODE 0 258 #define FWASREQEUI 1 259 #define FWASRESTL 2 260 #define FWASREQSTREAM 3 261 unsigned short len; 262 union { 263 struct fw_eui64 eui; 264 }dst; 265 }req; 266 struct fw_pkt pkt; 267 u_int32_t data[512]; 268 }; 269 270 struct fw_devinfo { 271 struct fw_eui64 eui; 272 u_int16_t dst; 273 u_int16_t status; 274 }; 275 276 #define FW_MAX_DEVLST 70 277 struct fw_devlstreq { 278 u_int16_t n; 279 u_int16_t info_len; 280 struct fw_devinfo dev[FW_MAX_DEVLST]; 281 }; 282 283 #define FW_SELF_ID_PORT_CONNECTED_TO_CHILD 3 284 #define FW_SELF_ID_PORT_CONNECTED_TO_PARENT 2 285 #define FW_SELF_ID_PORT_NOT_CONNECTED 1 286 #define FW_SELF_ID_PORT_NOT_EXISTS 0 287 #if BYTE_ORDER == BIG_ENDIAN 288 union fw_self_id { 289 struct { 290 u_int32_t id:2, 291 phy_id:6, 292 sequel:1, 293 link_active:1, 294 gap_count:6, 295 phy_speed:2, 296 phy_delay:2, 297 contender:1, 298 power_class:3, 299 port0:2, 300 port1:2, 301 port2:2, 302 initiated_reset:1, 303 more_packets:1; 304 } p0; 305 struct { 306 u_int32_t 307 id:2, 308 phy_id:6, 309 sequel:1, 310 sequence_num:3, 311 :2, 312 porta:2, 313 portb:2, 314 portc:2, 315 portd:2, 316 porte:2, 317 portf:2, 318 portg:2, 319 porth:2, 320 :1, 321 more_packets:1; 322 } p1; 323 }; 324 #else 325 union fw_self_id { 326 struct { 327 u_int32_t more_packets:1, 328 initiated_reset:1, 329 port2:2, 330 port1:2, 331 port0:2, 332 power_class:3, 333 contender:1, 334 phy_delay:2, 335 phy_speed:2, 336 gap_count:6, 337 link_active:1, 338 sequel:1, 339 phy_id:6, 340 id:2; 341 } p0; 342 struct { 343 u_int32_t more_packets:1, 344 reserved1:1, 345 porth:2, 346 portg:2, 347 portf:2, 348 porte:2, 349 portd:2, 350 portc:2, 351 portb:2, 352 porta:2, 353 reserved2:2, 354 sequence_num:3, 355 sequel:1, 356 phy_id:6, 357 id:2; 358 } p1; 359 }; 360 #endif 361 362 363 struct fw_topology_map { 364 u_int32_t crc:16, 365 crc_len:16; 366 u_int32_t generation; 367 u_int32_t self_id_count:16, 368 node_count:16; 369 union fw_self_id self_id[4*64]; 370 }; 371 372 struct fw_speed_map { 373 u_int32_t crc:16, 374 crc_len:16; 375 u_int32_t generation; 376 u_int8_t speed[64][64]; 377 }; 378 379 struct fw_crom_buf { 380 struct fw_eui64 eui; 381 int len; 382 void *ptr; 383 }; 384 385 /* 386 * FireWire specific system requests. 387 */ 388 #define FW_SSTBUF _IOWR('S', 86, struct fw_isobufreq) 389 #define FW_GSTBUF _IOWR('S', 87, struct fw_isobufreq) 390 #define FW_SRSTREAM _IOWR('S', 88, struct fw_isochreq) 391 #define FW_GRSTREAM _IOWR('S', 89, struct fw_isochreq) 392 #define FW_STSTREAM _IOWR('S', 90, struct fw_isochreq) 393 #define FW_GTSTREAM _IOWR('S', 91, struct fw_isochreq) 394 395 #define FW_ASYREQ _IOWR('S', 92, struct fw_asyreq) 396 #define FW_IBUSRST _IOR('S', 1, unsigned int) 397 #define FW_GDEVLST _IOWR('S', 2, struct fw_devlstreq) 398 #define FW_SBINDADDR _IOWR('S', 3, struct fw_asybindreq) 399 #define FW_CBINDADDR _IOWR('S', 4, struct fw_asybindreq) 400 #define FW_GTPMAP _IOR('S', 5, struct fw_topology_map) 401 #define FW_GCROM _IOWR('S', 7, struct fw_crom_buf) 402 403 #define FW_SDEUI64 _IOW('S', 20, struct fw_eui64) 404 #define FW_GDEUI64 _IOR('S', 21, struct fw_eui64) 405 406 #define FWOHCI_RDREG _IOWR('S', 80, struct fw_reg_req_t) 407 #define FWOHCI_WRREG _IOWR('S', 81, struct fw_reg_req_t) 408 #define FWOHCI_RDPHYREG _IOWR('S', 82, struct fw_reg_req_t) 409 #define FWOHCI_WRPHYREG _IOWR('S', 83, struct fw_reg_req_t) 410 411 #define DUMPDMA _IOWR('S', 82, u_int32_t) 412 413 #ifdef _KERNEL 414 415 #define FWMAXNDMA 0x100 /* 8 bits DMA channel id. in device No. */ 416 417 #if defined(__DragonFly__) || __FreeBSD_version < 500000 418 #define dev2unit(x) ((minor(x) & 0xff) | (minor(x) >> 8)) 419 #define unit2minor(x) (((x) & 0xff) | (((x) << 8) & ~0xffff)) 420 #endif 421 422 #define MAKEMINOR(f, u, s) \ 423 unit2minor((f) | (((u) & 0xff) << 8) | (s & 0xff)) 424 #define DEV2UNIT(x) ((dev2unit(x) & 0xff00) >> 8) 425 #define DEV2SUB(x) (dev2unit(x) & 0xff) 426 427 #define FW_UNITMASK MAKEMINOR(0, -1, 0) 428 #define FW_UNIT(unit) MAKEMINOR(0, unit, 0) 429 430 #define FWMEM_FLAG 0x10000 431 #define DEV_FWMEM(x) (dev2unit(x) & FWMEM_FLAG) 432 #endif 433 #endif 434