1 /* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.72 2004/01/22 14:41:17 simokawa Exp $ 35 * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.1.2.19 2003/05/01 06:24:37 simokawa Exp $ 36 * $DragonFly: src/sys/bus/firewire/fwohci.c,v 1.8 2004/06/02 14:42:48 eirikn Exp $ 37 */ 38 39 #define ATRQ_CH 0 40 #define ATRS_CH 1 41 #define ARRQ_CH 2 42 #define ARRS_CH 3 43 #define ITX_CH 4 44 #define IRX_CH 0x24 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/sockio.h> 51 #include <sys/bus.h> 52 #include <sys/kernel.h> 53 #include <sys/conf.h> 54 #include <sys/endian.h> 55 56 #include <machine/bus.h> 57 58 #if defined(__DragonFly__) || __FreeBSD_version < 500000 59 #include <machine/clock.h> /* for DELAY() */ 60 #endif 61 62 #ifdef __DragonFly__ 63 #include "firewire.h" 64 #include "firewirereg.h" 65 #include "fwdma.h" 66 #include "fwohcireg.h" 67 #include "fwohcivar.h" 68 #include "firewire_phy.h" 69 #else 70 #include <dev/firewire/firewire.h> 71 #include <dev/firewire/firewirereg.h> 72 #include <dev/firewire/fwdma.h> 73 #include <dev/firewire/fwohcireg.h> 74 #include <dev/firewire/fwohcivar.h> 75 #include <dev/firewire/firewire_phy.h> 76 #endif 77 78 #undef OHCI_DEBUG 79 80 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 81 "STOR","LOAD","NOP ","STOP",}; 82 83 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 84 "UNDEF","REG","SYS","DEV"}; 85 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 86 char fwohcicode[32][0x20]={ 87 "No stat","Undef","long","miss Ack err", 88 "underrun","overrun","desc err", "data read err", 89 "data write err","bus reset","timeout","tcode err", 90 "Undef","Undef","unknown event","flushed", 91 "Undef","ack complete","ack pend","Undef", 92 "ack busy_X","ack busy_A","ack busy_B","Undef", 93 "Undef","Undef","Undef","ack tardy", 94 "Undef","ack data_err","ack type_err",""}; 95 96 #define MAX_SPEED 3 97 extern char *linkspeed[]; 98 u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 99 100 static struct tcode_info tinfo[] = { 101 /* hdr_len block flag*/ 102 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 103 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 104 /* 2 WRES */ {12, FWTI_RES}, 105 /* 3 XXX */ { 0, 0}, 106 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 107 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 108 /* 6 RRESQ */ {16, FWTI_RES}, 109 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 110 /* 8 CYCS */ { 0, 0}, 111 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 112 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 113 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 114 /* c XXX */ { 0, 0}, 115 /* d XXX */ { 0, 0}, 116 /* e PHY */ {12, FWTI_REQ}, 117 /* f XXX */ { 0, 0} 118 }; 119 120 #define OHCI_WRITE_SIGMASK 0xffff0000 121 #define OHCI_READ_SIGMASK 0xffff0000 122 123 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 124 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 125 126 static void fwohci_ibr (struct firewire_comm *); 127 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 128 static void fwohci_db_free (struct fwohci_dbch *); 129 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 130 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 131 static void fwohci_start_atq (struct firewire_comm *); 132 static void fwohci_start_ats (struct firewire_comm *); 133 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 134 static u_int32_t fwphy_wrdata ( struct fwohci_softc *, u_int32_t, u_int32_t); 135 static u_int32_t fwphy_rddata ( struct fwohci_softc *, u_int32_t); 136 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 137 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 138 static int fwohci_irx_enable (struct firewire_comm *, int); 139 static int fwohci_irx_disable (struct firewire_comm *, int); 140 #if BYTE_ORDER == BIG_ENDIAN 141 static void fwohci_irx_post (struct firewire_comm *, u_int32_t *); 142 #endif 143 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 144 static int fwohci_itx_disable (struct firewire_comm *, int); 145 static void fwohci_timeout (void *); 146 static void fwohci_set_intr (struct firewire_comm *, int); 147 148 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 149 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 150 static void dump_db (struct fwohci_softc *, u_int32_t); 151 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, u_int32_t , u_int32_t); 152 static void dump_dma (struct fwohci_softc *, u_int32_t); 153 static u_int32_t fwohci_cyctimer (struct firewire_comm *); 154 static void fwohci_rbuf_update (struct fwohci_softc *, int); 155 static void fwohci_tbuf_update (struct fwohci_softc *, int); 156 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 157 #if FWOHCI_TASKQUEUE 158 static void fwohci_complete(void *, int); 159 #endif 160 161 /* 162 * memory allocated for DMA programs 163 */ 164 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165 166 #define NDB FWMAXQUEUE 167 168 #define OHCI_VERSION 0x00 169 #define OHCI_ATRETRY 0x08 170 #define OHCI_CROMHDR 0x18 171 #define OHCI_BUS_OPT 0x20 172 #define OHCI_BUSIRMC (1 << 31) 173 #define OHCI_BUSCMC (1 << 30) 174 #define OHCI_BUSISC (1 << 29) 175 #define OHCI_BUSBMC (1 << 28) 176 #define OHCI_BUSPMC (1 << 27) 177 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 178 OHCI_BUSBMC | OHCI_BUSPMC 179 180 #define OHCI_EUID_HI 0x24 181 #define OHCI_EUID_LO 0x28 182 183 #define OHCI_CROMPTR 0x34 184 #define OHCI_HCCCTL 0x50 185 #define OHCI_HCCCTLCLR 0x54 186 #define OHCI_AREQHI 0x100 187 #define OHCI_AREQHICLR 0x104 188 #define OHCI_AREQLO 0x108 189 #define OHCI_AREQLOCLR 0x10c 190 #define OHCI_PREQHI 0x110 191 #define OHCI_PREQHICLR 0x114 192 #define OHCI_PREQLO 0x118 193 #define OHCI_PREQLOCLR 0x11c 194 #define OHCI_PREQUPPER 0x120 195 196 #define OHCI_SID_BUF 0x64 197 #define OHCI_SID_CNT 0x68 198 #define OHCI_SID_ERR (1 << 31) 199 #define OHCI_SID_CNT_MASK 0xffc 200 201 #define OHCI_IT_STAT 0x90 202 #define OHCI_IT_STATCLR 0x94 203 #define OHCI_IT_MASK 0x98 204 #define OHCI_IT_MASKCLR 0x9c 205 206 #define OHCI_IR_STAT 0xa0 207 #define OHCI_IR_STATCLR 0xa4 208 #define OHCI_IR_MASK 0xa8 209 #define OHCI_IR_MASKCLR 0xac 210 211 #define OHCI_LNKCTL 0xe0 212 #define OHCI_LNKCTLCLR 0xe4 213 214 #define OHCI_PHYACCESS 0xec 215 #define OHCI_CYCLETIMER 0xf0 216 217 #define OHCI_DMACTL(off) (off) 218 #define OHCI_DMACTLCLR(off) (off + 4) 219 #define OHCI_DMACMD(off) (off + 0xc) 220 #define OHCI_DMAMATCH(off) (off + 0x10) 221 222 #define OHCI_ATQOFF 0x180 223 #define OHCI_ATQCTL OHCI_ATQOFF 224 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227 228 #define OHCI_ATSOFF 0x1a0 229 #define OHCI_ATSCTL OHCI_ATSOFF 230 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233 234 #define OHCI_ARQOFF 0x1c0 235 #define OHCI_ARQCTL OHCI_ARQOFF 236 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239 240 #define OHCI_ARSOFF 0x1e0 241 #define OHCI_ARSCTL OHCI_ARSOFF 242 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245 246 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250 251 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256 257 d_ioctl_t fwohci_ioctl; 258 259 /* 260 * Communication with PHY device 261 */ 262 static u_int32_t 263 fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264 { 265 u_int32_t fun; 266 267 addr &= 0xf; 268 data &= 0xff; 269 270 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271 OWRITE(sc, OHCI_PHYACCESS, fun); 272 DELAY(100); 273 274 return(fwphy_rddata( sc, addr)); 275 } 276 277 static u_int32_t 278 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279 { 280 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281 int i; 282 u_int32_t bm; 283 284 #define OHCI_CSR_DATA 0x0c 285 #define OHCI_CSR_COMP 0x10 286 #define OHCI_CSR_CONT 0x14 287 #define OHCI_BUS_MANAGER_ID 0 288 289 OWRITE(sc, OHCI_CSR_DATA, node); 290 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293 DELAY(10); 294 bm = OREAD(sc, OHCI_CSR_DATA); 295 if((bm & 0x3f) == 0x3f) 296 bm = node; 297 if (bootverbose) 298 device_printf(sc->fc.dev, 299 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 300 301 return(bm); 302 } 303 304 static u_int32_t 305 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 306 { 307 u_int32_t fun, stat; 308 u_int i, retry = 0; 309 310 addr &= 0xf; 311 #define MAX_RETRY 100 312 again: 313 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 314 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 315 OWRITE(sc, OHCI_PHYACCESS, fun); 316 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 317 fun = OREAD(sc, OHCI_PHYACCESS); 318 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 319 break; 320 DELAY(100); 321 } 322 if(i >= MAX_RETRY) { 323 if (bootverbose) 324 device_printf(sc->fc.dev, "phy read failed(1).\n"); 325 if (++retry < MAX_RETRY) { 326 DELAY(100); 327 goto again; 328 } 329 } 330 /* Make sure that SCLK is started */ 331 stat = OREAD(sc, FWOHCI_INTSTAT); 332 if ((stat & OHCI_INT_REG_FAIL) != 0 || 333 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 334 if (bootverbose) 335 device_printf(sc->fc.dev, "phy read failed(2).\n"); 336 if (++retry < MAX_RETRY) { 337 DELAY(100); 338 goto again; 339 } 340 } 341 if (bootverbose || retry >= MAX_RETRY) 342 device_printf(sc->fc.dev, 343 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 344 #undef MAX_RETRY 345 return((fun >> PHYDEV_RDDATA )& 0xff); 346 } 347 /* Device specific ioctl. */ 348 int 349 fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 350 { 351 struct firewire_softc *sc; 352 struct fwohci_softc *fc; 353 int unit = DEV2UNIT(dev); 354 int err = 0; 355 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 356 u_int32_t *dmach = (u_int32_t *) data; 357 358 sc = devclass_get_softc(firewire_devclass, unit); 359 if(sc == NULL){ 360 return(EINVAL); 361 } 362 fc = (struct fwohci_softc *)sc->fc; 363 364 if (!data) 365 return(EINVAL); 366 367 switch (cmd) { 368 case FWOHCI_WRREG: 369 #define OHCI_MAX_REG 0x800 370 if(reg->addr <= OHCI_MAX_REG){ 371 OWRITE(fc, reg->addr, reg->data); 372 reg->data = OREAD(fc, reg->addr); 373 }else{ 374 err = EINVAL; 375 } 376 break; 377 case FWOHCI_RDREG: 378 if(reg->addr <= OHCI_MAX_REG){ 379 reg->data = OREAD(fc, reg->addr); 380 }else{ 381 err = EINVAL; 382 } 383 break; 384 /* Read DMA descriptors for debug */ 385 case DUMPDMA: 386 if(*dmach <= OHCI_MAX_DMA_CH ){ 387 dump_dma(fc, *dmach); 388 dump_db(fc, *dmach); 389 }else{ 390 err = EINVAL; 391 } 392 break; 393 /* Read/Write Phy registers */ 394 #define OHCI_MAX_PHY_REG 0xf 395 case FWOHCI_RDPHYREG: 396 if (reg->addr <= OHCI_MAX_PHY_REG) 397 reg->data = fwphy_rddata(fc, reg->addr); 398 else 399 err = EINVAL; 400 break; 401 case FWOHCI_WRPHYREG: 402 if (reg->addr <= OHCI_MAX_PHY_REG) 403 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 404 else 405 err = EINVAL; 406 break; 407 default: 408 err = EINVAL; 409 break; 410 } 411 return err; 412 } 413 414 static int 415 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 416 { 417 u_int32_t reg, reg2; 418 int e1394a = 1; 419 /* 420 * probe PHY parameters 421 * 0. to prove PHY version, whether compliance of 1394a. 422 * 1. to probe maximum speed supported by the PHY and 423 * number of port supported by core-logic. 424 * It is not actually available port on your PC . 425 */ 426 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 427 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 428 429 if((reg >> 5) != 7 ){ 430 sc->fc.mode &= ~FWPHYASYST; 431 sc->fc.nport = reg & FW_PHY_NP; 432 sc->fc.speed = reg & FW_PHY_SPD >> 6; 433 if (sc->fc.speed > MAX_SPEED) { 434 device_printf(dev, "invalid speed %d (fixed to %d).\n", 435 sc->fc.speed, MAX_SPEED); 436 sc->fc.speed = MAX_SPEED; 437 } 438 device_printf(dev, 439 "Phy 1394 only %s, %d ports.\n", 440 linkspeed[sc->fc.speed], sc->fc.nport); 441 }else{ 442 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 443 sc->fc.mode |= FWPHYASYST; 444 sc->fc.nport = reg & FW_PHY_NP; 445 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 446 if (sc->fc.speed > MAX_SPEED) { 447 device_printf(dev, "invalid speed %d (fixed to %d).\n", 448 sc->fc.speed, MAX_SPEED); 449 sc->fc.speed = MAX_SPEED; 450 } 451 device_printf(dev, 452 "Phy 1394a available %s, %d ports.\n", 453 linkspeed[sc->fc.speed], sc->fc.nport); 454 455 /* check programPhyEnable */ 456 reg2 = fwphy_rddata(sc, 5); 457 #if 0 458 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 459 #else /* XXX force to enable 1394a */ 460 if (e1394a) { 461 #endif 462 if (bootverbose) 463 device_printf(dev, 464 "Enable 1394a Enhancements\n"); 465 /* enable EAA EMC */ 466 reg2 |= 0x03; 467 /* set aPhyEnhanceEnable */ 468 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 469 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 470 } else { 471 /* for safe */ 472 reg2 &= ~0x83; 473 } 474 reg2 = fwphy_wrdata(sc, 5, reg2); 475 } 476 477 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 478 if((reg >> 5) == 7 ){ 479 reg = fwphy_rddata(sc, 4); 480 reg |= 1 << 6; 481 fwphy_wrdata(sc, 4, reg); 482 reg = fwphy_rddata(sc, 4); 483 } 484 return 0; 485 } 486 487 488 void 489 fwohci_reset(struct fwohci_softc *sc, device_t dev) 490 { 491 int i, max_rec, speed; 492 u_int32_t reg, reg2; 493 struct fwohcidb_tr *db_tr; 494 495 /* Disable interrupt */ 496 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 497 498 /* Now stopping all DMA channel */ 499 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 500 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 501 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 502 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 503 504 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 505 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 506 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 507 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 508 } 509 510 /* FLUSH FIFO and reset Transmitter/Reciever */ 511 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 512 if (bootverbose) 513 device_printf(dev, "resetting OHCI..."); 514 i = 0; 515 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 516 if (i++ > 100) break; 517 DELAY(1000); 518 } 519 if (bootverbose) 520 printf("done (loop=%d)\n", i); 521 522 /* Probe phy */ 523 fwohci_probe_phy(sc, dev); 524 525 /* Probe link */ 526 reg = OREAD(sc, OHCI_BUS_OPT); 527 reg2 = reg | OHCI_BUSFNC; 528 max_rec = (reg & 0x0000f000) >> 12; 529 speed = (reg & 0x00000007); 530 device_printf(dev, "Link %s, max_rec %d bytes.\n", 531 linkspeed[speed], MAXREC(max_rec)); 532 /* XXX fix max_rec */ 533 sc->fc.maxrec = sc->fc.speed + 8; 534 if (max_rec != sc->fc.maxrec) { 535 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 536 device_printf(dev, "max_rec %d -> %d\n", 537 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 538 } 539 if (bootverbose) 540 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 541 OWRITE(sc, OHCI_BUS_OPT, reg2); 542 543 /* Initialize registers */ 544 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 545 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 546 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 547 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 548 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 549 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 550 551 /* Enable link */ 552 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 553 554 /* Force to start async RX DMA */ 555 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 556 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 557 fwohci_rx_enable(sc, &sc->arrq); 558 fwohci_rx_enable(sc, &sc->arrs); 559 560 /* Initialize async TX */ 561 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 562 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 563 564 /* AT Retries */ 565 OWRITE(sc, FWOHCI_RETRY, 566 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 567 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 568 569 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 570 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 571 sc->atrq.bottom = sc->atrq.top; 572 sc->atrs.bottom = sc->atrs.top; 573 574 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 575 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 576 db_tr->xfer = NULL; 577 } 578 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 579 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 580 db_tr->xfer = NULL; 581 } 582 583 584 /* Enable interrupt */ 585 OWRITE(sc, FWOHCI_INTMASK, 586 OHCI_INT_ERR | OHCI_INT_PHY_SID 587 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 588 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 589 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 590 fwohci_set_intr(&sc->fc, 1); 591 592 } 593 594 int 595 fwohci_init(struct fwohci_softc *sc, device_t dev) 596 { 597 int i, mver; 598 u_int32_t reg; 599 u_int8_t ui[8]; 600 601 #if FWOHCI_TASKQUEUE 602 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 603 #endif 604 605 /* OHCI version */ 606 reg = OREAD(sc, OHCI_VERSION); 607 mver = (reg >> 16) & 0xff; 608 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 609 mver, reg & 0xff, (reg>>24) & 1); 610 if (mver < 1 || mver > 9) { 611 device_printf(dev, "invalid OHCI version\n"); 612 return (ENXIO); 613 } 614 615 /* Available Isochrounous DMA channel probe */ 616 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 617 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 618 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 619 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 620 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 621 for (i = 0; i < 0x20; i++) 622 if ((reg & (1 << i)) == 0) 623 break; 624 sc->fc.nisodma = i; 625 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 626 if (i == 0) 627 return (ENXIO); 628 629 sc->fc.arq = &sc->arrq.xferq; 630 sc->fc.ars = &sc->arrs.xferq; 631 sc->fc.atq = &sc->atrq.xferq; 632 sc->fc.ats = &sc->atrs.xferq; 633 634 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 635 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 636 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 637 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 638 639 sc->arrq.xferq.start = NULL; 640 sc->arrs.xferq.start = NULL; 641 sc->atrq.xferq.start = fwohci_start_atq; 642 sc->atrs.xferq.start = fwohci_start_ats; 643 644 sc->arrq.xferq.buf = NULL; 645 sc->arrs.xferq.buf = NULL; 646 sc->atrq.xferq.buf = NULL; 647 sc->atrs.xferq.buf = NULL; 648 649 sc->arrq.xferq.dmach = -1; 650 sc->arrs.xferq.dmach = -1; 651 sc->atrq.xferq.dmach = -1; 652 sc->atrs.xferq.dmach = -1; 653 654 sc->arrq.ndesc = 1; 655 sc->arrs.ndesc = 1; 656 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 657 sc->atrs.ndesc = 2; 658 659 sc->arrq.ndb = NDB; 660 sc->arrs.ndb = NDB / 2; 661 sc->atrq.ndb = NDB; 662 sc->atrs.ndb = NDB / 2; 663 664 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 665 sc->fc.it[i] = &sc->it[i].xferq; 666 sc->fc.ir[i] = &sc->ir[i].xferq; 667 sc->it[i].xferq.dmach = i; 668 sc->ir[i].xferq.dmach = i; 669 sc->it[i].ndb = 0; 670 sc->ir[i].ndb = 0; 671 } 672 673 sc->fc.tcode = tinfo; 674 sc->fc.dev = dev; 675 676 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 677 &sc->crom_dma, BUS_DMA_WAITOK); 678 if(sc->fc.config_rom == NULL){ 679 device_printf(dev, "config_rom alloc failed."); 680 return ENOMEM; 681 } 682 683 #if 0 684 bzero(&sc->fc.config_rom[0], CROMSIZE); 685 sc->fc.config_rom[1] = 0x31333934; 686 sc->fc.config_rom[2] = 0xf000a002; 687 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 688 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 689 sc->fc.config_rom[5] = 0; 690 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 691 692 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 693 #endif 694 695 696 /* SID recieve buffer must allign 2^11 */ 697 #define OHCI_SIDSIZE (1 << 11) 698 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 699 &sc->sid_dma, BUS_DMA_WAITOK); 700 if (sc->sid_buf == NULL) { 701 device_printf(dev, "sid_buf alloc failed."); 702 return ENOMEM; 703 } 704 705 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 706 &sc->dummy_dma, BUS_DMA_WAITOK); 707 708 if (sc->dummy_dma.v_addr == NULL) { 709 device_printf(dev, "dummy_dma alloc failed."); 710 return ENOMEM; 711 } 712 713 fwohci_db_init(sc, &sc->arrq); 714 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 715 return ENOMEM; 716 717 fwohci_db_init(sc, &sc->arrs); 718 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 719 return ENOMEM; 720 721 fwohci_db_init(sc, &sc->atrq); 722 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 723 return ENOMEM; 724 725 fwohci_db_init(sc, &sc->atrs); 726 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 727 return ENOMEM; 728 729 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 730 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 731 for( i = 0 ; i < 8 ; i ++) 732 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 733 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 734 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 735 736 sc->fc.ioctl = fwohci_ioctl; 737 sc->fc.cyctimer = fwohci_cyctimer; 738 sc->fc.set_bmr = fwohci_set_bus_manager; 739 sc->fc.ibr = fwohci_ibr; 740 sc->fc.irx_enable = fwohci_irx_enable; 741 sc->fc.irx_disable = fwohci_irx_disable; 742 743 sc->fc.itx_enable = fwohci_itxbuf_enable; 744 sc->fc.itx_disable = fwohci_itx_disable; 745 #if BYTE_ORDER == BIG_ENDIAN 746 sc->fc.irx_post = fwohci_irx_post; 747 #else 748 sc->fc.irx_post = NULL; 749 #endif 750 sc->fc.itx_post = NULL; 751 sc->fc.timeout = fwohci_timeout; 752 sc->fc.poll = fwohci_poll; 753 sc->fc.set_intr = fwohci_set_intr; 754 755 sc->intmask = sc->irstat = sc->itstat = 0; 756 757 fw_init(&sc->fc); 758 fwohci_reset(sc, dev); 759 760 return 0; 761 } 762 763 void 764 fwohci_timeout(void *arg) 765 { 766 struct fwohci_softc *sc; 767 768 sc = (struct fwohci_softc *)arg; 769 } 770 771 u_int32_t 772 fwohci_cyctimer(struct firewire_comm *fc) 773 { 774 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 775 return(OREAD(sc, OHCI_CYCLETIMER)); 776 } 777 778 int 779 fwohci_detach(struct fwohci_softc *sc, device_t dev) 780 { 781 int i; 782 783 if (sc->sid_buf != NULL) 784 fwdma_free(&sc->fc, &sc->sid_dma); 785 if (sc->fc.config_rom != NULL) 786 fwdma_free(&sc->fc, &sc->crom_dma); 787 788 fwohci_db_free(&sc->arrq); 789 fwohci_db_free(&sc->arrs); 790 791 fwohci_db_free(&sc->atrq); 792 fwohci_db_free(&sc->atrs); 793 794 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 795 fwohci_db_free(&sc->it[i]); 796 fwohci_db_free(&sc->ir[i]); 797 } 798 799 return 0; 800 } 801 802 #define LAST_DB(dbtr, db) do { \ 803 struct fwohcidb_tr *_dbtr = (dbtr); \ 804 int _cnt = _dbtr->dbcnt; \ 805 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 806 } while (0) 807 808 static void 809 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 810 { 811 struct fwohcidb_tr *db_tr; 812 struct fwohcidb *db; 813 bus_dma_segment_t *s; 814 int i; 815 816 db_tr = (struct fwohcidb_tr *)arg; 817 db = &db_tr->db[db_tr->dbcnt]; 818 if (error) { 819 if (firewire_debug || error != EFBIG) 820 printf("fwohci_execute_db: error=%d\n", error); 821 return; 822 } 823 for (i = 0; i < nseg; i++) { 824 s = &segs[i]; 825 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 826 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 827 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 828 db++; 829 db_tr->dbcnt++; 830 } 831 } 832 833 static void 834 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 835 bus_size_t size, int error) 836 { 837 fwohci_execute_db(arg, segs, nseg, error); 838 } 839 840 static void 841 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 842 { 843 int i, s; 844 int tcode, hdr_len, pl_off; 845 int fsegment = -1; 846 u_int32_t off; 847 struct fw_xfer *xfer; 848 struct fw_pkt *fp; 849 struct fwohci_txpkthdr *ohcifp; 850 struct fwohcidb_tr *db_tr; 851 struct fwohcidb *db; 852 u_int32_t *ld; 853 struct tcode_info *info; 854 static int maxdesc=0; 855 856 if(&sc->atrq == dbch){ 857 off = OHCI_ATQOFF; 858 }else if(&sc->atrs == dbch){ 859 off = OHCI_ATSOFF; 860 }else{ 861 return; 862 } 863 864 if (dbch->flags & FWOHCI_DBCH_FULL) 865 return; 866 867 s = splfw(); 868 db_tr = dbch->top; 869 txloop: 870 xfer = STAILQ_FIRST(&dbch->xferq.q); 871 if(xfer == NULL){ 872 goto kick; 873 } 874 if(dbch->xferq.queued == 0 ){ 875 device_printf(sc->fc.dev, "TX queue empty\n"); 876 } 877 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 878 db_tr->xfer = xfer; 879 xfer->state = FWXF_START; 880 881 fp = &xfer->send.hdr; 882 tcode = fp->mode.common.tcode; 883 884 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 885 info = &tinfo[tcode]; 886 hdr_len = pl_off = info->hdr_len; 887 888 ld = &ohcifp->mode.ld[0]; 889 ld[0] = ld[1] = ld[2] = ld[3] = 0; 890 for( i = 0 ; i < pl_off ; i+= 4) 891 ld[i/4] = fp->mode.ld[i/4]; 892 893 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 894 if (tcode == FWTCODE_STREAM ){ 895 hdr_len = 8; 896 ohcifp->mode.stream.len = fp->mode.stream.len; 897 } else if (tcode == FWTCODE_PHY) { 898 hdr_len = 12; 899 ld[1] = fp->mode.ld[1]; 900 ld[2] = fp->mode.ld[2]; 901 ohcifp->mode.common.spd = 0; 902 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 903 } else { 904 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 905 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 906 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 907 } 908 db = &db_tr->db[0]; 909 FWOHCI_DMA_WRITE(db->db.desc.cmd, 910 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 911 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 912 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 913 /* Specify bound timer of asy. responce */ 914 if(&sc->atrs == dbch){ 915 FWOHCI_DMA_WRITE(db->db.desc.res, 916 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 917 } 918 #if BYTE_ORDER == BIG_ENDIAN 919 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 920 hdr_len = 12; 921 for (i = 0; i < hdr_len/4; i ++) 922 FWOHCI_DMA_WRITE(ld[i], ld[i]); 923 #endif 924 925 again: 926 db_tr->dbcnt = 2; 927 db = &db_tr->db[db_tr->dbcnt]; 928 if (xfer->send.pay_len > 0) { 929 int err; 930 /* handle payload */ 931 if (xfer->mbuf == NULL) { 932 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 933 &xfer->send.payload[0], xfer->send.pay_len, 934 fwohci_execute_db, db_tr, 935 /*flags*/0); 936 } else { 937 /* XXX we can handle only 6 (=8-2) mbuf chains */ 938 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 939 xfer->mbuf, 940 fwohci_execute_db2, db_tr, 941 /* flags */0); 942 if (err == EFBIG) { 943 struct mbuf *m0; 944 945 if (firewire_debug) 946 device_printf(sc->fc.dev, "EFBIG.\n"); 947 m0 = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 948 if (m0 != NULL) { 949 m_copydata(xfer->mbuf, 0, 950 xfer->mbuf->m_pkthdr.len, 951 mtod(m0, caddr_t)); 952 m0->m_len = m0->m_pkthdr.len = 953 xfer->mbuf->m_pkthdr.len; 954 m_freem(xfer->mbuf); 955 xfer->mbuf = m0; 956 goto again; 957 } 958 device_printf(sc->fc.dev, "m_getcl failed.\n"); 959 } 960 } 961 if (err) 962 printf("dmamap_load: err=%d\n", err); 963 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 964 BUS_DMASYNC_PREWRITE); 965 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 966 for (i = 2; i < db_tr->dbcnt; i++) 967 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 968 OHCI_OUTPUT_MORE); 969 #endif 970 } 971 if (maxdesc < db_tr->dbcnt) { 972 maxdesc = db_tr->dbcnt; 973 if (bootverbose) 974 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 975 } 976 /* last db */ 977 LAST_DB(db_tr, db); 978 FWOHCI_DMA_SET(db->db.desc.cmd, 979 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 980 FWOHCI_DMA_WRITE(db->db.desc.depend, 981 STAILQ_NEXT(db_tr, link)->bus_addr); 982 983 if(fsegment == -1 ) 984 fsegment = db_tr->dbcnt; 985 if (dbch->pdb_tr != NULL) { 986 LAST_DB(dbch->pdb_tr, db); 987 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 988 } 989 dbch->pdb_tr = db_tr; 990 db_tr = STAILQ_NEXT(db_tr, link); 991 if(db_tr != dbch->bottom){ 992 goto txloop; 993 } else { 994 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 995 dbch->flags |= FWOHCI_DBCH_FULL; 996 } 997 kick: 998 /* kick asy q */ 999 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1000 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1001 1002 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1003 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1004 } else { 1005 if (bootverbose) 1006 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1007 OREAD(sc, OHCI_DMACTL(off))); 1008 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1009 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1010 dbch->xferq.flag |= FWXFERQ_RUNNING; 1011 } 1012 1013 dbch->top = db_tr; 1014 splx(s); 1015 return; 1016 } 1017 1018 static void 1019 fwohci_start_atq(struct firewire_comm *fc) 1020 { 1021 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1022 fwohci_start( sc, &(sc->atrq)); 1023 return; 1024 } 1025 1026 static void 1027 fwohci_start_ats(struct firewire_comm *fc) 1028 { 1029 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1030 fwohci_start( sc, &(sc->atrs)); 1031 return; 1032 } 1033 1034 void 1035 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1036 { 1037 int s, ch, err = 0; 1038 struct fwohcidb_tr *tr; 1039 struct fwohcidb *db; 1040 struct fw_xfer *xfer; 1041 u_int32_t off; 1042 u_int stat, status; 1043 int packets; 1044 struct firewire_comm *fc = (struct firewire_comm *)sc; 1045 1046 if(&sc->atrq == dbch){ 1047 off = OHCI_ATQOFF; 1048 ch = ATRQ_CH; 1049 }else if(&sc->atrs == dbch){ 1050 off = OHCI_ATSOFF; 1051 ch = ATRS_CH; 1052 }else{ 1053 return; 1054 } 1055 s = splfw(); 1056 tr = dbch->bottom; 1057 packets = 0; 1058 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1059 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1060 while(dbch->xferq.queued > 0){ 1061 LAST_DB(tr, db); 1062 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1063 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1064 if (fc->status != FWBUSRESET) 1065 /* maybe out of order?? */ 1066 goto out; 1067 } 1068 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1069 BUS_DMASYNC_POSTWRITE); 1070 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1071 #if 1 1072 if (firewire_debug) 1073 dump_db(sc, ch); 1074 #endif 1075 if(status & OHCI_CNTL_DMA_DEAD) { 1076 /* Stop DMA */ 1077 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1078 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1079 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1080 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1081 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1082 } 1083 stat = status & FWOHCIEV_MASK; 1084 switch(stat){ 1085 case FWOHCIEV_ACKPEND: 1086 case FWOHCIEV_ACKCOMPL: 1087 err = 0; 1088 break; 1089 case FWOHCIEV_ACKBSA: 1090 case FWOHCIEV_ACKBSB: 1091 case FWOHCIEV_ACKBSX: 1092 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1093 err = EBUSY; 1094 break; 1095 case FWOHCIEV_FLUSHED: 1096 case FWOHCIEV_ACKTARD: 1097 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1098 err = EAGAIN; 1099 break; 1100 case FWOHCIEV_MISSACK: 1101 case FWOHCIEV_UNDRRUN: 1102 case FWOHCIEV_OVRRUN: 1103 case FWOHCIEV_DESCERR: 1104 case FWOHCIEV_DTRDERR: 1105 case FWOHCIEV_TIMEOUT: 1106 case FWOHCIEV_TCODERR: 1107 case FWOHCIEV_UNKNOWN: 1108 case FWOHCIEV_ACKDERR: 1109 case FWOHCIEV_ACKTERR: 1110 default: 1111 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1112 stat, fwohcicode[stat]); 1113 err = EINVAL; 1114 break; 1115 } 1116 if (tr->xfer != NULL) { 1117 xfer = tr->xfer; 1118 if (xfer->state == FWXF_RCVD) { 1119 #if 0 1120 if (firewire_debug) 1121 printf("already rcvd\n"); 1122 #endif 1123 fw_xfer_done(xfer); 1124 } else { 1125 xfer->state = FWXF_SENT; 1126 if (err == EBUSY && fc->status != FWBUSRESET) { 1127 xfer->state = FWXF_BUSY; 1128 xfer->resp = err; 1129 if (xfer->retry_req != NULL) 1130 xfer->retry_req(xfer); 1131 else { 1132 xfer->recv.pay_len = 0; 1133 fw_xfer_done(xfer); 1134 } 1135 } else if (stat != FWOHCIEV_ACKPEND) { 1136 if (stat != FWOHCIEV_ACKCOMPL) 1137 xfer->state = FWXF_SENTERR; 1138 xfer->resp = err; 1139 xfer->recv.pay_len = 0; 1140 fw_xfer_done(xfer); 1141 } 1142 } 1143 /* 1144 * The watchdog timer takes care of split 1145 * transcation timeout for ACKPEND case. 1146 */ 1147 } else { 1148 printf("this shouldn't happen\n"); 1149 } 1150 dbch->xferq.queued --; 1151 tr->xfer = NULL; 1152 1153 packets ++; 1154 tr = STAILQ_NEXT(tr, link); 1155 dbch->bottom = tr; 1156 if (dbch->bottom == dbch->top) { 1157 /* we reaches the end of context program */ 1158 if (firewire_debug && dbch->xferq.queued > 0) 1159 printf("queued > 0\n"); 1160 break; 1161 } 1162 } 1163 out: 1164 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1165 printf("make free slot\n"); 1166 dbch->flags &= ~FWOHCI_DBCH_FULL; 1167 fwohci_start(sc, dbch); 1168 } 1169 splx(s); 1170 } 1171 1172 static void 1173 fwohci_db_free(struct fwohci_dbch *dbch) 1174 { 1175 struct fwohcidb_tr *db_tr; 1176 int idb; 1177 1178 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1179 return; 1180 1181 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1182 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1183 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1184 db_tr->buf != NULL) { 1185 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1186 db_tr->buf, dbch->xferq.psize); 1187 db_tr->buf = NULL; 1188 } else if (db_tr->dma_map != NULL) 1189 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1190 } 1191 dbch->ndb = 0; 1192 db_tr = STAILQ_FIRST(&dbch->db_trq); 1193 fwdma_free_multiseg(dbch->am); 1194 free(db_tr, M_FW); 1195 STAILQ_INIT(&dbch->db_trq); 1196 dbch->flags &= ~FWOHCI_DBCH_INIT; 1197 } 1198 1199 static void 1200 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1201 { 1202 int idb; 1203 struct fwohcidb_tr *db_tr; 1204 1205 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1206 goto out; 1207 1208 /* create dma_tag for buffers */ 1209 #define MAX_REQCOUNT 0xffff 1210 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1211 /*alignment*/ 1, /*boundary*/ 0, 1212 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1213 /*highaddr*/ BUS_SPACE_MAXADDR, 1214 /*filter*/NULL, /*filterarg*/NULL, 1215 /*maxsize*/ dbch->xferq.psize, 1216 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1217 /*maxsegsz*/ MAX_REQCOUNT, 1218 /*flags*/ 0, 1219 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1220 /*lockfunc*/busdma_lock_mutex, 1221 /*lockarg*/&Giant, 1222 #endif 1223 &dbch->dmat)) 1224 return; 1225 1226 /* allocate DB entries and attach one to each DMA channels */ 1227 /* DB entry must start at 16 bytes bounary. */ 1228 STAILQ_INIT(&dbch->db_trq); 1229 db_tr = (struct fwohcidb_tr *) 1230 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1231 M_FW, M_WAITOK | M_ZERO); 1232 if(db_tr == NULL){ 1233 printf("fwohci_db_init: malloc(1) failed\n"); 1234 return; 1235 } 1236 1237 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1238 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1239 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1240 if (dbch->am == NULL) { 1241 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1242 free(db_tr, M_FW); 1243 return; 1244 } 1245 /* Attach DB to DMA ch. */ 1246 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1247 db_tr->dbcnt = 0; 1248 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1249 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1250 /* create dmamap for buffers */ 1251 /* XXX do we need 4bytes alignment tag? */ 1252 /* XXX don't alloc dma_map for AR */ 1253 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1254 printf("bus_dmamap_create failed\n"); 1255 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1256 fwohci_db_free(dbch); 1257 return; 1258 } 1259 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1260 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1261 if (idb % dbch->xferq.bnpacket == 0) 1262 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1263 ].start = (caddr_t)db_tr; 1264 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1265 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1266 ].end = (caddr_t)db_tr; 1267 } 1268 db_tr++; 1269 } 1270 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1271 = STAILQ_FIRST(&dbch->db_trq); 1272 out: 1273 dbch->xferq.queued = 0; 1274 dbch->pdb_tr = NULL; 1275 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1276 dbch->bottom = dbch->top; 1277 dbch->flags = FWOHCI_DBCH_INIT; 1278 } 1279 1280 static int 1281 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1282 { 1283 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1284 int sleepch; 1285 1286 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1287 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1288 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1289 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1290 /* XXX we cannot free buffers until the DMA really stops */ 1291 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1292 fwohci_db_free(&sc->it[dmach]); 1293 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1294 return 0; 1295 } 1296 1297 static int 1298 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1299 { 1300 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1301 int sleepch; 1302 1303 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1304 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1305 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1306 /* XXX we cannot free buffers until the DMA really stops */ 1307 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1308 fwohci_db_free(&sc->ir[dmach]); 1309 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1310 return 0; 1311 } 1312 1313 #if BYTE_ORDER == BIG_ENDIAN 1314 static void 1315 fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1316 { 1317 qld[0] = FWOHCI_DMA_READ(qld[0]); 1318 return; 1319 } 1320 #endif 1321 1322 static int 1323 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1324 { 1325 int err = 0; 1326 int idb, z, i, dmach = 0, ldesc; 1327 u_int32_t off = 0; 1328 struct fwohcidb_tr *db_tr; 1329 struct fwohcidb *db; 1330 1331 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1332 err = EINVAL; 1333 return err; 1334 } 1335 z = dbch->ndesc; 1336 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1337 if( &sc->it[dmach] == dbch){ 1338 off = OHCI_ITOFF(dmach); 1339 break; 1340 } 1341 } 1342 if(off == 0){ 1343 err = EINVAL; 1344 return err; 1345 } 1346 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1347 return err; 1348 dbch->xferq.flag |= FWXFERQ_RUNNING; 1349 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1350 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1351 } 1352 db_tr = dbch->top; 1353 for (idb = 0; idb < dbch->ndb; idb ++) { 1354 fwohci_add_tx_buf(dbch, db_tr, idb); 1355 if(STAILQ_NEXT(db_tr, link) == NULL){ 1356 break; 1357 } 1358 db = db_tr->db; 1359 ldesc = db_tr->dbcnt - 1; 1360 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1361 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1362 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1363 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1364 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1365 FWOHCI_DMA_SET( 1366 db[ldesc].db.desc.cmd, 1367 OHCI_INTERRUPT_ALWAYS); 1368 /* OHCI 1.1 and above */ 1369 FWOHCI_DMA_SET( 1370 db[0].db.desc.cmd, 1371 OHCI_INTERRUPT_ALWAYS); 1372 } 1373 } 1374 db_tr = STAILQ_NEXT(db_tr, link); 1375 } 1376 FWOHCI_DMA_CLEAR( 1377 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1378 return err; 1379 } 1380 1381 static int 1382 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1383 { 1384 int err = 0; 1385 int idb, z, i, dmach = 0, ldesc; 1386 u_int32_t off = 0; 1387 struct fwohcidb_tr *db_tr; 1388 struct fwohcidb *db; 1389 1390 z = dbch->ndesc; 1391 if(&sc->arrq == dbch){ 1392 off = OHCI_ARQOFF; 1393 }else if(&sc->arrs == dbch){ 1394 off = OHCI_ARSOFF; 1395 }else{ 1396 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1397 if( &sc->ir[dmach] == dbch){ 1398 off = OHCI_IROFF(dmach); 1399 break; 1400 } 1401 } 1402 } 1403 if(off == 0){ 1404 err = EINVAL; 1405 return err; 1406 } 1407 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1408 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1409 return err; 1410 }else{ 1411 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1412 err = EBUSY; 1413 return err; 1414 } 1415 } 1416 dbch->xferq.flag |= FWXFERQ_RUNNING; 1417 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1418 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1419 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1420 } 1421 db_tr = dbch->top; 1422 for (idb = 0; idb < dbch->ndb; idb ++) { 1423 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1424 if (STAILQ_NEXT(db_tr, link) == NULL) 1425 break; 1426 db = db_tr->db; 1427 ldesc = db_tr->dbcnt - 1; 1428 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1429 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1430 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1431 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1432 FWOHCI_DMA_SET( 1433 db[ldesc].db.desc.cmd, 1434 OHCI_INTERRUPT_ALWAYS); 1435 FWOHCI_DMA_CLEAR( 1436 db[ldesc].db.desc.depend, 1437 0xf); 1438 } 1439 } 1440 db_tr = STAILQ_NEXT(db_tr, link); 1441 } 1442 FWOHCI_DMA_CLEAR( 1443 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1444 dbch->buf_offset = 0; 1445 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1446 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1447 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1448 return err; 1449 }else{ 1450 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1451 } 1452 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1453 return err; 1454 } 1455 1456 static int 1457 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1458 { 1459 int sec, cycle, cycle_match; 1460 1461 cycle = cycle_now & 0x1fff; 1462 sec = cycle_now >> 13; 1463 #define CYCLE_MOD 0x10 1464 #if 1 1465 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1466 #else 1467 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1468 #endif 1469 cycle = cycle + CYCLE_DELAY; 1470 if (cycle >= 8000) { 1471 sec ++; 1472 cycle -= 8000; 1473 } 1474 cycle = roundup2(cycle, CYCLE_MOD); 1475 if (cycle >= 8000) { 1476 sec ++; 1477 if (cycle == 8000) 1478 cycle = 0; 1479 else 1480 cycle = CYCLE_MOD; 1481 } 1482 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1483 1484 return(cycle_match); 1485 } 1486 1487 static int 1488 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1489 { 1490 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1491 int err = 0; 1492 unsigned short tag, ich; 1493 struct fwohci_dbch *dbch; 1494 int cycle_match, cycle_now, s, ldesc; 1495 u_int32_t stat; 1496 struct fw_bulkxfer *first, *chunk, *prev; 1497 struct fw_xferq *it; 1498 1499 dbch = &sc->it[dmach]; 1500 it = &dbch->xferq; 1501 1502 tag = (it->flag >> 6) & 3; 1503 ich = it->flag & 0x3f; 1504 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1505 dbch->ndb = it->bnpacket * it->bnchunk; 1506 dbch->ndesc = 3; 1507 fwohci_db_init(sc, dbch); 1508 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1509 return ENOMEM; 1510 err = fwohci_tx_enable(sc, dbch); 1511 } 1512 if(err) 1513 return err; 1514 1515 ldesc = dbch->ndesc - 1; 1516 s = splfw(); 1517 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1518 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1519 struct fwohcidb *db; 1520 1521 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1522 BUS_DMASYNC_PREWRITE); 1523 fwohci_txbufdb(sc, dmach, chunk); 1524 if (prev != NULL) { 1525 db = ((struct fwohcidb_tr *)(prev->end))->db; 1526 #if 0 /* XXX necessary? */ 1527 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1528 OHCI_BRANCH_ALWAYS); 1529 #endif 1530 #if 0 /* if bulkxfer->npacket changes */ 1531 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1532 ((struct fwohcidb_tr *) 1533 (chunk->start))->bus_addr | dbch->ndesc; 1534 #else 1535 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1536 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1537 #endif 1538 } 1539 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1540 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1541 prev = chunk; 1542 } 1543 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1544 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1545 splx(s); 1546 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1547 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1548 printf("stat 0x%x\n", stat); 1549 1550 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1551 return 0; 1552 1553 #if 0 1554 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1555 #endif 1556 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1557 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1558 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1559 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1560 1561 first = STAILQ_FIRST(&it->stdma); 1562 OWRITE(sc, OHCI_ITCMD(dmach), 1563 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1564 if (firewire_debug) { 1565 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1566 #if 1 1567 dump_dma(sc, ITX_CH + dmach); 1568 #endif 1569 } 1570 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1571 #if 1 1572 /* Don't start until all chunks are buffered */ 1573 if (STAILQ_FIRST(&it->stfree) != NULL) 1574 goto out; 1575 #endif 1576 #if 1 1577 /* Clear cycle match counter bits */ 1578 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1579 1580 /* 2bit second + 13bit cycle */ 1581 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1582 cycle_match = fwohci_next_cycle(fc, cycle_now); 1583 1584 OWRITE(sc, OHCI_ITCTL(dmach), 1585 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1586 | OHCI_CNTL_DMA_RUN); 1587 #else 1588 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1589 #endif 1590 if (firewire_debug) { 1591 printf("cycle_match: 0x%04x->0x%04x\n", 1592 cycle_now, cycle_match); 1593 dump_dma(sc, ITX_CH + dmach); 1594 dump_db(sc, ITX_CH + dmach); 1595 } 1596 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1597 device_printf(sc->fc.dev, 1598 "IT DMA underrun (0x%08x)\n", stat); 1599 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1600 } 1601 out: 1602 return err; 1603 } 1604 1605 static int 1606 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1607 { 1608 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1609 int err = 0, s, ldesc; 1610 unsigned short tag, ich; 1611 u_int32_t stat; 1612 struct fwohci_dbch *dbch; 1613 struct fwohcidb_tr *db_tr; 1614 struct fw_bulkxfer *first, *prev, *chunk; 1615 struct fw_xferq *ir; 1616 1617 dbch = &sc->ir[dmach]; 1618 ir = &dbch->xferq; 1619 1620 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1621 tag = (ir->flag >> 6) & 3; 1622 ich = ir->flag & 0x3f; 1623 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1624 1625 ir->queued = 0; 1626 dbch->ndb = ir->bnpacket * ir->bnchunk; 1627 dbch->ndesc = 2; 1628 fwohci_db_init(sc, dbch); 1629 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1630 return ENOMEM; 1631 err = fwohci_rx_enable(sc, dbch); 1632 } 1633 if(err) 1634 return err; 1635 1636 first = STAILQ_FIRST(&ir->stfree); 1637 if (first == NULL) { 1638 device_printf(fc->dev, "IR DMA no free chunk\n"); 1639 return 0; 1640 } 1641 1642 ldesc = dbch->ndesc - 1; 1643 s = splfw(); 1644 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1645 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1646 struct fwohcidb *db; 1647 1648 #if 1 /* XXX for if_fwe */ 1649 if (chunk->mbuf != NULL) { 1650 db_tr = (struct fwohcidb_tr *)(chunk->start); 1651 db_tr->dbcnt = 1; 1652 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1653 chunk->mbuf, fwohci_execute_db2, db_tr, 1654 /* flags */0); 1655 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1656 OHCI_UPDATE | OHCI_INPUT_LAST | 1657 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1658 } 1659 #endif 1660 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1661 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1662 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1663 if (prev != NULL) { 1664 db = ((struct fwohcidb_tr *)(prev->end))->db; 1665 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1666 } 1667 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1668 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1669 prev = chunk; 1670 } 1671 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1672 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1673 splx(s); 1674 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1675 if (stat & OHCI_CNTL_DMA_ACTIVE) 1676 return 0; 1677 if (stat & OHCI_CNTL_DMA_RUN) { 1678 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1679 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1680 } 1681 1682 if (firewire_debug) 1683 printf("start IR DMA 0x%x\n", stat); 1684 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1685 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1686 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1687 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1688 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1689 OWRITE(sc, OHCI_IRCMD(dmach), 1690 ((struct fwohcidb_tr *)(first->start))->bus_addr 1691 | dbch->ndesc); 1692 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1693 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1694 #if 0 1695 dump_db(sc, IRX_CH + dmach); 1696 #endif 1697 return err; 1698 } 1699 1700 int 1701 fwohci_stop(struct fwohci_softc *sc, device_t dev) 1702 { 1703 u_int i; 1704 1705 /* Now stopping all DMA channel */ 1706 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1707 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1708 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1709 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1710 1711 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1712 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1713 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1714 } 1715 1716 /* FLUSH FIFO and reset Transmitter/Reciever */ 1717 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1718 1719 /* Stop interrupt */ 1720 OWRITE(sc, FWOHCI_INTMASKCLR, 1721 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1722 | OHCI_INT_PHY_INT 1723 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1724 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1725 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1726 | OHCI_INT_PHY_BUS_R); 1727 1728 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1729 fw_drain_txq(&sc->fc); 1730 1731 /* XXX Link down? Bus reset? */ 1732 return 0; 1733 } 1734 1735 int 1736 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1737 { 1738 int i; 1739 struct fw_xferq *ir; 1740 struct fw_bulkxfer *chunk; 1741 1742 fwohci_reset(sc, dev); 1743 /* XXX resume isochronus receive automatically. (how about TX?) */ 1744 for(i = 0; i < sc->fc.nisodma; i ++) { 1745 ir = &sc->ir[i].xferq; 1746 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1747 device_printf(sc->fc.dev, 1748 "resume iso receive ch: %d\n", i); 1749 ir->flag &= ~FWXFERQ_RUNNING; 1750 /* requeue stdma to stfree */ 1751 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1752 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1753 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1754 } 1755 sc->fc.irx_enable(&sc->fc, i); 1756 } 1757 } 1758 1759 bus_generic_resume(dev); 1760 sc->fc.ibr(&sc->fc); 1761 return 0; 1762 } 1763 1764 #define ACK_ALL 1765 static void 1766 fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1767 { 1768 u_int32_t irstat, itstat; 1769 u_int i; 1770 struct firewire_comm *fc = (struct firewire_comm *)sc; 1771 1772 #ifdef OHCI_DEBUG 1773 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1774 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1775 stat & OHCI_INT_EN ? "DMA_EN ":"", 1776 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1777 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1778 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1779 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1780 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1781 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1782 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1783 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1784 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1785 stat & OHCI_INT_PHY_SID ? "SID ":"", 1786 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1787 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1788 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1789 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1790 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1791 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1792 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1793 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1794 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1795 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1796 stat, OREAD(sc, FWOHCI_INTMASK) 1797 ); 1798 #endif 1799 /* Bus reset */ 1800 if(stat & OHCI_INT_PHY_BUS_R ){ 1801 if (fc->status == FWBUSRESET) 1802 goto busresetout; 1803 /* Disable bus reset interrupt until sid recv. */ 1804 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1805 1806 device_printf(fc->dev, "BUS reset\n"); 1807 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1808 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1809 1810 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1811 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1812 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1813 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1814 1815 #ifndef ACK_ALL 1816 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1817 #endif 1818 fw_busreset(fc); 1819 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1820 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1821 } 1822 busresetout: 1823 if((stat & OHCI_INT_DMA_IR )){ 1824 #ifndef ACK_ALL 1825 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1826 #endif 1827 #if defined(__DragonFly__) || __FreeBSD_version < 500000 1828 irstat = sc->irstat; 1829 sc->irstat = 0; 1830 #else 1831 irstat = atomic_readandclear_int(&sc->irstat); 1832 #endif 1833 for(i = 0; i < fc->nisodma ; i++){ 1834 struct fwohci_dbch *dbch; 1835 1836 if((irstat & (1 << i)) != 0){ 1837 dbch = &sc->ir[i]; 1838 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1839 device_printf(sc->fc.dev, 1840 "dma(%d) not active\n", i); 1841 continue; 1842 } 1843 fwohci_rbuf_update(sc, i); 1844 } 1845 } 1846 } 1847 if((stat & OHCI_INT_DMA_IT )){ 1848 #ifndef ACK_ALL 1849 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1850 #endif 1851 #if defined(__DragonFly__) || __FreeBSD_version < 500000 1852 itstat = sc->itstat; 1853 sc->itstat = 0; 1854 #else 1855 itstat = atomic_readandclear_int(&sc->itstat); 1856 #endif 1857 for(i = 0; i < fc->nisodma ; i++){ 1858 if((itstat & (1 << i)) != 0){ 1859 fwohci_tbuf_update(sc, i); 1860 } 1861 } 1862 } 1863 if((stat & OHCI_INT_DMA_PRRS )){ 1864 #ifndef ACK_ALL 1865 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1866 #endif 1867 #if 0 1868 dump_dma(sc, ARRS_CH); 1869 dump_db(sc, ARRS_CH); 1870 #endif 1871 fwohci_arcv(sc, &sc->arrs, count); 1872 } 1873 if((stat & OHCI_INT_DMA_PRRQ )){ 1874 #ifndef ACK_ALL 1875 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1876 #endif 1877 #if 0 1878 dump_dma(sc, ARRQ_CH); 1879 dump_db(sc, ARRQ_CH); 1880 #endif 1881 fwohci_arcv(sc, &sc->arrq, count); 1882 } 1883 if(stat & OHCI_INT_PHY_SID){ 1884 u_int32_t *buf, node_id; 1885 int plen; 1886 1887 #ifndef ACK_ALL 1888 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1889 #endif 1890 /* Enable bus reset interrupt */ 1891 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1892 /* Allow async. request to us */ 1893 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1894 /* XXX insecure ?? */ 1895 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1896 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1897 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1898 /* Set ATRetries register */ 1899 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1900 /* 1901 ** Checking whether the node is root or not. If root, turn on 1902 ** cycle master. 1903 */ 1904 node_id = OREAD(sc, FWOHCI_NODEID); 1905 plen = OREAD(sc, OHCI_SID_CNT); 1906 1907 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1908 node_id, (plen >> 16) & 0xff); 1909 if (!(node_id & OHCI_NODE_VALID)) { 1910 printf("Bus reset failure\n"); 1911 goto sidout; 1912 } 1913 if (node_id & OHCI_NODE_ROOT) { 1914 printf("CYCLEMASTER mode\n"); 1915 OWRITE(sc, OHCI_LNKCTL, 1916 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1917 } else { 1918 printf("non CYCLEMASTER mode\n"); 1919 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1920 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1921 } 1922 fc->nodeid = node_id & 0x3f; 1923 1924 if (plen & OHCI_SID_ERR) { 1925 device_printf(fc->dev, "SID Error\n"); 1926 goto sidout; 1927 } 1928 plen &= OHCI_SID_CNT_MASK; 1929 if (plen < 4 || plen > OHCI_SIDSIZE) { 1930 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1931 goto sidout; 1932 } 1933 plen -= 4; /* chop control info */ 1934 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_INTWAIT); 1935 if (buf == NULL) { 1936 device_printf(fc->dev, "malloc failed\n"); 1937 goto sidout; 1938 } 1939 for (i = 0; i < plen / 4; i ++) 1940 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1941 #if 1 1942 /* pending all pre-bus_reset packets */ 1943 fwohci_txd(sc, &sc->atrq); 1944 fwohci_txd(sc, &sc->atrs); 1945 fwohci_arcv(sc, &sc->arrs, -1); 1946 fwohci_arcv(sc, &sc->arrq, -1); 1947 fw_drain_txq(fc); 1948 #endif 1949 fw_sidrcv(fc, buf, plen); 1950 free(buf, M_FW); 1951 } 1952 sidout: 1953 if((stat & OHCI_INT_DMA_ATRQ )){ 1954 #ifndef ACK_ALL 1955 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1956 #endif 1957 fwohci_txd(sc, &(sc->atrq)); 1958 } 1959 if((stat & OHCI_INT_DMA_ATRS )){ 1960 #ifndef ACK_ALL 1961 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1962 #endif 1963 fwohci_txd(sc, &(sc->atrs)); 1964 } 1965 if((stat & OHCI_INT_PW_ERR )){ 1966 #ifndef ACK_ALL 1967 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1968 #endif 1969 device_printf(fc->dev, "posted write error\n"); 1970 } 1971 if((stat & OHCI_INT_ERR )){ 1972 #ifndef ACK_ALL 1973 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1974 #endif 1975 device_printf(fc->dev, "unrecoverable error\n"); 1976 } 1977 if((stat & OHCI_INT_PHY_INT)) { 1978 #ifndef ACK_ALL 1979 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1980 #endif 1981 device_printf(fc->dev, "phy int\n"); 1982 } 1983 1984 return; 1985 } 1986 1987 #if FWOHCI_TASKQUEUE 1988 static void 1989 fwohci_complete(void *arg, int pending) 1990 { 1991 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1992 u_int32_t stat; 1993 1994 again: 1995 stat = atomic_readandclear_int(&sc->intstat); 1996 if (stat) 1997 fwohci_intr_body(sc, stat, -1); 1998 else 1999 return; 2000 goto again; 2001 } 2002 #endif 2003 2004 static u_int32_t 2005 fwochi_check_stat(struct fwohci_softc *sc) 2006 { 2007 u_int32_t stat, irstat, itstat; 2008 2009 stat = OREAD(sc, FWOHCI_INTSTAT); 2010 if (stat == 0xffffffff) { 2011 device_printf(sc->fc.dev, 2012 "device physically ejected?\n"); 2013 return(stat); 2014 } 2015 #ifdef ACK_ALL 2016 if (stat) 2017 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2018 #endif 2019 if (stat & OHCI_INT_DMA_IR) { 2020 irstat = OREAD(sc, OHCI_IR_STAT); 2021 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2022 atomic_set_int(&sc->irstat, irstat); 2023 } 2024 if (stat & OHCI_INT_DMA_IT) { 2025 itstat = OREAD(sc, OHCI_IT_STAT); 2026 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2027 atomic_set_int(&sc->itstat, itstat); 2028 } 2029 return(stat); 2030 } 2031 2032 void 2033 fwohci_intr(void *arg) 2034 { 2035 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2036 u_int32_t stat; 2037 #if !FWOHCI_TASKQUEUE 2038 u_int32_t bus_reset = 0; 2039 #endif 2040 2041 if (!(sc->intmask & OHCI_INT_EN)) { 2042 /* polling mode */ 2043 return; 2044 } 2045 2046 #if !FWOHCI_TASKQUEUE 2047 again: 2048 #endif 2049 stat = fwochi_check_stat(sc); 2050 if (stat == 0 || stat == 0xffffffff) 2051 return; 2052 #if FWOHCI_TASKQUEUE 2053 atomic_set_int(&sc->intstat, stat); 2054 /* XXX mask bus reset intr. during bus reset phase */ 2055 if (stat) 2056 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2057 #else 2058 /* We cannot clear bus reset event during bus reset phase */ 2059 if ((stat & ~bus_reset) == 0) 2060 return; 2061 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2062 fwohci_intr_body(sc, stat, -1); 2063 goto again; 2064 #endif 2065 } 2066 2067 void 2068 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2069 { 2070 int s; 2071 u_int32_t stat; 2072 struct fwohci_softc *sc; 2073 2074 2075 sc = (struct fwohci_softc *)fc; 2076 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2077 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2078 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2079 #if 0 2080 if (!quick) { 2081 #else 2082 if (1) { 2083 #endif 2084 stat = fwochi_check_stat(sc); 2085 if (stat == 0 || stat == 0xffffffff) 2086 return; 2087 } 2088 s = splfw(); 2089 fwohci_intr_body(sc, stat, count); 2090 splx(s); 2091 } 2092 2093 static void 2094 fwohci_set_intr(struct firewire_comm *fc, int enable) 2095 { 2096 struct fwohci_softc *sc; 2097 2098 sc = (struct fwohci_softc *)fc; 2099 if (bootverbose) 2100 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2101 if (enable) { 2102 sc->intmask |= OHCI_INT_EN; 2103 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2104 } else { 2105 sc->intmask &= ~OHCI_INT_EN; 2106 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2107 } 2108 } 2109 2110 static void 2111 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2112 { 2113 struct firewire_comm *fc = &sc->fc; 2114 struct fwohcidb *db; 2115 struct fw_bulkxfer *chunk; 2116 struct fw_xferq *it; 2117 u_int32_t stat, count; 2118 int s, w=0, ldesc; 2119 2120 it = fc->it[dmach]; 2121 ldesc = sc->it[dmach].ndesc - 1; 2122 s = splfw(); /* unnecessary ? */ 2123 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2124 if (firewire_debug) 2125 dump_db(sc, ITX_CH + dmach); 2126 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2127 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2128 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2129 >> OHCI_STATUS_SHIFT; 2130 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2131 /* timestamp */ 2132 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2133 & OHCI_COUNT_MASK; 2134 if (stat == 0) 2135 break; 2136 STAILQ_REMOVE_HEAD(&it->stdma, link); 2137 switch (stat & FWOHCIEV_MASK){ 2138 case FWOHCIEV_ACKCOMPL: 2139 #if 0 2140 device_printf(fc->dev, "0x%08x\n", count); 2141 #endif 2142 break; 2143 default: 2144 device_printf(fc->dev, 2145 "Isochronous transmit err %02x(%s)\n", 2146 stat, fwohcicode[stat & 0x1f]); 2147 } 2148 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2149 w++; 2150 } 2151 splx(s); 2152 if (w) 2153 wakeup(it); 2154 } 2155 2156 static void 2157 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2158 { 2159 struct firewire_comm *fc = &sc->fc; 2160 struct fwohcidb_tr *db_tr; 2161 struct fw_bulkxfer *chunk; 2162 struct fw_xferq *ir; 2163 u_int32_t stat; 2164 int s, w=0, ldesc; 2165 2166 ir = fc->ir[dmach]; 2167 ldesc = sc->ir[dmach].ndesc - 1; 2168 #if 0 2169 dump_db(sc, dmach); 2170 #endif 2171 s = splfw(); 2172 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2173 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2174 db_tr = (struct fwohcidb_tr *)chunk->end; 2175 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2176 >> OHCI_STATUS_SHIFT; 2177 if (stat == 0) 2178 break; 2179 2180 if (chunk->mbuf != NULL) { 2181 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2182 BUS_DMASYNC_POSTREAD); 2183 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2184 } else if (ir->buf != NULL) { 2185 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2186 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2187 } else { 2188 /* XXX */ 2189 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2190 } 2191 2192 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2193 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2194 switch (stat & FWOHCIEV_MASK) { 2195 case FWOHCIEV_ACKCOMPL: 2196 chunk->resp = 0; 2197 break; 2198 default: 2199 chunk->resp = EINVAL; 2200 device_printf(fc->dev, 2201 "Isochronous receive err %02x(%s)\n", 2202 stat, fwohcicode[stat & 0x1f]); 2203 } 2204 w++; 2205 } 2206 splx(s); 2207 if (w) { 2208 if (ir->flag & FWXFERQ_HANDLER) 2209 ir->hand(ir); 2210 else 2211 wakeup(ir); 2212 } 2213 } 2214 2215 void 2216 dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2217 { 2218 u_int32_t off, cntl, stat, cmd, match; 2219 2220 if(ch == 0){ 2221 off = OHCI_ATQOFF; 2222 }else if(ch == 1){ 2223 off = OHCI_ATSOFF; 2224 }else if(ch == 2){ 2225 off = OHCI_ARQOFF; 2226 }else if(ch == 3){ 2227 off = OHCI_ARSOFF; 2228 }else if(ch < IRX_CH){ 2229 off = OHCI_ITCTL(ch - ITX_CH); 2230 }else{ 2231 off = OHCI_IRCTL(ch - IRX_CH); 2232 } 2233 cntl = stat = OREAD(sc, off); 2234 cmd = OREAD(sc, off + 0xc); 2235 match = OREAD(sc, off + 0x10); 2236 2237 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2238 ch, 2239 cntl, 2240 cmd, 2241 match); 2242 stat &= 0xffff ; 2243 if (stat) { 2244 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2245 ch, 2246 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2247 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2248 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2249 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2250 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2251 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2252 fwohcicode[stat & 0x1f], 2253 stat & 0x1f 2254 ); 2255 }else{ 2256 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2257 } 2258 } 2259 2260 void 2261 dump_db(struct fwohci_softc *sc, u_int32_t ch) 2262 { 2263 struct fwohci_dbch *dbch; 2264 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2265 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2266 int idb, jdb; 2267 u_int32_t cmd, off; 2268 if(ch == 0){ 2269 off = OHCI_ATQOFF; 2270 dbch = &sc->atrq; 2271 }else if(ch == 1){ 2272 off = OHCI_ATSOFF; 2273 dbch = &sc->atrs; 2274 }else if(ch == 2){ 2275 off = OHCI_ARQOFF; 2276 dbch = &sc->arrq; 2277 }else if(ch == 3){ 2278 off = OHCI_ARSOFF; 2279 dbch = &sc->arrs; 2280 }else if(ch < IRX_CH){ 2281 off = OHCI_ITCTL(ch - ITX_CH); 2282 dbch = &sc->it[ch - ITX_CH]; 2283 }else { 2284 off = OHCI_IRCTL(ch - IRX_CH); 2285 dbch = &sc->ir[ch - IRX_CH]; 2286 } 2287 cmd = OREAD(sc, off + 0xc); 2288 2289 if( dbch->ndb == 0 ){ 2290 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2291 return; 2292 } 2293 pp = dbch->top; 2294 prev = pp->db; 2295 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2296 if(pp == NULL){ 2297 curr = NULL; 2298 goto outdb; 2299 } 2300 cp = STAILQ_NEXT(pp, link); 2301 if(cp == NULL){ 2302 curr = NULL; 2303 goto outdb; 2304 } 2305 np = STAILQ_NEXT(cp, link); 2306 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2307 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2308 curr = cp->db; 2309 if(np != NULL){ 2310 next = np->db; 2311 }else{ 2312 next = NULL; 2313 } 2314 goto outdb; 2315 } 2316 } 2317 pp = STAILQ_NEXT(pp, link); 2318 prev = pp->db; 2319 } 2320 outdb: 2321 if( curr != NULL){ 2322 #if 0 2323 printf("Prev DB %d\n", ch); 2324 print_db(pp, prev, ch, dbch->ndesc); 2325 #endif 2326 printf("Current DB %d\n", ch); 2327 print_db(cp, curr, ch, dbch->ndesc); 2328 #if 0 2329 printf("Next DB %d\n", ch); 2330 print_db(np, next, ch, dbch->ndesc); 2331 #endif 2332 }else{ 2333 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2334 } 2335 return; 2336 } 2337 2338 void 2339 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2340 u_int32_t ch, u_int32_t max) 2341 { 2342 fwohcireg_t stat; 2343 int i, key; 2344 u_int32_t cmd, res; 2345 2346 if(db == NULL){ 2347 printf("No Descriptor is found\n"); 2348 return; 2349 } 2350 2351 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2352 ch, 2353 "Current", 2354 "OP ", 2355 "KEY", 2356 "INT", 2357 "BR ", 2358 "len", 2359 "Addr", 2360 "Depend", 2361 "Stat", 2362 "Cnt"); 2363 for( i = 0 ; i <= max ; i ++){ 2364 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2365 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2366 key = cmd & OHCI_KEY_MASK; 2367 stat = res >> OHCI_STATUS_SHIFT; 2368 #if defined(__DragonFly__) || __FreeBSD_version < 500000 2369 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2370 db_tr->bus_addr, 2371 #else 2372 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2373 (uintmax_t)db_tr->bus_addr, 2374 #endif 2375 dbcode[(cmd >> 28) & 0xf], 2376 dbkey[(cmd >> 24) & 0x7], 2377 dbcond[(cmd >> 20) & 0x3], 2378 dbcond[(cmd >> 18) & 0x3], 2379 cmd & OHCI_COUNT_MASK, 2380 FWOHCI_DMA_READ(db[i].db.desc.addr), 2381 FWOHCI_DMA_READ(db[i].db.desc.depend), 2382 stat, 2383 res & OHCI_COUNT_MASK); 2384 if(stat & 0xff00){ 2385 printf(" %s%s%s%s%s%s %s(%x)\n", 2386 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2387 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2388 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2389 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2390 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2391 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2392 fwohcicode[stat & 0x1f], 2393 stat & 0x1f 2394 ); 2395 }else{ 2396 printf(" Nostat\n"); 2397 } 2398 if(key == OHCI_KEY_ST2 ){ 2399 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2400 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2401 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2402 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2403 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2404 } 2405 if(key == OHCI_KEY_DEVICE){ 2406 return; 2407 } 2408 if((cmd & OHCI_BRANCH_MASK) 2409 == OHCI_BRANCH_ALWAYS){ 2410 return; 2411 } 2412 if((cmd & OHCI_CMD_MASK) 2413 == OHCI_OUTPUT_LAST){ 2414 return; 2415 } 2416 if((cmd & OHCI_CMD_MASK) 2417 == OHCI_INPUT_LAST){ 2418 return; 2419 } 2420 if(key == OHCI_KEY_ST2 ){ 2421 i++; 2422 } 2423 } 2424 return; 2425 } 2426 2427 void 2428 fwohci_ibr(struct firewire_comm *fc) 2429 { 2430 struct fwohci_softc *sc; 2431 u_int32_t fun; 2432 2433 device_printf(fc->dev, "Initiate bus reset\n"); 2434 sc = (struct fwohci_softc *)fc; 2435 2436 /* 2437 * Set root hold-off bit so that non cyclemaster capable node 2438 * shouldn't became the root node. 2439 */ 2440 #if 1 2441 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2442 fun |= FW_PHY_IBR | FW_PHY_RHB; 2443 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2444 #else /* Short bus reset */ 2445 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2446 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2447 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2448 #endif 2449 } 2450 2451 void 2452 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2453 { 2454 struct fwohcidb_tr *db_tr, *fdb_tr; 2455 struct fwohci_dbch *dbch; 2456 struct fwohcidb *db; 2457 struct fw_pkt *fp; 2458 struct fwohci_txpkthdr *ohcifp; 2459 unsigned short chtag; 2460 int idb; 2461 2462 dbch = &sc->it[dmach]; 2463 chtag = sc->it[dmach].xferq.flag & 0xff; 2464 2465 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2466 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2467 /* 2468 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2469 */ 2470 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2471 db = db_tr->db; 2472 fp = (struct fw_pkt *)db_tr->buf; 2473 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2474 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2475 ohcifp->mode.common.spd = 0 & 0x7; 2476 ohcifp->mode.stream.len = fp->mode.stream.len; 2477 ohcifp->mode.stream.chtag = chtag; 2478 ohcifp->mode.stream.tcode = 0xa; 2479 #if BYTE_ORDER == BIG_ENDIAN 2480 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2481 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2482 #endif 2483 2484 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2485 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2486 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2487 #if 0 /* if bulkxfer->npackets changes */ 2488 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2489 | OHCI_UPDATE 2490 | OHCI_BRANCH_ALWAYS; 2491 db[0].db.desc.depend = 2492 = db[dbch->ndesc - 1].db.desc.depend 2493 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2494 #else 2495 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2496 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2497 #endif 2498 bulkxfer->end = (caddr_t)db_tr; 2499 db_tr = STAILQ_NEXT(db_tr, link); 2500 } 2501 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2502 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2503 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2504 #if 0 /* if bulkxfer->npackets changes */ 2505 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2506 /* OHCI 1.1 and above */ 2507 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2508 #endif 2509 /* 2510 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2511 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2512 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2513 */ 2514 return; 2515 } 2516 2517 static int 2518 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2519 int poffset) 2520 { 2521 struct fwohcidb *db = db_tr->db; 2522 struct fw_xferq *it; 2523 int err = 0; 2524 2525 it = &dbch->xferq; 2526 if(it->buf == 0){ 2527 err = EINVAL; 2528 return err; 2529 } 2530 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2531 db_tr->dbcnt = 3; 2532 2533 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2534 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2535 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2536 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2537 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2538 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2539 2540 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2541 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2542 #if 1 2543 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2544 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2545 #endif 2546 return 0; 2547 } 2548 2549 int 2550 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2551 int poffset, struct fwdma_alloc *dummy_dma) 2552 { 2553 struct fwohcidb *db = db_tr->db; 2554 struct fw_xferq *ir; 2555 int i, ldesc; 2556 bus_addr_t dbuf[2]; 2557 int dsiz[2]; 2558 2559 ir = &dbch->xferq; 2560 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2561 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2562 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2563 if (db_tr->buf == NULL) 2564 return(ENOMEM); 2565 db_tr->dbcnt = 1; 2566 dsiz[0] = ir->psize; 2567 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2568 BUS_DMASYNC_PREREAD); 2569 } else { 2570 db_tr->dbcnt = 0; 2571 if (dummy_dma != NULL) { 2572 dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2573 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2574 } 2575 dsiz[db_tr->dbcnt] = ir->psize; 2576 if (ir->buf != NULL) { 2577 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2578 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2579 } 2580 db_tr->dbcnt++; 2581 } 2582 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2583 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2584 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2585 if (ir->flag & FWXFERQ_STREAM) { 2586 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2587 } 2588 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2589 } 2590 ldesc = db_tr->dbcnt - 1; 2591 if (ir->flag & FWXFERQ_STREAM) { 2592 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2593 } 2594 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2595 return 0; 2596 } 2597 2598 2599 static int 2600 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2601 { 2602 struct fw_pkt *fp0; 2603 u_int32_t ld0; 2604 int slen, hlen; 2605 #if BYTE_ORDER == BIG_ENDIAN 2606 int i; 2607 #endif 2608 2609 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2610 #if 0 2611 printf("ld0: x%08x\n", ld0); 2612 #endif 2613 fp0 = (struct fw_pkt *)&ld0; 2614 /* determine length to swap */ 2615 switch (fp0->mode.common.tcode) { 2616 case FWTCODE_RREQQ: 2617 case FWTCODE_WRES: 2618 case FWTCODE_WREQQ: 2619 case FWTCODE_RRESQ: 2620 case FWOHCITCODE_PHY: 2621 slen = 12; 2622 break; 2623 case FWTCODE_RREQB: 2624 case FWTCODE_WREQB: 2625 case FWTCODE_LREQ: 2626 case FWTCODE_RRESB: 2627 case FWTCODE_LRES: 2628 slen = 16; 2629 break; 2630 default: 2631 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2632 return(0); 2633 } 2634 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2635 if (hlen > len) { 2636 if (firewire_debug) 2637 printf("splitted header\n"); 2638 return(-hlen); 2639 } 2640 #if BYTE_ORDER == BIG_ENDIAN 2641 for(i = 0; i < slen/4; i ++) 2642 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2643 #endif 2644 return(hlen); 2645 } 2646 2647 static int 2648 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2649 { 2650 struct tcode_info *info; 2651 int r; 2652 2653 info = &tinfo[fp->mode.common.tcode]; 2654 r = info->hdr_len + sizeof(u_int32_t); 2655 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2656 r += roundup2(fp->mode.wreqb.len, sizeof(u_int32_t)); 2657 2658 if (r == sizeof(u_int32_t)) 2659 /* XXX */ 2660 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2661 fp->mode.common.tcode); 2662 2663 if (r > dbch->xferq.psize) { 2664 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2665 /* panic ? */ 2666 } 2667 2668 return r; 2669 } 2670 2671 static void 2672 fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2673 { 2674 struct fwohcidb *db = &db_tr->db[0]; 2675 2676 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2677 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2678 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2679 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2680 dbch->bottom = db_tr; 2681 } 2682 2683 static void 2684 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2685 { 2686 struct fwohcidb_tr *db_tr; 2687 struct iovec vec[2]; 2688 struct fw_pkt pktbuf; 2689 int nvec; 2690 struct fw_pkt *fp; 2691 u_int8_t *ld; 2692 u_int32_t stat, off, status; 2693 u_int spd; 2694 int len, plen, hlen, pcnt, offset; 2695 int s; 2696 caddr_t buf; 2697 int resCount; 2698 2699 if(&sc->arrq == dbch){ 2700 off = OHCI_ARQOFF; 2701 }else if(&sc->arrs == dbch){ 2702 off = OHCI_ARSOFF; 2703 }else{ 2704 return; 2705 } 2706 2707 s = splfw(); 2708 db_tr = dbch->top; 2709 pcnt = 0; 2710 /* XXX we cannot handle a packet which lies in more than two buf */ 2711 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2712 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2713 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2714 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2715 #if 0 2716 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2717 #endif 2718 while (status & OHCI_CNTL_DMA_ACTIVE) { 2719 len = dbch->xferq.psize - resCount; 2720 ld = (u_int8_t *)db_tr->buf; 2721 if (dbch->pdb_tr == NULL) { 2722 len -= dbch->buf_offset; 2723 ld += dbch->buf_offset; 2724 } 2725 if (len > 0) 2726 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2727 BUS_DMASYNC_POSTREAD); 2728 while (len > 0 ) { 2729 if (count >= 0 && count-- == 0) 2730 goto out; 2731 if(dbch->pdb_tr != NULL){ 2732 /* we have a fragment in previous buffer */ 2733 int rlen; 2734 2735 offset = dbch->buf_offset; 2736 if (offset < 0) 2737 offset = - offset; 2738 buf = dbch->pdb_tr->buf + offset; 2739 rlen = dbch->xferq.psize - offset; 2740 if (firewire_debug) 2741 printf("rlen=%d, offset=%d\n", 2742 rlen, dbch->buf_offset); 2743 if (dbch->buf_offset < 0) { 2744 /* splitted in header, pull up */ 2745 char *p; 2746 2747 p = (char *)&pktbuf; 2748 bcopy(buf, p, rlen); 2749 p += rlen; 2750 /* this must be too long but harmless */ 2751 rlen = sizeof(pktbuf) - rlen; 2752 if (rlen < 0) 2753 printf("why rlen < 0\n"); 2754 bcopy(db_tr->buf, p, rlen); 2755 ld += rlen; 2756 len -= rlen; 2757 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2758 if (hlen < 0) { 2759 printf("hlen < 0 shouldn't happen"); 2760 } 2761 offset = sizeof(pktbuf); 2762 vec[0].iov_base = (char *)&pktbuf; 2763 vec[0].iov_len = offset; 2764 } else { 2765 /* splitted in payload */ 2766 offset = rlen; 2767 vec[0].iov_base = buf; 2768 vec[0].iov_len = rlen; 2769 } 2770 fp=(struct fw_pkt *)vec[0].iov_base; 2771 nvec = 1; 2772 } else { 2773 /* no fragment in previous buffer */ 2774 fp=(struct fw_pkt *)ld; 2775 hlen = fwohci_arcv_swap(fp, len); 2776 if (hlen == 0) 2777 /* XXX need reset */ 2778 goto out; 2779 if (hlen < 0) { 2780 dbch->pdb_tr = db_tr; 2781 dbch->buf_offset = - dbch->buf_offset; 2782 /* sanity check */ 2783 if (resCount != 0) 2784 printf("resCount = %d !?\n", 2785 resCount); 2786 /* XXX clear pdb_tr */ 2787 goto out; 2788 } 2789 offset = 0; 2790 nvec = 0; 2791 } 2792 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2793 if (plen < 0) { 2794 /* minimum header size + trailer 2795 = sizeof(fw_pkt) so this shouldn't happens */ 2796 printf("plen(%d) is negative! offset=%d\n", 2797 plen, offset); 2798 /* XXX clear pdb_tr */ 2799 goto out; 2800 } 2801 if (plen > 0) { 2802 len -= plen; 2803 if (len < 0) { 2804 dbch->pdb_tr = db_tr; 2805 if (firewire_debug) 2806 printf("splitted payload\n"); 2807 /* sanity check */ 2808 if (resCount != 0) 2809 printf("resCount = %d !?\n", 2810 resCount); 2811 /* XXX clear pdb_tr */ 2812 goto out; 2813 } 2814 vec[nvec].iov_base = ld; 2815 vec[nvec].iov_len = plen; 2816 nvec ++; 2817 ld += plen; 2818 } 2819 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2820 if (nvec == 0) 2821 printf("nvec == 0\n"); 2822 2823 /* DMA result-code will be written at the tail of packet */ 2824 #if BYTE_ORDER == BIG_ENDIAN 2825 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2826 #else 2827 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2828 #endif 2829 #if 0 2830 printf("plen: %d, stat %x\n", 2831 plen ,stat); 2832 #endif 2833 spd = (stat >> 5) & 0x3; 2834 stat &= 0x1f; 2835 switch(stat){ 2836 case FWOHCIEV_ACKPEND: 2837 #if 0 2838 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2839 #endif 2840 /* fall through */ 2841 case FWOHCIEV_ACKCOMPL: 2842 { 2843 struct fw_rcv_buf rb; 2844 2845 if ((vec[nvec-1].iov_len -= 2846 sizeof(struct fwohci_trailer)) == 0) 2847 nvec--; 2848 rb.fc = &sc->fc; 2849 rb.vec = vec; 2850 rb.nvec = nvec; 2851 rb.spd = spd; 2852 fw_rcv(&rb); 2853 break; 2854 } 2855 case FWOHCIEV_BUSRST: 2856 if (sc->fc.status != FWBUSRESET) 2857 printf("got BUSRST packet!?\n"); 2858 break; 2859 default: 2860 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2861 #if 0 /* XXX */ 2862 goto out; 2863 #endif 2864 break; 2865 } 2866 pcnt ++; 2867 if (dbch->pdb_tr != NULL) { 2868 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2869 dbch->pdb_tr = NULL; 2870 } 2871 2872 } 2873 out: 2874 if (resCount == 0) { 2875 /* done on this buffer */ 2876 if (dbch->pdb_tr == NULL) { 2877 fwohci_arcv_free_buf(dbch, db_tr); 2878 dbch->buf_offset = 0; 2879 } else 2880 if (dbch->pdb_tr != db_tr) 2881 printf("pdb_tr != db_tr\n"); 2882 db_tr = STAILQ_NEXT(db_tr, link); 2883 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2884 >> OHCI_STATUS_SHIFT; 2885 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2886 & OHCI_COUNT_MASK; 2887 /* XXX check buffer overrun */ 2888 dbch->top = db_tr; 2889 } else { 2890 dbch->buf_offset = dbch->xferq.psize - resCount; 2891 break; 2892 } 2893 /* XXX make sure DMA is not dead */ 2894 } 2895 #if 0 2896 if (pcnt < 1) 2897 printf("fwohci_arcv: no packets\n"); 2898 #endif 2899 splx(s); 2900 } 2901