1 /* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.72 2004/01/22 14:41:17 simokawa Exp $ 35 * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.1.2.19 2003/05/01 06:24:37 simokawa Exp $ 36 * $DragonFly: src/sys/bus/firewire/fwohci.c,v 1.15 2006/12/22 23:12:16 swildner Exp $ 37 */ 38 39 #define ATRQ_CH 0 40 #define ATRS_CH 1 41 #define ARRQ_CH 2 42 #define ARRS_CH 3 43 #define ITX_CH 4 44 #define IRX_CH 0x24 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/sockio.h> 51 #include <sys/bus.h> 52 #include <sys/kernel.h> 53 #include <sys/conf.h> 54 #include <sys/device.h> 55 #include <sys/endian.h> 56 57 #include <sys/thread2.h> 58 59 #if defined(__DragonFly__) || __FreeBSD_version < 500000 60 #include <machine/clock.h> /* for DELAY() */ 61 #endif 62 63 #ifdef __DragonFly__ 64 #include "firewire.h" 65 #include "firewirereg.h" 66 #include "fwdma.h" 67 #include "fwohcireg.h" 68 #include "fwohcivar.h" 69 #include "firewire_phy.h" 70 #else 71 #include <dev/firewire/firewire.h> 72 #include <dev/firewire/firewirereg.h> 73 #include <dev/firewire/fwdma.h> 74 #include <dev/firewire/fwohcireg.h> 75 #include <dev/firewire/fwohcivar.h> 76 #include <dev/firewire/firewire_phy.h> 77 #endif 78 79 #undef OHCI_DEBUG 80 81 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 82 "STOR","LOAD","NOP ","STOP",}; 83 84 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 85 "UNDEF","REG","SYS","DEV"}; 86 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 87 char fwohcicode[32][0x20]={ 88 "No stat","Undef","long","miss Ack err", 89 "underrun","overrun","desc err", "data read err", 90 "data write err","bus reset","timeout","tcode err", 91 "Undef","Undef","unknown event","flushed", 92 "Undef","ack complete","ack pend","Undef", 93 "ack busy_X","ack busy_A","ack busy_B","Undef", 94 "Undef","Undef","Undef","ack tardy", 95 "Undef","ack data_err","ack type_err",""}; 96 97 #define MAX_SPEED 3 98 extern char *linkspeed[]; 99 u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 100 101 static struct tcode_info tinfo[] = { 102 /* hdr_len block flag*/ 103 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 104 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 105 /* 2 WRES */ {12, FWTI_RES}, 106 /* 3 XXX */ { 0, 0}, 107 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 108 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 109 /* 6 RRESQ */ {16, FWTI_RES}, 110 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 111 /* 8 CYCS */ { 0, 0}, 112 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 113 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 114 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 115 /* c XXX */ { 0, 0}, 116 /* d XXX */ { 0, 0}, 117 /* e PHY */ {12, FWTI_REQ}, 118 /* f XXX */ { 0, 0} 119 }; 120 121 #define OHCI_WRITE_SIGMASK 0xffff0000 122 #define OHCI_READ_SIGMASK 0xffff0000 123 124 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 125 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 126 127 static void fwohci_ibr (struct firewire_comm *); 128 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 129 static void fwohci_db_free (struct fwohci_dbch *); 130 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 131 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 132 static void fwohci_start_atq (struct firewire_comm *); 133 static void fwohci_start_ats (struct firewire_comm *); 134 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 135 static u_int32_t fwphy_wrdata ( struct fwohci_softc *, u_int32_t, u_int32_t); 136 static u_int32_t fwphy_rddata ( struct fwohci_softc *, u_int32_t); 137 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 138 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 139 static int fwohci_irx_enable (struct firewire_comm *, int); 140 static int fwohci_irx_disable (struct firewire_comm *, int); 141 #if BYTE_ORDER == BIG_ENDIAN 142 static void fwohci_irx_post (struct firewire_comm *, u_int32_t *); 143 #endif 144 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 145 static int fwohci_itx_disable (struct firewire_comm *, int); 146 static void fwohci_timeout (void *); 147 static void fwohci_set_intr (struct firewire_comm *, int); 148 149 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 150 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 151 static void dump_db (struct fwohci_softc *, u_int32_t); 152 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, u_int32_t , u_int32_t); 153 static void dump_dma (struct fwohci_softc *, u_int32_t); 154 static u_int32_t fwohci_cyctimer (struct firewire_comm *); 155 static void fwohci_rbuf_update (struct fwohci_softc *, int); 156 static void fwohci_tbuf_update (struct fwohci_softc *, int); 157 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 158 #if FWOHCI_TASKQUEUE 159 static void fwohci_complete(void *, int); 160 #endif 161 162 /* 163 * memory allocated for DMA programs 164 */ 165 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 166 167 #define NDB FWMAXQUEUE 168 169 #define OHCI_VERSION 0x00 170 #define OHCI_ATRETRY 0x08 171 #define OHCI_CROMHDR 0x18 172 #define OHCI_BUS_OPT 0x20 173 #define OHCI_BUSIRMC (1 << 31) 174 #define OHCI_BUSCMC (1 << 30) 175 #define OHCI_BUSISC (1 << 29) 176 #define OHCI_BUSBMC (1 << 28) 177 #define OHCI_BUSPMC (1 << 27) 178 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179 OHCI_BUSBMC | OHCI_BUSPMC 180 181 #define OHCI_EUID_HI 0x24 182 #define OHCI_EUID_LO 0x28 183 184 #define OHCI_CROMPTR 0x34 185 #define OHCI_HCCCTL 0x50 186 #define OHCI_HCCCTLCLR 0x54 187 #define OHCI_AREQHI 0x100 188 #define OHCI_AREQHICLR 0x104 189 #define OHCI_AREQLO 0x108 190 #define OHCI_AREQLOCLR 0x10c 191 #define OHCI_PREQHI 0x110 192 #define OHCI_PREQHICLR 0x114 193 #define OHCI_PREQLO 0x118 194 #define OHCI_PREQLOCLR 0x11c 195 #define OHCI_PREQUPPER 0x120 196 197 #define OHCI_SID_BUF 0x64 198 #define OHCI_SID_CNT 0x68 199 #define OHCI_SID_ERR (1 << 31) 200 #define OHCI_SID_CNT_MASK 0xffc 201 202 #define OHCI_IT_STAT 0x90 203 #define OHCI_IT_STATCLR 0x94 204 #define OHCI_IT_MASK 0x98 205 #define OHCI_IT_MASKCLR 0x9c 206 207 #define OHCI_IR_STAT 0xa0 208 #define OHCI_IR_STATCLR 0xa4 209 #define OHCI_IR_MASK 0xa8 210 #define OHCI_IR_MASKCLR 0xac 211 212 #define OHCI_LNKCTL 0xe0 213 #define OHCI_LNKCTLCLR 0xe4 214 215 #define OHCI_PHYACCESS 0xec 216 #define OHCI_CYCLETIMER 0xf0 217 218 #define OHCI_DMACTL(off) (off) 219 #define OHCI_DMACTLCLR(off) (off + 4) 220 #define OHCI_DMACMD(off) (off + 0xc) 221 #define OHCI_DMAMATCH(off) (off + 0x10) 222 223 #define OHCI_ATQOFF 0x180 224 #define OHCI_ATQCTL OHCI_ATQOFF 225 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 226 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 227 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 228 229 #define OHCI_ATSOFF 0x1a0 230 #define OHCI_ATSCTL OHCI_ATSOFF 231 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 232 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 233 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 234 235 #define OHCI_ARQOFF 0x1c0 236 #define OHCI_ARQCTL OHCI_ARQOFF 237 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 238 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 239 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 240 241 #define OHCI_ARSOFF 0x1e0 242 #define OHCI_ARSCTL OHCI_ARSOFF 243 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 244 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 245 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 246 247 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 248 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 249 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 250 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 251 252 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 253 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 254 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 255 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 256 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 257 258 d_ioctl_t fwohci_ioctl; 259 260 /* 261 * Communication with PHY device 262 */ 263 static u_int32_t 264 fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 265 { 266 u_int32_t fun; 267 268 addr &= 0xf; 269 data &= 0xff; 270 271 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 272 OWRITE(sc, OHCI_PHYACCESS, fun); 273 DELAY(100); 274 275 return(fwphy_rddata( sc, addr)); 276 } 277 278 static u_int32_t 279 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 280 { 281 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 282 int i; 283 u_int32_t bm; 284 285 #define OHCI_CSR_DATA 0x0c 286 #define OHCI_CSR_COMP 0x10 287 #define OHCI_CSR_CONT 0x14 288 #define OHCI_BUS_MANAGER_ID 0 289 290 OWRITE(sc, OHCI_CSR_DATA, node); 291 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 292 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 293 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 294 DELAY(10); 295 bm = OREAD(sc, OHCI_CSR_DATA); 296 if((bm & 0x3f) == 0x3f) 297 bm = node; 298 if (bootverbose) 299 device_printf(sc->fc.dev, 300 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 301 302 return(bm); 303 } 304 305 static u_int32_t 306 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 307 { 308 u_int32_t fun, stat; 309 u_int i, retry = 0; 310 311 addr &= 0xf; 312 #define MAX_RETRY 100 313 again: 314 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 315 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 316 OWRITE(sc, OHCI_PHYACCESS, fun); 317 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 318 fun = OREAD(sc, OHCI_PHYACCESS); 319 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 320 break; 321 DELAY(100); 322 } 323 if(i >= MAX_RETRY) { 324 if (bootverbose) 325 device_printf(sc->fc.dev, "phy read failed(1).\n"); 326 if (++retry < MAX_RETRY) { 327 DELAY(100); 328 goto again; 329 } 330 } 331 /* Make sure that SCLK is started */ 332 stat = OREAD(sc, FWOHCI_INTSTAT); 333 if ((stat & OHCI_INT_REG_FAIL) != 0 || 334 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 335 if (bootverbose) 336 device_printf(sc->fc.dev, "phy read failed(2).\n"); 337 if (++retry < MAX_RETRY) { 338 DELAY(100); 339 goto again; 340 } 341 } 342 if (bootverbose || retry >= MAX_RETRY) 343 device_printf(sc->fc.dev, 344 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 345 #undef MAX_RETRY 346 return((fun >> PHYDEV_RDDATA )& 0xff); 347 } 348 /* Device specific ioctl. */ 349 int 350 fwohci_ioctl (struct dev_ioctl_args *ap) 351 { 352 cdev_t dev = ap->a_head.a_dev; 353 struct firewire_softc *sc; 354 struct fwohci_softc *fc; 355 int unit = DEV2UNIT(dev); 356 int err = 0; 357 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) ap->a_data; 358 u_int32_t *dmach = (u_int32_t *) ap->a_data; 359 360 sc = devclass_get_softc(firewire_devclass, unit); 361 if(sc == NULL){ 362 return(EINVAL); 363 } 364 fc = (struct fwohci_softc *)sc->fc; 365 366 if (!ap->a_data) 367 return(EINVAL); 368 369 switch (ap->a_cmd) { 370 case FWOHCI_WRREG: 371 #define OHCI_MAX_REG 0x800 372 if(reg->addr <= OHCI_MAX_REG){ 373 OWRITE(fc, reg->addr, reg->data); 374 reg->data = OREAD(fc, reg->addr); 375 }else{ 376 err = EINVAL; 377 } 378 break; 379 case FWOHCI_RDREG: 380 if(reg->addr <= OHCI_MAX_REG){ 381 reg->data = OREAD(fc, reg->addr); 382 }else{ 383 err = EINVAL; 384 } 385 break; 386 /* Read DMA descriptors for debug */ 387 case DUMPDMA: 388 if(*dmach <= OHCI_MAX_DMA_CH ){ 389 dump_dma(fc, *dmach); 390 dump_db(fc, *dmach); 391 }else{ 392 err = EINVAL; 393 } 394 break; 395 /* Read/Write Phy registers */ 396 #define OHCI_MAX_PHY_REG 0xf 397 case FWOHCI_RDPHYREG: 398 if (reg->addr <= OHCI_MAX_PHY_REG) 399 reg->data = fwphy_rddata(fc, reg->addr); 400 else 401 err = EINVAL; 402 break; 403 case FWOHCI_WRPHYREG: 404 if (reg->addr <= OHCI_MAX_PHY_REG) 405 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 406 else 407 err = EINVAL; 408 break; 409 default: 410 err = EINVAL; 411 break; 412 } 413 return err; 414 } 415 416 static int 417 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 418 { 419 u_int32_t reg, reg2; 420 int e1394a = 1; 421 /* 422 * probe PHY parameters 423 * 0. to prove PHY version, whether compliance of 1394a. 424 * 1. to probe maximum speed supported by the PHY and 425 * number of port supported by core-logic. 426 * It is not actually available port on your PC . 427 */ 428 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 429 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 430 431 if((reg >> 5) != 7 ){ 432 sc->fc.mode &= ~FWPHYASYST; 433 sc->fc.nport = reg & FW_PHY_NP; 434 sc->fc.speed = reg & FW_PHY_SPD >> 6; 435 if (sc->fc.speed > MAX_SPEED) { 436 device_printf(dev, "invalid speed %d (fixed to %d).\n", 437 sc->fc.speed, MAX_SPEED); 438 sc->fc.speed = MAX_SPEED; 439 } 440 device_printf(dev, 441 "Phy 1394 only %s, %d ports.\n", 442 linkspeed[sc->fc.speed], sc->fc.nport); 443 }else{ 444 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 445 sc->fc.mode |= FWPHYASYST; 446 sc->fc.nport = reg & FW_PHY_NP; 447 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 448 if (sc->fc.speed > MAX_SPEED) { 449 device_printf(dev, "invalid speed %d (fixed to %d).\n", 450 sc->fc.speed, MAX_SPEED); 451 sc->fc.speed = MAX_SPEED; 452 } 453 device_printf(dev, 454 "Phy 1394a available %s, %d ports.\n", 455 linkspeed[sc->fc.speed], sc->fc.nport); 456 457 /* check programPhyEnable */ 458 reg2 = fwphy_rddata(sc, 5); 459 #if 0 460 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 461 #else /* XXX force to enable 1394a */ 462 if (e1394a) { 463 #endif 464 if (bootverbose) 465 device_printf(dev, 466 "Enable 1394a Enhancements\n"); 467 /* enable EAA EMC */ 468 reg2 |= 0x03; 469 /* set aPhyEnhanceEnable */ 470 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 471 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 472 } else { 473 /* for safe */ 474 reg2 &= ~0x83; 475 } 476 reg2 = fwphy_wrdata(sc, 5, reg2); 477 } 478 479 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 480 if((reg >> 5) == 7 ){ 481 reg = fwphy_rddata(sc, 4); 482 reg |= 1 << 6; 483 fwphy_wrdata(sc, 4, reg); 484 reg = fwphy_rddata(sc, 4); 485 } 486 return 0; 487 } 488 489 490 void 491 fwohci_reset(struct fwohci_softc *sc, device_t dev) 492 { 493 int i, max_rec, speed; 494 u_int32_t reg, reg2; 495 struct fwohcidb_tr *db_tr; 496 497 /* Disable interrupt */ 498 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 499 500 /* Now stopping all DMA channel */ 501 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 502 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 503 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 504 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 505 506 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 507 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 508 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 509 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 510 } 511 512 /* FLUSH FIFO and reset Transmitter/Reciever */ 513 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 514 if (bootverbose) 515 device_printf(dev, "resetting OHCI..."); 516 i = 0; 517 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 518 if (i++ > 100) break; 519 DELAY(1000); 520 } 521 if (bootverbose) 522 kprintf("done (loop=%d)\n", i); 523 524 /* Probe phy */ 525 fwohci_probe_phy(sc, dev); 526 527 /* Probe link */ 528 reg = OREAD(sc, OHCI_BUS_OPT); 529 reg2 = reg | OHCI_BUSFNC; 530 max_rec = (reg & 0x0000f000) >> 12; 531 speed = (reg & 0x00000007); 532 device_printf(dev, "Link %s, max_rec %d bytes.\n", 533 linkspeed[speed], MAXREC(max_rec)); 534 /* XXX fix max_rec */ 535 sc->fc.maxrec = sc->fc.speed + 8; 536 if (max_rec != sc->fc.maxrec) { 537 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 538 device_printf(dev, "max_rec %d -> %d\n", 539 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 540 } 541 if (bootverbose) 542 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 543 OWRITE(sc, OHCI_BUS_OPT, reg2); 544 545 /* Initialize registers */ 546 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 547 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 548 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 549 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 550 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 551 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 552 553 /* Enable link */ 554 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 555 556 /* Force to start async RX DMA */ 557 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 558 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 559 fwohci_rx_enable(sc, &sc->arrq); 560 fwohci_rx_enable(sc, &sc->arrs); 561 562 /* Initialize async TX */ 563 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 564 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 565 566 /* AT Retries */ 567 OWRITE(sc, FWOHCI_RETRY, 568 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 569 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 570 571 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 572 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 573 sc->atrq.bottom = sc->atrq.top; 574 sc->atrs.bottom = sc->atrs.top; 575 576 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 577 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 578 db_tr->xfer = NULL; 579 } 580 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 581 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 582 db_tr->xfer = NULL; 583 } 584 585 586 /* Enable interrupt */ 587 OWRITE(sc, FWOHCI_INTMASK, 588 OHCI_INT_ERR | OHCI_INT_PHY_SID 589 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 590 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 591 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 592 fwohci_set_intr(&sc->fc, 1); 593 594 } 595 596 int 597 fwohci_init(struct fwohci_softc *sc, device_t dev) 598 { 599 int i, mver; 600 u_int32_t reg; 601 u_int8_t ui[8]; 602 603 #if FWOHCI_TASKQUEUE 604 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 605 #endif 606 607 /* OHCI version */ 608 reg = OREAD(sc, OHCI_VERSION); 609 mver = (reg >> 16) & 0xff; 610 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 611 mver, reg & 0xff, (reg>>24) & 1); 612 if (mver < 1 || mver > 9) { 613 device_printf(dev, "invalid OHCI version\n"); 614 return (ENXIO); 615 } 616 617 /* Available Isochrounous DMA channel probe */ 618 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 619 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 620 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 621 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 622 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 623 for (i = 0; i < 0x20; i++) 624 if ((reg & (1 << i)) == 0) 625 break; 626 sc->fc.nisodma = i; 627 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 628 if (i == 0) 629 return (ENXIO); 630 631 sc->fc.arq = &sc->arrq.xferq; 632 sc->fc.ars = &sc->arrs.xferq; 633 sc->fc.atq = &sc->atrq.xferq; 634 sc->fc.ats = &sc->atrs.xferq; 635 636 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 637 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 638 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 639 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 640 641 sc->arrq.xferq.start = NULL; 642 sc->arrs.xferq.start = NULL; 643 sc->atrq.xferq.start = fwohci_start_atq; 644 sc->atrs.xferq.start = fwohci_start_ats; 645 646 sc->arrq.xferq.buf = NULL; 647 sc->arrs.xferq.buf = NULL; 648 sc->atrq.xferq.buf = NULL; 649 sc->atrs.xferq.buf = NULL; 650 651 sc->arrq.xferq.dmach = -1; 652 sc->arrs.xferq.dmach = -1; 653 sc->atrq.xferq.dmach = -1; 654 sc->atrs.xferq.dmach = -1; 655 656 sc->arrq.ndesc = 1; 657 sc->arrs.ndesc = 1; 658 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 659 sc->atrs.ndesc = 2; 660 661 sc->arrq.ndb = NDB; 662 sc->arrs.ndb = NDB / 2; 663 sc->atrq.ndb = NDB; 664 sc->atrs.ndb = NDB / 2; 665 666 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 667 sc->fc.it[i] = &sc->it[i].xferq; 668 sc->fc.ir[i] = &sc->ir[i].xferq; 669 sc->it[i].xferq.dmach = i; 670 sc->ir[i].xferq.dmach = i; 671 sc->it[i].ndb = 0; 672 sc->ir[i].ndb = 0; 673 } 674 675 sc->fc.tcode = tinfo; 676 sc->fc.dev = dev; 677 678 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 679 &sc->crom_dma, BUS_DMA_WAITOK); 680 if(sc->fc.config_rom == NULL){ 681 device_printf(dev, "config_rom alloc failed."); 682 return ENOMEM; 683 } 684 685 #if 0 686 bzero(&sc->fc.config_rom[0], CROMSIZE); 687 sc->fc.config_rom[1] = 0x31333934; 688 sc->fc.config_rom[2] = 0xf000a002; 689 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 690 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 691 sc->fc.config_rom[5] = 0; 692 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 693 694 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 695 #endif 696 697 698 /* SID recieve buffer must allign 2^11 */ 699 #define OHCI_SIDSIZE (1 << 11) 700 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 701 &sc->sid_dma, BUS_DMA_WAITOK); 702 if (sc->sid_buf == NULL) { 703 device_printf(dev, "sid_buf alloc failed."); 704 return ENOMEM; 705 } 706 707 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), 708 &sc->dummy_dma, BUS_DMA_WAITOK); 709 710 if (sc->dummy_dma.v_addr == NULL) { 711 device_printf(dev, "dummy_dma alloc failed."); 712 return ENOMEM; 713 } 714 715 fwohci_db_init(sc, &sc->arrq); 716 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 717 return ENOMEM; 718 719 fwohci_db_init(sc, &sc->arrs); 720 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 721 return ENOMEM; 722 723 fwohci_db_init(sc, &sc->atrq); 724 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 725 return ENOMEM; 726 727 fwohci_db_init(sc, &sc->atrs); 728 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 729 return ENOMEM; 730 731 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 732 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 733 for( i = 0 ; i < 8 ; i ++) 734 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 735 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 736 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 737 738 sc->fc.ioctl = fwohci_ioctl; 739 sc->fc.cyctimer = fwohci_cyctimer; 740 sc->fc.set_bmr = fwohci_set_bus_manager; 741 sc->fc.ibr = fwohci_ibr; 742 sc->fc.irx_enable = fwohci_irx_enable; 743 sc->fc.irx_disable = fwohci_irx_disable; 744 745 sc->fc.itx_enable = fwohci_itxbuf_enable; 746 sc->fc.itx_disable = fwohci_itx_disable; 747 #if BYTE_ORDER == BIG_ENDIAN 748 sc->fc.irx_post = fwohci_irx_post; 749 #else 750 sc->fc.irx_post = NULL; 751 #endif 752 sc->fc.itx_post = NULL; 753 sc->fc.timeout = fwohci_timeout; 754 sc->fc.poll = fwohci_poll; 755 sc->fc.set_intr = fwohci_set_intr; 756 757 sc->intmask = sc->irstat = sc->itstat = 0; 758 759 fw_init(&sc->fc); 760 fwohci_reset(sc, dev); 761 762 return 0; 763 } 764 765 void 766 fwohci_timeout(void *arg) 767 { 768 struct fwohci_softc *sc; 769 770 sc = (struct fwohci_softc *)arg; 771 } 772 773 u_int32_t 774 fwohci_cyctimer(struct firewire_comm *fc) 775 { 776 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 777 return(OREAD(sc, OHCI_CYCLETIMER)); 778 } 779 780 int 781 fwohci_detach(struct fwohci_softc *sc, device_t dev) 782 { 783 int i; 784 785 if (sc->sid_buf != NULL) 786 fwdma_free(&sc->fc, &sc->sid_dma); 787 if (sc->fc.config_rom != NULL) 788 fwdma_free(&sc->fc, &sc->crom_dma); 789 790 fwohci_db_free(&sc->arrq); 791 fwohci_db_free(&sc->arrs); 792 793 fwohci_db_free(&sc->atrq); 794 fwohci_db_free(&sc->atrs); 795 796 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 797 fwohci_db_free(&sc->it[i]); 798 fwohci_db_free(&sc->ir[i]); 799 } 800 801 return 0; 802 } 803 804 #define LAST_DB(dbtr, db) do { \ 805 struct fwohcidb_tr *_dbtr = (dbtr); \ 806 int _cnt = _dbtr->dbcnt; \ 807 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 808 } while (0) 809 810 static void 811 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 812 { 813 struct fwohcidb_tr *db_tr; 814 struct fwohcidb *db; 815 bus_dma_segment_t *s; 816 int i; 817 818 db_tr = (struct fwohcidb_tr *)arg; 819 db = &db_tr->db[db_tr->dbcnt]; 820 if (error) { 821 if (firewire_debug || error != EFBIG) 822 kprintf("fwohci_execute_db: error=%d\n", error); 823 return; 824 } 825 for (i = 0; i < nseg; i++) { 826 s = &segs[i]; 827 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 828 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 829 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 830 db++; 831 db_tr->dbcnt++; 832 } 833 } 834 835 static void 836 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 837 bus_size_t size, int error) 838 { 839 fwohci_execute_db(arg, segs, nseg, error); 840 } 841 842 static void 843 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 844 { 845 int i; 846 int tcode, hdr_len, pl_off; 847 int fsegment = -1; 848 u_int32_t off; 849 struct fw_xfer *xfer; 850 struct fw_pkt *fp; 851 struct fwohci_txpkthdr *ohcifp; 852 struct fwohcidb_tr *db_tr; 853 struct fwohcidb *db; 854 u_int32_t *ld; 855 struct tcode_info *info; 856 static int maxdesc=0; 857 858 if(&sc->atrq == dbch){ 859 off = OHCI_ATQOFF; 860 }else if(&sc->atrs == dbch){ 861 off = OHCI_ATSOFF; 862 }else{ 863 return; 864 } 865 866 if (dbch->flags & FWOHCI_DBCH_FULL) 867 return; 868 869 crit_enter(); 870 db_tr = dbch->top; 871 txloop: 872 xfer = STAILQ_FIRST(&dbch->xferq.q); 873 if(xfer == NULL){ 874 goto kick; 875 } 876 if(dbch->xferq.queued == 0 ){ 877 device_printf(sc->fc.dev, "TX queue empty\n"); 878 } 879 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 880 db_tr->xfer = xfer; 881 xfer->state = FWXF_START; 882 883 fp = &xfer->send.hdr; 884 tcode = fp->mode.common.tcode; 885 886 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 887 info = &tinfo[tcode]; 888 hdr_len = pl_off = info->hdr_len; 889 890 ld = &ohcifp->mode.ld[0]; 891 ld[0] = ld[1] = ld[2] = ld[3] = 0; 892 for( i = 0 ; i < pl_off ; i+= 4) 893 ld[i/4] = fp->mode.ld[i/4]; 894 895 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 896 if (tcode == FWTCODE_STREAM ){ 897 hdr_len = 8; 898 ohcifp->mode.stream.len = fp->mode.stream.len; 899 } else if (tcode == FWTCODE_PHY) { 900 hdr_len = 12; 901 ld[1] = fp->mode.ld[1]; 902 ld[2] = fp->mode.ld[2]; 903 ohcifp->mode.common.spd = 0; 904 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 905 } else { 906 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 907 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 908 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 909 } 910 db = &db_tr->db[0]; 911 FWOHCI_DMA_WRITE(db->db.desc.cmd, 912 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 913 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 914 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 915 /* Specify bound timer of asy. responce */ 916 if(&sc->atrs == dbch){ 917 FWOHCI_DMA_WRITE(db->db.desc.res, 918 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 919 } 920 #if BYTE_ORDER == BIG_ENDIAN 921 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 922 hdr_len = 12; 923 for (i = 0; i < hdr_len/4; i ++) 924 FWOHCI_DMA_WRITE(ld[i], ld[i]); 925 #endif 926 927 again: 928 db_tr->dbcnt = 2; 929 db = &db_tr->db[db_tr->dbcnt]; 930 if (xfer->send.pay_len > 0) { 931 int err; 932 /* handle payload */ 933 if (xfer->mbuf == NULL) { 934 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, 935 &xfer->send.payload[0], xfer->send.pay_len, 936 fwohci_execute_db, db_tr, 937 /*flags*/0); 938 } else { 939 /* XXX we can handle only 6 (=8-2) mbuf chains */ 940 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 941 xfer->mbuf, 942 fwohci_execute_db2, db_tr, 943 /* flags */0); 944 if (err == EFBIG) { 945 struct mbuf *m0; 946 947 if (firewire_debug) 948 device_printf(sc->fc.dev, "EFBIG.\n"); 949 m0 = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 950 if (m0 != NULL) { 951 m_copydata(xfer->mbuf, 0, 952 xfer->mbuf->m_pkthdr.len, 953 mtod(m0, caddr_t)); 954 m0->m_len = m0->m_pkthdr.len = 955 xfer->mbuf->m_pkthdr.len; 956 m_freem(xfer->mbuf); 957 xfer->mbuf = m0; 958 goto again; 959 } 960 device_printf(sc->fc.dev, "m_getcl failed.\n"); 961 } 962 } 963 if (err) 964 kprintf("dmamap_load: err=%d\n", err); 965 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 966 BUS_DMASYNC_PREWRITE); 967 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 968 for (i = 2; i < db_tr->dbcnt; i++) 969 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 970 OHCI_OUTPUT_MORE); 971 #endif 972 } 973 if (maxdesc < db_tr->dbcnt) { 974 maxdesc = db_tr->dbcnt; 975 if (bootverbose) 976 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 977 } 978 /* last db */ 979 LAST_DB(db_tr, db); 980 FWOHCI_DMA_SET(db->db.desc.cmd, 981 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 982 FWOHCI_DMA_WRITE(db->db.desc.depend, 983 STAILQ_NEXT(db_tr, link)->bus_addr); 984 985 if(fsegment == -1 ) 986 fsegment = db_tr->dbcnt; 987 if (dbch->pdb_tr != NULL) { 988 LAST_DB(dbch->pdb_tr, db); 989 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 990 } 991 dbch->pdb_tr = db_tr; 992 db_tr = STAILQ_NEXT(db_tr, link); 993 if(db_tr != dbch->bottom){ 994 goto txloop; 995 } else { 996 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 997 dbch->flags |= FWOHCI_DBCH_FULL; 998 } 999 kick: 1000 /* kick asy q */ 1001 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1002 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1003 1004 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1005 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1006 } else { 1007 if (bootverbose) 1008 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1009 OREAD(sc, OHCI_DMACTL(off))); 1010 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1011 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1012 dbch->xferq.flag |= FWXFERQ_RUNNING; 1013 } 1014 1015 dbch->top = db_tr; 1016 crit_exit(); 1017 return; 1018 } 1019 1020 static void 1021 fwohci_start_atq(struct firewire_comm *fc) 1022 { 1023 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1024 fwohci_start( sc, &(sc->atrq)); 1025 return; 1026 } 1027 1028 static void 1029 fwohci_start_ats(struct firewire_comm *fc) 1030 { 1031 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1032 fwohci_start( sc, &(sc->atrs)); 1033 return; 1034 } 1035 1036 void 1037 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1038 { 1039 int ch, err = 0; 1040 struct fwohcidb_tr *tr; 1041 struct fwohcidb *db; 1042 struct fw_xfer *xfer; 1043 u_int32_t off; 1044 u_int stat, status; 1045 int packets; 1046 struct firewire_comm *fc = (struct firewire_comm *)sc; 1047 1048 if(&sc->atrq == dbch){ 1049 off = OHCI_ATQOFF; 1050 ch = ATRQ_CH; 1051 }else if(&sc->atrs == dbch){ 1052 off = OHCI_ATSOFF; 1053 ch = ATRS_CH; 1054 }else{ 1055 return; 1056 } 1057 crit_enter(); 1058 tr = dbch->bottom; 1059 packets = 0; 1060 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 1061 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 1062 while(dbch->xferq.queued > 0){ 1063 LAST_DB(tr, db); 1064 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1065 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1066 if (fc->status != FWBUSRESET) 1067 /* maybe out of order?? */ 1068 goto out; 1069 } 1070 bus_dmamap_sync(dbch->dmat, tr->dma_map, 1071 BUS_DMASYNC_POSTWRITE); 1072 bus_dmamap_unload(dbch->dmat, tr->dma_map); 1073 #if 1 1074 if (firewire_debug) 1075 dump_db(sc, ch); 1076 #endif 1077 if(status & OHCI_CNTL_DMA_DEAD) { 1078 /* Stop DMA */ 1079 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1080 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1081 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1082 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1083 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1084 } 1085 stat = status & FWOHCIEV_MASK; 1086 switch(stat){ 1087 case FWOHCIEV_ACKPEND: 1088 case FWOHCIEV_ACKCOMPL: 1089 err = 0; 1090 break; 1091 case FWOHCIEV_ACKBSA: 1092 case FWOHCIEV_ACKBSB: 1093 case FWOHCIEV_ACKBSX: 1094 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1095 err = EBUSY; 1096 break; 1097 case FWOHCIEV_FLUSHED: 1098 case FWOHCIEV_ACKTARD: 1099 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1100 err = EAGAIN; 1101 break; 1102 case FWOHCIEV_MISSACK: 1103 case FWOHCIEV_UNDRRUN: 1104 case FWOHCIEV_OVRRUN: 1105 case FWOHCIEV_DESCERR: 1106 case FWOHCIEV_DTRDERR: 1107 case FWOHCIEV_TIMEOUT: 1108 case FWOHCIEV_TCODERR: 1109 case FWOHCIEV_UNKNOWN: 1110 case FWOHCIEV_ACKDERR: 1111 case FWOHCIEV_ACKTERR: 1112 default: 1113 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1114 stat, fwohcicode[stat]); 1115 err = EINVAL; 1116 break; 1117 } 1118 if (tr->xfer != NULL) { 1119 xfer = tr->xfer; 1120 if (xfer->state == FWXF_RCVD) { 1121 #if 0 1122 if (firewire_debug) 1123 kprintf("already rcvd\n"); 1124 #endif 1125 fw_xfer_done(xfer); 1126 } else { 1127 xfer->state = FWXF_SENT; 1128 if (err == EBUSY && fc->status != FWBUSRESET) { 1129 xfer->state = FWXF_BUSY; 1130 xfer->resp = err; 1131 if (xfer->retry_req != NULL) 1132 xfer->retry_req(xfer); 1133 else { 1134 xfer->recv.pay_len = 0; 1135 fw_xfer_done(xfer); 1136 } 1137 } else if (stat != FWOHCIEV_ACKPEND) { 1138 if (stat != FWOHCIEV_ACKCOMPL) 1139 xfer->state = FWXF_SENTERR; 1140 xfer->resp = err; 1141 xfer->recv.pay_len = 0; 1142 fw_xfer_done(xfer); 1143 } 1144 } 1145 /* 1146 * The watchdog timer takes care of split 1147 * transcation timeout for ACKPEND case. 1148 */ 1149 } else { 1150 kprintf("this shouldn't happen\n"); 1151 } 1152 dbch->xferq.queued --; 1153 tr->xfer = NULL; 1154 1155 packets ++; 1156 tr = STAILQ_NEXT(tr, link); 1157 dbch->bottom = tr; 1158 if (dbch->bottom == dbch->top) { 1159 /* we reaches the end of context program */ 1160 if (firewire_debug && dbch->xferq.queued > 0) 1161 kprintf("queued > 0\n"); 1162 break; 1163 } 1164 } 1165 out: 1166 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1167 kprintf("make free slot\n"); 1168 dbch->flags &= ~FWOHCI_DBCH_FULL; 1169 fwohci_start(sc, dbch); 1170 } 1171 crit_exit(); 1172 } 1173 1174 static void 1175 fwohci_db_free(struct fwohci_dbch *dbch) 1176 { 1177 struct fwohcidb_tr *db_tr; 1178 int idb; 1179 1180 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1181 return; 1182 1183 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1184 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1185 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1186 db_tr->buf != NULL) { 1187 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1188 db_tr->buf, dbch->xferq.psize); 1189 db_tr->buf = NULL; 1190 } else if (db_tr->dma_map != NULL) 1191 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1192 } 1193 dbch->ndb = 0; 1194 db_tr = STAILQ_FIRST(&dbch->db_trq); 1195 fwdma_free_multiseg(dbch->am); 1196 kfree(db_tr, M_FW); 1197 STAILQ_INIT(&dbch->db_trq); 1198 dbch->flags &= ~FWOHCI_DBCH_INIT; 1199 } 1200 1201 static void 1202 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1203 { 1204 int idb; 1205 struct fwohcidb_tr *db_tr; 1206 1207 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1208 goto out; 1209 1210 /* create dma_tag for buffers */ 1211 #define MAX_REQCOUNT 0xffff 1212 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1213 /*alignment*/ 1, /*boundary*/ 0, 1214 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1215 /*highaddr*/ BUS_SPACE_MAXADDR, 1216 /*filter*/NULL, /*filterarg*/NULL, 1217 /*maxsize*/ dbch->xferq.psize, 1218 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1219 /*maxsegsz*/ MAX_REQCOUNT, 1220 /*flags*/ 0, 1221 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1222 /*lockfunc*/busdma_lock_mutex, 1223 /*lockarg*/&Giant, 1224 #endif 1225 &dbch->dmat)) 1226 return; 1227 1228 /* allocate DB entries and attach one to each DMA channels */ 1229 /* DB entry must start at 16 bytes bounary. */ 1230 STAILQ_INIT(&dbch->db_trq); 1231 db_tr = (struct fwohcidb_tr *) 1232 kmalloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1233 M_FW, M_WAITOK | M_ZERO); 1234 if(db_tr == NULL){ 1235 kprintf("fwohci_db_init: malloc(1) failed\n"); 1236 return; 1237 } 1238 1239 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1240 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1241 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1242 if (dbch->am == NULL) { 1243 kprintf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1244 kfree(db_tr, M_FW); 1245 return; 1246 } 1247 /* Attach DB to DMA ch. */ 1248 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1249 db_tr->dbcnt = 0; 1250 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1251 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1252 /* create dmamap for buffers */ 1253 /* XXX do we need 4bytes alignment tag? */ 1254 /* XXX don't alloc dma_map for AR */ 1255 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1256 kprintf("bus_dmamap_create failed\n"); 1257 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1258 fwohci_db_free(dbch); 1259 return; 1260 } 1261 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1262 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1263 if (idb % dbch->xferq.bnpacket == 0) 1264 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1265 ].start = (caddr_t)db_tr; 1266 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1267 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1268 ].end = (caddr_t)db_tr; 1269 } 1270 db_tr++; 1271 } 1272 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1273 = STAILQ_FIRST(&dbch->db_trq); 1274 out: 1275 dbch->xferq.queued = 0; 1276 dbch->pdb_tr = NULL; 1277 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1278 dbch->bottom = dbch->top; 1279 dbch->flags = FWOHCI_DBCH_INIT; 1280 } 1281 1282 static int 1283 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1284 { 1285 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1286 int sleepch; 1287 1288 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1289 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1290 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1291 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1292 /* XXX we cannot free buffers until the DMA really stops */ 1293 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1294 fwohci_db_free(&sc->it[dmach]); 1295 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1296 return 0; 1297 } 1298 1299 static int 1300 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1301 { 1302 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1303 int sleepch; 1304 1305 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1306 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1307 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1308 /* XXX we cannot free buffers until the DMA really stops */ 1309 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1310 fwohci_db_free(&sc->ir[dmach]); 1311 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1312 return 0; 1313 } 1314 1315 #if BYTE_ORDER == BIG_ENDIAN 1316 static void 1317 fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1318 { 1319 qld[0] = FWOHCI_DMA_READ(qld[0]); 1320 return; 1321 } 1322 #endif 1323 1324 static int 1325 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1326 { 1327 int err = 0; 1328 int idb, z, i, dmach = 0, ldesc; 1329 u_int32_t off = 0; 1330 struct fwohcidb_tr *db_tr; 1331 struct fwohcidb *db; 1332 1333 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1334 err = EINVAL; 1335 return err; 1336 } 1337 z = dbch->ndesc; 1338 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1339 if( &sc->it[dmach] == dbch){ 1340 off = OHCI_ITOFF(dmach); 1341 break; 1342 } 1343 } 1344 if(off == 0){ 1345 err = EINVAL; 1346 return err; 1347 } 1348 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1349 return err; 1350 dbch->xferq.flag |= FWXFERQ_RUNNING; 1351 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1352 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1353 } 1354 db_tr = dbch->top; 1355 for (idb = 0; idb < dbch->ndb; idb ++) { 1356 fwohci_add_tx_buf(dbch, db_tr, idb); 1357 if(STAILQ_NEXT(db_tr, link) == NULL){ 1358 break; 1359 } 1360 db = db_tr->db; 1361 ldesc = db_tr->dbcnt - 1; 1362 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1363 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1364 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1365 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1366 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1367 FWOHCI_DMA_SET( 1368 db[ldesc].db.desc.cmd, 1369 OHCI_INTERRUPT_ALWAYS); 1370 /* OHCI 1.1 and above */ 1371 FWOHCI_DMA_SET( 1372 db[0].db.desc.cmd, 1373 OHCI_INTERRUPT_ALWAYS); 1374 } 1375 } 1376 db_tr = STAILQ_NEXT(db_tr, link); 1377 } 1378 FWOHCI_DMA_CLEAR( 1379 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1380 return err; 1381 } 1382 1383 static int 1384 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1385 { 1386 int err = 0; 1387 int idb, z, i, dmach = 0, ldesc; 1388 u_int32_t off = 0; 1389 struct fwohcidb_tr *db_tr; 1390 struct fwohcidb *db; 1391 1392 z = dbch->ndesc; 1393 if(&sc->arrq == dbch){ 1394 off = OHCI_ARQOFF; 1395 }else if(&sc->arrs == dbch){ 1396 off = OHCI_ARSOFF; 1397 }else{ 1398 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1399 if( &sc->ir[dmach] == dbch){ 1400 off = OHCI_IROFF(dmach); 1401 break; 1402 } 1403 } 1404 } 1405 if(off == 0){ 1406 err = EINVAL; 1407 return err; 1408 } 1409 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1410 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1411 return err; 1412 }else{ 1413 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1414 err = EBUSY; 1415 return err; 1416 } 1417 } 1418 dbch->xferq.flag |= FWXFERQ_RUNNING; 1419 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1420 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1421 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1422 } 1423 db_tr = dbch->top; 1424 for (idb = 0; idb < dbch->ndb; idb ++) { 1425 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1426 if (STAILQ_NEXT(db_tr, link) == NULL) 1427 break; 1428 db = db_tr->db; 1429 ldesc = db_tr->dbcnt - 1; 1430 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1431 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1432 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1433 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1434 FWOHCI_DMA_SET( 1435 db[ldesc].db.desc.cmd, 1436 OHCI_INTERRUPT_ALWAYS); 1437 FWOHCI_DMA_CLEAR( 1438 db[ldesc].db.desc.depend, 1439 0xf); 1440 } 1441 } 1442 db_tr = STAILQ_NEXT(db_tr, link); 1443 } 1444 FWOHCI_DMA_CLEAR( 1445 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1446 dbch->buf_offset = 0; 1447 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1448 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1449 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1450 return err; 1451 }else{ 1452 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1453 } 1454 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1455 return err; 1456 } 1457 1458 static int 1459 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1460 { 1461 int sec, cycle, cycle_match; 1462 1463 cycle = cycle_now & 0x1fff; 1464 sec = cycle_now >> 13; 1465 #define CYCLE_MOD 0x10 1466 #if 1 1467 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1468 #else 1469 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1470 #endif 1471 cycle = cycle + CYCLE_DELAY; 1472 if (cycle >= 8000) { 1473 sec ++; 1474 cycle -= 8000; 1475 } 1476 cycle = roundup2(cycle, CYCLE_MOD); 1477 if (cycle >= 8000) { 1478 sec ++; 1479 if (cycle == 8000) 1480 cycle = 0; 1481 else 1482 cycle = CYCLE_MOD; 1483 } 1484 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1485 1486 return(cycle_match); 1487 } 1488 1489 static int 1490 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1491 { 1492 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1493 int err = 0; 1494 unsigned short tag, ich; 1495 struct fwohci_dbch *dbch; 1496 int cycle_match, cycle_now, ldesc; 1497 u_int32_t stat; 1498 struct fw_bulkxfer *first, *chunk, *prev; 1499 struct fw_xferq *it; 1500 1501 dbch = &sc->it[dmach]; 1502 it = &dbch->xferq; 1503 1504 tag = (it->flag >> 6) & 3; 1505 ich = it->flag & 0x3f; 1506 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1507 dbch->ndb = it->bnpacket * it->bnchunk; 1508 dbch->ndesc = 3; 1509 fwohci_db_init(sc, dbch); 1510 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1511 return ENOMEM; 1512 err = fwohci_tx_enable(sc, dbch); 1513 } 1514 if(err) 1515 return err; 1516 1517 ldesc = dbch->ndesc - 1; 1518 crit_enter(); 1519 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1520 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1521 struct fwohcidb *db; 1522 1523 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1524 BUS_DMASYNC_PREWRITE); 1525 fwohci_txbufdb(sc, dmach, chunk); 1526 if (prev != NULL) { 1527 db = ((struct fwohcidb_tr *)(prev->end))->db; 1528 #if 0 /* XXX necessary? */ 1529 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1530 OHCI_BRANCH_ALWAYS); 1531 #endif 1532 #if 0 /* if bulkxfer->npacket changes */ 1533 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1534 ((struct fwohcidb_tr *) 1535 (chunk->start))->bus_addr | dbch->ndesc; 1536 #else 1537 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1538 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1539 #endif 1540 } 1541 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1542 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1543 prev = chunk; 1544 } 1545 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1546 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1547 crit_exit(); 1548 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1549 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1550 kprintf("stat 0x%x\n", stat); 1551 1552 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1553 return 0; 1554 1555 #if 0 1556 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1557 #endif 1558 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1559 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1560 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1561 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1562 1563 first = STAILQ_FIRST(&it->stdma); 1564 OWRITE(sc, OHCI_ITCMD(dmach), 1565 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1566 if (firewire_debug) { 1567 kprintf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1568 #if 1 1569 dump_dma(sc, ITX_CH + dmach); 1570 #endif 1571 } 1572 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1573 #if 1 1574 /* Don't start until all chunks are buffered */ 1575 if (STAILQ_FIRST(&it->stfree) != NULL) 1576 goto out; 1577 #endif 1578 #if 1 1579 /* Clear cycle match counter bits */ 1580 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1581 1582 /* 2bit second + 13bit cycle */ 1583 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1584 cycle_match = fwohci_next_cycle(fc, cycle_now); 1585 1586 OWRITE(sc, OHCI_ITCTL(dmach), 1587 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1588 | OHCI_CNTL_DMA_RUN); 1589 #else 1590 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1591 #endif 1592 if (firewire_debug) { 1593 kprintf("cycle_match: 0x%04x->0x%04x\n", 1594 cycle_now, cycle_match); 1595 dump_dma(sc, ITX_CH + dmach); 1596 dump_db(sc, ITX_CH + dmach); 1597 } 1598 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1599 device_printf(sc->fc.dev, 1600 "IT DMA underrun (0x%08x)\n", stat); 1601 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1602 } 1603 out: 1604 return err; 1605 } 1606 1607 static int 1608 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1609 { 1610 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1611 int err = 0, ldesc; 1612 unsigned short tag, ich; 1613 u_int32_t stat; 1614 struct fwohci_dbch *dbch; 1615 struct fwohcidb_tr *db_tr; 1616 struct fw_bulkxfer *first, *prev, *chunk; 1617 struct fw_xferq *ir; 1618 1619 dbch = &sc->ir[dmach]; 1620 ir = &dbch->xferq; 1621 1622 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1623 tag = (ir->flag >> 6) & 3; 1624 ich = ir->flag & 0x3f; 1625 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1626 1627 ir->queued = 0; 1628 dbch->ndb = ir->bnpacket * ir->bnchunk; 1629 dbch->ndesc = 2; 1630 fwohci_db_init(sc, dbch); 1631 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1632 return ENOMEM; 1633 err = fwohci_rx_enable(sc, dbch); 1634 } 1635 if(err) 1636 return err; 1637 1638 first = STAILQ_FIRST(&ir->stfree); 1639 if (first == NULL) { 1640 device_printf(fc->dev, "IR DMA no free chunk\n"); 1641 return 0; 1642 } 1643 1644 ldesc = dbch->ndesc - 1; 1645 crit_enter(); 1646 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1647 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1648 struct fwohcidb *db; 1649 1650 #if 1 /* XXX for if_fwe */ 1651 if (chunk->mbuf != NULL) { 1652 db_tr = (struct fwohcidb_tr *)(chunk->start); 1653 db_tr->dbcnt = 1; 1654 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, 1655 chunk->mbuf, fwohci_execute_db2, db_tr, 1656 /* flags */0); 1657 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1658 OHCI_UPDATE | OHCI_INPUT_LAST | 1659 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1660 } 1661 #endif 1662 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1663 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1664 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1665 if (prev != NULL) { 1666 db = ((struct fwohcidb_tr *)(prev->end))->db; 1667 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1668 } 1669 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1670 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1671 prev = chunk; 1672 } 1673 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 1674 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1675 crit_exit(); 1676 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1677 if (stat & OHCI_CNTL_DMA_ACTIVE) 1678 return 0; 1679 if (stat & OHCI_CNTL_DMA_RUN) { 1680 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1681 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1682 } 1683 1684 if (firewire_debug) 1685 kprintf("start IR DMA 0x%x\n", stat); 1686 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1687 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1688 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1689 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1690 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1691 OWRITE(sc, OHCI_IRCMD(dmach), 1692 ((struct fwohcidb_tr *)(first->start))->bus_addr 1693 | dbch->ndesc); 1694 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1695 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1696 #if 0 1697 dump_db(sc, IRX_CH + dmach); 1698 #endif 1699 return err; 1700 } 1701 1702 int 1703 fwohci_stop(struct fwohci_softc *sc, device_t dev) 1704 { 1705 u_int i; 1706 1707 /* Now stopping all DMA channel */ 1708 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1709 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1710 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1711 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1712 1713 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1714 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1715 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1716 } 1717 1718 /* FLUSH FIFO and reset Transmitter/Reciever */ 1719 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1720 1721 /* Stop interrupt */ 1722 OWRITE(sc, FWOHCI_INTMASKCLR, 1723 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1724 | OHCI_INT_PHY_INT 1725 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1726 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1727 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1728 | OHCI_INT_PHY_BUS_R); 1729 1730 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1731 fw_drain_txq(&sc->fc); 1732 1733 /* XXX Link down? Bus reset? */ 1734 return 0; 1735 } 1736 1737 int 1738 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1739 { 1740 int i; 1741 struct fw_xferq *ir; 1742 struct fw_bulkxfer *chunk; 1743 1744 fwohci_reset(sc, dev); 1745 /* XXX resume isochronus receive automatically. (how about TX?) */ 1746 for(i = 0; i < sc->fc.nisodma; i ++) { 1747 ir = &sc->ir[i].xferq; 1748 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1749 device_printf(sc->fc.dev, 1750 "resume iso receive ch: %d\n", i); 1751 ir->flag &= ~FWXFERQ_RUNNING; 1752 /* requeue stdma to stfree */ 1753 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1754 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1755 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1756 } 1757 sc->fc.irx_enable(&sc->fc, i); 1758 } 1759 } 1760 1761 bus_generic_resume(dev); 1762 sc->fc.ibr(&sc->fc); 1763 return 0; 1764 } 1765 1766 #define ACK_ALL 1767 static void 1768 fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1769 { 1770 u_int32_t irstat, itstat; 1771 u_int i; 1772 struct firewire_comm *fc = (struct firewire_comm *)sc; 1773 1774 #ifdef OHCI_DEBUG 1775 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1776 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1777 stat & OHCI_INT_EN ? "DMA_EN ":"", 1778 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1779 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1780 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1781 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1782 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1783 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1784 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1785 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1786 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1787 stat & OHCI_INT_PHY_SID ? "SID ":"", 1788 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1789 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1790 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1791 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1792 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1793 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1794 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1795 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1796 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1797 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1798 stat, OREAD(sc, FWOHCI_INTMASK) 1799 ); 1800 #endif 1801 /* Bus reset */ 1802 if(stat & OHCI_INT_PHY_BUS_R ){ 1803 if (fc->status == FWBUSRESET) 1804 goto busresetout; 1805 /* Disable bus reset interrupt until sid recv. */ 1806 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1807 1808 device_printf(fc->dev, "BUS reset\n"); 1809 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1810 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1811 1812 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1813 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1814 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1815 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1816 1817 #ifndef ACK_ALL 1818 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1819 #endif 1820 fw_busreset(fc); 1821 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1822 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1823 } 1824 busresetout: 1825 if((stat & OHCI_INT_DMA_IR )){ 1826 #ifndef ACK_ALL 1827 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1828 #endif 1829 #if defined(__DragonFly__) || __FreeBSD_version < 500000 1830 irstat = sc->irstat; 1831 sc->irstat = 0; 1832 #else 1833 irstat = atomic_readandclear_int(&sc->irstat); 1834 #endif 1835 for(i = 0; i < fc->nisodma ; i++){ 1836 struct fwohci_dbch *dbch; 1837 1838 if((irstat & (1 << i)) != 0){ 1839 dbch = &sc->ir[i]; 1840 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1841 device_printf(sc->fc.dev, 1842 "dma(%d) not active\n", i); 1843 continue; 1844 } 1845 fwohci_rbuf_update(sc, i); 1846 } 1847 } 1848 } 1849 if((stat & OHCI_INT_DMA_IT )){ 1850 #ifndef ACK_ALL 1851 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1852 #endif 1853 #if defined(__DragonFly__) || __FreeBSD_version < 500000 1854 itstat = sc->itstat; 1855 sc->itstat = 0; 1856 #else 1857 itstat = atomic_readandclear_int(&sc->itstat); 1858 #endif 1859 for(i = 0; i < fc->nisodma ; i++){ 1860 if((itstat & (1 << i)) != 0){ 1861 fwohci_tbuf_update(sc, i); 1862 } 1863 } 1864 } 1865 if((stat & OHCI_INT_DMA_PRRS )){ 1866 #ifndef ACK_ALL 1867 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1868 #endif 1869 #if 0 1870 dump_dma(sc, ARRS_CH); 1871 dump_db(sc, ARRS_CH); 1872 #endif 1873 fwohci_arcv(sc, &sc->arrs, count); 1874 } 1875 if((stat & OHCI_INT_DMA_PRRQ )){ 1876 #ifndef ACK_ALL 1877 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1878 #endif 1879 #if 0 1880 dump_dma(sc, ARRQ_CH); 1881 dump_db(sc, ARRQ_CH); 1882 #endif 1883 fwohci_arcv(sc, &sc->arrq, count); 1884 } 1885 if(stat & OHCI_INT_PHY_SID){ 1886 u_int32_t *buf, node_id; 1887 int plen; 1888 1889 #ifndef ACK_ALL 1890 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1891 #endif 1892 /* Enable bus reset interrupt */ 1893 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1894 /* Allow async. request to us */ 1895 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1896 /* XXX insecure ?? */ 1897 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1898 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1899 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1900 /* Set ATRetries register */ 1901 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1902 /* 1903 ** Checking whether the node is root or not. If root, turn on 1904 ** cycle master. 1905 */ 1906 node_id = OREAD(sc, FWOHCI_NODEID); 1907 plen = OREAD(sc, OHCI_SID_CNT); 1908 1909 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 1910 node_id, (plen >> 16) & 0xff); 1911 if (!(node_id & OHCI_NODE_VALID)) { 1912 kprintf("Bus reset failure\n"); 1913 goto sidout; 1914 } 1915 if (node_id & OHCI_NODE_ROOT) { 1916 kprintf("CYCLEMASTER mode\n"); 1917 OWRITE(sc, OHCI_LNKCTL, 1918 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1919 } else { 1920 kprintf("non CYCLEMASTER mode\n"); 1921 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1922 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1923 } 1924 fc->nodeid = node_id & 0x3f; 1925 1926 if (plen & OHCI_SID_ERR) { 1927 device_printf(fc->dev, "SID Error\n"); 1928 goto sidout; 1929 } 1930 plen &= OHCI_SID_CNT_MASK; 1931 if (plen < 4 || plen > OHCI_SIDSIZE) { 1932 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1933 goto sidout; 1934 } 1935 plen -= 4; /* chop control info */ 1936 buf = (u_int32_t *)kmalloc(OHCI_SIDSIZE, M_FW, M_INTWAIT); 1937 if (buf == NULL) { 1938 device_printf(fc->dev, "malloc failed\n"); 1939 goto sidout; 1940 } 1941 for (i = 0; i < plen / 4; i ++) 1942 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 1943 #if 1 1944 /* pending all pre-bus_reset packets */ 1945 fwohci_txd(sc, &sc->atrq); 1946 fwohci_txd(sc, &sc->atrs); 1947 fwohci_arcv(sc, &sc->arrs, -1); 1948 fwohci_arcv(sc, &sc->arrq, -1); 1949 fw_drain_txq(fc); 1950 #endif 1951 fw_sidrcv(fc, buf, plen); 1952 kfree(buf, M_FW); 1953 } 1954 sidout: 1955 if((stat & OHCI_INT_DMA_ATRQ )){ 1956 #ifndef ACK_ALL 1957 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1958 #endif 1959 fwohci_txd(sc, &(sc->atrq)); 1960 } 1961 if((stat & OHCI_INT_DMA_ATRS )){ 1962 #ifndef ACK_ALL 1963 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1964 #endif 1965 fwohci_txd(sc, &(sc->atrs)); 1966 } 1967 if((stat & OHCI_INT_PW_ERR )){ 1968 #ifndef ACK_ALL 1969 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1970 #endif 1971 device_printf(fc->dev, "posted write error\n"); 1972 } 1973 if((stat & OHCI_INT_ERR )){ 1974 #ifndef ACK_ALL 1975 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1976 #endif 1977 device_printf(fc->dev, "unrecoverable error\n"); 1978 } 1979 if((stat & OHCI_INT_PHY_INT)) { 1980 #ifndef ACK_ALL 1981 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1982 #endif 1983 device_printf(fc->dev, "phy int\n"); 1984 } 1985 1986 return; 1987 } 1988 1989 #if FWOHCI_TASKQUEUE 1990 static void 1991 fwohci_complete(void *arg, int pending) 1992 { 1993 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1994 u_int32_t stat; 1995 1996 again: 1997 stat = atomic_readandclear_int(&sc->intstat); 1998 if (stat) 1999 fwohci_intr_body(sc, stat, -1); 2000 else 2001 return; 2002 goto again; 2003 } 2004 #endif 2005 2006 static u_int32_t 2007 fwochi_check_stat(struct fwohci_softc *sc) 2008 { 2009 u_int32_t stat, irstat, itstat; 2010 2011 stat = OREAD(sc, FWOHCI_INTSTAT); 2012 if (stat == 0xffffffff) { 2013 device_printf(sc->fc.dev, 2014 "device physically ejected?\n"); 2015 return(stat); 2016 } 2017 #ifdef ACK_ALL 2018 if (stat) 2019 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2020 #endif 2021 if (stat & OHCI_INT_DMA_IR) { 2022 irstat = OREAD(sc, OHCI_IR_STAT); 2023 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2024 atomic_set_int(&sc->irstat, irstat); 2025 } 2026 if (stat & OHCI_INT_DMA_IT) { 2027 itstat = OREAD(sc, OHCI_IT_STAT); 2028 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2029 atomic_set_int(&sc->itstat, itstat); 2030 } 2031 return(stat); 2032 } 2033 2034 void 2035 fwohci_intr(void *arg) 2036 { 2037 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2038 u_int32_t stat; 2039 #if !FWOHCI_TASKQUEUE 2040 u_int32_t bus_reset = 0; 2041 #endif 2042 2043 if (!(sc->intmask & OHCI_INT_EN)) { 2044 /* polling mode */ 2045 return; 2046 } 2047 2048 #if !FWOHCI_TASKQUEUE 2049 again: 2050 #endif 2051 stat = fwochi_check_stat(sc); 2052 if (stat == 0 || stat == 0xffffffff) 2053 return; 2054 #if FWOHCI_TASKQUEUE 2055 atomic_set_int(&sc->intstat, stat); 2056 /* XXX mask bus reset intr. during bus reset phase */ 2057 if (stat) 2058 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); 2059 #else 2060 /* We cannot clear bus reset event during bus reset phase */ 2061 if ((stat & ~bus_reset) == 0) 2062 return; 2063 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2064 fwohci_intr_body(sc, stat, -1); 2065 goto again; 2066 #endif 2067 } 2068 2069 void 2070 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2071 { 2072 u_int32_t stat; 2073 struct fwohci_softc *sc; 2074 2075 2076 sc = (struct fwohci_softc *)fc; 2077 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2078 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2079 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2080 #if 0 2081 if (!quick) { 2082 #else 2083 if (1) { 2084 #endif 2085 stat = fwochi_check_stat(sc); 2086 if (stat == 0 || stat == 0xffffffff) 2087 return; 2088 } 2089 crit_enter(); 2090 fwohci_intr_body(sc, stat, count); 2091 crit_exit(); 2092 } 2093 2094 static void 2095 fwohci_set_intr(struct firewire_comm *fc, int enable) 2096 { 2097 struct fwohci_softc *sc; 2098 2099 sc = (struct fwohci_softc *)fc; 2100 if (bootverbose) 2101 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2102 if (enable) { 2103 sc->intmask |= OHCI_INT_EN; 2104 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2105 } else { 2106 sc->intmask &= ~OHCI_INT_EN; 2107 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2108 } 2109 } 2110 2111 static void 2112 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2113 { 2114 struct firewire_comm *fc = &sc->fc; 2115 struct fwohcidb *db; 2116 struct fw_bulkxfer *chunk; 2117 struct fw_xferq *it; 2118 u_int32_t stat, count; 2119 int w=0, ldesc; 2120 2121 it = fc->it[dmach]; 2122 ldesc = sc->it[dmach].ndesc - 1; 2123 crit_enter(); /* unnecessary? */ 2124 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2125 if (firewire_debug) 2126 dump_db(sc, ITX_CH + dmach); 2127 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2128 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2129 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2130 >> OHCI_STATUS_SHIFT; 2131 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2132 /* timestamp */ 2133 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2134 & OHCI_COUNT_MASK; 2135 if (stat == 0) 2136 break; 2137 STAILQ_REMOVE_HEAD(&it->stdma, link); 2138 switch (stat & FWOHCIEV_MASK){ 2139 case FWOHCIEV_ACKCOMPL: 2140 #if 0 2141 device_printf(fc->dev, "0x%08x\n", count); 2142 #endif 2143 break; 2144 default: 2145 device_printf(fc->dev, 2146 "Isochronous transmit err %02x(%s)\n", 2147 stat, fwohcicode[stat & 0x1f]); 2148 } 2149 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2150 w++; 2151 } 2152 crit_exit(); 2153 if (w) 2154 wakeup(it); 2155 } 2156 2157 static void 2158 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2159 { 2160 struct firewire_comm *fc = &sc->fc; 2161 struct fwohcidb_tr *db_tr; 2162 struct fw_bulkxfer *chunk; 2163 struct fw_xferq *ir; 2164 u_int32_t stat; 2165 int w=0, ldesc; 2166 2167 ir = fc->ir[dmach]; 2168 ldesc = sc->ir[dmach].ndesc - 1; 2169 #if 0 2170 dump_db(sc, dmach); 2171 #endif 2172 crit_enter(); 2173 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2174 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2175 db_tr = (struct fwohcidb_tr *)chunk->end; 2176 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2177 >> OHCI_STATUS_SHIFT; 2178 if (stat == 0) 2179 break; 2180 2181 if (chunk->mbuf != NULL) { 2182 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2183 BUS_DMASYNC_POSTREAD); 2184 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); 2185 } else if (ir->buf != NULL) { 2186 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2187 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2188 } else { 2189 /* XXX */ 2190 kprintf("fwohci_rbuf_update: this shouldn't happend\n"); 2191 } 2192 2193 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2194 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2195 switch (stat & FWOHCIEV_MASK) { 2196 case FWOHCIEV_ACKCOMPL: 2197 chunk->resp = 0; 2198 break; 2199 default: 2200 chunk->resp = EINVAL; 2201 device_printf(fc->dev, 2202 "Isochronous receive err %02x(%s)\n", 2203 stat, fwohcicode[stat & 0x1f]); 2204 } 2205 w++; 2206 } 2207 crit_exit(); 2208 if (w) { 2209 if (ir->flag & FWXFERQ_HANDLER) 2210 ir->hand(ir); 2211 else 2212 wakeup(ir); 2213 } 2214 } 2215 2216 void 2217 dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2218 { 2219 u_int32_t off, cntl, stat, cmd, match; 2220 2221 if(ch == 0){ 2222 off = OHCI_ATQOFF; 2223 }else if(ch == 1){ 2224 off = OHCI_ATSOFF; 2225 }else if(ch == 2){ 2226 off = OHCI_ARQOFF; 2227 }else if(ch == 3){ 2228 off = OHCI_ARSOFF; 2229 }else if(ch < IRX_CH){ 2230 off = OHCI_ITCTL(ch - ITX_CH); 2231 }else{ 2232 off = OHCI_IRCTL(ch - IRX_CH); 2233 } 2234 cntl = stat = OREAD(sc, off); 2235 cmd = OREAD(sc, off + 0xc); 2236 match = OREAD(sc, off + 0x10); 2237 2238 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2239 ch, 2240 cntl, 2241 cmd, 2242 match); 2243 stat &= 0xffff ; 2244 if (stat) { 2245 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2246 ch, 2247 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2248 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2249 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2250 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2251 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2252 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2253 fwohcicode[stat & 0x1f], 2254 stat & 0x1f 2255 ); 2256 }else{ 2257 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2258 } 2259 } 2260 2261 void 2262 dump_db(struct fwohci_softc *sc, u_int32_t ch) 2263 { 2264 struct fwohci_dbch *dbch; 2265 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2266 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2267 int idb, jdb; 2268 u_int32_t cmd, off; 2269 if(ch == 0){ 2270 off = OHCI_ATQOFF; 2271 dbch = &sc->atrq; 2272 }else if(ch == 1){ 2273 off = OHCI_ATSOFF; 2274 dbch = &sc->atrs; 2275 }else if(ch == 2){ 2276 off = OHCI_ARQOFF; 2277 dbch = &sc->arrq; 2278 }else if(ch == 3){ 2279 off = OHCI_ARSOFF; 2280 dbch = &sc->arrs; 2281 }else if(ch < IRX_CH){ 2282 off = OHCI_ITCTL(ch - ITX_CH); 2283 dbch = &sc->it[ch - ITX_CH]; 2284 }else { 2285 off = OHCI_IRCTL(ch - IRX_CH); 2286 dbch = &sc->ir[ch - IRX_CH]; 2287 } 2288 cmd = OREAD(sc, off + 0xc); 2289 2290 if( dbch->ndb == 0 ){ 2291 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2292 return; 2293 } 2294 pp = dbch->top; 2295 prev = pp->db; 2296 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2297 if(pp == NULL){ 2298 curr = NULL; 2299 goto outdb; 2300 } 2301 cp = STAILQ_NEXT(pp, link); 2302 if(cp == NULL){ 2303 curr = NULL; 2304 goto outdb; 2305 } 2306 np = STAILQ_NEXT(cp, link); 2307 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2308 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2309 curr = cp->db; 2310 if(np != NULL){ 2311 next = np->db; 2312 }else{ 2313 next = NULL; 2314 } 2315 goto outdb; 2316 } 2317 } 2318 pp = STAILQ_NEXT(pp, link); 2319 prev = pp->db; 2320 } 2321 outdb: 2322 if( curr != NULL){ 2323 #if 0 2324 kprintf("Prev DB %d\n", ch); 2325 print_db(pp, prev, ch, dbch->ndesc); 2326 #endif 2327 kprintf("Current DB %d\n", ch); 2328 print_db(cp, curr, ch, dbch->ndesc); 2329 #if 0 2330 kprintf("Next DB %d\n", ch); 2331 print_db(np, next, ch, dbch->ndesc); 2332 #endif 2333 }else{ 2334 kprintf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2335 } 2336 return; 2337 } 2338 2339 void 2340 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2341 u_int32_t ch, u_int32_t max) 2342 { 2343 fwohcireg_t stat; 2344 int i, key; 2345 u_int32_t cmd, res; 2346 2347 if(db == NULL){ 2348 kprintf("No Descriptor is found\n"); 2349 return; 2350 } 2351 2352 kprintf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2353 ch, 2354 "Current", 2355 "OP ", 2356 "KEY", 2357 "INT", 2358 "BR ", 2359 "len", 2360 "Addr", 2361 "Depend", 2362 "Stat", 2363 "Cnt"); 2364 for( i = 0 ; i <= max ; i ++){ 2365 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2366 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2367 key = cmd & OHCI_KEY_MASK; 2368 stat = res >> OHCI_STATUS_SHIFT; 2369 #if defined(__DragonFly__) || __FreeBSD_version < 500000 2370 kprintf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2371 db_tr->bus_addr, 2372 #else 2373 kprintf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2374 (uintmax_t)db_tr->bus_addr, 2375 #endif 2376 dbcode[(cmd >> 28) & 0xf], 2377 dbkey[(cmd >> 24) & 0x7], 2378 dbcond[(cmd >> 20) & 0x3], 2379 dbcond[(cmd >> 18) & 0x3], 2380 cmd & OHCI_COUNT_MASK, 2381 FWOHCI_DMA_READ(db[i].db.desc.addr), 2382 FWOHCI_DMA_READ(db[i].db.desc.depend), 2383 stat, 2384 res & OHCI_COUNT_MASK); 2385 if(stat & 0xff00){ 2386 kprintf(" %s%s%s%s%s%s %s(%x)\n", 2387 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2388 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2389 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2390 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2391 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2392 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2393 fwohcicode[stat & 0x1f], 2394 stat & 0x1f 2395 ); 2396 }else{ 2397 kprintf(" Nostat\n"); 2398 } 2399 if(key == OHCI_KEY_ST2 ){ 2400 kprintf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2401 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2402 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2403 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2404 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2405 } 2406 if(key == OHCI_KEY_DEVICE){ 2407 return; 2408 } 2409 if((cmd & OHCI_BRANCH_MASK) 2410 == OHCI_BRANCH_ALWAYS){ 2411 return; 2412 } 2413 if((cmd & OHCI_CMD_MASK) 2414 == OHCI_OUTPUT_LAST){ 2415 return; 2416 } 2417 if((cmd & OHCI_CMD_MASK) 2418 == OHCI_INPUT_LAST){ 2419 return; 2420 } 2421 if(key == OHCI_KEY_ST2 ){ 2422 i++; 2423 } 2424 } 2425 return; 2426 } 2427 2428 void 2429 fwohci_ibr(struct firewire_comm *fc) 2430 { 2431 struct fwohci_softc *sc; 2432 u_int32_t fun; 2433 2434 device_printf(fc->dev, "Initiate bus reset\n"); 2435 sc = (struct fwohci_softc *)fc; 2436 2437 /* 2438 * Set root hold-off bit so that non cyclemaster capable node 2439 * shouldn't became the root node. 2440 */ 2441 #if 1 2442 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2443 fun |= FW_PHY_IBR | FW_PHY_RHB; 2444 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2445 #else /* Short bus reset */ 2446 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2447 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2448 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2449 #endif 2450 } 2451 2452 void 2453 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2454 { 2455 struct fwohcidb_tr *db_tr, *fdb_tr; 2456 struct fwohci_dbch *dbch; 2457 struct fwohcidb *db; 2458 struct fw_pkt *fp; 2459 struct fwohci_txpkthdr *ohcifp; 2460 unsigned short chtag; 2461 int idb; 2462 2463 dbch = &sc->it[dmach]; 2464 chtag = sc->it[dmach].xferq.flag & 0xff; 2465 2466 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2467 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2468 /* 2469 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2470 */ 2471 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2472 db = db_tr->db; 2473 fp = (struct fw_pkt *)db_tr->buf; 2474 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2475 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2476 ohcifp->mode.common.spd = 0 & 0x7; 2477 ohcifp->mode.stream.len = fp->mode.stream.len; 2478 ohcifp->mode.stream.chtag = chtag; 2479 ohcifp->mode.stream.tcode = 0xa; 2480 #if BYTE_ORDER == BIG_ENDIAN 2481 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2482 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2483 #endif 2484 2485 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2486 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2487 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2488 #if 0 /* if bulkxfer->npackets changes */ 2489 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2490 | OHCI_UPDATE 2491 | OHCI_BRANCH_ALWAYS; 2492 db[0].db.desc.depend = 2493 = db[dbch->ndesc - 1].db.desc.depend 2494 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2495 #else 2496 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2497 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2498 #endif 2499 bulkxfer->end = (caddr_t)db_tr; 2500 db_tr = STAILQ_NEXT(db_tr, link); 2501 } 2502 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2503 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2504 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2505 #if 0 /* if bulkxfer->npackets changes */ 2506 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2507 /* OHCI 1.1 and above */ 2508 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2509 #endif 2510 /* 2511 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2512 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2513 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2514 */ 2515 return; 2516 } 2517 2518 static int 2519 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2520 int poffset) 2521 { 2522 struct fwohcidb *db = db_tr->db; 2523 struct fw_xferq *it; 2524 int err = 0; 2525 2526 it = &dbch->xferq; 2527 if(it->buf == 0){ 2528 err = EINVAL; 2529 return err; 2530 } 2531 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2532 db_tr->dbcnt = 3; 2533 2534 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2535 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2536 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2537 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2538 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2539 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); 2540 2541 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2542 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2543 #if 1 2544 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2545 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2546 #endif 2547 return 0; 2548 } 2549 2550 int 2551 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2552 int poffset, struct fwdma_alloc *dummy_dma) 2553 { 2554 struct fwohcidb *db = db_tr->db; 2555 struct fw_xferq *ir; 2556 int i, ldesc; 2557 bus_addr_t dbuf[2]; 2558 int dsiz[2]; 2559 2560 ir = &dbch->xferq; 2561 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2562 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2563 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2564 if (db_tr->buf == NULL) 2565 return(ENOMEM); 2566 db_tr->dbcnt = 1; 2567 dsiz[0] = ir->psize; 2568 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2569 BUS_DMASYNC_PREREAD); 2570 } else { 2571 db_tr->dbcnt = 0; 2572 if (dummy_dma != NULL) { 2573 dsiz[db_tr->dbcnt] = sizeof(u_int32_t); 2574 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2575 } 2576 dsiz[db_tr->dbcnt] = ir->psize; 2577 if (ir->buf != NULL) { 2578 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2579 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2580 } 2581 db_tr->dbcnt++; 2582 } 2583 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2584 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2585 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2586 if (ir->flag & FWXFERQ_STREAM) { 2587 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2588 } 2589 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2590 } 2591 ldesc = db_tr->dbcnt - 1; 2592 if (ir->flag & FWXFERQ_STREAM) { 2593 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2594 } 2595 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2596 return 0; 2597 } 2598 2599 2600 static int 2601 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2602 { 2603 struct fw_pkt *fp0; 2604 u_int32_t ld0; 2605 int slen, hlen; 2606 #if BYTE_ORDER == BIG_ENDIAN 2607 int i; 2608 #endif 2609 2610 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2611 #if 0 2612 kprintf("ld0: x%08x\n", ld0); 2613 #endif 2614 fp0 = (struct fw_pkt *)&ld0; 2615 /* determine length to swap */ 2616 switch (fp0->mode.common.tcode) { 2617 case FWTCODE_RREQQ: 2618 case FWTCODE_WRES: 2619 case FWTCODE_WREQQ: 2620 case FWTCODE_RRESQ: 2621 case FWOHCITCODE_PHY: 2622 slen = 12; 2623 break; 2624 case FWTCODE_RREQB: 2625 case FWTCODE_WREQB: 2626 case FWTCODE_LREQ: 2627 case FWTCODE_RRESB: 2628 case FWTCODE_LRES: 2629 slen = 16; 2630 break; 2631 default: 2632 kprintf("Unknown tcode %d\n", fp0->mode.common.tcode); 2633 return(0); 2634 } 2635 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2636 if (hlen > len) { 2637 if (firewire_debug) 2638 kprintf("splitted header\n"); 2639 return(-hlen); 2640 } 2641 #if BYTE_ORDER == BIG_ENDIAN 2642 for(i = 0; i < slen/4; i ++) 2643 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2644 #endif 2645 return(hlen); 2646 } 2647 2648 static int 2649 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2650 { 2651 struct tcode_info *info; 2652 int r; 2653 2654 info = &tinfo[fp->mode.common.tcode]; 2655 r = info->hdr_len + sizeof(u_int32_t); 2656 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2657 r += roundup2(fp->mode.wreqb.len, sizeof(u_int32_t)); 2658 2659 if (r == sizeof(u_int32_t)) 2660 /* XXX */ 2661 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2662 fp->mode.common.tcode); 2663 2664 if (r > dbch->xferq.psize) { 2665 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2666 /* panic ? */ 2667 } 2668 2669 return r; 2670 } 2671 2672 static void 2673 fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) 2674 { 2675 struct fwohcidb *db = &db_tr->db[0]; 2676 2677 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2678 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2679 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2680 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); 2681 dbch->bottom = db_tr; 2682 } 2683 2684 static void 2685 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2686 { 2687 struct fwohcidb_tr *db_tr; 2688 struct iovec vec[2]; 2689 struct fw_pkt pktbuf; 2690 int nvec; 2691 struct fw_pkt *fp; 2692 u_int8_t *ld; 2693 u_int32_t stat, off, status; 2694 u_int spd; 2695 int len, plen, hlen, pcnt, offset; 2696 caddr_t buf; 2697 int resCount; 2698 2699 if(&sc->arrq == dbch){ 2700 off = OHCI_ARQOFF; 2701 }else if(&sc->arrs == dbch){ 2702 off = OHCI_ARSOFF; 2703 }else{ 2704 return; 2705 } 2706 2707 crit_enter(); 2708 db_tr = dbch->top; 2709 pcnt = 0; 2710 /* XXX we cannot handle a packet which lies in more than two buf */ 2711 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); 2712 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); 2713 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2714 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2715 #if 0 2716 kprintf("status 0x%04x, resCount 0x%04x\n", status, resCount); 2717 #endif 2718 while (status & OHCI_CNTL_DMA_ACTIVE) { 2719 len = dbch->xferq.psize - resCount; 2720 ld = (u_int8_t *)db_tr->buf; 2721 if (dbch->pdb_tr == NULL) { 2722 len -= dbch->buf_offset; 2723 ld += dbch->buf_offset; 2724 } 2725 if (len > 0) 2726 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2727 BUS_DMASYNC_POSTREAD); 2728 while (len > 0 ) { 2729 if (count >= 0 && count-- == 0) 2730 goto out; 2731 if(dbch->pdb_tr != NULL){ 2732 /* we have a fragment in previous buffer */ 2733 int rlen; 2734 2735 offset = dbch->buf_offset; 2736 if (offset < 0) 2737 offset = - offset; 2738 buf = dbch->pdb_tr->buf + offset; 2739 rlen = dbch->xferq.psize - offset; 2740 if (firewire_debug) 2741 kprintf("rlen=%d, offset=%d\n", 2742 rlen, dbch->buf_offset); 2743 if (dbch->buf_offset < 0) { 2744 /* splitted in header, pull up */ 2745 char *p; 2746 2747 p = (char *)&pktbuf; 2748 bcopy(buf, p, rlen); 2749 p += rlen; 2750 /* this must be too long but harmless */ 2751 rlen = sizeof(pktbuf) - rlen; 2752 if (rlen < 0) 2753 kprintf("why rlen < 0\n"); 2754 bcopy(db_tr->buf, p, rlen); 2755 ld += rlen; 2756 len -= rlen; 2757 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2758 if (hlen < 0) { 2759 kprintf("hlen < 0 shouldn't happen"); 2760 } 2761 offset = sizeof(pktbuf); 2762 vec[0].iov_base = (char *)&pktbuf; 2763 vec[0].iov_len = offset; 2764 } else { 2765 /* splitted in payload */ 2766 offset = rlen; 2767 vec[0].iov_base = buf; 2768 vec[0].iov_len = rlen; 2769 } 2770 fp=(struct fw_pkt *)vec[0].iov_base; 2771 nvec = 1; 2772 } else { 2773 /* no fragment in previous buffer */ 2774 fp=(struct fw_pkt *)ld; 2775 hlen = fwohci_arcv_swap(fp, len); 2776 if (hlen == 0) 2777 /* XXX need reset */ 2778 goto out; 2779 if (hlen < 0) { 2780 dbch->pdb_tr = db_tr; 2781 dbch->buf_offset = - dbch->buf_offset; 2782 /* sanity check */ 2783 if (resCount != 0) 2784 kprintf("resCount = %d !?\n", 2785 resCount); 2786 /* XXX clear pdb_tr */ 2787 goto out; 2788 } 2789 offset = 0; 2790 nvec = 0; 2791 } 2792 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2793 if (plen < 0) { 2794 /* minimum header size + trailer 2795 = sizeof(fw_pkt) so this shouldn't happens */ 2796 kprintf("plen(%d) is negative! offset=%d\n", 2797 plen, offset); 2798 /* XXX clear pdb_tr */ 2799 goto out; 2800 } 2801 if (plen > 0) { 2802 len -= plen; 2803 if (len < 0) { 2804 dbch->pdb_tr = db_tr; 2805 if (firewire_debug) 2806 kprintf("splitted payload\n"); 2807 /* sanity check */ 2808 if (resCount != 0) 2809 kprintf("resCount = %d !?\n", 2810 resCount); 2811 /* XXX clear pdb_tr */ 2812 goto out; 2813 } 2814 vec[nvec].iov_base = ld; 2815 vec[nvec].iov_len = plen; 2816 nvec ++; 2817 ld += plen; 2818 } 2819 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; 2820 if (nvec == 0) 2821 kprintf("nvec == 0\n"); 2822 2823 /* DMA result-code will be written at the tail of packet */ 2824 #if BYTE_ORDER == BIG_ENDIAN 2825 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; 2826 #else 2827 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2828 #endif 2829 #if 0 2830 kprintf("plen: %d, stat %x\n", 2831 plen ,stat); 2832 #endif 2833 spd = (stat >> 5) & 0x3; 2834 stat &= 0x1f; 2835 switch(stat){ 2836 case FWOHCIEV_ACKPEND: 2837 #if 0 2838 kprintf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2839 #endif 2840 /* fall through */ 2841 case FWOHCIEV_ACKCOMPL: 2842 { 2843 struct fw_rcv_buf rb; 2844 2845 if ((vec[nvec-1].iov_len -= 2846 sizeof(struct fwohci_trailer)) == 0) 2847 nvec--; 2848 rb.fc = &sc->fc; 2849 rb.vec = vec; 2850 rb.nvec = nvec; 2851 rb.spd = spd; 2852 fw_rcv(&rb); 2853 break; 2854 } 2855 case FWOHCIEV_BUSRST: 2856 if (sc->fc.status != FWBUSRESET) 2857 kprintf("got BUSRST packet!?\n"); 2858 break; 2859 default: 2860 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2861 #if 0 /* XXX */ 2862 goto out; 2863 #endif 2864 break; 2865 } 2866 pcnt ++; 2867 if (dbch->pdb_tr != NULL) { 2868 fwohci_arcv_free_buf(dbch, dbch->pdb_tr); 2869 dbch->pdb_tr = NULL; 2870 } 2871 2872 } 2873 out: 2874 if (resCount == 0) { 2875 /* done on this buffer */ 2876 if (dbch->pdb_tr == NULL) { 2877 fwohci_arcv_free_buf(dbch, db_tr); 2878 dbch->buf_offset = 0; 2879 } else 2880 if (dbch->pdb_tr != db_tr) 2881 kprintf("pdb_tr != db_tr\n"); 2882 db_tr = STAILQ_NEXT(db_tr, link); 2883 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2884 >> OHCI_STATUS_SHIFT; 2885 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 2886 & OHCI_COUNT_MASK; 2887 /* XXX check buffer overrun */ 2888 dbch->top = db_tr; 2889 } else { 2890 dbch->buf_offset = dbch->xferq.psize - resCount; 2891 break; 2892 } 2893 /* XXX make sure DMA is not dead */ 2894 } 2895 #if 0 2896 if (pcnt < 1) 2897 kprintf("fwohci_arcv: no packets\n"); 2898 #endif 2899 crit_exit(); 2900 } 2901