1bca7db71SImre Vadász#- 2bca7db71SImre Vadász# Copyright (c) 2016 The DragonFly Project. All rights reserved. 3bca7db71SImre Vadász# 4bca7db71SImre Vadász# This code is derived from software contributed to The DragonFly Project 5bca7db71SImre Vadász# by Imre Vadász <imre@vdsz.com> 6bca7db71SImre Vadász# 7bca7db71SImre Vadász# Redistribution and use in source and binary forms, with or without 8bca7db71SImre Vadász# modification, are permitted provided that the following conditions 9bca7db71SImre Vadász# are met: 10bca7db71SImre Vadász# 11bca7db71SImre Vadász# 1. Redistributions of source code must retain the above copyright 12bca7db71SImre Vadász# notice, this list of conditions and the following disclaimer. 13bca7db71SImre Vadász# 2. Redistributions in binary form must reproduce the above copyright 14bca7db71SImre Vadász# notice, this list of conditions and the following disclaimer in 15bca7db71SImre Vadász# the documentation and/or other materials provided with the 16bca7db71SImre Vadász# distribution. 17bca7db71SImre Vadász# 3. Neither the name of The DragonFly Project nor the names of its 18bca7db71SImre Vadász# contributors may be used to endorse or promote products derived 19bca7db71SImre Vadász# from this software without specific, prior written permission. 20bca7db71SImre Vadász# 21bca7db71SImre Vadász# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22bca7db71SImre Vadász# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23bca7db71SImre Vadász# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24bca7db71SImre Vadász# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25bca7db71SImre Vadász# COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26bca7db71SImre Vadász# INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27bca7db71SImre Vadász# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28bca7db71SImre Vadász# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29bca7db71SImre Vadász# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30bca7db71SImre Vadász# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31bca7db71SImre Vadász# OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32bca7db71SImre Vadász# SUCH DAMAGE. 33bca7db71SImre Vadász# 34bca7db71SImre Vadász 35bca7db71SImre Vadász#include <sys/bus.h> 36bca7db71SImre Vadász 37bca7db71SImre VadászINTERFACE gpio; 38bca7db71SImre Vadász 39bca7db71SImre Vadász# 40*0b0166b0SImre Vadász# Allocate GPIO interrupt. 41bca7db71SImre Vadász# XXX trigger, polarity and termination constants are currently used from 42bca7db71SImre Vadász# sys/contrib/dev/acpica/source/include/acrestyp.h 43bca7db71SImre Vadász# 44bca7db71SImre VadászMETHOD int alloc_intr { 45bca7db71SImre Vadász device_t dev; 46bca7db71SImre Vadász u_int pin; 47bca7db71SImre Vadász int trigger; 48bca7db71SImre Vadász int polarity; 49bca7db71SImre Vadász int termination; 50*0b0166b0SImre Vadász}; 51*0b0166b0SImre Vadász 52*0b0166b0SImre Vadász# 53*0b0166b0SImre Vadász# Deallocate GPIO interrupt. 54*0b0166b0SImre Vadász# 55*0b0166b0SImre VadászMETHOD int free_intr { 56*0b0166b0SImre Vadász device_t dev; 57*0b0166b0SImre Vadász u_int pin; 58*0b0166b0SImre Vadász}; 59*0b0166b0SImre Vadász 60*0b0166b0SImre Vadász# 61*0b0166b0SImre Vadász# Setup GPIO interrupt. 62*0b0166b0SImre Vadász# 63*0b0166b0SImre VadászMETHOD int setup_intr { 64*0b0166b0SImre Vadász device_t dev; 65*0b0166b0SImre Vadász u_int pin; 66bca7db71SImre Vadász void *arg; 67bca7db71SImre Vadász driver_intr_t *handler; 68bca7db71SImre Vadász}; 69bca7db71SImre Vadász 70bca7db71SImre Vadász# 71*0b0166b0SImre Vadász# Disable GPIO interrupt. 72bca7db71SImre Vadász# 73*0b0166b0SImre VadászMETHOD int teardown_intr { 74bca7db71SImre Vadász device_t dev; 75bca7db71SImre Vadász u_int pin; 76bca7db71SImre Vadász}; 77bca7db71SImre Vadász 78bca7db71SImre Vadász# 79bca7db71SImre Vadász# XXX Add a method for allocating pins for read/write IO. 80bca7db71SImre Vadász# Allocating a pin for IO should perform the necessary checks to 81bca7db71SImre Vadász# make sure that read_/write_pin doesn't trigger an assertion. 82bca7db71SImre Vadász# 83bca7db71SImre Vadász 84bca7db71SImre Vadász# 85bca7db71SImre Vadász# Read pin value, returns 0 or 1. 86bca7db71SImre Vadász# 87bca7db71SImre VadászMETHOD int read_pin { 88bca7db71SImre Vadász device_t dev; 89bca7db71SImre Vadász u_int pin; 90bca7db71SImre Vadász}; 91bca7db71SImre Vadász 92bca7db71SImre Vadász# 93bca7db71SImre Vadász# Write pin value, value can be either 0 or 1. 94bca7db71SImre Vadász# 95bca7db71SImre VadászMETHOD void write_pin { 96bca7db71SImre Vadász device_t dev; 97bca7db71SImre Vadász u_int pin; 98bca7db71SImre Vadász int value; 99bca7db71SImre Vadász}; 100