1 /* 2 * Copyright (c) 1996, Sujal M. Patel 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Sujal M. Patel 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/isa/pnpreg.h,v 1.3.2.1 2000/05/11 11:10:35 nyan Exp $ 33 * $DragonFly: src/sys/bus/isa/pnpreg.h,v 1.3 2005/06/12 20:55:14 swildner Exp $ 34 * from: pnp.h,v 1.7 1998/09/13 22:15:44 eivind Exp 35 */ 36 37 #ifndef _ISA_PNPREG_H_ 38 #define _ISA_PNPREG_H_ 39 40 /* Maximum Number of PnP Devices. 8 should be plenty */ 41 #define PNP_MAX_CARDS 8 42 43 #if 0 44 /* 45 * the following is the maximum number of PnP Logical devices that 46 * userconfig can handle. 47 */ 48 #define MAX_PNP_LDN 20 49 #endif 50 51 /* Static ports to access PnP state machine */ 52 #define _PNP_ADDRESS 0x279 53 #define _PNP_WRITE_DATA 0xa79 54 55 /* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */ 56 #define PNP_SET_RD_DATA 0x00 57 /*** 58 Writing to this location modifies the address of the port used for 59 reading from the Plug and Play ISA cards. Bits[7:0] become I/O 60 read port address bits[9:2]. Reads from this register are ignored. 61 ***/ 62 63 #define PNP_SERIAL_ISOLATION 0x01 64 /*** 65 A read to this register causes a Plug and Play cards in the Isolation 66 state to compare one bit of the boards ID. 67 This register is read only. 68 ***/ 69 70 #define PNP_CONFIG_CONTROL 0x02 71 #define PNP_CONFIG_CONTROL_RESET_CSN 0x04 72 #define PNP_CONFIG_CONTROL_WAIT_FOR_KEY 0x02 73 #define PNP_CONFIG_CONTROL_RESET 0x01 74 /*** 75 Bit[2] Reset CSN to 0 76 Bit[1] Return to the Wait for Key state 77 Bit[0] Reset all logical devices and restore configuration 78 registers to their power-up values. 79 80 A write to bit[0] of this register performs a reset function on 81 all logical devices. This resets the contents of configuration 82 registers to their default state. All card's logical devices 83 enter their default state and the CSN is preserved. 84 85 A write to bit[1] of this register causes all cards to enter the 86 Wait for Key state but all CSNs are preserved and logical devices 87 are not affected. 88 89 A write to bit[2] of this register causes all cards to reset their 90 CSN to zero . 91 92 This register is write-only. The values are not sticky, that is, 93 hardware will automatically clear them and there is no need for 94 software to clear the bits. 95 ***/ 96 97 #define PNP_WAKE 0x03 98 /*** 99 A write to this port will cause all cards that have a CSN that 100 matches the write data[7:0] to go from the Sleep state to the either 101 the Isolation state if the write data for this command is zero or 102 the Config state if the write data is not zero. Additionally, the 103 pointer to the byte-serial device is reset. This register is 104 writeonly. 105 ***/ 106 107 #define PNP_RESOURCE_DATA 0x04 108 /*** 109 A read from this address reads the next byte of resource information. 110 The Status register must be polled until bit[0] is set before this 111 register may be read. This register is read only. 112 ***/ 113 114 #define PNP_STATUS 0x05 115 /*** 116 Bit[0] when set indicates it is okay to read the next data byte 117 from the Resource Data register. This register is readonly. 118 ***/ 119 120 #define PNP_SET_CSN 0x06 121 /*** 122 A write to this port sets a card's CSN. The CSN is a value uniquely 123 assigned to each ISA card after the serial identification process 124 so that each card may be individually selected during a Wake[CSN] 125 command. This register is read/write. 126 ***/ 127 128 #define PNP_SET_LDN 0x07 129 /*** 130 Selects the current logical device. All reads and writes of memory, 131 I/O, interrupt and DMA configuration information access the registers 132 of the logical device written here. In addition, the I/O Range 133 Check and Activate commands operate only on the selected logical 134 device. This register is read/write. If a card has only 1 logical 135 device, this location should be a read-only value of 0x00. 136 ***/ 137 138 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/ 139 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/ 140 141 #define PNP_ACTIVATE 0x30 142 /*** 143 For each logical device there is one activate register that controls 144 whether or not the logical device is active on the ISA bus. Bit[0], 145 if set, activates the logical device. Bits[7:1] are reserved and 146 must return 0 on reads. This is a read/write register. Before a 147 logical device is activated, I/O range check must be disabled. 148 ***/ 149 150 #define PNP_IO_RANGE_CHECK 0x31 151 #define PNP_IO_RANGE_CHECK_ENABLE 0x02 152 #define PNP_IO_RANGE_CHECK_READ_AS_55 0x01 153 /*** 154 This register is used to perform a conflict check on the I/O port 155 range programmed for use by a logical device. 156 157 Bit[7:2] Reserved and must return 0 on reads 158 Bit[1] Enable I/O Range check, if set then I/O Range Check 159 is enabled. I/O range check is only valid when the logical 160 device is inactive. 161 162 Bit[0], if set, forces the logical device to respond to I/O reads 163 of the logical device's assigned I/O range with a 0x55 when I/O 164 range check is in operation. If clear, the logical device drives 165 0xAA. This register is read/write. 166 ***/ 167 168 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/ 169 /*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/ 170 171 #define PNP_MEM_BASE_HIGH(i) (0x40 + 8*(i)) 172 #define PNP_MEM_BASE_LOW(i) (0x41 + 8*(i)) 173 #define PNP_MEM_CONTROL(i) (0x42 * 8*(i)) 174 #define PNP_MEM_CONTROL_16BIT 0x2 175 #define PNP_MEM_CONTROL_LIMIT 0x1 176 #define PNP_MEM_RANGE_HIGH(i) (0x43 + 8*(i)) 177 #define PNP_MEM_RANGE_LOW(i) (0x44 + 8*(i)) 178 /*** 179 Four memory resource registers per range, four ranges. 180 Fill with 0 if no ranges are enabled. 181 182 Offset 0: RW Memory base address bits[23:16] 183 Offset 1: RW Memory base address bits[15:8] 184 Offset 2: Memory control 185 Bit[1] specifies 8/16-bit control. This bit is set to indicate 186 16-bit memory, and cleared to indicate 8-bit memory. 187 Bit[0], if cleared, indicates the next field can be used as a range 188 length for decode (implies range length and base alignment of memory 189 descriptor are equal). 190 Bit[0], if set, indicates the next field is the upper limit for 191 the address. - - Bit[0] is read-only. 192 Offset 3: RW upper limit or range len, bits[23:16] 193 Offset 4: RW upper limit or range len, bits[15:8] 194 Offset 5-Offset 7: filler, unused. 195 ***/ 196 197 #define PNP_IO_BASE_HIGH(i) (0x60 + 2*(i)) 198 #define PNP_IO_BASE_LOW(i) (0x61 + 2*(i)) 199 /*** 200 Eight ranges, two bytes per range. 201 Offset 0: I/O port base address bits[15:8] 202 Offset 1: I/O port base address bits[7:0] 203 ***/ 204 205 #define PNP_IRQ_LEVEL(i) (0x70 + 2*(i)) 206 #define PNP_IRQ_TYPE(i) (0x71 + 2*(i)) 207 /*** 208 Two entries, two bytes per entry. 209 Offset 0: RW interrupt level (1..15, 0=unused). 210 Offset 1: Bit[1]: level(1:hi, 0:low), 211 Bit[0]: type (1:level, 0:edge) 212 byte 1 can be readonly if 1 type of int is used. 213 ***/ 214 215 #define PNP_DMA_CHANNEL(i) (0x74 + 1*(i)) 216 /*** 217 Two entries, one byte per entry. Bits[2:0] select 218 which DMA channel is in use for DMA 0. Zero selects DMA channel 219 0, seven selects DMA channel 7. DMA channel 4, the cascade channel 220 is used to indicate no DMA channel is active. 221 ***/ 222 223 /*** 32-bit memory accesses are at 0x76 ***/ 224 225 /* Macros to parse Resource IDs */ 226 #define PNP_RES_TYPE(a) (a >> 7) 227 #define PNP_SRES_NUM(a) (a >> 3) 228 #define PNP_SRES_LEN(a) (a & 0x07) 229 #define PNP_LRES_NUM(a) (a & 0x7f) 230 231 /* Small Resource Item names */ 232 #define PNP_TAG_VERSION 0x1 233 #define PNP_TAG_LOGICAL_DEVICE 0x2 234 #define PNP_TAG_COMPAT_DEVICE 0x3 235 #define PNP_TAG_IRQ_FORMAT 0x4 236 #define PNP_TAG_DMA_FORMAT 0x5 237 #define PNP_TAG_START_DEPENDANT 0x6 238 #define PNP_TAG_END_DEPENDANT 0x7 239 #define PNP_TAG_IO_RANGE 0x8 240 #define PNP_TAG_IO_FIXED 0x9 241 #define PNP_TAG_RESERVED 0xa-0xd 242 #define PNP_TAG_VENDOR 0xe 243 #define PNP_TAG_END 0xf 244 245 /* Large Resource Item names */ 246 #define PNP_TAG_MEMORY_RANGE 0x1 247 #define PNP_TAG_ID_ANSI 0x2 248 #define PNP_TAG_ID_UNICODE 0x3 249 #define PNP_TAG_LARGE_VENDOR 0x4 250 #define PNP_TAG_MEMORY32_RANGE 0x5 251 #define PNP_TAG_MEMORY32_FIXED 0x6 252 #define PNP_TAG_LARGE_RESERVED 0x7-0x7f 253 254 #endif /* !_ISA_PNPREG_H_ */ 255