1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 33 * $FreeBSD: src/sys/i386/isa/isa_dma.c,v 1.4.2.1 2000/08/08 19:49:53 peter Exp $ 34 */ 35 36 /* 37 * code to manage AT bus 38 * 39 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 40 * Fixed uninitialized variable problem and added code to deal 41 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 42 * mode DMA count compution and reorganized DMA setup code in 43 * isa_dmastart() 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/bus.h> 49 #include <sys/kernel.h> 50 #include <sys/malloc.h> 51 #include <sys/buf.h> 52 #include <vm/vm.h> 53 #include <vm/vm_param.h> 54 #include <vm/pmap.h> 55 #include "isa.h" 56 #include <machine_base/isa/ic/i8237.h> 57 #include <machine/pmap.h> 58 #include <bus/isa/isavar.h> 59 60 /* 61 ** Register definitions for DMA controller 1 (channels 0..3): 62 */ 63 #define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 64 #define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 65 #define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 66 #define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 67 68 /* 69 ** Register definitions for DMA controller 2 (channels 4..7): 70 */ 71 #define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 72 #define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 73 #define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 74 #define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 75 76 static int isa_dmarangecheck (caddr_t va, u_int length, int chan); 77 78 static caddr_t dma_bouncebuf[8]; 79 static u_int dma_bouncebufsize[8]; 80 static u_int8_t dma_bounced = 0; 81 static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 82 static u_int8_t dma_inuse = 0; /* User for acquire/release */ 83 static u_int8_t dma_auto_mode = 0; 84 85 #define VALID_DMA_MASK (7) 86 87 /* high byte of address is stored in this port for i-th dma channel */ 88 static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 89 90 /* 91 * Setup a DMA channel's bounce buffer. 92 */ 93 int 94 isa_dma_init(int chan, u_int bouncebufsize, int flags) 95 { 96 void *buf; 97 98 #ifdef DIAGNOSTIC 99 if (chan & ~VALID_DMA_MASK) 100 panic("isa_dma_init: channel out of range"); 101 102 if (dma_bouncebuf[chan] != NULL) 103 panic("isa_dma_init: impossible request"); 104 #endif 105 106 /* Try malloc() first. It works better if it works. */ 107 buf = kmalloc(bouncebufsize, M_DEVBUF, flags); 108 if (buf != NULL) { 109 if (isa_dmarangecheck(buf, bouncebufsize, chan) != 0) { 110 kfree(buf, M_DEVBUF); 111 buf = NULL; 112 if (bootverbose) 113 kprintf("isa_dma_init: kmalloc rejected\n"); 114 } 115 } 116 117 if (buf == NULL) { 118 buf = contigmalloc(bouncebufsize, M_DEVBUF, flags, 0ul, 0xfffffful, 119 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 120 } 121 122 if (buf == NULL) { 123 kprintf("isa_dma_init(%d, %d) failed\n", chan, bouncebufsize); 124 return ENOMEM; 125 } 126 127 dma_bouncebufsize[chan] = bouncebufsize; 128 dma_bouncebuf[chan] = buf; 129 130 return 0; 131 } 132 133 /* 134 * Register a DMA channel's usage. Usually called from a device driver 135 * in open() or during its initialization. 136 */ 137 int 138 isa_dma_acquire(int chan) 139 { 140 #ifdef DIAGNOSTIC 141 if (chan & ~VALID_DMA_MASK) 142 panic("isa_dma_acquire: channel out of range"); 143 #endif 144 145 if (dma_inuse & (1 << chan)) { 146 kprintf("isa_dma_acquire: channel %d already in use\n", chan); 147 return (EBUSY); 148 } 149 dma_inuse |= (1 << chan); 150 dma_auto_mode &= ~(1 << chan); 151 152 return (0); 153 } 154 155 /* 156 * Unregister a DMA channel's usage. Usually called from a device driver 157 * during close() or during its shutdown. 158 */ 159 void 160 isa_dma_release(int chan) 161 { 162 #ifdef DIAGNOSTIC 163 if (chan & ~VALID_DMA_MASK) 164 panic("isa_dma_release: channel out of range"); 165 166 if ((dma_inuse & (1 << chan)) == 0) 167 kprintf("isa_dma_release: channel %d not in use\n", chan); 168 #endif 169 170 if (dma_busy & (1 << chan)) { 171 dma_busy &= ~(1 << chan); 172 /* 173 * XXX We should also do "dma_bounced &= (1 << chan);" 174 * because we are acting on behalf of isa_dmadone() which 175 * was not called to end the last DMA operation. This does 176 * not matter now, but it may in the future. 177 */ 178 } 179 180 dma_inuse &= ~(1 << chan); 181 dma_auto_mode &= ~(1 << chan); 182 } 183 184 /* 185 * isa_dmacascade(): program 8237 DMA controller channel to accept 186 * external dma control by a board. 187 */ 188 void 189 isa_dmacascade(int chan) 190 { 191 #ifdef DIAGNOSTIC 192 if (chan & ~VALID_DMA_MASK) 193 panic("isa_dmacascade: channel out of range"); 194 #endif 195 196 /* set dma channel mode, and set dma channel mode */ 197 if ((chan & 4) == 0) { 198 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 199 outb(DMA1_SMSK, chan); 200 } else { 201 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 202 outb(DMA2_SMSK, chan & 3); 203 } 204 } 205 206 /* 207 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 208 * problems by using a bounce buffer. 209 */ 210 void 211 isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 212 { 213 vm_paddr_t phys; 214 int waport; 215 caddr_t newaddr; 216 217 #ifdef DIAGNOSTIC 218 if (chan & ~VALID_DMA_MASK) 219 panic("isa_dmastart: channel out of range"); 220 221 if ((chan < 4 && nbytes > (1<<16)) 222 || (chan >= 4 && (nbytes > (1<<17) || (u_int)(uintptr_t)addr & 1))) 223 panic("isa_dmastart: impossible request"); 224 225 if ((dma_inuse & (1 << chan)) == 0) 226 kprintf("isa_dmastart: channel %d not acquired\n", chan); 227 #endif 228 229 #if 0 230 /* 231 * XXX This should be checked, but drivers like ad1848 only call 232 * isa_dmastart() once because they use Auto DMA mode. If we 233 * leave this in, drivers that do this will print this continuously. 234 */ 235 if (dma_busy & (1 << chan)) 236 kprintf("isa_dmastart: channel %d busy\n", chan); 237 #endif 238 239 dma_busy |= (1 << chan); 240 241 if (isa_dmarangecheck(addr, nbytes, chan)) { 242 if (dma_bouncebuf[chan] == NULL 243 || dma_bouncebufsize[chan] < nbytes) 244 panic("isa_dmastart: bad bounce buffer"); 245 dma_bounced |= (1 << chan); 246 newaddr = dma_bouncebuf[chan]; 247 248 /* copy bounce buffer on write */ 249 if (flags & ISADMA_WRITE) 250 bcopy(addr, newaddr, nbytes); 251 addr = newaddr; 252 } 253 254 /* translate to physical */ 255 phys = pmap_kextract((vm_offset_t)addr); 256 257 if (flags & ISADMA_RAW) { 258 dma_auto_mode |= (1 << chan); 259 } else { 260 dma_auto_mode &= ~(1 << chan); 261 } 262 263 if ((chan & 4) == 0) { 264 /* 265 * Program one of DMA channels 0..3. These are 266 * byte mode channels. 267 */ 268 /* set dma channel mode, and reset address ff */ 269 270 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 271 if (flags & ISADMA_RAW) { 272 if (flags & ISADMA_READ) 273 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 274 else 275 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 276 } 277 else 278 if (flags & ISADMA_READ) 279 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 280 else 281 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 282 outb(DMA1_FFC, 0); 283 284 /* send start address */ 285 waport = DMA1_CHN(chan); 286 outb(waport, phys); 287 outb(waport, phys>>8); 288 outb(dmapageport[chan], phys>>16); 289 290 /* send count */ 291 outb(waport + 1, --nbytes); 292 outb(waport + 1, nbytes>>8); 293 294 /* unmask channel */ 295 outb(DMA1_SMSK, chan); 296 } else { 297 /* 298 * Program one of DMA channels 4..7. These are 299 * word mode channels. 300 */ 301 /* set dma channel mode, and reset address ff */ 302 303 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 304 if (flags & ISADMA_RAW) { 305 if (flags & ISADMA_READ) 306 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 307 else 308 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 309 } 310 else 311 if (flags & ISADMA_READ) 312 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 313 else 314 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 315 outb(DMA2_FFC, 0); 316 317 /* send start address */ 318 waport = DMA2_CHN(chan - 4); 319 outb(waport, phys>>1); 320 outb(waport, phys>>9); 321 outb(dmapageport[chan], phys>>16); 322 323 /* send count */ 324 nbytes >>= 1; 325 outb(waport + 2, --nbytes); 326 outb(waport + 2, nbytes>>8); 327 328 /* unmask channel */ 329 outb(DMA2_SMSK, chan & 3); 330 } 331 } 332 333 void 334 isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 335 { 336 #ifdef DIAGNOSTIC 337 if (chan & ~VALID_DMA_MASK) 338 panic("isa_dmadone: channel out of range"); 339 340 if ((dma_inuse & (1 << chan)) == 0) 341 kprintf("isa_dmadone: channel %d not acquired\n", chan); 342 #endif 343 344 if (((dma_busy & (1 << chan)) == 0) && 345 (dma_auto_mode & (1 << chan)) == 0 ) 346 kprintf("isa_dmadone: channel %d not busy\n", chan); 347 348 if ((dma_auto_mode & (1 << chan)) == 0) 349 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 350 351 if (dma_bounced & (1 << chan)) { 352 /* copy bounce buffer on read */ 353 if (flags & ISADMA_READ) 354 bcopy(dma_bouncebuf[chan], addr, nbytes); 355 356 dma_bounced &= ~(1 << chan); 357 } 358 dma_busy &= ~(1 << chan); 359 } 360 361 /* 362 * Check for problems with the address range of a DMA transfer 363 * (non-contiguous physical pages, outside of bus address space, 364 * crossing DMA page boundaries). 365 * Return true if special handling needed. 366 */ 367 368 static int 369 isa_dmarangecheck(caddr_t va, u_int length, int chan) 370 { 371 vm_paddr_t phys, priorpage = 0; 372 vm_offset_t endva; 373 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 374 375 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 376 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 377 phys = trunc_page(pmap_kextract((vm_offset_t)va)); 378 #define ISARAM_END RAM_END 379 if (phys == 0) 380 panic("isa_dmacheck: no physical page present"); 381 if (phys >= ISARAM_END) 382 return (1); 383 if (priorpage) { 384 if (priorpage + PAGE_SIZE != phys) 385 return (1); 386 /* check if crossing a DMA page boundary */ 387 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 388 return (1); 389 } 390 priorpage = phys; 391 } 392 return (0); 393 } 394 395 /* 396 * Query the progress of a transfer on a DMA channel. 397 * 398 * To avoid having to interrupt a transfer in progress, we sample 399 * each of the high and low databytes twice, and apply the following 400 * logic to determine the correct count. 401 * 402 * Reads are performed with interrupts disabled, thus it is to be 403 * expected that the time between reads is very small. At most 404 * one rollover in the low count byte can be expected within the 405 * four reads that are performed. 406 * 407 * There are three gaps in which a rollover can occur : 408 * 409 * - read low1 410 * gap1 411 * - read high1 412 * gap2 413 * - read low2 414 * gap3 415 * - read high2 416 * 417 * If a rollover occurs in gap1 or gap2, the low2 value will be 418 * greater than the low1 value. In this case, low2 and high2 are a 419 * corresponding pair. 420 * 421 * In any other case, low1 and high1 can be considered to be correct. 422 * 423 * The function returns the number of bytes remaining in the transfer, 424 * or -1 if the channel requested is not active. 425 * 426 */ 427 int 428 isa_dmastatus(int chan) 429 { 430 u_long cnt = 0; 431 int ffport, waport; 432 u_long low1, high1, low2, high2; 433 434 /* channel active? */ 435 if ((dma_inuse & (1 << chan)) == 0) { 436 kprintf("isa_dmastatus: channel %d not active\n", chan); 437 return(-1); 438 } 439 /* channel busy? */ 440 441 if (((dma_busy & (1 << chan)) == 0) && 442 (dma_auto_mode & (1 << chan)) == 0 ) { 443 kprintf("chan %d not busy\n", chan); 444 return -2 ; 445 } 446 if (chan < 4) { /* low DMA controller */ 447 ffport = DMA1_FFC; 448 waport = DMA1_CHN(chan) + 1; 449 } else { /* high DMA controller */ 450 ffport = DMA2_FFC; 451 waport = DMA2_CHN(chan - 4) + 2; 452 } 453 454 cpu_disable_intr(); /* YYY *//* no interrupts Mr Jones! */ 455 outb(ffport, 0); /* clear register LSB flipflop */ 456 low1 = inb(waport); 457 high1 = inb(waport); 458 outb(ffport, 0); /* clear again */ 459 low2 = inb(waport); 460 high2 = inb(waport); 461 cpu_enable_intr(); /* enable interrupts again */ 462 463 /* 464 * Now decide if a wrap has tried to skew our results. 465 * Note that after TC, the count will read 0xffff, while we want 466 * to return zero, so we add and then mask to compensate. 467 */ 468 if (low1 >= low2) { 469 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 470 } else { 471 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 472 } 473 474 if (chan >= 4) /* high channels move words */ 475 cnt *= 2; 476 return(cnt); 477 } 478 479 /* 480 * Stop a DMA transfer currently in progress. 481 */ 482 int 483 isa_dmastop(int chan) 484 { 485 if ((dma_inuse & (1 << chan)) == 0) 486 kprintf("isa_dmastop: channel %d not acquired\n", chan); 487 488 if (((dma_busy & (1 << chan)) == 0) && 489 ((dma_auto_mode & (1 << chan)) == 0)) { 490 kprintf("chan %d not busy\n", chan); 491 return -2 ; 492 } 493 494 if ((chan & 4) == 0) { 495 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 496 } else { 497 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 498 } 499 return(isa_dmastatus(chan)); 500 } 501 502 unsigned 503 isa_dmabp(struct buf *bp) 504 { 505 unsigned flags = 0; 506 507 KKASSERT(bp->b_cmd != BUF_CMD_DONE); 508 if (bp->b_flags & B_RAW) 509 flags |= ISADMA_RAW; 510 if (bp->b_cmd == BUF_CMD_READ) { 511 flags |= ISADMA_READ; 512 } else { 513 /* BUF_CMD_WRITE, BUF_CMD_FORMAT */ 514 flags |= ISADMA_WRITE; 515 } 516 return(flags); 517 } 518 519