1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $ 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.27 2005/06/14 16:35:42 joerg Exp $ 28 * 29 */ 30 31 #include "opt_bus.h" 32 #include "opt_pci.h" 33 34 #include "opt_simos.h" 35 #include "opt_compat_oldpci.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/fcntl.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/buf.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 #include <vm/vm_extern.h> 51 52 #include <sys/bus.h> 53 #include <machine/bus.h> 54 #include <sys/rman.h> 55 #include <machine/resource.h> 56 #include <machine/md_var.h> /* For the Alpha */ 57 #ifdef __i386__ 58 #include <bus/pci/i386/pci_cfgreg.h> 59 #endif 60 61 #include <sys/pciio.h> 62 #include "pcireg.h" 63 #include "pcivar.h" 64 #include "pci_private.h" 65 66 #include "pcib_if.h" 67 68 #ifdef APIC_IO 69 #include <machine/smp.h> 70 #endif /* APIC_IO */ 71 72 devclass_t pci_devclass; 73 74 static void pci_read_extcap(device_t dev, pcicfgregs *cfg); 75 76 struct pci_quirk { 77 u_int32_t devid; /* Vendor/device of the card */ 78 int type; 79 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 80 int arg1; 81 int arg2; 82 }; 83 84 struct pci_quirk pci_quirks[] = { 85 /* 86 * The Intel 82371AB and 82443MX has a map register at offset 0x90. 87 */ 88 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 89 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 90 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 91 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 92 93 { 0 } 94 }; 95 96 /* map register information */ 97 #define PCI_MAPMEM 0x01 /* memory map */ 98 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 99 #define PCI_MAPPORT 0x04 /* port map */ 100 101 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 102 u_int32_t pci_numdevs = 0; 103 static u_int32_t pci_generation = 0; 104 105 device_t 106 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func) 107 { 108 struct pci_devinfo *dinfo; 109 110 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 111 if ((dinfo->cfg.bus == bus) && 112 (dinfo->cfg.slot == slot) && 113 (dinfo->cfg.func == func)) { 114 return (dinfo->cfg.dev); 115 } 116 } 117 118 return (NULL); 119 } 120 121 device_t 122 pci_find_device (u_int16_t vendor, u_int16_t device) 123 { 124 struct pci_devinfo *dinfo; 125 126 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 127 if ((dinfo->cfg.vendor == vendor) && 128 (dinfo->cfg.device == device)) { 129 return (dinfo->cfg.dev); 130 } 131 } 132 133 return (NULL); 134 } 135 136 /* return base address of memory or port map */ 137 138 static u_int32_t 139 pci_mapbase(unsigned mapreg) 140 { 141 int mask = 0x03; 142 if ((mapreg & 0x01) == 0) 143 mask = 0x0f; 144 return (mapreg & ~mask); 145 } 146 147 /* return map type of memory or port map */ 148 149 static int 150 pci_maptype(unsigned mapreg) 151 { 152 static u_int8_t maptype[0x10] = { 153 PCI_MAPMEM, PCI_MAPPORT, 154 PCI_MAPMEM, 0, 155 PCI_MAPMEM, PCI_MAPPORT, 156 0, 0, 157 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 158 PCI_MAPMEM|PCI_MAPMEMP, 0, 159 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 160 0, 0, 161 }; 162 163 return maptype[mapreg & 0x0f]; 164 } 165 166 /* return log2 of map size decoded for memory or port map */ 167 168 static int 169 pci_mapsize(unsigned testval) 170 { 171 int ln2size; 172 173 testval = pci_mapbase(testval); 174 ln2size = 0; 175 if (testval != 0) { 176 while ((testval & 1) == 0) 177 { 178 ln2size++; 179 testval >>= 1; 180 } 181 } 182 return (ln2size); 183 } 184 185 /* return log2 of address range supported by map register */ 186 187 static int 188 pci_maprange(unsigned mapreg) 189 { 190 int ln2range = 0; 191 switch (mapreg & 0x07) { 192 case 0x00: 193 case 0x01: 194 case 0x05: 195 ln2range = 32; 196 break; 197 case 0x02: 198 ln2range = 20; 199 break; 200 case 0x04: 201 ln2range = 64; 202 break; 203 } 204 return (ln2range); 205 } 206 207 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 208 209 static void 210 pci_fixancient(pcicfgregs *cfg) 211 { 212 if (cfg->hdrtype != 0) 213 return; 214 215 /* PCI to PCI bridges use header type 1 */ 216 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 217 cfg->hdrtype = 1; 218 } 219 220 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 221 222 static void * 223 pci_readppb(device_t pcib, int b, int s, int f) 224 { 225 pcih1cfgregs *p; 226 227 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 228 if (p == NULL) 229 return (NULL); 230 231 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2); 232 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2); 233 234 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1); 235 236 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f, 237 PCIR_IOBASEH_1, 2), 238 PCIB_READ_CONFIG(pcib, b, s, f, 239 PCIR_IOBASEL_1, 1)); 240 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f, 241 PCIR_IOLIMITH_1, 2), 242 PCIB_READ_CONFIG(pcib, b, s, f, 243 PCIR_IOLIMITL_1, 1)); 244 245 p->membase = PCI_PPBMEMBASE (0, 246 PCIB_READ_CONFIG(pcib, b, s, f, 247 PCIR_MEMBASE_1, 2)); 248 p->memlimit = PCI_PPBMEMLIMIT (0, 249 PCIB_READ_CONFIG(pcib, b, s, f, 250 PCIR_MEMLIMIT_1, 2)); 251 252 p->pmembase = PCI_PPBMEMBASE ( 253 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4), 254 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2)); 255 256 p->pmemlimit = PCI_PPBMEMLIMIT ( 257 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, 258 PCIR_PMLIMITH_1, 4), 259 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2)); 260 261 return (p); 262 } 263 264 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 265 266 static void * 267 pci_readpcb(device_t pcib, int b, int s, int f) 268 { 269 pcih2cfgregs *p; 270 271 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 272 if (p == NULL) 273 return (NULL); 274 275 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2); 276 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2); 277 278 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1); 279 280 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4); 281 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4); 282 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4); 283 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4); 284 285 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4); 286 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4); 287 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4); 288 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4); 289 290 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4); 291 return p; 292 } 293 294 /* extract header type specific config data */ 295 296 static void 297 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 298 { 299 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 300 switch (cfg->hdrtype) { 301 case 0: 302 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 303 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 304 cfg->nummaps = PCI_MAXMAPS_0; 305 break; 306 case 1: 307 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 308 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 309 cfg->secondarybus = REG(PCIR_SECBUS_1, 1); 310 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1); 311 cfg->nummaps = PCI_MAXMAPS_1; 312 cfg->hdrspec = pci_readppb(pcib, b, s, f); 313 break; 314 case 2: 315 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 316 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 317 cfg->secondarybus = REG(PCIR_SECBUS_2, 1); 318 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1); 319 cfg->nummaps = PCI_MAXMAPS_2; 320 cfg->hdrspec = pci_readpcb(pcib, b, s, f); 321 break; 322 } 323 #undef REG 324 } 325 326 /* read configuration header into pcicfgrect structure */ 327 328 struct pci_devinfo * 329 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 330 { 331 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 332 333 pcicfgregs *cfg = NULL; 334 struct pci_devinfo *devlist_entry; 335 struct devlist *devlist_head; 336 337 devlist_head = &pci_devq; 338 339 devlist_entry = NULL; 340 341 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 342 343 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 344 if (devlist_entry == NULL) 345 return (NULL); 346 347 cfg = &devlist_entry->cfg; 348 349 cfg->bus = b; 350 cfg->slot = s; 351 cfg->func = f; 352 cfg->vendor = REG(PCIR_VENDOR, 2); 353 cfg->device = REG(PCIR_DEVICE, 2); 354 cfg->cmdreg = REG(PCIR_COMMAND, 2); 355 cfg->statreg = REG(PCIR_STATUS, 2); 356 cfg->baseclass = REG(PCIR_CLASS, 1); 357 cfg->subclass = REG(PCIR_SUBCLASS, 1); 358 cfg->progif = REG(PCIR_PROGIF, 1); 359 cfg->revid = REG(PCIR_REVID, 1); 360 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 361 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 362 cfg->lattimer = REG(PCIR_LATTIMER, 1); 363 cfg->intpin = REG(PCIR_INTPIN, 1); 364 cfg->intline = REG(PCIR_INTLINE, 1); 365 366 #ifdef APIC_IO 367 if (cfg->intpin != 0) { 368 int airq; 369 370 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 371 if (airq >= 0) { 372 /* PCI specific entry found in MP table */ 373 if (airq != cfg->intline) { 374 undirect_pci_irq(cfg->intline); 375 cfg->intline = airq; 376 } 377 } else { 378 /* 379 * PCI interrupts might be redirected to the 380 * ISA bus according to some MP tables. Use the 381 * same methods as used by the ISA devices 382 * devices to find the proper IOAPIC int pin. 383 */ 384 airq = isa_apic_irq(cfg->intline); 385 if ((airq >= 0) && (airq != cfg->intline)) { 386 /* XXX: undirect_pci_irq() ? */ 387 undirect_isa_irq(cfg->intline); 388 cfg->intline = airq; 389 } 390 } 391 } 392 #endif /* APIC_IO */ 393 394 cfg->mingnt = REG(PCIR_MINGNT, 1); 395 cfg->maxlat = REG(PCIR_MAXLAT, 1); 396 397 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 398 cfg->hdrtype &= ~PCIM_MFDEV; 399 400 pci_fixancient(cfg); 401 pci_hdrtypedata(pcib, b, s, f, cfg); 402 403 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 404 pci_read_extcap(pcib, cfg); 405 406 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 407 408 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 409 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 410 devlist_entry->conf.pc_sel.pc_func = cfg->func; 411 devlist_entry->conf.pc_hdr = cfg->hdrtype; 412 413 devlist_entry->conf.pc_subvendor = cfg->subvendor; 414 devlist_entry->conf.pc_subdevice = cfg->subdevice; 415 devlist_entry->conf.pc_vendor = cfg->vendor; 416 devlist_entry->conf.pc_device = cfg->device; 417 418 devlist_entry->conf.pc_class = cfg->baseclass; 419 devlist_entry->conf.pc_subclass = cfg->subclass; 420 devlist_entry->conf.pc_progif = cfg->progif; 421 devlist_entry->conf.pc_revid = cfg->revid; 422 423 pci_numdevs++; 424 pci_generation++; 425 } 426 return (devlist_entry); 427 #undef REG 428 } 429 430 static void 431 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 432 { 433 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 434 int ptr, nextptr, ptrptr; 435 436 switch (cfg->hdrtype) { 437 case 0: 438 ptrptr = 0x34; 439 break; 440 case 2: 441 ptrptr = 0x14; 442 break; 443 default: 444 return; /* no extended capabilities support */ 445 } 446 nextptr = REG(ptrptr, 1); /* sanity check? */ 447 448 /* 449 * Read capability entries. 450 */ 451 while (nextptr != 0) { 452 /* Sanity check */ 453 if (nextptr > 255) { 454 printf("illegal PCI extended capability offset %d\n", 455 nextptr); 456 return; 457 } 458 /* Find the next entry */ 459 ptr = nextptr; 460 nextptr = REG(ptr + 1, 1); 461 462 /* Process this entry */ 463 switch (REG(ptr, 1)) { 464 case 0x01: /* PCI power management */ 465 if (cfg->pp_cap == 0) { 466 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 467 cfg->pp_status = ptr + PCIR_POWER_STATUS; 468 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 469 if ((nextptr - ptr) > PCIR_POWER_DATA) 470 cfg->pp_data = ptr + PCIR_POWER_DATA; 471 } 472 break; 473 default: 474 break; 475 } 476 } 477 #undef REG 478 } 479 480 /* free pcicfgregs structure and all depending data structures */ 481 482 int 483 pci_freecfg(struct pci_devinfo *dinfo) 484 { 485 struct devlist *devlist_head; 486 487 devlist_head = &pci_devq; 488 489 if (dinfo->cfg.hdrspec != NULL) 490 free(dinfo->cfg.hdrspec, M_DEVBUF); 491 /* XXX this hasn't been tested */ 492 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 493 free(dinfo, M_DEVBUF); 494 495 /* increment the generation count */ 496 pci_generation++; 497 498 /* we're losing one device */ 499 pci_numdevs--; 500 return (0); 501 } 502 503 504 /* 505 * PCI power manangement 506 */ 507 int 508 pci_set_powerstate_method(device_t dev, device_t child, int state) 509 { 510 struct pci_devinfo *dinfo = device_get_ivars(child); 511 pcicfgregs *cfg = &dinfo->cfg; 512 u_int16_t status; 513 int result; 514 515 if (cfg->pp_cap != 0) { 516 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 517 result = 0; 518 switch (state) { 519 case PCI_POWERSTATE_D0: 520 status |= PCIM_PSTAT_D0; 521 break; 522 case PCI_POWERSTATE_D1: 523 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 524 status |= PCIM_PSTAT_D1; 525 } else { 526 result = EOPNOTSUPP; 527 } 528 break; 529 case PCI_POWERSTATE_D2: 530 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 531 status |= PCIM_PSTAT_D2; 532 } else { 533 result = EOPNOTSUPP; 534 } 535 break; 536 case PCI_POWERSTATE_D3: 537 status |= PCIM_PSTAT_D3; 538 break; 539 default: 540 result = EINVAL; 541 } 542 if (result == 0) 543 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 544 } else { 545 result = ENXIO; 546 } 547 return(result); 548 } 549 550 int 551 pci_get_powerstate_method(device_t dev, device_t child) 552 { 553 struct pci_devinfo *dinfo = device_get_ivars(child); 554 pcicfgregs *cfg = &dinfo->cfg; 555 u_int16_t status; 556 int result; 557 558 if (cfg->pp_cap != 0) { 559 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 560 switch (status & PCIM_PSTAT_DMASK) { 561 case PCIM_PSTAT_D0: 562 result = PCI_POWERSTATE_D0; 563 break; 564 case PCIM_PSTAT_D1: 565 result = PCI_POWERSTATE_D1; 566 break; 567 case PCIM_PSTAT_D2: 568 result = PCI_POWERSTATE_D2; 569 break; 570 case PCIM_PSTAT_D3: 571 result = PCI_POWERSTATE_D3; 572 break; 573 default: 574 result = PCI_POWERSTATE_UNKNOWN; 575 break; 576 } 577 } else { 578 /* No support, device is always at D0 */ 579 result = PCI_POWERSTATE_D0; 580 } 581 return(result); 582 } 583 584 /* 585 * Some convenience functions for PCI device drivers. 586 */ 587 588 static __inline void 589 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 590 { 591 u_int16_t command; 592 593 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 594 command |= bit; 595 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 596 } 597 598 static __inline void 599 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 600 { 601 u_int16_t command; 602 603 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 604 command &= ~bit; 605 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 606 } 607 608 int 609 pci_enable_busmaster_method(device_t dev, device_t child) 610 { 611 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 612 return(0); 613 } 614 615 int 616 pci_disable_busmaster_method(device_t dev, device_t child) 617 { 618 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 619 return(0); 620 } 621 622 int 623 pci_enable_io_method(device_t dev, device_t child, int space) 624 { 625 uint16_t command; 626 uint16_t bit; 627 char *error; 628 629 bit = 0; 630 error = NULL; 631 632 switch(space) { 633 case SYS_RES_IOPORT: 634 bit = PCIM_CMD_PORTEN; 635 error = "port"; 636 break; 637 case SYS_RES_MEMORY: 638 bit = PCIM_CMD_MEMEN; 639 error = "memory"; 640 break; 641 default: 642 return(EINVAL); 643 } 644 pci_set_command_bit(dev, child, bit); 645 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 646 if (command & bit) 647 return(0); 648 device_printf(child, "failed to enable %s mapping!\n", error); 649 return(ENXIO); 650 } 651 652 int 653 pci_disable_io_method(device_t dev, device_t child, int space) 654 { 655 uint16_t command; 656 uint16_t bit; 657 char *error; 658 659 bit = 0; 660 error = NULL; 661 662 switch(space) { 663 case SYS_RES_IOPORT: 664 bit = PCIM_CMD_PORTEN; 665 error = "port"; 666 break; 667 case SYS_RES_MEMORY: 668 bit = PCIM_CMD_MEMEN; 669 error = "memory"; 670 break; 671 default: 672 return (EINVAL); 673 } 674 pci_clear_command_bit(dev, child, bit); 675 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 676 if (command & bit) { 677 device_printf(child, "failed to disable %s mapping!\n", error); 678 return (ENXIO); 679 } 680 return (0); 681 } 682 683 /* 684 * This is the user interface to PCI configuration space. 685 */ 686 687 static int 688 pci_open(dev_t dev, int oflags, int devtype, struct thread *td) 689 { 690 if ((oflags & FWRITE) && securelevel > 0) { 691 return EPERM; 692 } 693 return 0; 694 } 695 696 static int 697 pci_close(dev_t dev, int flag, int devtype, struct thread *td) 698 { 699 return 0; 700 } 701 702 /* 703 * Match a single pci_conf structure against an array of pci_match_conf 704 * structures. The first argument, 'matches', is an array of num_matches 705 * pci_match_conf structures. match_buf is a pointer to the pci_conf 706 * structure that will be compared to every entry in the matches array. 707 * This function returns 1 on failure, 0 on success. 708 */ 709 static int 710 pci_conf_match(struct pci_match_conf *matches, int num_matches, 711 struct pci_conf *match_buf) 712 { 713 int i; 714 715 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 716 return(1); 717 718 for (i = 0; i < num_matches; i++) { 719 /* 720 * I'm not sure why someone would do this...but... 721 */ 722 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 723 continue; 724 725 /* 726 * Look at each of the match flags. If it's set, do the 727 * comparison. If the comparison fails, we don't have a 728 * match, go on to the next item if there is one. 729 */ 730 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 731 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 732 continue; 733 734 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 735 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 736 continue; 737 738 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 739 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 740 continue; 741 742 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 743 && (match_buf->pc_vendor != matches[i].pc_vendor)) 744 continue; 745 746 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 747 && (match_buf->pc_device != matches[i].pc_device)) 748 continue; 749 750 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 751 && (match_buf->pc_class != matches[i].pc_class)) 752 continue; 753 754 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 755 && (match_buf->pd_unit != matches[i].pd_unit)) 756 continue; 757 758 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 759 && (strncmp(matches[i].pd_name, match_buf->pd_name, 760 sizeof(match_buf->pd_name)) != 0)) 761 continue; 762 763 return(0); 764 } 765 766 return(1); 767 } 768 769 /* 770 * Locate the parent of a PCI device by scanning the PCI devlist 771 * and return the entry for the parent. 772 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 773 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 774 */ 775 776 pcicfgregs * 777 pci_devlist_get_parent(pcicfgregs *cfg) 778 { 779 struct devlist *devlist_head; 780 struct pci_devinfo *dinfo; 781 pcicfgregs *bridge_cfg; 782 int i; 783 784 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 785 786 /* If the device is on PCI bus 0, look for the host */ 787 if (cfg->bus == 0) { 788 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 789 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 790 bridge_cfg = &dinfo->cfg; 791 if (bridge_cfg->baseclass == PCIC_BRIDGE 792 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 793 && bridge_cfg->bus == cfg->bus) { 794 return bridge_cfg; 795 } 796 } 797 } 798 799 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 800 if (cfg->bus > 0) { 801 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 802 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 803 bridge_cfg = &dinfo->cfg; 804 if (bridge_cfg->baseclass == PCIC_BRIDGE 805 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 806 && bridge_cfg->secondarybus == cfg->bus) { 807 return bridge_cfg; 808 } 809 } 810 } 811 812 return NULL; 813 } 814 815 static int 816 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td) 817 { 818 device_t pci, pcib; 819 struct pci_io *io; 820 const char *name; 821 int error; 822 823 if (!(flag & FWRITE)) 824 return EPERM; 825 826 827 switch(cmd) { 828 case PCIOCGETCONF: 829 { 830 struct pci_devinfo *dinfo; 831 struct pci_conf_io *cio; 832 struct devlist *devlist_head; 833 struct pci_match_conf *pattern_buf; 834 int num_patterns; 835 size_t iolen; 836 int ionum, i; 837 838 cio = (struct pci_conf_io *)data; 839 840 num_patterns = 0; 841 dinfo = NULL; 842 843 /* 844 * Hopefully the user won't pass in a null pointer, but it 845 * can't hurt to check. 846 */ 847 if (cio == NULL) { 848 error = EINVAL; 849 break; 850 } 851 852 /* 853 * If the user specified an offset into the device list, 854 * but the list has changed since they last called this 855 * ioctl, tell them that the list has changed. They will 856 * have to get the list from the beginning. 857 */ 858 if ((cio->offset != 0) 859 && (cio->generation != pci_generation)){ 860 cio->num_matches = 0; 861 cio->status = PCI_GETCONF_LIST_CHANGED; 862 error = 0; 863 break; 864 } 865 866 /* 867 * Check to see whether the user has asked for an offset 868 * past the end of our list. 869 */ 870 if (cio->offset >= pci_numdevs) { 871 cio->num_matches = 0; 872 cio->status = PCI_GETCONF_LAST_DEVICE; 873 error = 0; 874 break; 875 } 876 877 /* get the head of the device queue */ 878 devlist_head = &pci_devq; 879 880 /* 881 * Determine how much room we have for pci_conf structures. 882 * Round the user's buffer size down to the nearest 883 * multiple of sizeof(struct pci_conf) in case the user 884 * didn't specify a multiple of that size. 885 */ 886 iolen = min(cio->match_buf_len - 887 (cio->match_buf_len % sizeof(struct pci_conf)), 888 pci_numdevs * sizeof(struct pci_conf)); 889 890 /* 891 * Since we know that iolen is a multiple of the size of 892 * the pciconf union, it's okay to do this. 893 */ 894 ionum = iolen / sizeof(struct pci_conf); 895 896 /* 897 * If this test is true, the user wants the pci_conf 898 * structures returned to match the supplied entries. 899 */ 900 if ((cio->num_patterns > 0) 901 && (cio->pat_buf_len > 0)) { 902 /* 903 * pat_buf_len needs to be: 904 * num_patterns * sizeof(struct pci_match_conf) 905 * While it is certainly possible the user just 906 * allocated a large buffer, but set the number of 907 * matches correctly, it is far more likely that 908 * their kernel doesn't match the userland utility 909 * they're using. It's also possible that the user 910 * forgot to initialize some variables. Yes, this 911 * may be overly picky, but I hazard to guess that 912 * it's far more likely to just catch folks that 913 * updated their kernel but not their userland. 914 */ 915 if ((cio->num_patterns * 916 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 917 /* The user made a mistake, return an error*/ 918 cio->status = PCI_GETCONF_ERROR; 919 printf("pci_ioctl: pat_buf_len %d != " 920 "num_patterns (%d) * sizeof(struct " 921 "pci_match_conf) (%d)\npci_ioctl: " 922 "pat_buf_len should be = %d\n", 923 cio->pat_buf_len, cio->num_patterns, 924 (int)sizeof(struct pci_match_conf), 925 (int)sizeof(struct pci_match_conf) * 926 cio->num_patterns); 927 printf("pci_ioctl: do your headers match your " 928 "kernel?\n"); 929 cio->num_matches = 0; 930 error = EINVAL; 931 break; 932 } 933 934 /* 935 * Check the user's buffer to make sure it's readable. 936 */ 937 if (!useracc((caddr_t)cio->patterns, 938 cio->pat_buf_len, VM_PROT_READ)) { 939 printf("pci_ioctl: pattern buffer %p, " 940 "length %u isn't user accessible for" 941 " READ\n", cio->patterns, 942 cio->pat_buf_len); 943 error = EACCES; 944 break; 945 } 946 /* 947 * Allocate a buffer to hold the patterns. 948 */ 949 pattern_buf = malloc(cio->pat_buf_len, M_TEMP, 950 M_WAITOK); 951 error = copyin(cio->patterns, pattern_buf, 952 cio->pat_buf_len); 953 if (error != 0) 954 break; 955 num_patterns = cio->num_patterns; 956 957 } else if ((cio->num_patterns > 0) 958 || (cio->pat_buf_len > 0)) { 959 /* 960 * The user made a mistake, spit out an error. 961 */ 962 cio->status = PCI_GETCONF_ERROR; 963 cio->num_matches = 0; 964 printf("pci_ioctl: invalid GETCONF arguments\n"); 965 error = EINVAL; 966 break; 967 } else 968 pattern_buf = NULL; 969 970 /* 971 * Make sure we can write to the match buffer. 972 */ 973 if (!useracc((caddr_t)cio->matches, 974 cio->match_buf_len, VM_PROT_WRITE)) { 975 printf("pci_ioctl: match buffer %p, length %u " 976 "isn't user accessible for WRITE\n", 977 cio->matches, cio->match_buf_len); 978 error = EACCES; 979 break; 980 } 981 982 /* 983 * Go through the list of devices and copy out the devices 984 * that match the user's criteria. 985 */ 986 for (cio->num_matches = 0, error = 0, i = 0, 987 dinfo = STAILQ_FIRST(devlist_head); 988 (dinfo != NULL) && (cio->num_matches < ionum) 989 && (error == 0) && (i < pci_numdevs); 990 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 991 992 if (i < cio->offset) 993 continue; 994 995 /* Populate pd_name and pd_unit */ 996 name = NULL; 997 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 998 name = device_get_name(dinfo->cfg.dev); 999 if (name) { 1000 strncpy(dinfo->conf.pd_name, name, 1001 sizeof(dinfo->conf.pd_name)); 1002 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 1003 dinfo->conf.pd_unit = 1004 device_get_unit(dinfo->cfg.dev); 1005 } 1006 1007 if ((pattern_buf == NULL) || 1008 (pci_conf_match(pattern_buf, num_patterns, 1009 &dinfo->conf) == 0)) { 1010 1011 /* 1012 * If we've filled up the user's buffer, 1013 * break out at this point. Since we've 1014 * got a match here, we'll pick right back 1015 * up at the matching entry. We can also 1016 * tell the user that there are more matches 1017 * left. 1018 */ 1019 if (cio->num_matches >= ionum) 1020 break; 1021 1022 error = copyout(&dinfo->conf, 1023 &cio->matches[cio->num_matches], 1024 sizeof(struct pci_conf)); 1025 cio->num_matches++; 1026 } 1027 } 1028 1029 /* 1030 * Set the pointer into the list, so if the user is getting 1031 * n records at a time, where n < pci_numdevs, 1032 */ 1033 cio->offset = i; 1034 1035 /* 1036 * Set the generation, the user will need this if they make 1037 * another ioctl call with offset != 0. 1038 */ 1039 cio->generation = pci_generation; 1040 1041 /* 1042 * If this is the last device, inform the user so he won't 1043 * bother asking for more devices. If dinfo isn't NULL, we 1044 * know that there are more matches in the list because of 1045 * the way the traversal is done. 1046 */ 1047 if (dinfo == NULL) 1048 cio->status = PCI_GETCONF_LAST_DEVICE; 1049 else 1050 cio->status = PCI_GETCONF_MORE_DEVS; 1051 1052 if (pattern_buf != NULL) 1053 free(pattern_buf, M_TEMP); 1054 1055 break; 1056 } 1057 case PCIOCREAD: 1058 io = (struct pci_io *)data; 1059 switch(io->pi_width) { 1060 case 4: 1061 case 2: 1062 case 1: 1063 /* 1064 * Assume that the user-level bus number is 1065 * actually the pciN instance number. We map 1066 * from that to the real pcib+bus combination. 1067 */ 1068 pci = devclass_get_device(pci_devclass, 1069 io->pi_sel.pc_bus); 1070 if (pci) { 1071 int b = pcib_get_bus(pci); 1072 pcib = device_get_parent(pci); 1073 io->pi_data = 1074 PCIB_READ_CONFIG(pcib, 1075 b, 1076 io->pi_sel.pc_dev, 1077 io->pi_sel.pc_func, 1078 io->pi_reg, 1079 io->pi_width); 1080 error = 0; 1081 } else { 1082 error = ENODEV; 1083 } 1084 break; 1085 default: 1086 error = ENODEV; 1087 break; 1088 } 1089 break; 1090 1091 case PCIOCWRITE: 1092 io = (struct pci_io *)data; 1093 switch(io->pi_width) { 1094 case 4: 1095 case 2: 1096 case 1: 1097 /* 1098 * Assume that the user-level bus number is 1099 * actually the pciN instance number. We map 1100 * from that to the real pcib+bus combination. 1101 */ 1102 pci = devclass_get_device(pci_devclass, 1103 io->pi_sel.pc_bus); 1104 if (pci) { 1105 int b = pcib_get_bus(pci); 1106 pcib = device_get_parent(pci); 1107 PCIB_WRITE_CONFIG(pcib, 1108 b, 1109 io->pi_sel.pc_dev, 1110 io->pi_sel.pc_func, 1111 io->pi_reg, 1112 io->pi_data, 1113 io->pi_width); 1114 error = 0; 1115 } else { 1116 error = ENODEV; 1117 } 1118 break; 1119 default: 1120 error = ENODEV; 1121 break; 1122 } 1123 break; 1124 1125 default: 1126 error = ENOTTY; 1127 break; 1128 } 1129 1130 return (error); 1131 } 1132 1133 #define PCI_CDEV 78 1134 1135 static struct cdevsw pcicdev = { 1136 /* name */ "pci", 1137 /* maj */ PCI_CDEV, 1138 /* flags */ 0, 1139 /* port */ NULL, 1140 /* clone */ NULL, 1141 1142 /* open */ pci_open, 1143 /* close */ pci_close, 1144 /* read */ noread, 1145 /* write */ nowrite, 1146 /* ioctl */ pci_ioctl, 1147 /* poll */ nopoll, 1148 /* mmap */ nommap, 1149 /* strategy */ nostrategy, 1150 /* dump */ nodump, 1151 /* psize */ nopsize 1152 }; 1153 1154 #include "pci_if.h" 1155 1156 /* 1157 * New style pci driver. Parent device is either a pci-host-bridge or a 1158 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1159 */ 1160 const char * 1161 pci_class_to_string(int baseclass) 1162 { 1163 const char *name; 1164 1165 switch(baseclass) { 1166 case PCIC_OLD: 1167 name = "OLD"; 1168 break; 1169 case PCIC_STORAGE: 1170 name = "STORAGE"; 1171 break; 1172 case PCIC_NETWORK: 1173 name = "NETWORK"; 1174 break; 1175 case PCIC_DISPLAY: 1176 name = "DISPLAY"; 1177 break; 1178 case PCIC_MULTIMEDIA: 1179 name = "MULTIMEDIA"; 1180 break; 1181 case PCIC_MEMORY: 1182 name = "MEMORY"; 1183 break; 1184 case PCIC_BRIDGE: 1185 name = "BRIDGE"; 1186 break; 1187 case PCIC_SIMPLECOMM: 1188 name = "SIMPLECOMM"; 1189 break; 1190 case PCIC_BASEPERIPH: 1191 name = "BASEPERIPH"; 1192 break; 1193 case PCIC_INPUTDEV: 1194 name = "INPUTDEV"; 1195 break; 1196 case PCIC_DOCKING: 1197 name = "DOCKING"; 1198 break; 1199 case PCIC_PROCESSOR: 1200 name = "PROCESSOR"; 1201 break; 1202 case PCIC_SERIALBUS: 1203 name = "SERIALBUS"; 1204 break; 1205 case PCIC_WIRELESS: 1206 name = "WIRELESS"; 1207 break; 1208 case PCIC_I2O: 1209 name = "I20"; 1210 break; 1211 case PCIC_SATELLITE: 1212 name = "SATELLITE"; 1213 break; 1214 case PCIC_CRYPTO: 1215 name = "CRYPTO"; 1216 break; 1217 case PCIC_SIGPROC: 1218 name = "SIGPROC"; 1219 break; 1220 case PCIC_OTHER: 1221 name = "OTHER"; 1222 break; 1223 default: 1224 name = "?"; 1225 break; 1226 } 1227 return(name); 1228 } 1229 1230 void 1231 pci_print_verbose(struct pci_devinfo *dinfo) 1232 { 1233 if (bootverbose) { 1234 pcicfgregs *cfg = &dinfo->cfg; 1235 1236 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1237 cfg->vendor, cfg->device, cfg->revid); 1238 printf("\tbus=%d, slot=%d, func=%d\n", 1239 cfg->bus, cfg->slot, cfg->func); 1240 printf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1241 pci_class_to_string(cfg->baseclass), 1242 cfg->baseclass, cfg->subclass, cfg->progif, 1243 cfg->hdrtype, cfg->mfdev); 1244 printf("\tsubordinatebus=%x \tsecondarybus=%x\n", 1245 cfg->subordinatebus, cfg->secondarybus); 1246 #ifdef PCI_DEBUG 1247 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1248 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1249 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1250 cfg->lattimer, cfg->lattimer * 30, 1251 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1252 #endif /* PCI_DEBUG */ 1253 if (cfg->intpin > 0) 1254 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 1255 } 1256 } 1257 1258 static int 1259 pci_porten(device_t pcib, int b, int s, int f) 1260 { 1261 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1262 & PCIM_CMD_PORTEN) != 0; 1263 } 1264 1265 static int 1266 pci_memen(device_t pcib, int b, int s, int f) 1267 { 1268 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1269 & PCIM_CMD_MEMEN) != 0; 1270 } 1271 1272 /* 1273 * Add a resource based on a pci map register. Return 1 if the map 1274 * register is a 32bit map register or 2 if it is a 64bit register. 1275 */ 1276 static int 1277 pci_add_map(device_t pcib, int b, int s, int f, int reg, 1278 struct resource_list *rl) 1279 { 1280 u_int32_t map; 1281 u_int64_t base; 1282 u_int8_t ln2size; 1283 u_int8_t ln2range; 1284 u_int32_t testval; 1285 1286 1287 #ifdef PCI_ENABLE_IO_MODES 1288 u_int16_t cmd; 1289 #endif 1290 int type; 1291 1292 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1293 1294 if (map == 0 || map == 0xffffffff) 1295 return 1; /* skip invalid entry */ 1296 1297 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1298 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1299 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1300 1301 base = pci_mapbase(map); 1302 if (pci_maptype(map) & PCI_MAPMEM) 1303 type = SYS_RES_MEMORY; 1304 else 1305 type = SYS_RES_IOPORT; 1306 ln2size = pci_mapsize(testval); 1307 ln2range = pci_maprange(testval); 1308 if (ln2range == 64) { 1309 /* Read the other half of a 64bit map register */ 1310 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4); 1311 } 1312 1313 /* 1314 * This code theoretically does the right thing, but has 1315 * undesirable side effects in some cases where 1316 * peripherals respond oddly to having these bits 1317 * enabled. Leave them alone by default. 1318 */ 1319 #ifdef PCI_ENABLE_IO_MODES 1320 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1321 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1322 cmd |= PCIM_CMD_PORTEN; 1323 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1324 } 1325 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1326 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1327 cmd |= PCIM_CMD_MEMEN; 1328 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1329 } 1330 #else 1331 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1332 return 1; 1333 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1334 return 1; 1335 #endif 1336 1337 resource_list_add(rl, type, reg, 1338 base, base + (1 << ln2size) - 1, 1339 (1 << ln2size)); 1340 1341 if (bootverbose) { 1342 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n", 1343 reg, pci_maptype(base), ln2range, 1344 (unsigned int) base, ln2size); 1345 } 1346 1347 return (ln2range == 64) ? 2 : 1; 1348 } 1349 1350 static void 1351 pci_add_resources(device_t pcib, device_t bus, device_t dev) 1352 { 1353 struct pci_devinfo *dinfo = device_get_ivars(dev); 1354 pcicfgregs *cfg = &dinfo->cfg; 1355 struct resource_list *rl = &dinfo->resources; 1356 struct pci_quirk *q; 1357 int b, i, f, s; 1358 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */ 1359 int irq; 1360 #endif 1361 1362 b = cfg->bus; 1363 s = cfg->slot; 1364 f = cfg->func; 1365 for (i = 0; i < cfg->nummaps;) { 1366 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl); 1367 } 1368 1369 for (q = &pci_quirks[0]; q->devid; q++) { 1370 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1371 && q->type == PCI_QUIRK_MAP_REG) 1372 pci_add_map(pcib, b, s, f, q->arg1, rl); 1373 } 1374 1375 if (cfg->intpin > 0 && cfg->intline != 255) 1376 resource_list_add(rl, SYS_RES_IRQ, 0, 1377 cfg->intline, cfg->intline, 1); 1378 } 1379 1380 void 1381 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1382 { 1383 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1384 device_t pcib = device_get_parent(dev); 1385 struct pci_devinfo *dinfo; 1386 int maxslots; 1387 int s, f, pcifunchigh; 1388 uint8_t hdrtype; 1389 1390 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo)); 1391 1392 maxslots = PCIB_MAXSLOTS(pcib); 1393 1394 for (s = 0; s <= maxslots; s++) { 1395 pcifunchigh = 0; 1396 f = 0; 1397 hdrtype = REG(PCIR_HDRTYPE, 1); 1398 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1399 continue; 1400 if (hdrtype & PCIM_MFDEV) 1401 pcifunchigh = PCI_FUNCMAX; 1402 for (f = 0; f <= pcifunchigh; f++) { 1403 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1404 if (dinfo != NULL) { 1405 pci_add_child(dev, dinfo); 1406 } 1407 } 1408 } 1409 #undef REG 1410 } 1411 1412 void 1413 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1414 { 1415 device_t pcib; 1416 1417 pcib = device_get_parent(bus); 1418 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1419 device_set_ivars(dinfo->cfg.dev, dinfo); 1420 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1421 pci_print_verbose(dinfo); 1422 } 1423 1424 /* 1425 * Probe the PCI bus. Note: probe code is not supposed to add children 1426 * or call attach. 1427 */ 1428 static int 1429 pci_probe(device_t dev) 1430 { 1431 device_set_desc(dev, "PCI bus"); 1432 1433 /* Allow other subclasses to override this driver */ 1434 return(-1000); 1435 } 1436 1437 static int 1438 pci_attach(device_t dev) 1439 { 1440 int busno; 1441 int lunit = device_get_unit(dev); 1442 1443 cdevsw_add(&pcicdev, -1, lunit); 1444 make_dev(&pcicdev, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit); 1445 1446 /* 1447 * Since there can be multiple independantly numbered PCI 1448 * busses on some large alpha systems, we can't use the unit 1449 * number to decide what bus we are probing. We ask the parent 1450 * pcib what our bus number is. 1451 */ 1452 busno = pcib_get_bus(dev); 1453 if (bootverbose) 1454 device_printf(dev, "pci_attach() physical bus=%d\n", busno); 1455 1456 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1457 1458 return (bus_generic_attach(dev)); 1459 } 1460 1461 static int 1462 pci_print_resources(struct resource_list *rl, const char *name, int type, 1463 const char *format) 1464 { 1465 struct resource_list_entry *rle; 1466 int printed, retval; 1467 1468 printed = 0; 1469 retval = 0; 1470 /* Yes, this is kinda cheating */ 1471 SLIST_FOREACH(rle, rl, link) { 1472 if (rle->type == type) { 1473 if (printed == 0) 1474 retval += printf(" %s ", name); 1475 else if (printed > 0) 1476 retval += printf(","); 1477 printed++; 1478 retval += printf(format, rle->start); 1479 if (rle->count > 1) { 1480 retval += printf("-"); 1481 retval += printf(format, rle->start + 1482 rle->count - 1); 1483 } 1484 } 1485 } 1486 return retval; 1487 } 1488 1489 int 1490 pci_print_child(device_t dev, device_t child) 1491 { 1492 struct pci_devinfo *dinfo; 1493 struct resource_list *rl; 1494 pcicfgregs *cfg; 1495 int retval = 0; 1496 1497 dinfo = device_get_ivars(child); 1498 cfg = &dinfo->cfg; 1499 rl = &dinfo->resources; 1500 1501 retval += bus_print_child_header(dev, child); 1502 1503 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 1504 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1505 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 1506 if (device_get_flags(dev)) 1507 retval += printf(" flags %#x", device_get_flags(dev)); 1508 1509 retval += printf(" at device %d.%d", pci_get_slot(child), 1510 pci_get_function(child)); 1511 1512 retval += bus_print_child_footer(dev, child); 1513 1514 return (retval); 1515 } 1516 1517 void 1518 pci_probe_nomatch(device_t dev, device_t child) 1519 { 1520 struct pci_devinfo *dinfo; 1521 pcicfgregs *cfg; 1522 const char *desc; 1523 int unknown; 1524 1525 unknown = 0; 1526 dinfo = device_get_ivars(child); 1527 cfg = &dinfo->cfg; 1528 desc = pci_ata_match(child); 1529 if (!desc) desc = pci_usb_match(child); 1530 if (!desc) desc = pci_vga_match(child); 1531 if (!desc) desc = pci_chip_match(child); 1532 if (!desc) { 1533 desc = "unknown card"; 1534 unknown++; 1535 } 1536 device_printf(dev, "<%s>", desc); 1537 if (bootverbose || unknown) { 1538 printf(" (vendor=0x%04x, dev=0x%04x)", 1539 cfg->vendor, 1540 cfg->device); 1541 } 1542 printf(" at %d.%d", 1543 pci_get_slot(child), 1544 pci_get_function(child)); 1545 if (cfg->intpin > 0 && cfg->intline != 255) { 1546 printf(" irq %d", cfg->intline); 1547 } 1548 printf("\n"); 1549 1550 return; 1551 } 1552 1553 int 1554 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1555 { 1556 struct pci_devinfo *dinfo; 1557 pcicfgregs *cfg; 1558 1559 dinfo = device_get_ivars(child); 1560 cfg = &dinfo->cfg; 1561 1562 switch (which) { 1563 case PCI_IVAR_SUBVENDOR: 1564 *result = cfg->subvendor; 1565 break; 1566 case PCI_IVAR_SUBDEVICE: 1567 *result = cfg->subdevice; 1568 break; 1569 case PCI_IVAR_VENDOR: 1570 *result = cfg->vendor; 1571 break; 1572 case PCI_IVAR_DEVICE: 1573 *result = cfg->device; 1574 break; 1575 case PCI_IVAR_DEVID: 1576 *result = (cfg->device << 16) | cfg->vendor; 1577 break; 1578 case PCI_IVAR_CLASS: 1579 *result = cfg->baseclass; 1580 break; 1581 case PCI_IVAR_SUBCLASS: 1582 *result = cfg->subclass; 1583 break; 1584 case PCI_IVAR_PROGIF: 1585 *result = cfg->progif; 1586 break; 1587 case PCI_IVAR_REVID: 1588 *result = cfg->revid; 1589 break; 1590 case PCI_IVAR_INTPIN: 1591 *result = cfg->intpin; 1592 break; 1593 case PCI_IVAR_IRQ: 1594 *result = cfg->intline; 1595 break; 1596 case PCI_IVAR_BUS: 1597 *result = cfg->bus; 1598 break; 1599 case PCI_IVAR_SLOT: 1600 *result = cfg->slot; 1601 break; 1602 case PCI_IVAR_FUNCTION: 1603 *result = cfg->func; 1604 break; 1605 case PCI_IVAR_SECONDARYBUS: 1606 *result = cfg->secondarybus; 1607 break; 1608 case PCI_IVAR_SUBORDINATEBUS: 1609 *result = cfg->subordinatebus; 1610 break; 1611 case PCI_IVAR_ETHADDR: 1612 /* 1613 * The generic accessor doesn't deal with failure, so 1614 * we set the return value, then return an error. 1615 */ 1616 *result = NULL; 1617 return (EINVAL); 1618 default: 1619 return ENOENT; 1620 } 1621 return 0; 1622 } 1623 1624 int 1625 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1626 { 1627 struct pci_devinfo *dinfo; 1628 pcicfgregs *cfg; 1629 1630 dinfo = device_get_ivars(child); 1631 cfg = &dinfo->cfg; 1632 1633 switch (which) { 1634 case PCI_IVAR_SUBVENDOR: 1635 case PCI_IVAR_SUBDEVICE: 1636 case PCI_IVAR_VENDOR: 1637 case PCI_IVAR_DEVICE: 1638 case PCI_IVAR_DEVID: 1639 case PCI_IVAR_CLASS: 1640 case PCI_IVAR_SUBCLASS: 1641 case PCI_IVAR_PROGIF: 1642 case PCI_IVAR_REVID: 1643 case PCI_IVAR_INTPIN: 1644 case PCI_IVAR_IRQ: 1645 case PCI_IVAR_BUS: 1646 case PCI_IVAR_SLOT: 1647 case PCI_IVAR_FUNCTION: 1648 case PCI_IVAR_ETHADDR: 1649 return EINVAL; /* disallow for now */ 1650 1651 case PCI_IVAR_SECONDARYBUS: 1652 cfg->secondarybus = value; 1653 break; 1654 case PCI_IVAR_SUBORDINATEBUS: 1655 cfg->subordinatebus = value; 1656 break; 1657 default: 1658 return ENOENT; 1659 } 1660 return 0; 1661 } 1662 1663 struct resource * 1664 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1665 u_long start, u_long end, u_long count, u_int flags) 1666 { 1667 struct pci_devinfo *dinfo = device_get_ivars(child); 1668 struct resource_list *rl = &dinfo->resources; 1669 pcicfgregs *cfg = &dinfo->cfg; 1670 1671 /* 1672 * Perform lazy resource allocation 1673 * 1674 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1675 */ 1676 if (device_get_parent(child) == dev) { 1677 switch (type) { 1678 case SYS_RES_IRQ: 1679 #ifdef __i386__ 1680 /* 1681 * If device doesn't have an interrupt routed, and is 1682 * deserving of an interrupt, try to assign it one. 1683 */ 1684 if ((cfg->intline == 255 || cfg->intline == 0) && 1685 (cfg->intpin != 0) && 1686 (start == 0) && (end == ~0UL)) { 1687 cfg->intline = PCIB_ROUTE_INTERRUPT( 1688 device_get_parent(dev), child, 1689 cfg->intpin); 1690 if (cfg->intline != 255) { 1691 pci_write_config(child, PCIR_INTLINE, 1692 cfg->intline, 1); 1693 resource_list_add(rl, SYS_RES_IRQ, 0, 1694 cfg->intline, cfg->intline, 1); 1695 } 1696 } 1697 break; 1698 #endif 1699 case SYS_RES_IOPORT: 1700 case SYS_RES_MEMORY: 1701 if (*rid < PCIR_BAR(cfg->nummaps)) { 1702 /* 1703 * Enable the I/O mode. We should 1704 * also be assigning resources too 1705 * when none are present. The 1706 * resource_list_alloc kind of sorta does 1707 * this... 1708 */ 1709 if (PCI_ENABLE_IO(dev, child, type)) 1710 return (NULL); 1711 } 1712 break; 1713 } 1714 } 1715 return resource_list_alloc(rl, dev, child, type, rid, 1716 start, end, count, flags); 1717 } 1718 1719 static int 1720 pci_release_resource(device_t dev, device_t child, int type, int rid, 1721 struct resource *r) 1722 { 1723 struct pci_devinfo *dinfo = device_get_ivars(child); 1724 struct resource_list *rl = &dinfo->resources; 1725 1726 return resource_list_release(rl, dev, child, type, rid, r); 1727 } 1728 1729 static int 1730 pci_set_resource(device_t dev, device_t child, int type, int rid, 1731 u_long start, u_long count) 1732 { 1733 struct pci_devinfo *dinfo = device_get_ivars(child); 1734 struct resource_list *rl = &dinfo->resources; 1735 1736 resource_list_add(rl, type, rid, start, start + count - 1, count); 1737 return 0; 1738 } 1739 1740 static int 1741 pci_get_resource(device_t dev, device_t child, int type, int rid, 1742 u_long *startp, u_long *countp) 1743 { 1744 struct pci_devinfo *dinfo = device_get_ivars(child); 1745 struct resource_list *rl = &dinfo->resources; 1746 struct resource_list_entry *rle; 1747 1748 rle = resource_list_find(rl, type, rid); 1749 if (!rle) 1750 return ENOENT; 1751 1752 if (startp) 1753 *startp = rle->start; 1754 if (countp) 1755 *countp = rle->count; 1756 1757 return 0; 1758 } 1759 1760 void 1761 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1762 { 1763 printf("pci_delete_resource: PCI resources can not be deleted\n"); 1764 } 1765 1766 struct resource_list * 1767 pci_get_resource_list (device_t dev, device_t child) 1768 { 1769 struct pci_devinfo * dinfo = device_get_ivars(child); 1770 struct resource_list * rl = &dinfo->resources; 1771 1772 if (!rl) 1773 return (NULL); 1774 1775 return (rl); 1776 } 1777 1778 u_int32_t 1779 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1780 { 1781 struct pci_devinfo *dinfo = device_get_ivars(child); 1782 pcicfgregs *cfg = &dinfo->cfg; 1783 1784 return PCIB_READ_CONFIG(device_get_parent(dev), 1785 cfg->bus, cfg->slot, cfg->func, 1786 reg, width); 1787 } 1788 1789 void 1790 pci_write_config_method(device_t dev, device_t child, int reg, 1791 u_int32_t val, int width) 1792 { 1793 struct pci_devinfo *dinfo = device_get_ivars(child); 1794 pcicfgregs *cfg = &dinfo->cfg; 1795 1796 PCIB_WRITE_CONFIG(device_get_parent(dev), 1797 cfg->bus, cfg->slot, cfg->func, 1798 reg, val, width); 1799 } 1800 1801 int 1802 pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 1803 size_t buflen) 1804 { 1805 struct pci_devinfo *dinfo; 1806 1807 dinfo = device_get_ivars(child); 1808 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1809 pci_get_function(child)); 1810 return (0); 1811 } 1812 1813 int 1814 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 1815 size_t buflen) 1816 { 1817 struct pci_devinfo *dinfo; 1818 pcicfgregs *cfg; 1819 1820 dinfo = device_get_ivars(child); 1821 cfg = &dinfo->cfg; 1822 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1823 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1824 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1825 cfg->progif); 1826 return (0); 1827 } 1828 1829 int 1830 pci_assign_interrupt_method(device_t dev, device_t child) 1831 { 1832 struct pci_devinfo *dinfo = device_get_ivars(child); 1833 pcicfgregs *cfg = &dinfo->cfg; 1834 1835 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1836 cfg->intpin)); 1837 } 1838 1839 static int 1840 pci_modevent(module_t mod, int what, void *arg) 1841 { 1842 switch (what) { 1843 case MOD_LOAD: 1844 STAILQ_INIT(&pci_devq); 1845 break; 1846 case MOD_UNLOAD: 1847 break; 1848 } 1849 1850 return 0; 1851 } 1852 1853 int 1854 pci_resume(device_t dev) 1855 { 1856 int numdevs; 1857 int i; 1858 device_t *children; 1859 device_t child; 1860 struct pci_devinfo *dinfo; 1861 pcicfgregs *cfg; 1862 1863 device_get_children(dev, &children, &numdevs); 1864 1865 for (i = 0; i < numdevs; i++) { 1866 child = children[i]; 1867 1868 dinfo = device_get_ivars(child); 1869 cfg = &dinfo->cfg; 1870 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1871 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1872 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1873 pci_write_config(child, PCIR_INTLINE, 1874 cfg->intline, 1); 1875 } 1876 } 1877 } 1878 1879 free(children, M_TEMP); 1880 1881 return (bus_generic_resume(dev)); 1882 } 1883 1884 static device_method_t pci_methods[] = { 1885 /* Device interface */ 1886 DEVMETHOD(device_probe, pci_probe), 1887 DEVMETHOD(device_attach, pci_attach), 1888 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1889 DEVMETHOD(device_suspend, bus_generic_suspend), 1890 DEVMETHOD(device_resume, pci_resume), 1891 1892 /* Bus interface */ 1893 DEVMETHOD(bus_print_child, pci_print_child), 1894 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 1895 DEVMETHOD(bus_read_ivar, pci_read_ivar), 1896 DEVMETHOD(bus_write_ivar, pci_write_ivar), 1897 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1898 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1899 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1900 1901 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 1902 DEVMETHOD(bus_set_resource, pci_set_resource), 1903 DEVMETHOD(bus_get_resource, pci_get_resource), 1904 DEVMETHOD(bus_delete_resource, pci_delete_resource), 1905 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 1906 DEVMETHOD(bus_release_resource, pci_release_resource), 1907 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1908 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1909 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 1910 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 1911 1912 /* PCI interface */ 1913 DEVMETHOD(pci_read_config, pci_read_config_method), 1914 DEVMETHOD(pci_write_config, pci_write_config_method), 1915 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 1916 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 1917 DEVMETHOD(pci_enable_io, pci_enable_io_method), 1918 DEVMETHOD(pci_disable_io, pci_disable_io_method), 1919 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 1920 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 1921 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 1922 1923 { 0, 0 } 1924 }; 1925 1926 static driver_t pci_driver = { 1927 "pci", 1928 pci_methods, 1929 1, /* no softc */ 1930 }; 1931 1932 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 1933 MODULE_VERSION(pci, 1); 1934