1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $ 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.30 2006/07/28 02:17:34 dillon Exp $ 28 * 29 */ 30 31 #include "opt_bus.h" 32 #include "opt_pci.h" 33 34 #include "opt_simos.h" 35 #include "opt_compat_oldpci.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/fcntl.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/buf.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 #include <vm/vm_extern.h> 51 52 #include <sys/bus.h> 53 #include <machine/bus.h> 54 #include <sys/rman.h> 55 #include <machine/resource.h> 56 #include <machine/md_var.h> /* For the Alpha */ 57 #include <machine/smp.h> 58 #ifdef __i386__ 59 #include <bus/pci/i386/pci_cfgreg.h> 60 #endif 61 62 #include <sys/pciio.h> 63 #include "pcireg.h" 64 #include "pcivar.h" 65 #include "pci_private.h" 66 67 #include "pcib_if.h" 68 69 devclass_t pci_devclass; 70 const char *pcib_owner; 71 72 static void pci_read_extcap(device_t dev, pcicfgregs *cfg); 73 74 struct pci_quirk { 75 u_int32_t devid; /* Vendor/device of the card */ 76 int type; 77 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 78 int arg1; 79 int arg2; 80 }; 81 82 struct pci_quirk pci_quirks[] = { 83 /* 84 * The Intel 82371AB and 82443MX has a map register at offset 0x90. 85 */ 86 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 87 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 88 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 89 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 90 91 { 0 } 92 }; 93 94 /* map register information */ 95 #define PCI_MAPMEM 0x01 /* memory map */ 96 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 97 #define PCI_MAPPORT 0x04 /* port map */ 98 99 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 100 u_int32_t pci_numdevs = 0; 101 static u_int32_t pci_generation = 0; 102 103 device_t 104 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func) 105 { 106 struct pci_devinfo *dinfo; 107 108 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 109 if ((dinfo->cfg.bus == bus) && 110 (dinfo->cfg.slot == slot) && 111 (dinfo->cfg.func == func)) { 112 return (dinfo->cfg.dev); 113 } 114 } 115 116 return (NULL); 117 } 118 119 device_t 120 pci_find_device (u_int16_t vendor, u_int16_t device) 121 { 122 struct pci_devinfo *dinfo; 123 124 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 125 if ((dinfo->cfg.vendor == vendor) && 126 (dinfo->cfg.device == device)) { 127 return (dinfo->cfg.dev); 128 } 129 } 130 131 return (NULL); 132 } 133 134 /* return base address of memory or port map */ 135 136 static u_int32_t 137 pci_mapbase(unsigned mapreg) 138 { 139 int mask = 0x03; 140 if ((mapreg & 0x01) == 0) 141 mask = 0x0f; 142 return (mapreg & ~mask); 143 } 144 145 /* return map type of memory or port map */ 146 147 static int 148 pci_maptype(unsigned mapreg) 149 { 150 static u_int8_t maptype[0x10] = { 151 PCI_MAPMEM, PCI_MAPPORT, 152 PCI_MAPMEM, 0, 153 PCI_MAPMEM, PCI_MAPPORT, 154 0, 0, 155 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 156 PCI_MAPMEM|PCI_MAPMEMP, 0, 157 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 158 0, 0, 159 }; 160 161 return maptype[mapreg & 0x0f]; 162 } 163 164 /* return log2 of map size decoded for memory or port map */ 165 166 static int 167 pci_mapsize(unsigned testval) 168 { 169 int ln2size; 170 171 testval = pci_mapbase(testval); 172 ln2size = 0; 173 if (testval != 0) { 174 while ((testval & 1) == 0) 175 { 176 ln2size++; 177 testval >>= 1; 178 } 179 } 180 return (ln2size); 181 } 182 183 /* return log2 of address range supported by map register */ 184 185 static int 186 pci_maprange(unsigned mapreg) 187 { 188 int ln2range = 0; 189 switch (mapreg & 0x07) { 190 case 0x00: 191 case 0x01: 192 case 0x05: 193 ln2range = 32; 194 break; 195 case 0x02: 196 ln2range = 20; 197 break; 198 case 0x04: 199 ln2range = 64; 200 break; 201 } 202 return (ln2range); 203 } 204 205 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 206 207 static void 208 pci_fixancient(pcicfgregs *cfg) 209 { 210 if (cfg->hdrtype != 0) 211 return; 212 213 /* PCI to PCI bridges use header type 1 */ 214 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 215 cfg->hdrtype = 1; 216 } 217 218 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 219 220 static void * 221 pci_readppb(device_t pcib, int b, int s, int f) 222 { 223 pcih1cfgregs *p; 224 225 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 226 if (p == NULL) 227 return (NULL); 228 229 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2); 230 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2); 231 232 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1); 233 234 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f, 235 PCIR_IOBASEH_1, 2), 236 PCIB_READ_CONFIG(pcib, b, s, f, 237 PCIR_IOBASEL_1, 1)); 238 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f, 239 PCIR_IOLIMITH_1, 2), 240 PCIB_READ_CONFIG(pcib, b, s, f, 241 PCIR_IOLIMITL_1, 1)); 242 243 p->membase = PCI_PPBMEMBASE (0, 244 PCIB_READ_CONFIG(pcib, b, s, f, 245 PCIR_MEMBASE_1, 2)); 246 p->memlimit = PCI_PPBMEMLIMIT (0, 247 PCIB_READ_CONFIG(pcib, b, s, f, 248 PCIR_MEMLIMIT_1, 2)); 249 250 p->pmembase = PCI_PPBMEMBASE ( 251 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4), 252 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2)); 253 254 p->pmemlimit = PCI_PPBMEMLIMIT ( 255 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, 256 PCIR_PMLIMITH_1, 4), 257 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2)); 258 259 return (p); 260 } 261 262 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 263 264 static void * 265 pci_readpcb(device_t pcib, int b, int s, int f) 266 { 267 pcih2cfgregs *p; 268 269 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 270 if (p == NULL) 271 return (NULL); 272 273 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2); 274 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2); 275 276 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1); 277 278 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4); 279 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4); 280 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4); 281 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4); 282 283 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4); 284 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4); 285 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4); 286 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4); 287 288 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4); 289 return p; 290 } 291 292 /* extract header type specific config data */ 293 294 static void 295 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 296 { 297 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 298 switch (cfg->hdrtype) { 299 case 0: 300 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 301 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 302 cfg->nummaps = PCI_MAXMAPS_0; 303 break; 304 case 1: 305 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 306 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 307 cfg->secondarybus = REG(PCIR_SECBUS_1, 1); 308 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1); 309 cfg->nummaps = PCI_MAXMAPS_1; 310 cfg->hdrspec = pci_readppb(pcib, b, s, f); 311 break; 312 case 2: 313 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 314 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 315 cfg->secondarybus = REG(PCIR_SECBUS_2, 1); 316 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1); 317 cfg->nummaps = PCI_MAXMAPS_2; 318 cfg->hdrspec = pci_readpcb(pcib, b, s, f); 319 break; 320 } 321 #undef REG 322 } 323 324 /* read configuration header into pcicfgrect structure */ 325 326 struct pci_devinfo * 327 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 328 { 329 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 330 331 pcicfgregs *cfg = NULL; 332 struct pci_devinfo *devlist_entry; 333 struct devlist *devlist_head; 334 335 devlist_head = &pci_devq; 336 337 devlist_entry = NULL; 338 339 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 340 341 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 342 if (devlist_entry == NULL) 343 return (NULL); 344 345 cfg = &devlist_entry->cfg; 346 347 cfg->bus = b; 348 cfg->slot = s; 349 cfg->func = f; 350 cfg->vendor = REG(PCIR_VENDOR, 2); 351 cfg->device = REG(PCIR_DEVICE, 2); 352 cfg->cmdreg = REG(PCIR_COMMAND, 2); 353 cfg->statreg = REG(PCIR_STATUS, 2); 354 cfg->baseclass = REG(PCIR_CLASS, 1); 355 cfg->subclass = REG(PCIR_SUBCLASS, 1); 356 cfg->progif = REG(PCIR_PROGIF, 1); 357 cfg->revid = REG(PCIR_REVID, 1); 358 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 359 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 360 cfg->lattimer = REG(PCIR_LATTIMER, 1); 361 cfg->intpin = REG(PCIR_INTPIN, 1); 362 cfg->intline = REG(PCIR_INTLINE, 1); 363 364 #ifdef APIC_IO 365 /* 366 * If using the APIC the intpin is probably wrong, since it 367 * is often setup by the BIOS with the PIC in mind. 368 */ 369 if (cfg->intpin != 0) { 370 int airq; 371 372 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 373 if (airq >= 0) { 374 /* PCI specific entry found in MP table */ 375 if (airq != cfg->intline) { 376 undirect_pci_irq(cfg->intline); 377 cfg->intline = airq; 378 } 379 } else { 380 /* 381 * PCI interrupts might be redirected to the 382 * ISA bus according to some MP tables. Use the 383 * same methods as used by the ISA devices 384 * devices to find the proper IOAPIC int pin. 385 */ 386 airq = isa_apic_irq(cfg->intline); 387 if ((airq >= 0) && (airq != cfg->intline)) { 388 /* XXX: undirect_pci_irq() ? */ 389 undirect_isa_irq(cfg->intline); 390 cfg->intline = airq; 391 } 392 } 393 } 394 #endif /* APIC_IO */ 395 396 cfg->mingnt = REG(PCIR_MINGNT, 1); 397 cfg->maxlat = REG(PCIR_MAXLAT, 1); 398 399 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 400 cfg->hdrtype &= ~PCIM_MFDEV; 401 402 pci_fixancient(cfg); 403 pci_hdrtypedata(pcib, b, s, f, cfg); 404 405 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 406 pci_read_extcap(pcib, cfg); 407 408 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 409 410 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 411 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 412 devlist_entry->conf.pc_sel.pc_func = cfg->func; 413 devlist_entry->conf.pc_hdr = cfg->hdrtype; 414 415 devlist_entry->conf.pc_subvendor = cfg->subvendor; 416 devlist_entry->conf.pc_subdevice = cfg->subdevice; 417 devlist_entry->conf.pc_vendor = cfg->vendor; 418 devlist_entry->conf.pc_device = cfg->device; 419 420 devlist_entry->conf.pc_class = cfg->baseclass; 421 devlist_entry->conf.pc_subclass = cfg->subclass; 422 devlist_entry->conf.pc_progif = cfg->progif; 423 devlist_entry->conf.pc_revid = cfg->revid; 424 425 pci_numdevs++; 426 pci_generation++; 427 } 428 return (devlist_entry); 429 #undef REG 430 } 431 432 static void 433 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 434 { 435 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 436 int ptr, nextptr, ptrptr; 437 438 switch (cfg->hdrtype) { 439 case 0: 440 ptrptr = 0x34; 441 break; 442 case 2: 443 ptrptr = 0x14; 444 break; 445 default: 446 return; /* no extended capabilities support */ 447 } 448 nextptr = REG(ptrptr, 1); /* sanity check? */ 449 450 /* 451 * Read capability entries. 452 */ 453 while (nextptr != 0) { 454 /* Sanity check */ 455 if (nextptr > 255) { 456 printf("illegal PCI extended capability offset %d\n", 457 nextptr); 458 return; 459 } 460 /* Find the next entry */ 461 ptr = nextptr; 462 nextptr = REG(ptr + 1, 1); 463 464 /* Process this entry */ 465 switch (REG(ptr, 1)) { 466 case 0x01: /* PCI power management */ 467 if (cfg->pp_cap == 0) { 468 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 469 cfg->pp_status = ptr + PCIR_POWER_STATUS; 470 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 471 if ((nextptr - ptr) > PCIR_POWER_DATA) 472 cfg->pp_data = ptr + PCIR_POWER_DATA; 473 } 474 break; 475 default: 476 break; 477 } 478 } 479 #undef REG 480 } 481 482 /* free pcicfgregs structure and all depending data structures */ 483 484 int 485 pci_freecfg(struct pci_devinfo *dinfo) 486 { 487 struct devlist *devlist_head; 488 489 devlist_head = &pci_devq; 490 491 if (dinfo->cfg.hdrspec != NULL) 492 free(dinfo->cfg.hdrspec, M_DEVBUF); 493 /* XXX this hasn't been tested */ 494 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 495 free(dinfo, M_DEVBUF); 496 497 /* increment the generation count */ 498 pci_generation++; 499 500 /* we're losing one device */ 501 pci_numdevs--; 502 return (0); 503 } 504 505 506 /* 507 * PCI power manangement 508 */ 509 int 510 pci_set_powerstate_method(device_t dev, device_t child, int state) 511 { 512 struct pci_devinfo *dinfo = device_get_ivars(child); 513 pcicfgregs *cfg = &dinfo->cfg; 514 u_int16_t status; 515 int result; 516 517 if (cfg->pp_cap != 0) { 518 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 519 result = 0; 520 switch (state) { 521 case PCI_POWERSTATE_D0: 522 status |= PCIM_PSTAT_D0; 523 break; 524 case PCI_POWERSTATE_D1: 525 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 526 status |= PCIM_PSTAT_D1; 527 } else { 528 result = EOPNOTSUPP; 529 } 530 break; 531 case PCI_POWERSTATE_D2: 532 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 533 status |= PCIM_PSTAT_D2; 534 } else { 535 result = EOPNOTSUPP; 536 } 537 break; 538 case PCI_POWERSTATE_D3: 539 status |= PCIM_PSTAT_D3; 540 break; 541 default: 542 result = EINVAL; 543 } 544 if (result == 0) 545 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 546 } else { 547 result = ENXIO; 548 } 549 return(result); 550 } 551 552 int 553 pci_get_powerstate_method(device_t dev, device_t child) 554 { 555 struct pci_devinfo *dinfo = device_get_ivars(child); 556 pcicfgregs *cfg = &dinfo->cfg; 557 u_int16_t status; 558 int result; 559 560 if (cfg->pp_cap != 0) { 561 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 562 switch (status & PCIM_PSTAT_DMASK) { 563 case PCIM_PSTAT_D0: 564 result = PCI_POWERSTATE_D0; 565 break; 566 case PCIM_PSTAT_D1: 567 result = PCI_POWERSTATE_D1; 568 break; 569 case PCIM_PSTAT_D2: 570 result = PCI_POWERSTATE_D2; 571 break; 572 case PCIM_PSTAT_D3: 573 result = PCI_POWERSTATE_D3; 574 break; 575 default: 576 result = PCI_POWERSTATE_UNKNOWN; 577 break; 578 } 579 } else { 580 /* No support, device is always at D0 */ 581 result = PCI_POWERSTATE_D0; 582 } 583 return(result); 584 } 585 586 /* 587 * Some convenience functions for PCI device drivers. 588 */ 589 590 static __inline void 591 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 592 { 593 u_int16_t command; 594 595 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 596 command |= bit; 597 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 598 } 599 600 static __inline void 601 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 602 { 603 u_int16_t command; 604 605 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 606 command &= ~bit; 607 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 608 } 609 610 int 611 pci_enable_busmaster_method(device_t dev, device_t child) 612 { 613 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 614 return(0); 615 } 616 617 int 618 pci_disable_busmaster_method(device_t dev, device_t child) 619 { 620 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 621 return(0); 622 } 623 624 int 625 pci_enable_io_method(device_t dev, device_t child, int space) 626 { 627 uint16_t command; 628 uint16_t bit; 629 char *error; 630 631 bit = 0; 632 error = NULL; 633 634 switch(space) { 635 case SYS_RES_IOPORT: 636 bit = PCIM_CMD_PORTEN; 637 error = "port"; 638 break; 639 case SYS_RES_MEMORY: 640 bit = PCIM_CMD_MEMEN; 641 error = "memory"; 642 break; 643 default: 644 return(EINVAL); 645 } 646 pci_set_command_bit(dev, child, bit); 647 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 648 if (command & bit) 649 return(0); 650 device_printf(child, "failed to enable %s mapping!\n", error); 651 return(ENXIO); 652 } 653 654 int 655 pci_disable_io_method(device_t dev, device_t child, int space) 656 { 657 uint16_t command; 658 uint16_t bit; 659 char *error; 660 661 bit = 0; 662 error = NULL; 663 664 switch(space) { 665 case SYS_RES_IOPORT: 666 bit = PCIM_CMD_PORTEN; 667 error = "port"; 668 break; 669 case SYS_RES_MEMORY: 670 bit = PCIM_CMD_MEMEN; 671 error = "memory"; 672 break; 673 default: 674 return (EINVAL); 675 } 676 pci_clear_command_bit(dev, child, bit); 677 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 678 if (command & bit) { 679 device_printf(child, "failed to disable %s mapping!\n", error); 680 return (ENXIO); 681 } 682 return (0); 683 } 684 685 /* 686 * This is the user interface to PCI configuration space. 687 */ 688 689 static int 690 pci_open(struct dev_open_args *ap) 691 { 692 if ((ap->a_oflags & FWRITE) && securelevel > 0) { 693 return EPERM; 694 } 695 return 0; 696 } 697 698 static int 699 pci_close(struct dev_close_args *ap) 700 { 701 return 0; 702 } 703 704 /* 705 * Match a single pci_conf structure against an array of pci_match_conf 706 * structures. The first argument, 'matches', is an array of num_matches 707 * pci_match_conf structures. match_buf is a pointer to the pci_conf 708 * structure that will be compared to every entry in the matches array. 709 * This function returns 1 on failure, 0 on success. 710 */ 711 static int 712 pci_conf_match(struct pci_match_conf *matches, int num_matches, 713 struct pci_conf *match_buf) 714 { 715 int i; 716 717 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 718 return(1); 719 720 for (i = 0; i < num_matches; i++) { 721 /* 722 * I'm not sure why someone would do this...but... 723 */ 724 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 725 continue; 726 727 /* 728 * Look at each of the match flags. If it's set, do the 729 * comparison. If the comparison fails, we don't have a 730 * match, go on to the next item if there is one. 731 */ 732 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 733 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 734 continue; 735 736 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 737 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 738 continue; 739 740 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 741 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 742 continue; 743 744 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 745 && (match_buf->pc_vendor != matches[i].pc_vendor)) 746 continue; 747 748 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 749 && (match_buf->pc_device != matches[i].pc_device)) 750 continue; 751 752 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 753 && (match_buf->pc_class != matches[i].pc_class)) 754 continue; 755 756 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 757 && (match_buf->pd_unit != matches[i].pd_unit)) 758 continue; 759 760 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 761 && (strncmp(matches[i].pd_name, match_buf->pd_name, 762 sizeof(match_buf->pd_name)) != 0)) 763 continue; 764 765 return(0); 766 } 767 768 return(1); 769 } 770 771 /* 772 * Locate the parent of a PCI device by scanning the PCI devlist 773 * and return the entry for the parent. 774 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 775 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 776 */ 777 778 pcicfgregs * 779 pci_devlist_get_parent(pcicfgregs *cfg) 780 { 781 struct devlist *devlist_head; 782 struct pci_devinfo *dinfo; 783 pcicfgregs *bridge_cfg; 784 int i; 785 786 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 787 788 /* If the device is on PCI bus 0, look for the host */ 789 if (cfg->bus == 0) { 790 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 791 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 792 bridge_cfg = &dinfo->cfg; 793 if (bridge_cfg->baseclass == PCIC_BRIDGE 794 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 795 && bridge_cfg->bus == cfg->bus) { 796 return bridge_cfg; 797 } 798 } 799 } 800 801 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 802 if (cfg->bus > 0) { 803 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 804 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 805 bridge_cfg = &dinfo->cfg; 806 if (bridge_cfg->baseclass == PCIC_BRIDGE 807 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 808 && bridge_cfg->secondarybus == cfg->bus) { 809 return bridge_cfg; 810 } 811 } 812 } 813 814 return NULL; 815 } 816 817 static int 818 pci_ioctl(struct dev_ioctl_args *ap) 819 { 820 device_t pci, pcib; 821 struct pci_io *io; 822 const char *name; 823 int error; 824 825 if (!(ap->a_fflag & FWRITE)) 826 return EPERM; 827 828 switch(ap->a_cmd) { 829 case PCIOCGETCONF: 830 { 831 struct pci_devinfo *dinfo; 832 struct pci_conf_io *cio; 833 struct devlist *devlist_head; 834 struct pci_match_conf *pattern_buf; 835 int num_patterns; 836 size_t iolen; 837 int ionum, i; 838 839 cio = (struct pci_conf_io *)ap->a_data; 840 841 num_patterns = 0; 842 dinfo = NULL; 843 844 /* 845 * Hopefully the user won't pass in a null pointer, but it 846 * can't hurt to check. 847 */ 848 if (cio == NULL) { 849 error = EINVAL; 850 break; 851 } 852 853 /* 854 * If the user specified an offset into the device list, 855 * but the list has changed since they last called this 856 * ioctl, tell them that the list has changed. They will 857 * have to get the list from the beginning. 858 */ 859 if ((cio->offset != 0) 860 && (cio->generation != pci_generation)){ 861 cio->num_matches = 0; 862 cio->status = PCI_GETCONF_LIST_CHANGED; 863 error = 0; 864 break; 865 } 866 867 /* 868 * Check to see whether the user has asked for an offset 869 * past the end of our list. 870 */ 871 if (cio->offset >= pci_numdevs) { 872 cio->num_matches = 0; 873 cio->status = PCI_GETCONF_LAST_DEVICE; 874 error = 0; 875 break; 876 } 877 878 /* get the head of the device queue */ 879 devlist_head = &pci_devq; 880 881 /* 882 * Determine how much room we have for pci_conf structures. 883 * Round the user's buffer size down to the nearest 884 * multiple of sizeof(struct pci_conf) in case the user 885 * didn't specify a multiple of that size. 886 */ 887 iolen = min(cio->match_buf_len - 888 (cio->match_buf_len % sizeof(struct pci_conf)), 889 pci_numdevs * sizeof(struct pci_conf)); 890 891 /* 892 * Since we know that iolen is a multiple of the size of 893 * the pciconf union, it's okay to do this. 894 */ 895 ionum = iolen / sizeof(struct pci_conf); 896 897 /* 898 * If this test is true, the user wants the pci_conf 899 * structures returned to match the supplied entries. 900 */ 901 if ((cio->num_patterns > 0) 902 && (cio->pat_buf_len > 0)) { 903 /* 904 * pat_buf_len needs to be: 905 * num_patterns * sizeof(struct pci_match_conf) 906 * While it is certainly possible the user just 907 * allocated a large buffer, but set the number of 908 * matches correctly, it is far more likely that 909 * their kernel doesn't match the userland utility 910 * they're using. It's also possible that the user 911 * forgot to initialize some variables. Yes, this 912 * may be overly picky, but I hazard to guess that 913 * it's far more likely to just catch folks that 914 * updated their kernel but not their userland. 915 */ 916 if ((cio->num_patterns * 917 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 918 /* The user made a mistake, return an error*/ 919 cio->status = PCI_GETCONF_ERROR; 920 printf("pci_ioctl: pat_buf_len %d != " 921 "num_patterns (%d) * sizeof(struct " 922 "pci_match_conf) (%d)\npci_ioctl: " 923 "pat_buf_len should be = %d\n", 924 cio->pat_buf_len, cio->num_patterns, 925 (int)sizeof(struct pci_match_conf), 926 (int)sizeof(struct pci_match_conf) * 927 cio->num_patterns); 928 printf("pci_ioctl: do your headers match your " 929 "kernel?\n"); 930 cio->num_matches = 0; 931 error = EINVAL; 932 break; 933 } 934 935 /* 936 * Check the user's buffer to make sure it's readable. 937 */ 938 if (!useracc((caddr_t)cio->patterns, 939 cio->pat_buf_len, VM_PROT_READ)) { 940 printf("pci_ioctl: pattern buffer %p, " 941 "length %u isn't user accessible for" 942 " READ\n", cio->patterns, 943 cio->pat_buf_len); 944 error = EACCES; 945 break; 946 } 947 /* 948 * Allocate a buffer to hold the patterns. 949 */ 950 pattern_buf = malloc(cio->pat_buf_len, M_TEMP, 951 M_WAITOK); 952 error = copyin(cio->patterns, pattern_buf, 953 cio->pat_buf_len); 954 if (error != 0) 955 break; 956 num_patterns = cio->num_patterns; 957 958 } else if ((cio->num_patterns > 0) 959 || (cio->pat_buf_len > 0)) { 960 /* 961 * The user made a mistake, spit out an error. 962 */ 963 cio->status = PCI_GETCONF_ERROR; 964 cio->num_matches = 0; 965 printf("pci_ioctl: invalid GETCONF arguments\n"); 966 error = EINVAL; 967 break; 968 } else 969 pattern_buf = NULL; 970 971 /* 972 * Make sure we can write to the match buffer. 973 */ 974 if (!useracc((caddr_t)cio->matches, 975 cio->match_buf_len, VM_PROT_WRITE)) { 976 printf("pci_ioctl: match buffer %p, length %u " 977 "isn't user accessible for WRITE\n", 978 cio->matches, cio->match_buf_len); 979 error = EACCES; 980 break; 981 } 982 983 /* 984 * Go through the list of devices and copy out the devices 985 * that match the user's criteria. 986 */ 987 for (cio->num_matches = 0, error = 0, i = 0, 988 dinfo = STAILQ_FIRST(devlist_head); 989 (dinfo != NULL) && (cio->num_matches < ionum) 990 && (error == 0) && (i < pci_numdevs); 991 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 992 993 if (i < cio->offset) 994 continue; 995 996 /* Populate pd_name and pd_unit */ 997 name = NULL; 998 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 999 name = device_get_name(dinfo->cfg.dev); 1000 if (name) { 1001 strncpy(dinfo->conf.pd_name, name, 1002 sizeof(dinfo->conf.pd_name)); 1003 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 1004 dinfo->conf.pd_unit = 1005 device_get_unit(dinfo->cfg.dev); 1006 } 1007 1008 if ((pattern_buf == NULL) || 1009 (pci_conf_match(pattern_buf, num_patterns, 1010 &dinfo->conf) == 0)) { 1011 1012 /* 1013 * If we've filled up the user's buffer, 1014 * break out at this point. Since we've 1015 * got a match here, we'll pick right back 1016 * up at the matching entry. We can also 1017 * tell the user that there are more matches 1018 * left. 1019 */ 1020 if (cio->num_matches >= ionum) 1021 break; 1022 1023 error = copyout(&dinfo->conf, 1024 &cio->matches[cio->num_matches], 1025 sizeof(struct pci_conf)); 1026 cio->num_matches++; 1027 } 1028 } 1029 1030 /* 1031 * Set the pointer into the list, so if the user is getting 1032 * n records at a time, where n < pci_numdevs, 1033 */ 1034 cio->offset = i; 1035 1036 /* 1037 * Set the generation, the user will need this if they make 1038 * another ioctl call with offset != 0. 1039 */ 1040 cio->generation = pci_generation; 1041 1042 /* 1043 * If this is the last device, inform the user so he won't 1044 * bother asking for more devices. If dinfo isn't NULL, we 1045 * know that there are more matches in the list because of 1046 * the way the traversal is done. 1047 */ 1048 if (dinfo == NULL) 1049 cio->status = PCI_GETCONF_LAST_DEVICE; 1050 else 1051 cio->status = PCI_GETCONF_MORE_DEVS; 1052 1053 if (pattern_buf != NULL) 1054 free(pattern_buf, M_TEMP); 1055 1056 break; 1057 } 1058 case PCIOCREAD: 1059 io = (struct pci_io *)ap->a_data; 1060 switch(io->pi_width) { 1061 case 4: 1062 case 2: 1063 case 1: 1064 /* 1065 * Assume that the user-level bus number is 1066 * actually the pciN instance number. We map 1067 * from that to the real pcib+bus combination. 1068 */ 1069 pci = devclass_get_device(pci_devclass, 1070 io->pi_sel.pc_bus); 1071 if (pci) { 1072 /* 1073 * pci is the pci device and may contain 1074 * several children (for each function code). 1075 * The governing pci bus is the parent to 1076 * the pci device. 1077 */ 1078 int b; 1079 1080 pcib = device_get_parent(pci); 1081 b = pcib_get_bus(pcib); 1082 io->pi_data = 1083 PCIB_READ_CONFIG(pcib, 1084 b, 1085 io->pi_sel.pc_dev, 1086 io->pi_sel.pc_func, 1087 io->pi_reg, 1088 io->pi_width); 1089 error = 0; 1090 } else { 1091 error = ENODEV; 1092 } 1093 break; 1094 default: 1095 error = ENODEV; 1096 break; 1097 } 1098 break; 1099 1100 case PCIOCWRITE: 1101 io = (struct pci_io *)ap->a_data; 1102 switch(io->pi_width) { 1103 case 4: 1104 case 2: 1105 case 1: 1106 /* 1107 * Assume that the user-level bus number is 1108 * actually the pciN instance number. We map 1109 * from that to the real pcib+bus combination. 1110 */ 1111 pci = devclass_get_device(pci_devclass, 1112 io->pi_sel.pc_bus); 1113 if (pci) { 1114 /* 1115 * pci is the pci device and may contain 1116 * several children (for each function code). 1117 * The governing pci bus is the parent to 1118 * the pci device. 1119 */ 1120 int b; 1121 1122 pcib = device_get_parent(pci); 1123 b = pcib_get_bus(pcib); 1124 PCIB_WRITE_CONFIG(pcib, 1125 b, 1126 io->pi_sel.pc_dev, 1127 io->pi_sel.pc_func, 1128 io->pi_reg, 1129 io->pi_data, 1130 io->pi_width); 1131 error = 0; 1132 } else { 1133 error = ENODEV; 1134 } 1135 break; 1136 default: 1137 error = ENODEV; 1138 break; 1139 } 1140 break; 1141 1142 default: 1143 error = ENOTTY; 1144 break; 1145 } 1146 1147 return (error); 1148 } 1149 1150 #define PCI_CDEV 78 1151 1152 static struct dev_ops pcic_ops = { 1153 { "pci", PCI_CDEV, 0 }, 1154 .d_open = pci_open, 1155 .d_close = pci_close, 1156 .d_ioctl = pci_ioctl, 1157 }; 1158 1159 #include "pci_if.h" 1160 1161 /* 1162 * New style pci driver. Parent device is either a pci-host-bridge or a 1163 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1164 */ 1165 const char * 1166 pci_class_to_string(int baseclass) 1167 { 1168 const char *name; 1169 1170 switch(baseclass) { 1171 case PCIC_OLD: 1172 name = "OLD"; 1173 break; 1174 case PCIC_STORAGE: 1175 name = "STORAGE"; 1176 break; 1177 case PCIC_NETWORK: 1178 name = "NETWORK"; 1179 break; 1180 case PCIC_DISPLAY: 1181 name = "DISPLAY"; 1182 break; 1183 case PCIC_MULTIMEDIA: 1184 name = "MULTIMEDIA"; 1185 break; 1186 case PCIC_MEMORY: 1187 name = "MEMORY"; 1188 break; 1189 case PCIC_BRIDGE: 1190 name = "BRIDGE"; 1191 break; 1192 case PCIC_SIMPLECOMM: 1193 name = "SIMPLECOMM"; 1194 break; 1195 case PCIC_BASEPERIPH: 1196 name = "BASEPERIPH"; 1197 break; 1198 case PCIC_INPUTDEV: 1199 name = "INPUTDEV"; 1200 break; 1201 case PCIC_DOCKING: 1202 name = "DOCKING"; 1203 break; 1204 case PCIC_PROCESSOR: 1205 name = "PROCESSOR"; 1206 break; 1207 case PCIC_SERIALBUS: 1208 name = "SERIALBUS"; 1209 break; 1210 case PCIC_WIRELESS: 1211 name = "WIRELESS"; 1212 break; 1213 case PCIC_I2O: 1214 name = "I20"; 1215 break; 1216 case PCIC_SATELLITE: 1217 name = "SATELLITE"; 1218 break; 1219 case PCIC_CRYPTO: 1220 name = "CRYPTO"; 1221 break; 1222 case PCIC_SIGPROC: 1223 name = "SIGPROC"; 1224 break; 1225 case PCIC_OTHER: 1226 name = "OTHER"; 1227 break; 1228 default: 1229 name = "?"; 1230 break; 1231 } 1232 return(name); 1233 } 1234 1235 void 1236 pci_print_verbose(struct pci_devinfo *dinfo) 1237 { 1238 if (bootverbose) { 1239 pcicfgregs *cfg = &dinfo->cfg; 1240 1241 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1242 cfg->vendor, cfg->device, cfg->revid); 1243 printf("\tbus=%d, slot=%d, func=%d\n", 1244 cfg->bus, cfg->slot, cfg->func); 1245 printf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1246 pci_class_to_string(cfg->baseclass), 1247 cfg->baseclass, cfg->subclass, cfg->progif, 1248 cfg->hdrtype, cfg->mfdev); 1249 printf("\tsubordinatebus=%x \tsecondarybus=%x\n", 1250 cfg->subordinatebus, cfg->secondarybus); 1251 #ifdef PCI_DEBUG 1252 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1253 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1254 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1255 cfg->lattimer, cfg->lattimer * 30, 1256 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1257 #endif /* PCI_DEBUG */ 1258 if (cfg->intpin > 0) 1259 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 1260 } 1261 } 1262 1263 static int 1264 pci_porten(device_t pcib, int b, int s, int f) 1265 { 1266 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1267 & PCIM_CMD_PORTEN) != 0; 1268 } 1269 1270 static int 1271 pci_memen(device_t pcib, int b, int s, int f) 1272 { 1273 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1274 & PCIM_CMD_MEMEN) != 0; 1275 } 1276 1277 /* 1278 * Add a resource based on a pci map register. Return 1 if the map 1279 * register is a 32bit map register or 2 if it is a 64bit register. 1280 */ 1281 static int 1282 pci_add_map(device_t pcib, int b, int s, int f, int reg, 1283 struct resource_list *rl) 1284 { 1285 u_int32_t map; 1286 u_int64_t base; 1287 u_int8_t ln2size; 1288 u_int8_t ln2range; 1289 u_int32_t testval; 1290 1291 1292 #ifdef PCI_ENABLE_IO_MODES 1293 u_int16_t cmd; 1294 #endif 1295 int type; 1296 1297 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1298 1299 if (map == 0 || map == 0xffffffff) 1300 return 1; /* skip invalid entry */ 1301 1302 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1303 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1304 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1305 1306 base = pci_mapbase(map); 1307 if (pci_maptype(map) & PCI_MAPMEM) 1308 type = SYS_RES_MEMORY; 1309 else 1310 type = SYS_RES_IOPORT; 1311 ln2size = pci_mapsize(testval); 1312 ln2range = pci_maprange(testval); 1313 if (ln2range == 64) { 1314 /* Read the other half of a 64bit map register */ 1315 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4); 1316 } 1317 1318 /* 1319 * This code theoretically does the right thing, but has 1320 * undesirable side effects in some cases where 1321 * peripherals respond oddly to having these bits 1322 * enabled. Leave them alone by default. 1323 */ 1324 #ifdef PCI_ENABLE_IO_MODES 1325 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1326 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1327 cmd |= PCIM_CMD_PORTEN; 1328 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1329 } 1330 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1331 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1332 cmd |= PCIM_CMD_MEMEN; 1333 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1334 } 1335 #else 1336 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1337 return 1; 1338 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1339 return 1; 1340 #endif 1341 1342 resource_list_add(rl, type, reg, 1343 base, base + (1 << ln2size) - 1, 1344 (1 << ln2size)); 1345 1346 if (bootverbose) { 1347 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n", 1348 reg, pci_maptype(base), ln2range, 1349 (unsigned int) base, ln2size); 1350 } 1351 1352 return (ln2range == 64) ? 2 : 1; 1353 } 1354 1355 static void 1356 pci_add_resources(device_t pcib, device_t bus, device_t dev) 1357 { 1358 struct pci_devinfo *dinfo = device_get_ivars(dev); 1359 pcicfgregs *cfg = &dinfo->cfg; 1360 struct resource_list *rl = &dinfo->resources; 1361 struct pci_quirk *q; 1362 int b, i, f, s; 1363 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */ 1364 int irq; 1365 #endif 1366 1367 b = cfg->bus; 1368 s = cfg->slot; 1369 f = cfg->func; 1370 for (i = 0; i < cfg->nummaps;) { 1371 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl); 1372 } 1373 1374 for (q = &pci_quirks[0]; q->devid; q++) { 1375 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1376 && q->type == PCI_QUIRK_MAP_REG) 1377 pci_add_map(pcib, b, s, f, q->arg1, rl); 1378 } 1379 1380 if (cfg->intpin > 0 && cfg->intline != 255) 1381 resource_list_add(rl, SYS_RES_IRQ, 0, 1382 cfg->intline, cfg->intline, 1); 1383 } 1384 1385 void 1386 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1387 { 1388 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1389 device_t pcib = device_get_parent(dev); 1390 struct pci_devinfo *dinfo; 1391 int maxslots; 1392 int s, f, pcifunchigh; 1393 uint8_t hdrtype; 1394 1395 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo)); 1396 1397 maxslots = PCIB_MAXSLOTS(pcib); 1398 1399 for (s = 0; s <= maxslots; s++) { 1400 pcifunchigh = 0; 1401 f = 0; 1402 hdrtype = REG(PCIR_HDRTYPE, 1); 1403 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1404 continue; 1405 if (hdrtype & PCIM_MFDEV) 1406 pcifunchigh = PCI_FUNCMAX; 1407 for (f = 0; f <= pcifunchigh; f++) { 1408 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1409 if (dinfo != NULL) { 1410 pci_add_child(dev, dinfo); 1411 } 1412 } 1413 } 1414 #undef REG 1415 } 1416 1417 /* 1418 * The actual PCI child that we add has a NULL driver whos parent 1419 * device will be "pci". The child contains the ivars, not the parent. 1420 */ 1421 void 1422 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1423 { 1424 device_t pcib; 1425 1426 pcib = device_get_parent(bus); 1427 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1428 device_set_ivars(dinfo->cfg.dev, dinfo); 1429 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1430 pci_print_verbose(dinfo); 1431 } 1432 1433 /* 1434 * Probe the PCI bus. Note: probe code is not supposed to add children 1435 * or call attach. 1436 */ 1437 static int 1438 pci_probe(device_t dev) 1439 { 1440 device_set_desc(dev, "PCI bus"); 1441 1442 /* Allow other subclasses to override this driver */ 1443 return(-1000); 1444 } 1445 1446 static int 1447 pci_attach(device_t dev) 1448 { 1449 int busno; 1450 int lunit = device_get_unit(dev); 1451 1452 dev_ops_add(&pcic_ops, -1, lunit); 1453 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit); 1454 1455 /* 1456 * Since there can be multiple independantly numbered PCI 1457 * busses on some large alpha systems, we can't use the unit 1458 * number to decide what bus we are probing. We ask the parent 1459 * pcib what our bus number is. 1460 * 1461 * pcib_get_bus() must act on the pci bus device, not on the pci 1462 * device, because it uses badly hacked nexus-based ivars to 1463 * store and retrieve the physical bus number. XXX 1464 */ 1465 busno = pcib_get_bus(device_get_parent(dev)); 1466 if (bootverbose) 1467 device_printf(dev, "pci_attach() physical bus=%d\n", busno); 1468 1469 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1470 1471 return (bus_generic_attach(dev)); 1472 } 1473 1474 static int 1475 pci_print_resources(struct resource_list *rl, const char *name, int type, 1476 const char *format) 1477 { 1478 struct resource_list_entry *rle; 1479 int printed, retval; 1480 1481 printed = 0; 1482 retval = 0; 1483 /* Yes, this is kinda cheating */ 1484 SLIST_FOREACH(rle, rl, link) { 1485 if (rle->type == type) { 1486 if (printed == 0) 1487 retval += printf(" %s ", name); 1488 else if (printed > 0) 1489 retval += printf(","); 1490 printed++; 1491 retval += printf(format, rle->start); 1492 if (rle->count > 1) { 1493 retval += printf("-"); 1494 retval += printf(format, rle->start + 1495 rle->count - 1); 1496 } 1497 } 1498 } 1499 return retval; 1500 } 1501 1502 int 1503 pci_print_child(device_t dev, device_t child) 1504 { 1505 struct pci_devinfo *dinfo; 1506 struct resource_list *rl; 1507 pcicfgregs *cfg; 1508 int retval = 0; 1509 1510 dinfo = device_get_ivars(child); 1511 cfg = &dinfo->cfg; 1512 rl = &dinfo->resources; 1513 1514 retval += bus_print_child_header(dev, child); 1515 1516 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 1517 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1518 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 1519 if (device_get_flags(dev)) 1520 retval += printf(" flags %#x", device_get_flags(dev)); 1521 1522 retval += printf(" at device %d.%d", pci_get_slot(child), 1523 pci_get_function(child)); 1524 1525 retval += bus_print_child_footer(dev, child); 1526 1527 return (retval); 1528 } 1529 1530 void 1531 pci_probe_nomatch(device_t dev, device_t child) 1532 { 1533 struct pci_devinfo *dinfo; 1534 pcicfgregs *cfg; 1535 const char *desc; 1536 int unknown; 1537 1538 unknown = 0; 1539 dinfo = device_get_ivars(child); 1540 cfg = &dinfo->cfg; 1541 desc = pci_ata_match(child); 1542 if (!desc) desc = pci_usb_match(child); 1543 if (!desc) desc = pci_vga_match(child); 1544 if (!desc) desc = pci_chip_match(child); 1545 if (!desc) { 1546 desc = "unknown card"; 1547 unknown++; 1548 } 1549 device_printf(dev, "<%s>", desc); 1550 if (bootverbose || unknown) { 1551 printf(" (vendor=0x%04x, dev=0x%04x)", 1552 cfg->vendor, 1553 cfg->device); 1554 } 1555 printf(" at %d.%d", 1556 pci_get_slot(child), 1557 pci_get_function(child)); 1558 if (cfg->intpin > 0 && cfg->intline != 255) { 1559 printf(" irq %d", cfg->intline); 1560 } 1561 printf("\n"); 1562 1563 return; 1564 } 1565 1566 int 1567 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1568 { 1569 struct pci_devinfo *dinfo; 1570 pcicfgregs *cfg; 1571 1572 dinfo = device_get_ivars(child); 1573 cfg = &dinfo->cfg; 1574 1575 switch (which) { 1576 case PCI_IVAR_SUBVENDOR: 1577 *result = cfg->subvendor; 1578 break; 1579 case PCI_IVAR_SUBDEVICE: 1580 *result = cfg->subdevice; 1581 break; 1582 case PCI_IVAR_VENDOR: 1583 *result = cfg->vendor; 1584 break; 1585 case PCI_IVAR_DEVICE: 1586 *result = cfg->device; 1587 break; 1588 case PCI_IVAR_DEVID: 1589 *result = (cfg->device << 16) | cfg->vendor; 1590 break; 1591 case PCI_IVAR_CLASS: 1592 *result = cfg->baseclass; 1593 break; 1594 case PCI_IVAR_SUBCLASS: 1595 *result = cfg->subclass; 1596 break; 1597 case PCI_IVAR_PROGIF: 1598 *result = cfg->progif; 1599 break; 1600 case PCI_IVAR_REVID: 1601 *result = cfg->revid; 1602 break; 1603 case PCI_IVAR_INTPIN: 1604 *result = cfg->intpin; 1605 break; 1606 case PCI_IVAR_IRQ: 1607 *result = cfg->intline; 1608 break; 1609 case PCI_IVAR_BUS: 1610 *result = cfg->bus; 1611 break; 1612 case PCI_IVAR_SLOT: 1613 *result = cfg->slot; 1614 break; 1615 case PCI_IVAR_FUNCTION: 1616 *result = cfg->func; 1617 break; 1618 case PCI_IVAR_SECONDARYBUS: 1619 *result = cfg->secondarybus; 1620 break; 1621 case PCI_IVAR_SUBORDINATEBUS: 1622 *result = cfg->subordinatebus; 1623 break; 1624 case PCI_IVAR_ETHADDR: 1625 /* 1626 * The generic accessor doesn't deal with failure, so 1627 * we set the return value, then return an error. 1628 */ 1629 *result = NULL; 1630 return (EINVAL); 1631 default: 1632 return ENOENT; 1633 } 1634 return 0; 1635 } 1636 1637 int 1638 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1639 { 1640 struct pci_devinfo *dinfo; 1641 pcicfgregs *cfg; 1642 1643 dinfo = device_get_ivars(child); 1644 cfg = &dinfo->cfg; 1645 1646 switch (which) { 1647 case PCI_IVAR_SUBVENDOR: 1648 case PCI_IVAR_SUBDEVICE: 1649 case PCI_IVAR_VENDOR: 1650 case PCI_IVAR_DEVICE: 1651 case PCI_IVAR_DEVID: 1652 case PCI_IVAR_CLASS: 1653 case PCI_IVAR_SUBCLASS: 1654 case PCI_IVAR_PROGIF: 1655 case PCI_IVAR_REVID: 1656 case PCI_IVAR_INTPIN: 1657 case PCI_IVAR_IRQ: 1658 case PCI_IVAR_BUS: 1659 case PCI_IVAR_SLOT: 1660 case PCI_IVAR_FUNCTION: 1661 case PCI_IVAR_ETHADDR: 1662 return EINVAL; /* disallow for now */ 1663 1664 case PCI_IVAR_SECONDARYBUS: 1665 cfg->secondarybus = value; 1666 break; 1667 case PCI_IVAR_SUBORDINATEBUS: 1668 cfg->subordinatebus = value; 1669 break; 1670 default: 1671 return ENOENT; 1672 } 1673 return 0; 1674 } 1675 1676 struct resource * 1677 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1678 u_long start, u_long end, u_long count, u_int flags) 1679 { 1680 struct pci_devinfo *dinfo = device_get_ivars(child); 1681 struct resource_list *rl = &dinfo->resources; 1682 pcicfgregs *cfg = &dinfo->cfg; 1683 1684 /* 1685 * Perform lazy resource allocation 1686 * 1687 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1688 */ 1689 if (device_get_parent(child) == dev) { 1690 switch (type) { 1691 case SYS_RES_IRQ: 1692 #ifdef __i386__ 1693 /* 1694 * If device doesn't have an interrupt routed, and is 1695 * deserving of an interrupt, try to assign it one. 1696 */ 1697 if ((cfg->intline == 255 || cfg->intline == 0) && 1698 (cfg->intpin != 0) && 1699 (start == 0) && (end == ~0UL)) { 1700 cfg->intline = PCIB_ROUTE_INTERRUPT( 1701 device_get_parent(dev), child, 1702 cfg->intpin); 1703 if (cfg->intline != 255) { 1704 pci_write_config(child, PCIR_INTLINE, 1705 cfg->intline, 1); 1706 resource_list_add(rl, SYS_RES_IRQ, 0, 1707 cfg->intline, cfg->intline, 1); 1708 } 1709 } 1710 break; 1711 #endif 1712 case SYS_RES_IOPORT: 1713 case SYS_RES_MEMORY: 1714 if (*rid < PCIR_BAR(cfg->nummaps)) { 1715 /* 1716 * Enable the I/O mode. We should 1717 * also be assigning resources too 1718 * when none are present. The 1719 * resource_list_alloc kind of sorta does 1720 * this... 1721 */ 1722 if (PCI_ENABLE_IO(dev, child, type)) 1723 return (NULL); 1724 } 1725 break; 1726 } 1727 } 1728 return resource_list_alloc(rl, dev, child, type, rid, 1729 start, end, count, flags); 1730 } 1731 1732 static int 1733 pci_release_resource(device_t dev, device_t child, int type, int rid, 1734 struct resource *r) 1735 { 1736 struct pci_devinfo *dinfo = device_get_ivars(child); 1737 struct resource_list *rl = &dinfo->resources; 1738 1739 return resource_list_release(rl, dev, child, type, rid, r); 1740 } 1741 1742 static int 1743 pci_set_resource(device_t dev, device_t child, int type, int rid, 1744 u_long start, u_long count) 1745 { 1746 struct pci_devinfo *dinfo = device_get_ivars(child); 1747 struct resource_list *rl = &dinfo->resources; 1748 1749 resource_list_add(rl, type, rid, start, start + count - 1, count); 1750 return 0; 1751 } 1752 1753 static int 1754 pci_get_resource(device_t dev, device_t child, int type, int rid, 1755 u_long *startp, u_long *countp) 1756 { 1757 struct pci_devinfo *dinfo = device_get_ivars(child); 1758 struct resource_list *rl = &dinfo->resources; 1759 struct resource_list_entry *rle; 1760 1761 rle = resource_list_find(rl, type, rid); 1762 if (!rle) 1763 return ENOENT; 1764 1765 if (startp) 1766 *startp = rle->start; 1767 if (countp) 1768 *countp = rle->count; 1769 1770 return 0; 1771 } 1772 1773 void 1774 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1775 { 1776 printf("pci_delete_resource: PCI resources can not be deleted\n"); 1777 } 1778 1779 struct resource_list * 1780 pci_get_resource_list (device_t dev, device_t child) 1781 { 1782 struct pci_devinfo * dinfo = device_get_ivars(child); 1783 struct resource_list * rl = &dinfo->resources; 1784 1785 if (!rl) 1786 return (NULL); 1787 1788 return (rl); 1789 } 1790 1791 u_int32_t 1792 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1793 { 1794 struct pci_devinfo *dinfo = device_get_ivars(child); 1795 pcicfgregs *cfg = &dinfo->cfg; 1796 1797 return PCIB_READ_CONFIG(device_get_parent(dev), 1798 cfg->bus, cfg->slot, cfg->func, 1799 reg, width); 1800 } 1801 1802 void 1803 pci_write_config_method(device_t dev, device_t child, int reg, 1804 u_int32_t val, int width) 1805 { 1806 struct pci_devinfo *dinfo = device_get_ivars(child); 1807 pcicfgregs *cfg = &dinfo->cfg; 1808 1809 PCIB_WRITE_CONFIG(device_get_parent(dev), 1810 cfg->bus, cfg->slot, cfg->func, 1811 reg, val, width); 1812 } 1813 1814 int 1815 pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 1816 size_t buflen) 1817 { 1818 struct pci_devinfo *dinfo; 1819 1820 dinfo = device_get_ivars(child); 1821 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1822 pci_get_function(child)); 1823 return (0); 1824 } 1825 1826 int 1827 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 1828 size_t buflen) 1829 { 1830 struct pci_devinfo *dinfo; 1831 pcicfgregs *cfg; 1832 1833 dinfo = device_get_ivars(child); 1834 cfg = &dinfo->cfg; 1835 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1836 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1837 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1838 cfg->progif); 1839 return (0); 1840 } 1841 1842 int 1843 pci_assign_interrupt_method(device_t dev, device_t child) 1844 { 1845 struct pci_devinfo *dinfo = device_get_ivars(child); 1846 pcicfgregs *cfg = &dinfo->cfg; 1847 1848 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1849 cfg->intpin)); 1850 } 1851 1852 static int 1853 pci_modevent(module_t mod, int what, void *arg) 1854 { 1855 switch (what) { 1856 case MOD_LOAD: 1857 STAILQ_INIT(&pci_devq); 1858 break; 1859 case MOD_UNLOAD: 1860 break; 1861 } 1862 1863 return 0; 1864 } 1865 1866 int 1867 pci_resume(device_t dev) 1868 { 1869 int numdevs; 1870 int i; 1871 device_t *children; 1872 device_t child; 1873 struct pci_devinfo *dinfo; 1874 pcicfgregs *cfg; 1875 1876 device_get_children(dev, &children, &numdevs); 1877 1878 for (i = 0; i < numdevs; i++) { 1879 child = children[i]; 1880 1881 dinfo = device_get_ivars(child); 1882 cfg = &dinfo->cfg; 1883 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1884 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1885 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1886 pci_write_config(child, PCIR_INTLINE, 1887 cfg->intline, 1); 1888 } 1889 } 1890 } 1891 1892 free(children, M_TEMP); 1893 1894 return (bus_generic_resume(dev)); 1895 } 1896 1897 static device_method_t pci_methods[] = { 1898 /* Device interface */ 1899 DEVMETHOD(device_probe, pci_probe), 1900 DEVMETHOD(device_attach, pci_attach), 1901 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1902 DEVMETHOD(device_suspend, bus_generic_suspend), 1903 DEVMETHOD(device_resume, pci_resume), 1904 1905 /* Bus interface */ 1906 DEVMETHOD(bus_print_child, pci_print_child), 1907 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 1908 DEVMETHOD(bus_read_ivar, pci_read_ivar), 1909 DEVMETHOD(bus_write_ivar, pci_write_ivar), 1910 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1911 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1912 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1913 1914 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 1915 DEVMETHOD(bus_set_resource, pci_set_resource), 1916 DEVMETHOD(bus_get_resource, pci_get_resource), 1917 DEVMETHOD(bus_delete_resource, pci_delete_resource), 1918 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 1919 DEVMETHOD(bus_release_resource, pci_release_resource), 1920 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1921 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1922 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 1923 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 1924 1925 /* PCI interface */ 1926 DEVMETHOD(pci_read_config, pci_read_config_method), 1927 DEVMETHOD(pci_write_config, pci_write_config_method), 1928 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 1929 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 1930 DEVMETHOD(pci_enable_io, pci_enable_io_method), 1931 DEVMETHOD(pci_disable_io, pci_disable_io_method), 1932 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 1933 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 1934 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 1935 1936 { 0, 0 } 1937 }; 1938 1939 static driver_t pci_driver = { 1940 "pci", 1941 pci_methods, 1942 1, /* no softc */ 1943 }; 1944 1945 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 1946 MODULE_VERSION(pci, 1); 1947