1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $ 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.29 2005/11/04 08:57:22 dillon Exp $ 28 * 29 */ 30 31 #include "opt_bus.h" 32 #include "opt_pci.h" 33 34 #include "opt_simos.h" 35 #include "opt_compat_oldpci.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/fcntl.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/buf.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 #include <vm/vm_extern.h> 51 52 #include <sys/bus.h> 53 #include <machine/bus.h> 54 #include <sys/rman.h> 55 #include <machine/resource.h> 56 #include <machine/md_var.h> /* For the Alpha */ 57 #include <machine/smp.h> 58 #ifdef __i386__ 59 #include <bus/pci/i386/pci_cfgreg.h> 60 #endif 61 62 #include <sys/pciio.h> 63 #include "pcireg.h" 64 #include "pcivar.h" 65 #include "pci_private.h" 66 67 #include "pcib_if.h" 68 69 devclass_t pci_devclass; 70 const char *pcib_owner; 71 72 static void pci_read_extcap(device_t dev, pcicfgregs *cfg); 73 74 struct pci_quirk { 75 u_int32_t devid; /* Vendor/device of the card */ 76 int type; 77 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 78 int arg1; 79 int arg2; 80 }; 81 82 struct pci_quirk pci_quirks[] = { 83 /* 84 * The Intel 82371AB and 82443MX has a map register at offset 0x90. 85 */ 86 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 87 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 88 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 89 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 90 91 { 0 } 92 }; 93 94 /* map register information */ 95 #define PCI_MAPMEM 0x01 /* memory map */ 96 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 97 #define PCI_MAPPORT 0x04 /* port map */ 98 99 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 100 u_int32_t pci_numdevs = 0; 101 static u_int32_t pci_generation = 0; 102 103 device_t 104 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func) 105 { 106 struct pci_devinfo *dinfo; 107 108 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 109 if ((dinfo->cfg.bus == bus) && 110 (dinfo->cfg.slot == slot) && 111 (dinfo->cfg.func == func)) { 112 return (dinfo->cfg.dev); 113 } 114 } 115 116 return (NULL); 117 } 118 119 device_t 120 pci_find_device (u_int16_t vendor, u_int16_t device) 121 { 122 struct pci_devinfo *dinfo; 123 124 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 125 if ((dinfo->cfg.vendor == vendor) && 126 (dinfo->cfg.device == device)) { 127 return (dinfo->cfg.dev); 128 } 129 } 130 131 return (NULL); 132 } 133 134 /* return base address of memory or port map */ 135 136 static u_int32_t 137 pci_mapbase(unsigned mapreg) 138 { 139 int mask = 0x03; 140 if ((mapreg & 0x01) == 0) 141 mask = 0x0f; 142 return (mapreg & ~mask); 143 } 144 145 /* return map type of memory or port map */ 146 147 static int 148 pci_maptype(unsigned mapreg) 149 { 150 static u_int8_t maptype[0x10] = { 151 PCI_MAPMEM, PCI_MAPPORT, 152 PCI_MAPMEM, 0, 153 PCI_MAPMEM, PCI_MAPPORT, 154 0, 0, 155 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 156 PCI_MAPMEM|PCI_MAPMEMP, 0, 157 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 158 0, 0, 159 }; 160 161 return maptype[mapreg & 0x0f]; 162 } 163 164 /* return log2 of map size decoded for memory or port map */ 165 166 static int 167 pci_mapsize(unsigned testval) 168 { 169 int ln2size; 170 171 testval = pci_mapbase(testval); 172 ln2size = 0; 173 if (testval != 0) { 174 while ((testval & 1) == 0) 175 { 176 ln2size++; 177 testval >>= 1; 178 } 179 } 180 return (ln2size); 181 } 182 183 /* return log2 of address range supported by map register */ 184 185 static int 186 pci_maprange(unsigned mapreg) 187 { 188 int ln2range = 0; 189 switch (mapreg & 0x07) { 190 case 0x00: 191 case 0x01: 192 case 0x05: 193 ln2range = 32; 194 break; 195 case 0x02: 196 ln2range = 20; 197 break; 198 case 0x04: 199 ln2range = 64; 200 break; 201 } 202 return (ln2range); 203 } 204 205 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 206 207 static void 208 pci_fixancient(pcicfgregs *cfg) 209 { 210 if (cfg->hdrtype != 0) 211 return; 212 213 /* PCI to PCI bridges use header type 1 */ 214 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 215 cfg->hdrtype = 1; 216 } 217 218 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 219 220 static void * 221 pci_readppb(device_t pcib, int b, int s, int f) 222 { 223 pcih1cfgregs *p; 224 225 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 226 if (p == NULL) 227 return (NULL); 228 229 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2); 230 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2); 231 232 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1); 233 234 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f, 235 PCIR_IOBASEH_1, 2), 236 PCIB_READ_CONFIG(pcib, b, s, f, 237 PCIR_IOBASEL_1, 1)); 238 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f, 239 PCIR_IOLIMITH_1, 2), 240 PCIB_READ_CONFIG(pcib, b, s, f, 241 PCIR_IOLIMITL_1, 1)); 242 243 p->membase = PCI_PPBMEMBASE (0, 244 PCIB_READ_CONFIG(pcib, b, s, f, 245 PCIR_MEMBASE_1, 2)); 246 p->memlimit = PCI_PPBMEMLIMIT (0, 247 PCIB_READ_CONFIG(pcib, b, s, f, 248 PCIR_MEMLIMIT_1, 2)); 249 250 p->pmembase = PCI_PPBMEMBASE ( 251 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4), 252 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2)); 253 254 p->pmemlimit = PCI_PPBMEMLIMIT ( 255 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, 256 PCIR_PMLIMITH_1, 4), 257 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2)); 258 259 return (p); 260 } 261 262 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 263 264 static void * 265 pci_readpcb(device_t pcib, int b, int s, int f) 266 { 267 pcih2cfgregs *p; 268 269 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 270 if (p == NULL) 271 return (NULL); 272 273 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2); 274 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2); 275 276 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1); 277 278 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4); 279 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4); 280 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4); 281 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4); 282 283 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4); 284 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4); 285 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4); 286 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4); 287 288 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4); 289 return p; 290 } 291 292 /* extract header type specific config data */ 293 294 static void 295 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 296 { 297 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 298 switch (cfg->hdrtype) { 299 case 0: 300 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 301 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 302 cfg->nummaps = PCI_MAXMAPS_0; 303 break; 304 case 1: 305 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 306 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 307 cfg->secondarybus = REG(PCIR_SECBUS_1, 1); 308 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1); 309 cfg->nummaps = PCI_MAXMAPS_1; 310 cfg->hdrspec = pci_readppb(pcib, b, s, f); 311 break; 312 case 2: 313 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 314 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 315 cfg->secondarybus = REG(PCIR_SECBUS_2, 1); 316 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1); 317 cfg->nummaps = PCI_MAXMAPS_2; 318 cfg->hdrspec = pci_readpcb(pcib, b, s, f); 319 break; 320 } 321 #undef REG 322 } 323 324 /* read configuration header into pcicfgrect structure */ 325 326 struct pci_devinfo * 327 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 328 { 329 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 330 331 pcicfgregs *cfg = NULL; 332 struct pci_devinfo *devlist_entry; 333 struct devlist *devlist_head; 334 335 devlist_head = &pci_devq; 336 337 devlist_entry = NULL; 338 339 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 340 341 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 342 if (devlist_entry == NULL) 343 return (NULL); 344 345 cfg = &devlist_entry->cfg; 346 347 cfg->bus = b; 348 cfg->slot = s; 349 cfg->func = f; 350 cfg->vendor = REG(PCIR_VENDOR, 2); 351 cfg->device = REG(PCIR_DEVICE, 2); 352 cfg->cmdreg = REG(PCIR_COMMAND, 2); 353 cfg->statreg = REG(PCIR_STATUS, 2); 354 cfg->baseclass = REG(PCIR_CLASS, 1); 355 cfg->subclass = REG(PCIR_SUBCLASS, 1); 356 cfg->progif = REG(PCIR_PROGIF, 1); 357 cfg->revid = REG(PCIR_REVID, 1); 358 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 359 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 360 cfg->lattimer = REG(PCIR_LATTIMER, 1); 361 cfg->intpin = REG(PCIR_INTPIN, 1); 362 cfg->intline = REG(PCIR_INTLINE, 1); 363 364 #ifdef APIC_IO 365 /* 366 * If using the APIC the intpin is probably wrong, since it 367 * is often setup by the BIOS with the PIC in mind. 368 */ 369 if (cfg->intpin != 0) { 370 int airq; 371 372 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 373 if (airq >= 0) { 374 /* PCI specific entry found in MP table */ 375 if (airq != cfg->intline) { 376 undirect_pci_irq(cfg->intline); 377 cfg->intline = airq; 378 } 379 } else { 380 /* 381 * PCI interrupts might be redirected to the 382 * ISA bus according to some MP tables. Use the 383 * same methods as used by the ISA devices 384 * devices to find the proper IOAPIC int pin. 385 */ 386 airq = isa_apic_irq(cfg->intline); 387 if ((airq >= 0) && (airq != cfg->intline)) { 388 /* XXX: undirect_pci_irq() ? */ 389 undirect_isa_irq(cfg->intline); 390 cfg->intline = airq; 391 } 392 } 393 } 394 #endif /* APIC_IO */ 395 396 cfg->mingnt = REG(PCIR_MINGNT, 1); 397 cfg->maxlat = REG(PCIR_MAXLAT, 1); 398 399 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 400 cfg->hdrtype &= ~PCIM_MFDEV; 401 402 pci_fixancient(cfg); 403 pci_hdrtypedata(pcib, b, s, f, cfg); 404 405 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 406 pci_read_extcap(pcib, cfg); 407 408 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 409 410 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 411 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 412 devlist_entry->conf.pc_sel.pc_func = cfg->func; 413 devlist_entry->conf.pc_hdr = cfg->hdrtype; 414 415 devlist_entry->conf.pc_subvendor = cfg->subvendor; 416 devlist_entry->conf.pc_subdevice = cfg->subdevice; 417 devlist_entry->conf.pc_vendor = cfg->vendor; 418 devlist_entry->conf.pc_device = cfg->device; 419 420 devlist_entry->conf.pc_class = cfg->baseclass; 421 devlist_entry->conf.pc_subclass = cfg->subclass; 422 devlist_entry->conf.pc_progif = cfg->progif; 423 devlist_entry->conf.pc_revid = cfg->revid; 424 425 pci_numdevs++; 426 pci_generation++; 427 } 428 return (devlist_entry); 429 #undef REG 430 } 431 432 static void 433 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 434 { 435 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 436 int ptr, nextptr, ptrptr; 437 438 switch (cfg->hdrtype) { 439 case 0: 440 ptrptr = 0x34; 441 break; 442 case 2: 443 ptrptr = 0x14; 444 break; 445 default: 446 return; /* no extended capabilities support */ 447 } 448 nextptr = REG(ptrptr, 1); /* sanity check? */ 449 450 /* 451 * Read capability entries. 452 */ 453 while (nextptr != 0) { 454 /* Sanity check */ 455 if (nextptr > 255) { 456 printf("illegal PCI extended capability offset %d\n", 457 nextptr); 458 return; 459 } 460 /* Find the next entry */ 461 ptr = nextptr; 462 nextptr = REG(ptr + 1, 1); 463 464 /* Process this entry */ 465 switch (REG(ptr, 1)) { 466 case 0x01: /* PCI power management */ 467 if (cfg->pp_cap == 0) { 468 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 469 cfg->pp_status = ptr + PCIR_POWER_STATUS; 470 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 471 if ((nextptr - ptr) > PCIR_POWER_DATA) 472 cfg->pp_data = ptr + PCIR_POWER_DATA; 473 } 474 break; 475 default: 476 break; 477 } 478 } 479 #undef REG 480 } 481 482 /* free pcicfgregs structure and all depending data structures */ 483 484 int 485 pci_freecfg(struct pci_devinfo *dinfo) 486 { 487 struct devlist *devlist_head; 488 489 devlist_head = &pci_devq; 490 491 if (dinfo->cfg.hdrspec != NULL) 492 free(dinfo->cfg.hdrspec, M_DEVBUF); 493 /* XXX this hasn't been tested */ 494 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 495 free(dinfo, M_DEVBUF); 496 497 /* increment the generation count */ 498 pci_generation++; 499 500 /* we're losing one device */ 501 pci_numdevs--; 502 return (0); 503 } 504 505 506 /* 507 * PCI power manangement 508 */ 509 int 510 pci_set_powerstate_method(device_t dev, device_t child, int state) 511 { 512 struct pci_devinfo *dinfo = device_get_ivars(child); 513 pcicfgregs *cfg = &dinfo->cfg; 514 u_int16_t status; 515 int result; 516 517 if (cfg->pp_cap != 0) { 518 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 519 result = 0; 520 switch (state) { 521 case PCI_POWERSTATE_D0: 522 status |= PCIM_PSTAT_D0; 523 break; 524 case PCI_POWERSTATE_D1: 525 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 526 status |= PCIM_PSTAT_D1; 527 } else { 528 result = EOPNOTSUPP; 529 } 530 break; 531 case PCI_POWERSTATE_D2: 532 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 533 status |= PCIM_PSTAT_D2; 534 } else { 535 result = EOPNOTSUPP; 536 } 537 break; 538 case PCI_POWERSTATE_D3: 539 status |= PCIM_PSTAT_D3; 540 break; 541 default: 542 result = EINVAL; 543 } 544 if (result == 0) 545 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 546 } else { 547 result = ENXIO; 548 } 549 return(result); 550 } 551 552 int 553 pci_get_powerstate_method(device_t dev, device_t child) 554 { 555 struct pci_devinfo *dinfo = device_get_ivars(child); 556 pcicfgregs *cfg = &dinfo->cfg; 557 u_int16_t status; 558 int result; 559 560 if (cfg->pp_cap != 0) { 561 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 562 switch (status & PCIM_PSTAT_DMASK) { 563 case PCIM_PSTAT_D0: 564 result = PCI_POWERSTATE_D0; 565 break; 566 case PCIM_PSTAT_D1: 567 result = PCI_POWERSTATE_D1; 568 break; 569 case PCIM_PSTAT_D2: 570 result = PCI_POWERSTATE_D2; 571 break; 572 case PCIM_PSTAT_D3: 573 result = PCI_POWERSTATE_D3; 574 break; 575 default: 576 result = PCI_POWERSTATE_UNKNOWN; 577 break; 578 } 579 } else { 580 /* No support, device is always at D0 */ 581 result = PCI_POWERSTATE_D0; 582 } 583 return(result); 584 } 585 586 /* 587 * Some convenience functions for PCI device drivers. 588 */ 589 590 static __inline void 591 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 592 { 593 u_int16_t command; 594 595 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 596 command |= bit; 597 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 598 } 599 600 static __inline void 601 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 602 { 603 u_int16_t command; 604 605 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 606 command &= ~bit; 607 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 608 } 609 610 int 611 pci_enable_busmaster_method(device_t dev, device_t child) 612 { 613 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 614 return(0); 615 } 616 617 int 618 pci_disable_busmaster_method(device_t dev, device_t child) 619 { 620 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 621 return(0); 622 } 623 624 int 625 pci_enable_io_method(device_t dev, device_t child, int space) 626 { 627 uint16_t command; 628 uint16_t bit; 629 char *error; 630 631 bit = 0; 632 error = NULL; 633 634 switch(space) { 635 case SYS_RES_IOPORT: 636 bit = PCIM_CMD_PORTEN; 637 error = "port"; 638 break; 639 case SYS_RES_MEMORY: 640 bit = PCIM_CMD_MEMEN; 641 error = "memory"; 642 break; 643 default: 644 return(EINVAL); 645 } 646 pci_set_command_bit(dev, child, bit); 647 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 648 if (command & bit) 649 return(0); 650 device_printf(child, "failed to enable %s mapping!\n", error); 651 return(ENXIO); 652 } 653 654 int 655 pci_disable_io_method(device_t dev, device_t child, int space) 656 { 657 uint16_t command; 658 uint16_t bit; 659 char *error; 660 661 bit = 0; 662 error = NULL; 663 664 switch(space) { 665 case SYS_RES_IOPORT: 666 bit = PCIM_CMD_PORTEN; 667 error = "port"; 668 break; 669 case SYS_RES_MEMORY: 670 bit = PCIM_CMD_MEMEN; 671 error = "memory"; 672 break; 673 default: 674 return (EINVAL); 675 } 676 pci_clear_command_bit(dev, child, bit); 677 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 678 if (command & bit) { 679 device_printf(child, "failed to disable %s mapping!\n", error); 680 return (ENXIO); 681 } 682 return (0); 683 } 684 685 /* 686 * This is the user interface to PCI configuration space. 687 */ 688 689 static int 690 pci_open(dev_t dev, int oflags, int devtype, struct thread *td) 691 { 692 if ((oflags & FWRITE) && securelevel > 0) { 693 return EPERM; 694 } 695 return 0; 696 } 697 698 static int 699 pci_close(dev_t dev, int flag, int devtype, struct thread *td) 700 { 701 return 0; 702 } 703 704 /* 705 * Match a single pci_conf structure against an array of pci_match_conf 706 * structures. The first argument, 'matches', is an array of num_matches 707 * pci_match_conf structures. match_buf is a pointer to the pci_conf 708 * structure that will be compared to every entry in the matches array. 709 * This function returns 1 on failure, 0 on success. 710 */ 711 static int 712 pci_conf_match(struct pci_match_conf *matches, int num_matches, 713 struct pci_conf *match_buf) 714 { 715 int i; 716 717 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 718 return(1); 719 720 for (i = 0; i < num_matches; i++) { 721 /* 722 * I'm not sure why someone would do this...but... 723 */ 724 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 725 continue; 726 727 /* 728 * Look at each of the match flags. If it's set, do the 729 * comparison. If the comparison fails, we don't have a 730 * match, go on to the next item if there is one. 731 */ 732 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 733 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 734 continue; 735 736 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 737 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 738 continue; 739 740 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 741 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 742 continue; 743 744 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 745 && (match_buf->pc_vendor != matches[i].pc_vendor)) 746 continue; 747 748 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 749 && (match_buf->pc_device != matches[i].pc_device)) 750 continue; 751 752 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 753 && (match_buf->pc_class != matches[i].pc_class)) 754 continue; 755 756 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 757 && (match_buf->pd_unit != matches[i].pd_unit)) 758 continue; 759 760 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 761 && (strncmp(matches[i].pd_name, match_buf->pd_name, 762 sizeof(match_buf->pd_name)) != 0)) 763 continue; 764 765 return(0); 766 } 767 768 return(1); 769 } 770 771 /* 772 * Locate the parent of a PCI device by scanning the PCI devlist 773 * and return the entry for the parent. 774 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 775 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 776 */ 777 778 pcicfgregs * 779 pci_devlist_get_parent(pcicfgregs *cfg) 780 { 781 struct devlist *devlist_head; 782 struct pci_devinfo *dinfo; 783 pcicfgregs *bridge_cfg; 784 int i; 785 786 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 787 788 /* If the device is on PCI bus 0, look for the host */ 789 if (cfg->bus == 0) { 790 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 791 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 792 bridge_cfg = &dinfo->cfg; 793 if (bridge_cfg->baseclass == PCIC_BRIDGE 794 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 795 && bridge_cfg->bus == cfg->bus) { 796 return bridge_cfg; 797 } 798 } 799 } 800 801 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 802 if (cfg->bus > 0) { 803 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 804 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 805 bridge_cfg = &dinfo->cfg; 806 if (bridge_cfg->baseclass == PCIC_BRIDGE 807 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 808 && bridge_cfg->secondarybus == cfg->bus) { 809 return bridge_cfg; 810 } 811 } 812 } 813 814 return NULL; 815 } 816 817 static int 818 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td) 819 { 820 device_t pci, pcib; 821 struct pci_io *io; 822 const char *name; 823 int error; 824 825 if (!(flag & FWRITE)) 826 return EPERM; 827 828 829 switch(cmd) { 830 case PCIOCGETCONF: 831 { 832 struct pci_devinfo *dinfo; 833 struct pci_conf_io *cio; 834 struct devlist *devlist_head; 835 struct pci_match_conf *pattern_buf; 836 int num_patterns; 837 size_t iolen; 838 int ionum, i; 839 840 cio = (struct pci_conf_io *)data; 841 842 num_patterns = 0; 843 dinfo = NULL; 844 845 /* 846 * Hopefully the user won't pass in a null pointer, but it 847 * can't hurt to check. 848 */ 849 if (cio == NULL) { 850 error = EINVAL; 851 break; 852 } 853 854 /* 855 * If the user specified an offset into the device list, 856 * but the list has changed since they last called this 857 * ioctl, tell them that the list has changed. They will 858 * have to get the list from the beginning. 859 */ 860 if ((cio->offset != 0) 861 && (cio->generation != pci_generation)){ 862 cio->num_matches = 0; 863 cio->status = PCI_GETCONF_LIST_CHANGED; 864 error = 0; 865 break; 866 } 867 868 /* 869 * Check to see whether the user has asked for an offset 870 * past the end of our list. 871 */ 872 if (cio->offset >= pci_numdevs) { 873 cio->num_matches = 0; 874 cio->status = PCI_GETCONF_LAST_DEVICE; 875 error = 0; 876 break; 877 } 878 879 /* get the head of the device queue */ 880 devlist_head = &pci_devq; 881 882 /* 883 * Determine how much room we have for pci_conf structures. 884 * Round the user's buffer size down to the nearest 885 * multiple of sizeof(struct pci_conf) in case the user 886 * didn't specify a multiple of that size. 887 */ 888 iolen = min(cio->match_buf_len - 889 (cio->match_buf_len % sizeof(struct pci_conf)), 890 pci_numdevs * sizeof(struct pci_conf)); 891 892 /* 893 * Since we know that iolen is a multiple of the size of 894 * the pciconf union, it's okay to do this. 895 */ 896 ionum = iolen / sizeof(struct pci_conf); 897 898 /* 899 * If this test is true, the user wants the pci_conf 900 * structures returned to match the supplied entries. 901 */ 902 if ((cio->num_patterns > 0) 903 && (cio->pat_buf_len > 0)) { 904 /* 905 * pat_buf_len needs to be: 906 * num_patterns * sizeof(struct pci_match_conf) 907 * While it is certainly possible the user just 908 * allocated a large buffer, but set the number of 909 * matches correctly, it is far more likely that 910 * their kernel doesn't match the userland utility 911 * they're using. It's also possible that the user 912 * forgot to initialize some variables. Yes, this 913 * may be overly picky, but I hazard to guess that 914 * it's far more likely to just catch folks that 915 * updated their kernel but not their userland. 916 */ 917 if ((cio->num_patterns * 918 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 919 /* The user made a mistake, return an error*/ 920 cio->status = PCI_GETCONF_ERROR; 921 printf("pci_ioctl: pat_buf_len %d != " 922 "num_patterns (%d) * sizeof(struct " 923 "pci_match_conf) (%d)\npci_ioctl: " 924 "pat_buf_len should be = %d\n", 925 cio->pat_buf_len, cio->num_patterns, 926 (int)sizeof(struct pci_match_conf), 927 (int)sizeof(struct pci_match_conf) * 928 cio->num_patterns); 929 printf("pci_ioctl: do your headers match your " 930 "kernel?\n"); 931 cio->num_matches = 0; 932 error = EINVAL; 933 break; 934 } 935 936 /* 937 * Check the user's buffer to make sure it's readable. 938 */ 939 if (!useracc((caddr_t)cio->patterns, 940 cio->pat_buf_len, VM_PROT_READ)) { 941 printf("pci_ioctl: pattern buffer %p, " 942 "length %u isn't user accessible for" 943 " READ\n", cio->patterns, 944 cio->pat_buf_len); 945 error = EACCES; 946 break; 947 } 948 /* 949 * Allocate a buffer to hold the patterns. 950 */ 951 pattern_buf = malloc(cio->pat_buf_len, M_TEMP, 952 M_WAITOK); 953 error = copyin(cio->patterns, pattern_buf, 954 cio->pat_buf_len); 955 if (error != 0) 956 break; 957 num_patterns = cio->num_patterns; 958 959 } else if ((cio->num_patterns > 0) 960 || (cio->pat_buf_len > 0)) { 961 /* 962 * The user made a mistake, spit out an error. 963 */ 964 cio->status = PCI_GETCONF_ERROR; 965 cio->num_matches = 0; 966 printf("pci_ioctl: invalid GETCONF arguments\n"); 967 error = EINVAL; 968 break; 969 } else 970 pattern_buf = NULL; 971 972 /* 973 * Make sure we can write to the match buffer. 974 */ 975 if (!useracc((caddr_t)cio->matches, 976 cio->match_buf_len, VM_PROT_WRITE)) { 977 printf("pci_ioctl: match buffer %p, length %u " 978 "isn't user accessible for WRITE\n", 979 cio->matches, cio->match_buf_len); 980 error = EACCES; 981 break; 982 } 983 984 /* 985 * Go through the list of devices and copy out the devices 986 * that match the user's criteria. 987 */ 988 for (cio->num_matches = 0, error = 0, i = 0, 989 dinfo = STAILQ_FIRST(devlist_head); 990 (dinfo != NULL) && (cio->num_matches < ionum) 991 && (error == 0) && (i < pci_numdevs); 992 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 993 994 if (i < cio->offset) 995 continue; 996 997 /* Populate pd_name and pd_unit */ 998 name = NULL; 999 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 1000 name = device_get_name(dinfo->cfg.dev); 1001 if (name) { 1002 strncpy(dinfo->conf.pd_name, name, 1003 sizeof(dinfo->conf.pd_name)); 1004 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 1005 dinfo->conf.pd_unit = 1006 device_get_unit(dinfo->cfg.dev); 1007 } 1008 1009 if ((pattern_buf == NULL) || 1010 (pci_conf_match(pattern_buf, num_patterns, 1011 &dinfo->conf) == 0)) { 1012 1013 /* 1014 * If we've filled up the user's buffer, 1015 * break out at this point. Since we've 1016 * got a match here, we'll pick right back 1017 * up at the matching entry. We can also 1018 * tell the user that there are more matches 1019 * left. 1020 */ 1021 if (cio->num_matches >= ionum) 1022 break; 1023 1024 error = copyout(&dinfo->conf, 1025 &cio->matches[cio->num_matches], 1026 sizeof(struct pci_conf)); 1027 cio->num_matches++; 1028 } 1029 } 1030 1031 /* 1032 * Set the pointer into the list, so if the user is getting 1033 * n records at a time, where n < pci_numdevs, 1034 */ 1035 cio->offset = i; 1036 1037 /* 1038 * Set the generation, the user will need this if they make 1039 * another ioctl call with offset != 0. 1040 */ 1041 cio->generation = pci_generation; 1042 1043 /* 1044 * If this is the last device, inform the user so he won't 1045 * bother asking for more devices. If dinfo isn't NULL, we 1046 * know that there are more matches in the list because of 1047 * the way the traversal is done. 1048 */ 1049 if (dinfo == NULL) 1050 cio->status = PCI_GETCONF_LAST_DEVICE; 1051 else 1052 cio->status = PCI_GETCONF_MORE_DEVS; 1053 1054 if (pattern_buf != NULL) 1055 free(pattern_buf, M_TEMP); 1056 1057 break; 1058 } 1059 case PCIOCREAD: 1060 io = (struct pci_io *)data; 1061 switch(io->pi_width) { 1062 case 4: 1063 case 2: 1064 case 1: 1065 /* 1066 * Assume that the user-level bus number is 1067 * actually the pciN instance number. We map 1068 * from that to the real pcib+bus combination. 1069 */ 1070 pci = devclass_get_device(pci_devclass, 1071 io->pi_sel.pc_bus); 1072 if (pci) { 1073 /* 1074 * pci is the pci device and may contain 1075 * several children (for each function code). 1076 * The governing pci bus is the parent to 1077 * the pci device. 1078 */ 1079 int b; 1080 1081 pcib = device_get_parent(pci); 1082 b = pcib_get_bus(pcib); 1083 io->pi_data = 1084 PCIB_READ_CONFIG(pcib, 1085 b, 1086 io->pi_sel.pc_dev, 1087 io->pi_sel.pc_func, 1088 io->pi_reg, 1089 io->pi_width); 1090 error = 0; 1091 } else { 1092 error = ENODEV; 1093 } 1094 break; 1095 default: 1096 error = ENODEV; 1097 break; 1098 } 1099 break; 1100 1101 case PCIOCWRITE: 1102 io = (struct pci_io *)data; 1103 switch(io->pi_width) { 1104 case 4: 1105 case 2: 1106 case 1: 1107 /* 1108 * Assume that the user-level bus number is 1109 * actually the pciN instance number. We map 1110 * from that to the real pcib+bus combination. 1111 */ 1112 pci = devclass_get_device(pci_devclass, 1113 io->pi_sel.pc_bus); 1114 if (pci) { 1115 /* 1116 * pci is the pci device and may contain 1117 * several children (for each function code). 1118 * The governing pci bus is the parent to 1119 * the pci device. 1120 */ 1121 int b; 1122 1123 pcib = device_get_parent(pci); 1124 b = pcib_get_bus(pcib); 1125 PCIB_WRITE_CONFIG(pcib, 1126 b, 1127 io->pi_sel.pc_dev, 1128 io->pi_sel.pc_func, 1129 io->pi_reg, 1130 io->pi_data, 1131 io->pi_width); 1132 error = 0; 1133 } else { 1134 error = ENODEV; 1135 } 1136 break; 1137 default: 1138 error = ENODEV; 1139 break; 1140 } 1141 break; 1142 1143 default: 1144 error = ENOTTY; 1145 break; 1146 } 1147 1148 return (error); 1149 } 1150 1151 #define PCI_CDEV 78 1152 1153 static struct cdevsw pcicdev = { 1154 /* name */ "pci", 1155 /* maj */ PCI_CDEV, 1156 /* flags */ 0, 1157 /* port */ NULL, 1158 /* clone */ NULL, 1159 1160 /* open */ pci_open, 1161 /* close */ pci_close, 1162 /* read */ noread, 1163 /* write */ nowrite, 1164 /* ioctl */ pci_ioctl, 1165 /* poll */ nopoll, 1166 /* mmap */ nommap, 1167 /* strategy */ nostrategy, 1168 /* dump */ nodump, 1169 /* psize */ nopsize 1170 }; 1171 1172 #include "pci_if.h" 1173 1174 /* 1175 * New style pci driver. Parent device is either a pci-host-bridge or a 1176 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1177 */ 1178 const char * 1179 pci_class_to_string(int baseclass) 1180 { 1181 const char *name; 1182 1183 switch(baseclass) { 1184 case PCIC_OLD: 1185 name = "OLD"; 1186 break; 1187 case PCIC_STORAGE: 1188 name = "STORAGE"; 1189 break; 1190 case PCIC_NETWORK: 1191 name = "NETWORK"; 1192 break; 1193 case PCIC_DISPLAY: 1194 name = "DISPLAY"; 1195 break; 1196 case PCIC_MULTIMEDIA: 1197 name = "MULTIMEDIA"; 1198 break; 1199 case PCIC_MEMORY: 1200 name = "MEMORY"; 1201 break; 1202 case PCIC_BRIDGE: 1203 name = "BRIDGE"; 1204 break; 1205 case PCIC_SIMPLECOMM: 1206 name = "SIMPLECOMM"; 1207 break; 1208 case PCIC_BASEPERIPH: 1209 name = "BASEPERIPH"; 1210 break; 1211 case PCIC_INPUTDEV: 1212 name = "INPUTDEV"; 1213 break; 1214 case PCIC_DOCKING: 1215 name = "DOCKING"; 1216 break; 1217 case PCIC_PROCESSOR: 1218 name = "PROCESSOR"; 1219 break; 1220 case PCIC_SERIALBUS: 1221 name = "SERIALBUS"; 1222 break; 1223 case PCIC_WIRELESS: 1224 name = "WIRELESS"; 1225 break; 1226 case PCIC_I2O: 1227 name = "I20"; 1228 break; 1229 case PCIC_SATELLITE: 1230 name = "SATELLITE"; 1231 break; 1232 case PCIC_CRYPTO: 1233 name = "CRYPTO"; 1234 break; 1235 case PCIC_SIGPROC: 1236 name = "SIGPROC"; 1237 break; 1238 case PCIC_OTHER: 1239 name = "OTHER"; 1240 break; 1241 default: 1242 name = "?"; 1243 break; 1244 } 1245 return(name); 1246 } 1247 1248 void 1249 pci_print_verbose(struct pci_devinfo *dinfo) 1250 { 1251 if (bootverbose) { 1252 pcicfgregs *cfg = &dinfo->cfg; 1253 1254 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1255 cfg->vendor, cfg->device, cfg->revid); 1256 printf("\tbus=%d, slot=%d, func=%d\n", 1257 cfg->bus, cfg->slot, cfg->func); 1258 printf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1259 pci_class_to_string(cfg->baseclass), 1260 cfg->baseclass, cfg->subclass, cfg->progif, 1261 cfg->hdrtype, cfg->mfdev); 1262 printf("\tsubordinatebus=%x \tsecondarybus=%x\n", 1263 cfg->subordinatebus, cfg->secondarybus); 1264 #ifdef PCI_DEBUG 1265 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1266 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1267 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1268 cfg->lattimer, cfg->lattimer * 30, 1269 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1270 #endif /* PCI_DEBUG */ 1271 if (cfg->intpin > 0) 1272 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 1273 } 1274 } 1275 1276 static int 1277 pci_porten(device_t pcib, int b, int s, int f) 1278 { 1279 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1280 & PCIM_CMD_PORTEN) != 0; 1281 } 1282 1283 static int 1284 pci_memen(device_t pcib, int b, int s, int f) 1285 { 1286 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1287 & PCIM_CMD_MEMEN) != 0; 1288 } 1289 1290 /* 1291 * Add a resource based on a pci map register. Return 1 if the map 1292 * register is a 32bit map register or 2 if it is a 64bit register. 1293 */ 1294 static int 1295 pci_add_map(device_t pcib, int b, int s, int f, int reg, 1296 struct resource_list *rl) 1297 { 1298 u_int32_t map; 1299 u_int64_t base; 1300 u_int8_t ln2size; 1301 u_int8_t ln2range; 1302 u_int32_t testval; 1303 1304 1305 #ifdef PCI_ENABLE_IO_MODES 1306 u_int16_t cmd; 1307 #endif 1308 int type; 1309 1310 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1311 1312 if (map == 0 || map == 0xffffffff) 1313 return 1; /* skip invalid entry */ 1314 1315 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1316 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1317 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1318 1319 base = pci_mapbase(map); 1320 if (pci_maptype(map) & PCI_MAPMEM) 1321 type = SYS_RES_MEMORY; 1322 else 1323 type = SYS_RES_IOPORT; 1324 ln2size = pci_mapsize(testval); 1325 ln2range = pci_maprange(testval); 1326 if (ln2range == 64) { 1327 /* Read the other half of a 64bit map register */ 1328 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4); 1329 } 1330 1331 /* 1332 * This code theoretically does the right thing, but has 1333 * undesirable side effects in some cases where 1334 * peripherals respond oddly to having these bits 1335 * enabled. Leave them alone by default. 1336 */ 1337 #ifdef PCI_ENABLE_IO_MODES 1338 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1339 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1340 cmd |= PCIM_CMD_PORTEN; 1341 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1342 } 1343 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1344 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1345 cmd |= PCIM_CMD_MEMEN; 1346 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1347 } 1348 #else 1349 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1350 return 1; 1351 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1352 return 1; 1353 #endif 1354 1355 resource_list_add(rl, type, reg, 1356 base, base + (1 << ln2size) - 1, 1357 (1 << ln2size)); 1358 1359 if (bootverbose) { 1360 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n", 1361 reg, pci_maptype(base), ln2range, 1362 (unsigned int) base, ln2size); 1363 } 1364 1365 return (ln2range == 64) ? 2 : 1; 1366 } 1367 1368 static void 1369 pci_add_resources(device_t pcib, device_t bus, device_t dev) 1370 { 1371 struct pci_devinfo *dinfo = device_get_ivars(dev); 1372 pcicfgregs *cfg = &dinfo->cfg; 1373 struct resource_list *rl = &dinfo->resources; 1374 struct pci_quirk *q; 1375 int b, i, f, s; 1376 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */ 1377 int irq; 1378 #endif 1379 1380 b = cfg->bus; 1381 s = cfg->slot; 1382 f = cfg->func; 1383 for (i = 0; i < cfg->nummaps;) { 1384 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl); 1385 } 1386 1387 for (q = &pci_quirks[0]; q->devid; q++) { 1388 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1389 && q->type == PCI_QUIRK_MAP_REG) 1390 pci_add_map(pcib, b, s, f, q->arg1, rl); 1391 } 1392 1393 if (cfg->intpin > 0 && cfg->intline != 255) 1394 resource_list_add(rl, SYS_RES_IRQ, 0, 1395 cfg->intline, cfg->intline, 1); 1396 } 1397 1398 void 1399 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1400 { 1401 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1402 device_t pcib = device_get_parent(dev); 1403 struct pci_devinfo *dinfo; 1404 int maxslots; 1405 int s, f, pcifunchigh; 1406 uint8_t hdrtype; 1407 1408 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo)); 1409 1410 maxslots = PCIB_MAXSLOTS(pcib); 1411 1412 for (s = 0; s <= maxslots; s++) { 1413 pcifunchigh = 0; 1414 f = 0; 1415 hdrtype = REG(PCIR_HDRTYPE, 1); 1416 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1417 continue; 1418 if (hdrtype & PCIM_MFDEV) 1419 pcifunchigh = PCI_FUNCMAX; 1420 for (f = 0; f <= pcifunchigh; f++) { 1421 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1422 if (dinfo != NULL) { 1423 pci_add_child(dev, dinfo); 1424 } 1425 } 1426 } 1427 #undef REG 1428 } 1429 1430 /* 1431 * The actual PCI child that we add has a NULL driver whos parent 1432 * device will be "pci". The child contains the ivars, not the parent. 1433 */ 1434 void 1435 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1436 { 1437 device_t pcib; 1438 1439 pcib = device_get_parent(bus); 1440 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1441 device_set_ivars(dinfo->cfg.dev, dinfo); 1442 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1443 pci_print_verbose(dinfo); 1444 } 1445 1446 /* 1447 * Probe the PCI bus. Note: probe code is not supposed to add children 1448 * or call attach. 1449 */ 1450 static int 1451 pci_probe(device_t dev) 1452 { 1453 device_set_desc(dev, "PCI bus"); 1454 1455 /* Allow other subclasses to override this driver */ 1456 return(-1000); 1457 } 1458 1459 static int 1460 pci_attach(device_t dev) 1461 { 1462 int busno; 1463 int lunit = device_get_unit(dev); 1464 1465 cdevsw_add(&pcicdev, -1, lunit); 1466 make_dev(&pcicdev, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit); 1467 1468 /* 1469 * Since there can be multiple independantly numbered PCI 1470 * busses on some large alpha systems, we can't use the unit 1471 * number to decide what bus we are probing. We ask the parent 1472 * pcib what our bus number is. 1473 * 1474 * pcib_get_bus() must act on the pci bus device, not on the pci 1475 * device, because it uses badly hacked nexus-based ivars to 1476 * store and retrieve the physical bus number. XXX 1477 */ 1478 busno = pcib_get_bus(device_get_parent(dev)); 1479 if (bootverbose) 1480 device_printf(dev, "pci_attach() physical bus=%d\n", busno); 1481 1482 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1483 1484 return (bus_generic_attach(dev)); 1485 } 1486 1487 static int 1488 pci_print_resources(struct resource_list *rl, const char *name, int type, 1489 const char *format) 1490 { 1491 struct resource_list_entry *rle; 1492 int printed, retval; 1493 1494 printed = 0; 1495 retval = 0; 1496 /* Yes, this is kinda cheating */ 1497 SLIST_FOREACH(rle, rl, link) { 1498 if (rle->type == type) { 1499 if (printed == 0) 1500 retval += printf(" %s ", name); 1501 else if (printed > 0) 1502 retval += printf(","); 1503 printed++; 1504 retval += printf(format, rle->start); 1505 if (rle->count > 1) { 1506 retval += printf("-"); 1507 retval += printf(format, rle->start + 1508 rle->count - 1); 1509 } 1510 } 1511 } 1512 return retval; 1513 } 1514 1515 int 1516 pci_print_child(device_t dev, device_t child) 1517 { 1518 struct pci_devinfo *dinfo; 1519 struct resource_list *rl; 1520 pcicfgregs *cfg; 1521 int retval = 0; 1522 1523 dinfo = device_get_ivars(child); 1524 cfg = &dinfo->cfg; 1525 rl = &dinfo->resources; 1526 1527 retval += bus_print_child_header(dev, child); 1528 1529 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 1530 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1531 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 1532 if (device_get_flags(dev)) 1533 retval += printf(" flags %#x", device_get_flags(dev)); 1534 1535 retval += printf(" at device %d.%d", pci_get_slot(child), 1536 pci_get_function(child)); 1537 1538 retval += bus_print_child_footer(dev, child); 1539 1540 return (retval); 1541 } 1542 1543 void 1544 pci_probe_nomatch(device_t dev, device_t child) 1545 { 1546 struct pci_devinfo *dinfo; 1547 pcicfgregs *cfg; 1548 const char *desc; 1549 int unknown; 1550 1551 unknown = 0; 1552 dinfo = device_get_ivars(child); 1553 cfg = &dinfo->cfg; 1554 desc = pci_ata_match(child); 1555 if (!desc) desc = pci_usb_match(child); 1556 if (!desc) desc = pci_vga_match(child); 1557 if (!desc) desc = pci_chip_match(child); 1558 if (!desc) { 1559 desc = "unknown card"; 1560 unknown++; 1561 } 1562 device_printf(dev, "<%s>", desc); 1563 if (bootverbose || unknown) { 1564 printf(" (vendor=0x%04x, dev=0x%04x)", 1565 cfg->vendor, 1566 cfg->device); 1567 } 1568 printf(" at %d.%d", 1569 pci_get_slot(child), 1570 pci_get_function(child)); 1571 if (cfg->intpin > 0 && cfg->intline != 255) { 1572 printf(" irq %d", cfg->intline); 1573 } 1574 printf("\n"); 1575 1576 return; 1577 } 1578 1579 int 1580 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1581 { 1582 struct pci_devinfo *dinfo; 1583 pcicfgregs *cfg; 1584 1585 dinfo = device_get_ivars(child); 1586 cfg = &dinfo->cfg; 1587 1588 switch (which) { 1589 case PCI_IVAR_SUBVENDOR: 1590 *result = cfg->subvendor; 1591 break; 1592 case PCI_IVAR_SUBDEVICE: 1593 *result = cfg->subdevice; 1594 break; 1595 case PCI_IVAR_VENDOR: 1596 *result = cfg->vendor; 1597 break; 1598 case PCI_IVAR_DEVICE: 1599 *result = cfg->device; 1600 break; 1601 case PCI_IVAR_DEVID: 1602 *result = (cfg->device << 16) | cfg->vendor; 1603 break; 1604 case PCI_IVAR_CLASS: 1605 *result = cfg->baseclass; 1606 break; 1607 case PCI_IVAR_SUBCLASS: 1608 *result = cfg->subclass; 1609 break; 1610 case PCI_IVAR_PROGIF: 1611 *result = cfg->progif; 1612 break; 1613 case PCI_IVAR_REVID: 1614 *result = cfg->revid; 1615 break; 1616 case PCI_IVAR_INTPIN: 1617 *result = cfg->intpin; 1618 break; 1619 case PCI_IVAR_IRQ: 1620 *result = cfg->intline; 1621 break; 1622 case PCI_IVAR_BUS: 1623 *result = cfg->bus; 1624 break; 1625 case PCI_IVAR_SLOT: 1626 *result = cfg->slot; 1627 break; 1628 case PCI_IVAR_FUNCTION: 1629 *result = cfg->func; 1630 break; 1631 case PCI_IVAR_SECONDARYBUS: 1632 *result = cfg->secondarybus; 1633 break; 1634 case PCI_IVAR_SUBORDINATEBUS: 1635 *result = cfg->subordinatebus; 1636 break; 1637 case PCI_IVAR_ETHADDR: 1638 /* 1639 * The generic accessor doesn't deal with failure, so 1640 * we set the return value, then return an error. 1641 */ 1642 *result = NULL; 1643 return (EINVAL); 1644 default: 1645 return ENOENT; 1646 } 1647 return 0; 1648 } 1649 1650 int 1651 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1652 { 1653 struct pci_devinfo *dinfo; 1654 pcicfgregs *cfg; 1655 1656 dinfo = device_get_ivars(child); 1657 cfg = &dinfo->cfg; 1658 1659 switch (which) { 1660 case PCI_IVAR_SUBVENDOR: 1661 case PCI_IVAR_SUBDEVICE: 1662 case PCI_IVAR_VENDOR: 1663 case PCI_IVAR_DEVICE: 1664 case PCI_IVAR_DEVID: 1665 case PCI_IVAR_CLASS: 1666 case PCI_IVAR_SUBCLASS: 1667 case PCI_IVAR_PROGIF: 1668 case PCI_IVAR_REVID: 1669 case PCI_IVAR_INTPIN: 1670 case PCI_IVAR_IRQ: 1671 case PCI_IVAR_BUS: 1672 case PCI_IVAR_SLOT: 1673 case PCI_IVAR_FUNCTION: 1674 case PCI_IVAR_ETHADDR: 1675 return EINVAL; /* disallow for now */ 1676 1677 case PCI_IVAR_SECONDARYBUS: 1678 cfg->secondarybus = value; 1679 break; 1680 case PCI_IVAR_SUBORDINATEBUS: 1681 cfg->subordinatebus = value; 1682 break; 1683 default: 1684 return ENOENT; 1685 } 1686 return 0; 1687 } 1688 1689 struct resource * 1690 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1691 u_long start, u_long end, u_long count, u_int flags) 1692 { 1693 struct pci_devinfo *dinfo = device_get_ivars(child); 1694 struct resource_list *rl = &dinfo->resources; 1695 pcicfgregs *cfg = &dinfo->cfg; 1696 1697 /* 1698 * Perform lazy resource allocation 1699 * 1700 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1701 */ 1702 if (device_get_parent(child) == dev) { 1703 switch (type) { 1704 case SYS_RES_IRQ: 1705 #ifdef __i386__ 1706 /* 1707 * If device doesn't have an interrupt routed, and is 1708 * deserving of an interrupt, try to assign it one. 1709 */ 1710 if ((cfg->intline == 255 || cfg->intline == 0) && 1711 (cfg->intpin != 0) && 1712 (start == 0) && (end == ~0UL)) { 1713 cfg->intline = PCIB_ROUTE_INTERRUPT( 1714 device_get_parent(dev), child, 1715 cfg->intpin); 1716 if (cfg->intline != 255) { 1717 pci_write_config(child, PCIR_INTLINE, 1718 cfg->intline, 1); 1719 resource_list_add(rl, SYS_RES_IRQ, 0, 1720 cfg->intline, cfg->intline, 1); 1721 } 1722 } 1723 break; 1724 #endif 1725 case SYS_RES_IOPORT: 1726 case SYS_RES_MEMORY: 1727 if (*rid < PCIR_BAR(cfg->nummaps)) { 1728 /* 1729 * Enable the I/O mode. We should 1730 * also be assigning resources too 1731 * when none are present. The 1732 * resource_list_alloc kind of sorta does 1733 * this... 1734 */ 1735 if (PCI_ENABLE_IO(dev, child, type)) 1736 return (NULL); 1737 } 1738 break; 1739 } 1740 } 1741 return resource_list_alloc(rl, dev, child, type, rid, 1742 start, end, count, flags); 1743 } 1744 1745 static int 1746 pci_release_resource(device_t dev, device_t child, int type, int rid, 1747 struct resource *r) 1748 { 1749 struct pci_devinfo *dinfo = device_get_ivars(child); 1750 struct resource_list *rl = &dinfo->resources; 1751 1752 return resource_list_release(rl, dev, child, type, rid, r); 1753 } 1754 1755 static int 1756 pci_set_resource(device_t dev, device_t child, int type, int rid, 1757 u_long start, u_long count) 1758 { 1759 struct pci_devinfo *dinfo = device_get_ivars(child); 1760 struct resource_list *rl = &dinfo->resources; 1761 1762 resource_list_add(rl, type, rid, start, start + count - 1, count); 1763 return 0; 1764 } 1765 1766 static int 1767 pci_get_resource(device_t dev, device_t child, int type, int rid, 1768 u_long *startp, u_long *countp) 1769 { 1770 struct pci_devinfo *dinfo = device_get_ivars(child); 1771 struct resource_list *rl = &dinfo->resources; 1772 struct resource_list_entry *rle; 1773 1774 rle = resource_list_find(rl, type, rid); 1775 if (!rle) 1776 return ENOENT; 1777 1778 if (startp) 1779 *startp = rle->start; 1780 if (countp) 1781 *countp = rle->count; 1782 1783 return 0; 1784 } 1785 1786 void 1787 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1788 { 1789 printf("pci_delete_resource: PCI resources can not be deleted\n"); 1790 } 1791 1792 struct resource_list * 1793 pci_get_resource_list (device_t dev, device_t child) 1794 { 1795 struct pci_devinfo * dinfo = device_get_ivars(child); 1796 struct resource_list * rl = &dinfo->resources; 1797 1798 if (!rl) 1799 return (NULL); 1800 1801 return (rl); 1802 } 1803 1804 u_int32_t 1805 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1806 { 1807 struct pci_devinfo *dinfo = device_get_ivars(child); 1808 pcicfgregs *cfg = &dinfo->cfg; 1809 1810 return PCIB_READ_CONFIG(device_get_parent(dev), 1811 cfg->bus, cfg->slot, cfg->func, 1812 reg, width); 1813 } 1814 1815 void 1816 pci_write_config_method(device_t dev, device_t child, int reg, 1817 u_int32_t val, int width) 1818 { 1819 struct pci_devinfo *dinfo = device_get_ivars(child); 1820 pcicfgregs *cfg = &dinfo->cfg; 1821 1822 PCIB_WRITE_CONFIG(device_get_parent(dev), 1823 cfg->bus, cfg->slot, cfg->func, 1824 reg, val, width); 1825 } 1826 1827 int 1828 pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 1829 size_t buflen) 1830 { 1831 struct pci_devinfo *dinfo; 1832 1833 dinfo = device_get_ivars(child); 1834 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1835 pci_get_function(child)); 1836 return (0); 1837 } 1838 1839 int 1840 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 1841 size_t buflen) 1842 { 1843 struct pci_devinfo *dinfo; 1844 pcicfgregs *cfg; 1845 1846 dinfo = device_get_ivars(child); 1847 cfg = &dinfo->cfg; 1848 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1849 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1850 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1851 cfg->progif); 1852 return (0); 1853 } 1854 1855 int 1856 pci_assign_interrupt_method(device_t dev, device_t child) 1857 { 1858 struct pci_devinfo *dinfo = device_get_ivars(child); 1859 pcicfgregs *cfg = &dinfo->cfg; 1860 1861 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1862 cfg->intpin)); 1863 } 1864 1865 static int 1866 pci_modevent(module_t mod, int what, void *arg) 1867 { 1868 switch (what) { 1869 case MOD_LOAD: 1870 STAILQ_INIT(&pci_devq); 1871 break; 1872 case MOD_UNLOAD: 1873 break; 1874 } 1875 1876 return 0; 1877 } 1878 1879 int 1880 pci_resume(device_t dev) 1881 { 1882 int numdevs; 1883 int i; 1884 device_t *children; 1885 device_t child; 1886 struct pci_devinfo *dinfo; 1887 pcicfgregs *cfg; 1888 1889 device_get_children(dev, &children, &numdevs); 1890 1891 for (i = 0; i < numdevs; i++) { 1892 child = children[i]; 1893 1894 dinfo = device_get_ivars(child); 1895 cfg = &dinfo->cfg; 1896 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1897 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1898 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1899 pci_write_config(child, PCIR_INTLINE, 1900 cfg->intline, 1); 1901 } 1902 } 1903 } 1904 1905 free(children, M_TEMP); 1906 1907 return (bus_generic_resume(dev)); 1908 } 1909 1910 static device_method_t pci_methods[] = { 1911 /* Device interface */ 1912 DEVMETHOD(device_probe, pci_probe), 1913 DEVMETHOD(device_attach, pci_attach), 1914 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1915 DEVMETHOD(device_suspend, bus_generic_suspend), 1916 DEVMETHOD(device_resume, pci_resume), 1917 1918 /* Bus interface */ 1919 DEVMETHOD(bus_print_child, pci_print_child), 1920 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 1921 DEVMETHOD(bus_read_ivar, pci_read_ivar), 1922 DEVMETHOD(bus_write_ivar, pci_write_ivar), 1923 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1924 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1925 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1926 1927 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 1928 DEVMETHOD(bus_set_resource, pci_set_resource), 1929 DEVMETHOD(bus_get_resource, pci_get_resource), 1930 DEVMETHOD(bus_delete_resource, pci_delete_resource), 1931 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 1932 DEVMETHOD(bus_release_resource, pci_release_resource), 1933 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1934 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1935 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 1936 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 1937 1938 /* PCI interface */ 1939 DEVMETHOD(pci_read_config, pci_read_config_method), 1940 DEVMETHOD(pci_write_config, pci_write_config_method), 1941 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 1942 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 1943 DEVMETHOD(pci_enable_io, pci_enable_io_method), 1944 DEVMETHOD(pci_disable_io, pci_disable_io_method), 1945 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 1946 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 1947 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 1948 1949 { 0, 0 } 1950 }; 1951 1952 static driver_t pci_driver = { 1953 "pci", 1954 pci_methods, 1955 1, /* no softc */ 1956 }; 1957 1958 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 1959 MODULE_VERSION(pci, 1); 1960