1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $ 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.19 2004/02/24 11:52:31 joerg Exp $ 28 * 29 */ 30 31 #include "opt_bus.h" 32 #include "opt_pci.h" 33 34 #include "opt_simos.h" 35 #include "opt_compat_oldpci.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/fcntl.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/buf.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 #include <vm/vm_extern.h> 51 52 #include <sys/bus.h> 53 #include <machine/bus.h> 54 #include <sys/rman.h> 55 #include <machine/resource.h> 56 #include <machine/md_var.h> /* For the Alpha */ 57 #ifdef __i386__ 58 #include <bus/pci/i386/pci_cfgreg.h> 59 #endif 60 61 #include <sys/pciio.h> 62 #include "pcireg.h" 63 #include "pcivar.h" 64 #include "pci_private.h" 65 66 #include "pcib_if.h" 67 68 #ifdef __alpha__ 69 #include <machine/rpb.h> 70 #endif 71 72 #ifdef APIC_IO 73 #include <machine/smp.h> 74 #endif /* APIC_IO */ 75 76 devclass_t pci_devclass; 77 78 static void pci_read_extcap(device_t dev, pcicfgregs *cfg); 79 80 struct pci_quirk { 81 u_int32_t devid; /* Vendor/device of the card */ 82 int type; 83 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 84 int arg1; 85 int arg2; 86 }; 87 88 struct pci_quirk pci_quirks[] = { 89 /* 90 * The Intel 82371AB and 82443MX has a map register at offset 0x90. 91 */ 92 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 93 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 94 95 { 0 } 96 }; 97 98 /* map register information */ 99 #define PCI_MAPMEM 0x01 /* memory map */ 100 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 101 #define PCI_MAPPORT 0x04 /* port map */ 102 103 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 104 u_int32_t pci_numdevs = 0; 105 static u_int32_t pci_generation = 0; 106 107 device_t 108 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func) 109 { 110 struct pci_devinfo *dinfo; 111 112 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 113 if ((dinfo->cfg.bus == bus) && 114 (dinfo->cfg.slot == slot) && 115 (dinfo->cfg.func == func)) { 116 return (dinfo->cfg.dev); 117 } 118 } 119 120 return (NULL); 121 } 122 123 device_t 124 pci_find_device (u_int16_t vendor, u_int16_t device) 125 { 126 struct pci_devinfo *dinfo; 127 128 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 129 if ((dinfo->cfg.vendor == vendor) && 130 (dinfo->cfg.device == device)) { 131 return (dinfo->cfg.dev); 132 } 133 } 134 135 return (NULL); 136 } 137 138 /* return base address of memory or port map */ 139 140 static u_int32_t 141 pci_mapbase(unsigned mapreg) 142 { 143 int mask = 0x03; 144 if ((mapreg & 0x01) == 0) 145 mask = 0x0f; 146 return (mapreg & ~mask); 147 } 148 149 /* return map type of memory or port map */ 150 151 static int 152 pci_maptype(unsigned mapreg) 153 { 154 static u_int8_t maptype[0x10] = { 155 PCI_MAPMEM, PCI_MAPPORT, 156 PCI_MAPMEM, 0, 157 PCI_MAPMEM, PCI_MAPPORT, 158 0, 0, 159 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 160 PCI_MAPMEM|PCI_MAPMEMP, 0, 161 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 162 0, 0, 163 }; 164 165 return maptype[mapreg & 0x0f]; 166 } 167 168 /* return log2 of map size decoded for memory or port map */ 169 170 static int 171 pci_mapsize(unsigned testval) 172 { 173 int ln2size; 174 175 testval = pci_mapbase(testval); 176 ln2size = 0; 177 if (testval != 0) { 178 while ((testval & 1) == 0) 179 { 180 ln2size++; 181 testval >>= 1; 182 } 183 } 184 return (ln2size); 185 } 186 187 /* return log2 of address range supported by map register */ 188 189 static int 190 pci_maprange(unsigned mapreg) 191 { 192 int ln2range = 0; 193 switch (mapreg & 0x07) { 194 case 0x00: 195 case 0x01: 196 case 0x05: 197 ln2range = 32; 198 break; 199 case 0x02: 200 ln2range = 20; 201 break; 202 case 0x04: 203 ln2range = 64; 204 break; 205 } 206 return (ln2range); 207 } 208 209 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 210 211 static void 212 pci_fixancient(pcicfgregs *cfg) 213 { 214 if (cfg->hdrtype != 0) 215 return; 216 217 /* PCI to PCI bridges use header type 1 */ 218 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 219 cfg->hdrtype = 1; 220 } 221 222 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 223 224 static void * 225 pci_readppb(device_t pcib, int b, int s, int f) 226 { 227 pcih1cfgregs *p; 228 229 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 230 if (p == NULL) 231 return (NULL); 232 233 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2); 234 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2); 235 236 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1); 237 238 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f, 239 PCIR_IOBASEH_1, 2), 240 PCIB_READ_CONFIG(pcib, b, s, f, 241 PCIR_IOBASEL_1, 1)); 242 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f, 243 PCIR_IOLIMITH_1, 2), 244 PCIB_READ_CONFIG(pcib, b, s, f, 245 PCIR_IOLIMITL_1, 1)); 246 247 p->membase = PCI_PPBMEMBASE (0, 248 PCIB_READ_CONFIG(pcib, b, s, f, 249 PCIR_MEMBASE_1, 2)); 250 p->memlimit = PCI_PPBMEMLIMIT (0, 251 PCIB_READ_CONFIG(pcib, b, s, f, 252 PCIR_MEMLIMIT_1, 2)); 253 254 p->pmembase = PCI_PPBMEMBASE ( 255 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4), 256 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2)); 257 258 p->pmemlimit = PCI_PPBMEMLIMIT ( 259 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, 260 PCIR_PMLIMITH_1, 4), 261 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2)); 262 263 return (p); 264 } 265 266 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 267 268 static void * 269 pci_readpcb(device_t pcib, int b, int s, int f) 270 { 271 pcih2cfgregs *p; 272 273 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 274 if (p == NULL) 275 return (NULL); 276 277 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2); 278 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2); 279 280 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1); 281 282 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4); 283 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4); 284 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4); 285 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4); 286 287 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4); 288 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4); 289 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4); 290 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4); 291 292 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4); 293 return p; 294 } 295 296 /* extract header type specific config data */ 297 298 static void 299 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 300 { 301 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 302 switch (cfg->hdrtype) { 303 case 0: 304 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 305 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 306 cfg->nummaps = PCI_MAXMAPS_0; 307 break; 308 case 1: 309 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 310 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 311 cfg->secondarybus = REG(PCIR_SECBUS_1, 1); 312 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1); 313 cfg->nummaps = PCI_MAXMAPS_1; 314 cfg->hdrspec = pci_readppb(pcib, b, s, f); 315 break; 316 case 2: 317 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 318 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 319 cfg->secondarybus = REG(PCIR_SECBUS_2, 1); 320 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1); 321 cfg->nummaps = PCI_MAXMAPS_2; 322 cfg->hdrspec = pci_readpcb(pcib, b, s, f); 323 break; 324 } 325 #undef REG 326 } 327 328 /* read configuration header into pcicfgrect structure */ 329 330 struct pci_devinfo * 331 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 332 { 333 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 334 335 pcicfgregs *cfg = NULL; 336 struct pci_devinfo *devlist_entry; 337 struct devlist *devlist_head; 338 339 devlist_head = &pci_devq; 340 341 devlist_entry = NULL; 342 343 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 344 345 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 346 if (devlist_entry == NULL) 347 return (NULL); 348 349 cfg = &devlist_entry->cfg; 350 351 cfg->bus = b; 352 cfg->slot = s; 353 cfg->func = f; 354 cfg->vendor = REG(PCIR_VENDOR, 2); 355 cfg->device = REG(PCIR_DEVICE, 2); 356 cfg->cmdreg = REG(PCIR_COMMAND, 2); 357 cfg->statreg = REG(PCIR_STATUS, 2); 358 cfg->baseclass = REG(PCIR_CLASS, 1); 359 cfg->subclass = REG(PCIR_SUBCLASS, 1); 360 cfg->progif = REG(PCIR_PROGIF, 1); 361 cfg->revid = REG(PCIR_REVID, 1); 362 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 363 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 364 cfg->lattimer = REG(PCIR_LATTIMER, 1); 365 cfg->intpin = REG(PCIR_INTPIN, 1); 366 cfg->intline = REG(PCIR_INTLINE, 1); 367 #ifdef __alpha__ 368 alpha_platform_assign_pciintr(cfg); 369 #endif 370 371 #ifdef APIC_IO 372 if (cfg->intpin != 0) { 373 int airq; 374 375 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 376 if (airq >= 0) { 377 /* PCI specific entry found in MP table */ 378 if (airq != cfg->intline) { 379 undirect_pci_irq(cfg->intline); 380 cfg->intline = airq; 381 } 382 } else { 383 /* 384 * PCI interrupts might be redirected to the 385 * ISA bus according to some MP tables. Use the 386 * same methods as used by the ISA devices 387 * devices to find the proper IOAPIC int pin. 388 */ 389 airq = isa_apic_irq(cfg->intline); 390 if ((airq >= 0) && (airq != cfg->intline)) { 391 /* XXX: undirect_pci_irq() ? */ 392 undirect_isa_irq(cfg->intline); 393 cfg->intline = airq; 394 } 395 } 396 } 397 #endif /* APIC_IO */ 398 399 cfg->mingnt = REG(PCIR_MINGNT, 1); 400 cfg->maxlat = REG(PCIR_MAXLAT, 1); 401 402 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 403 cfg->hdrtype &= ~PCIM_MFDEV; 404 405 pci_fixancient(cfg); 406 pci_hdrtypedata(pcib, b, s, f, cfg); 407 408 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 409 pci_read_extcap(pcib, cfg); 410 411 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 412 413 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 414 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 415 devlist_entry->conf.pc_sel.pc_func = cfg->func; 416 devlist_entry->conf.pc_hdr = cfg->hdrtype; 417 418 devlist_entry->conf.pc_subvendor = cfg->subvendor; 419 devlist_entry->conf.pc_subdevice = cfg->subdevice; 420 devlist_entry->conf.pc_vendor = cfg->vendor; 421 devlist_entry->conf.pc_device = cfg->device; 422 423 devlist_entry->conf.pc_class = cfg->baseclass; 424 devlist_entry->conf.pc_subclass = cfg->subclass; 425 devlist_entry->conf.pc_progif = cfg->progif; 426 devlist_entry->conf.pc_revid = cfg->revid; 427 428 pci_numdevs++; 429 pci_generation++; 430 } 431 return (devlist_entry); 432 #undef REG 433 } 434 435 static void 436 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 437 { 438 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 439 int ptr, nextptr, ptrptr; 440 441 switch (cfg->hdrtype) { 442 case 0: 443 ptrptr = 0x34; 444 break; 445 case 2: 446 ptrptr = 0x14; 447 break; 448 default: 449 return; /* no extended capabilities support */ 450 } 451 nextptr = REG(ptrptr, 1); /* sanity check? */ 452 453 /* 454 * Read capability entries. 455 */ 456 while (nextptr != 0) { 457 /* Sanity check */ 458 if (nextptr > 255) { 459 printf("illegal PCI extended capability offset %d\n", 460 nextptr); 461 return; 462 } 463 /* Find the next entry */ 464 ptr = nextptr; 465 nextptr = REG(ptr + 1, 1); 466 467 /* Process this entry */ 468 switch (REG(ptr, 1)) { 469 case 0x01: /* PCI power management */ 470 if (cfg->pp_cap == 0) { 471 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 472 cfg->pp_status = ptr + PCIR_POWER_STATUS; 473 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 474 if ((nextptr - ptr) > PCIR_POWER_DATA) 475 cfg->pp_data = ptr + PCIR_POWER_DATA; 476 } 477 break; 478 default: 479 break; 480 } 481 } 482 #undef REG 483 } 484 485 /* free pcicfgregs structure and all depending data structures */ 486 487 int 488 pci_freecfg(struct pci_devinfo *dinfo) 489 { 490 struct devlist *devlist_head; 491 492 devlist_head = &pci_devq; 493 494 if (dinfo->cfg.hdrspec != NULL) 495 free(dinfo->cfg.hdrspec, M_DEVBUF); 496 /* XXX this hasn't been tested */ 497 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 498 free(dinfo, M_DEVBUF); 499 500 /* increment the generation count */ 501 pci_generation++; 502 503 /* we're losing one device */ 504 pci_numdevs--; 505 return (0); 506 } 507 508 509 /* 510 * PCI power manangement 511 */ 512 int 513 pci_set_powerstate_method(device_t dev, device_t child, int state) 514 { 515 struct pci_devinfo *dinfo = device_get_ivars(child); 516 pcicfgregs *cfg = &dinfo->cfg; 517 u_int16_t status; 518 int result; 519 520 if (cfg->pp_cap != 0) { 521 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 522 result = 0; 523 switch (state) { 524 case PCI_POWERSTATE_D0: 525 status |= PCIM_PSTAT_D0; 526 break; 527 case PCI_POWERSTATE_D1: 528 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 529 status |= PCIM_PSTAT_D1; 530 } else { 531 result = EOPNOTSUPP; 532 } 533 break; 534 case PCI_POWERSTATE_D2: 535 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 536 status |= PCIM_PSTAT_D2; 537 } else { 538 result = EOPNOTSUPP; 539 } 540 break; 541 case PCI_POWERSTATE_D3: 542 status |= PCIM_PSTAT_D3; 543 break; 544 default: 545 result = EINVAL; 546 } 547 if (result == 0) 548 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 549 } else { 550 result = ENXIO; 551 } 552 return(result); 553 } 554 555 int 556 pci_get_powerstate_method(device_t dev, device_t child) 557 { 558 struct pci_devinfo *dinfo = device_get_ivars(child); 559 pcicfgregs *cfg = &dinfo->cfg; 560 u_int16_t status; 561 int result; 562 563 if (cfg->pp_cap != 0) { 564 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 565 switch (status & PCIM_PSTAT_DMASK) { 566 case PCIM_PSTAT_D0: 567 result = PCI_POWERSTATE_D0; 568 break; 569 case PCIM_PSTAT_D1: 570 result = PCI_POWERSTATE_D1; 571 break; 572 case PCIM_PSTAT_D2: 573 result = PCI_POWERSTATE_D2; 574 break; 575 case PCIM_PSTAT_D3: 576 result = PCI_POWERSTATE_D3; 577 break; 578 default: 579 result = PCI_POWERSTATE_UNKNOWN; 580 break; 581 } 582 } else { 583 /* No support, device is always at D0 */ 584 result = PCI_POWERSTATE_D0; 585 } 586 return(result); 587 } 588 589 /* 590 * Some convenience functions for PCI device drivers. 591 */ 592 593 static __inline void 594 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 595 { 596 u_int16_t command; 597 598 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 599 command |= bit; 600 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 601 } 602 603 static __inline void 604 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 605 { 606 u_int16_t command; 607 608 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 609 command &= ~bit; 610 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 611 } 612 613 int 614 pci_enable_busmaster_method(device_t dev, device_t child) 615 { 616 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 617 return(0); 618 } 619 620 int 621 pci_disable_busmaster_method(device_t dev, device_t child) 622 { 623 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 624 return(0); 625 } 626 627 int 628 pci_enable_io_method(device_t dev, device_t child, int space) 629 { 630 uint16_t command; 631 uint16_t bit; 632 char *error; 633 634 bit = 0; 635 error = NULL; 636 637 switch(space) { 638 case SYS_RES_IOPORT: 639 bit = PCIM_CMD_PORTEN; 640 error = "port"; 641 break; 642 case SYS_RES_MEMORY: 643 bit = PCIM_CMD_MEMEN; 644 error = "memory"; 645 break; 646 default: 647 return(EINVAL); 648 } 649 pci_set_command_bit(dev, child, bit); 650 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 651 if (command & bit) 652 return(0); 653 device_printf(child, "failed to enable %s mapping!\n", error); 654 return(ENXIO); 655 } 656 657 int 658 pci_disable_io_method(device_t dev, device_t child, int space) 659 { 660 uint16_t command; 661 uint16_t bit; 662 char *error; 663 664 bit = 0; 665 error = NULL; 666 667 switch(space) { 668 case SYS_RES_IOPORT: 669 bit = PCIM_CMD_PORTEN; 670 error = "port"; 671 break; 672 case SYS_RES_MEMORY: 673 bit = PCIM_CMD_MEMEN; 674 error = "memory"; 675 break; 676 default: 677 return (EINVAL); 678 } 679 pci_clear_command_bit(dev, child, bit); 680 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 681 if (command & bit) { 682 device_printf(child, "failed to disable %s mapping!\n", error); 683 return (ENXIO); 684 } 685 return (0); 686 } 687 688 /* 689 * This is the user interface to PCI configuration space. 690 */ 691 692 static int 693 pci_open(dev_t dev, int oflags, int devtype, struct thread *td) 694 { 695 if ((oflags & FWRITE) && securelevel > 0) { 696 return EPERM; 697 } 698 return 0; 699 } 700 701 static int 702 pci_close(dev_t dev, int flag, int devtype, struct thread *td) 703 { 704 return 0; 705 } 706 707 /* 708 * Match a single pci_conf structure against an array of pci_match_conf 709 * structures. The first argument, 'matches', is an array of num_matches 710 * pci_match_conf structures. match_buf is a pointer to the pci_conf 711 * structure that will be compared to every entry in the matches array. 712 * This function returns 1 on failure, 0 on success. 713 */ 714 static int 715 pci_conf_match(struct pci_match_conf *matches, int num_matches, 716 struct pci_conf *match_buf) 717 { 718 int i; 719 720 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 721 return(1); 722 723 for (i = 0; i < num_matches; i++) { 724 /* 725 * I'm not sure why someone would do this...but... 726 */ 727 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 728 continue; 729 730 /* 731 * Look at each of the match flags. If it's set, do the 732 * comparison. If the comparison fails, we don't have a 733 * match, go on to the next item if there is one. 734 */ 735 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 736 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 737 continue; 738 739 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 740 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 741 continue; 742 743 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 744 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 745 continue; 746 747 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 748 && (match_buf->pc_vendor != matches[i].pc_vendor)) 749 continue; 750 751 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 752 && (match_buf->pc_device != matches[i].pc_device)) 753 continue; 754 755 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 756 && (match_buf->pc_class != matches[i].pc_class)) 757 continue; 758 759 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 760 && (match_buf->pd_unit != matches[i].pd_unit)) 761 continue; 762 763 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 764 && (strncmp(matches[i].pd_name, match_buf->pd_name, 765 sizeof(match_buf->pd_name)) != 0)) 766 continue; 767 768 return(0); 769 } 770 771 return(1); 772 } 773 774 /* 775 * Locate the parent of a PCI device by scanning the PCI devlist 776 * and return the entry for the parent. 777 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 778 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 779 */ 780 781 pcicfgregs * 782 pci_devlist_get_parent(pcicfgregs *cfg) 783 { 784 struct devlist *devlist_head; 785 struct pci_devinfo *dinfo; 786 pcicfgregs *bridge_cfg; 787 int i; 788 789 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 790 791 /* If the device is on PCI bus 0, look for the host */ 792 if (cfg->bus == 0) { 793 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 794 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 795 bridge_cfg = &dinfo->cfg; 796 if (bridge_cfg->baseclass == PCIC_BRIDGE 797 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 798 && bridge_cfg->bus == cfg->bus) { 799 return bridge_cfg; 800 } 801 } 802 } 803 804 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 805 if (cfg->bus > 0) { 806 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 807 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 808 bridge_cfg = &dinfo->cfg; 809 if (bridge_cfg->baseclass == PCIC_BRIDGE 810 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 811 && bridge_cfg->secondarybus == cfg->bus) { 812 return bridge_cfg; 813 } 814 } 815 } 816 817 return NULL; 818 } 819 820 static int 821 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td) 822 { 823 device_t pci, pcib; 824 struct pci_io *io; 825 const char *name; 826 int error; 827 828 if (!(flag & FWRITE)) 829 return EPERM; 830 831 832 switch(cmd) { 833 case PCIOCGETCONF: 834 { 835 struct pci_devinfo *dinfo; 836 struct pci_conf_io *cio; 837 struct devlist *devlist_head; 838 struct pci_match_conf *pattern_buf; 839 int num_patterns; 840 size_t iolen; 841 int ionum, i; 842 843 cio = (struct pci_conf_io *)data; 844 845 num_patterns = 0; 846 dinfo = NULL; 847 848 /* 849 * Hopefully the user won't pass in a null pointer, but it 850 * can't hurt to check. 851 */ 852 if (cio == NULL) { 853 error = EINVAL; 854 break; 855 } 856 857 /* 858 * If the user specified an offset into the device list, 859 * but the list has changed since they last called this 860 * ioctl, tell them that the list has changed. They will 861 * have to get the list from the beginning. 862 */ 863 if ((cio->offset != 0) 864 && (cio->generation != pci_generation)){ 865 cio->num_matches = 0; 866 cio->status = PCI_GETCONF_LIST_CHANGED; 867 error = 0; 868 break; 869 } 870 871 /* 872 * Check to see whether the user has asked for an offset 873 * past the end of our list. 874 */ 875 if (cio->offset >= pci_numdevs) { 876 cio->num_matches = 0; 877 cio->status = PCI_GETCONF_LAST_DEVICE; 878 error = 0; 879 break; 880 } 881 882 /* get the head of the device queue */ 883 devlist_head = &pci_devq; 884 885 /* 886 * Determine how much room we have for pci_conf structures. 887 * Round the user's buffer size down to the nearest 888 * multiple of sizeof(struct pci_conf) in case the user 889 * didn't specify a multiple of that size. 890 */ 891 iolen = min(cio->match_buf_len - 892 (cio->match_buf_len % sizeof(struct pci_conf)), 893 pci_numdevs * sizeof(struct pci_conf)); 894 895 /* 896 * Since we know that iolen is a multiple of the size of 897 * the pciconf union, it's okay to do this. 898 */ 899 ionum = iolen / sizeof(struct pci_conf); 900 901 /* 902 * If this test is true, the user wants the pci_conf 903 * structures returned to match the supplied entries. 904 */ 905 if ((cio->num_patterns > 0) 906 && (cio->pat_buf_len > 0)) { 907 /* 908 * pat_buf_len needs to be: 909 * num_patterns * sizeof(struct pci_match_conf) 910 * While it is certainly possible the user just 911 * allocated a large buffer, but set the number of 912 * matches correctly, it is far more likely that 913 * their kernel doesn't match the userland utility 914 * they're using. It's also possible that the user 915 * forgot to initialize some variables. Yes, this 916 * may be overly picky, but I hazard to guess that 917 * it's far more likely to just catch folks that 918 * updated their kernel but not their userland. 919 */ 920 if ((cio->num_patterns * 921 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 922 /* The user made a mistake, return an error*/ 923 cio->status = PCI_GETCONF_ERROR; 924 printf("pci_ioctl: pat_buf_len %d != " 925 "num_patterns (%d) * sizeof(struct " 926 "pci_match_conf) (%d)\npci_ioctl: " 927 "pat_buf_len should be = %d\n", 928 cio->pat_buf_len, cio->num_patterns, 929 (int)sizeof(struct pci_match_conf), 930 (int)sizeof(struct pci_match_conf) * 931 cio->num_patterns); 932 printf("pci_ioctl: do your headers match your " 933 "kernel?\n"); 934 cio->num_matches = 0; 935 error = EINVAL; 936 break; 937 } 938 939 /* 940 * Check the user's buffer to make sure it's readable. 941 */ 942 if (!useracc((caddr_t)cio->patterns, 943 cio->pat_buf_len, VM_PROT_READ)) { 944 printf("pci_ioctl: pattern buffer %p, " 945 "length %u isn't user accessible for" 946 " READ\n", cio->patterns, 947 cio->pat_buf_len); 948 error = EACCES; 949 break; 950 } 951 /* 952 * Allocate a buffer to hold the patterns. 953 */ 954 pattern_buf = malloc(cio->pat_buf_len, M_TEMP, 955 M_WAITOK); 956 error = copyin(cio->patterns, pattern_buf, 957 cio->pat_buf_len); 958 if (error != 0) 959 break; 960 num_patterns = cio->num_patterns; 961 962 } else if ((cio->num_patterns > 0) 963 || (cio->pat_buf_len > 0)) { 964 /* 965 * The user made a mistake, spit out an error. 966 */ 967 cio->status = PCI_GETCONF_ERROR; 968 cio->num_matches = 0; 969 printf("pci_ioctl: invalid GETCONF arguments\n"); 970 error = EINVAL; 971 break; 972 } else 973 pattern_buf = NULL; 974 975 /* 976 * Make sure we can write to the match buffer. 977 */ 978 if (!useracc((caddr_t)cio->matches, 979 cio->match_buf_len, VM_PROT_WRITE)) { 980 printf("pci_ioctl: match buffer %p, length %u " 981 "isn't user accessible for WRITE\n", 982 cio->matches, cio->match_buf_len); 983 error = EACCES; 984 break; 985 } 986 987 /* 988 * Go through the list of devices and copy out the devices 989 * that match the user's criteria. 990 */ 991 for (cio->num_matches = 0, error = 0, i = 0, 992 dinfo = STAILQ_FIRST(devlist_head); 993 (dinfo != NULL) && (cio->num_matches < ionum) 994 && (error == 0) && (i < pci_numdevs); 995 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 996 997 if (i < cio->offset) 998 continue; 999 1000 /* Populate pd_name and pd_unit */ 1001 name = NULL; 1002 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 1003 name = device_get_name(dinfo->cfg.dev); 1004 if (name) { 1005 strncpy(dinfo->conf.pd_name, name, 1006 sizeof(dinfo->conf.pd_name)); 1007 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 1008 dinfo->conf.pd_unit = 1009 device_get_unit(dinfo->cfg.dev); 1010 } 1011 1012 if ((pattern_buf == NULL) || 1013 (pci_conf_match(pattern_buf, num_patterns, 1014 &dinfo->conf) == 0)) { 1015 1016 /* 1017 * If we've filled up the user's buffer, 1018 * break out at this point. Since we've 1019 * got a match here, we'll pick right back 1020 * up at the matching entry. We can also 1021 * tell the user that there are more matches 1022 * left. 1023 */ 1024 if (cio->num_matches >= ionum) 1025 break; 1026 1027 error = copyout(&dinfo->conf, 1028 &cio->matches[cio->num_matches], 1029 sizeof(struct pci_conf)); 1030 cio->num_matches++; 1031 } 1032 } 1033 1034 /* 1035 * Set the pointer into the list, so if the user is getting 1036 * n records at a time, where n < pci_numdevs, 1037 */ 1038 cio->offset = i; 1039 1040 /* 1041 * Set the generation, the user will need this if they make 1042 * another ioctl call with offset != 0. 1043 */ 1044 cio->generation = pci_generation; 1045 1046 /* 1047 * If this is the last device, inform the user so he won't 1048 * bother asking for more devices. If dinfo isn't NULL, we 1049 * know that there are more matches in the list because of 1050 * the way the traversal is done. 1051 */ 1052 if (dinfo == NULL) 1053 cio->status = PCI_GETCONF_LAST_DEVICE; 1054 else 1055 cio->status = PCI_GETCONF_MORE_DEVS; 1056 1057 if (pattern_buf != NULL) 1058 free(pattern_buf, M_TEMP); 1059 1060 break; 1061 } 1062 case PCIOCREAD: 1063 io = (struct pci_io *)data; 1064 switch(io->pi_width) { 1065 case 4: 1066 case 2: 1067 case 1: 1068 /* 1069 * Assume that the user-level bus number is 1070 * actually the pciN instance number. We map 1071 * from that to the real pcib+bus combination. 1072 */ 1073 pci = devclass_get_device(pci_devclass, 1074 io->pi_sel.pc_bus); 1075 if (pci) { 1076 int b = pcib_get_bus(pci); 1077 pcib = device_get_parent(pci); 1078 io->pi_data = 1079 PCIB_READ_CONFIG(pcib, 1080 b, 1081 io->pi_sel.pc_dev, 1082 io->pi_sel.pc_func, 1083 io->pi_reg, 1084 io->pi_width); 1085 error = 0; 1086 } else { 1087 error = ENODEV; 1088 } 1089 break; 1090 default: 1091 error = ENODEV; 1092 break; 1093 } 1094 break; 1095 1096 case PCIOCWRITE: 1097 io = (struct pci_io *)data; 1098 switch(io->pi_width) { 1099 case 4: 1100 case 2: 1101 case 1: 1102 /* 1103 * Assume that the user-level bus number is 1104 * actually the pciN instance number. We map 1105 * from that to the real pcib+bus combination. 1106 */ 1107 pci = devclass_get_device(pci_devclass, 1108 io->pi_sel.pc_bus); 1109 if (pci) { 1110 int b = pcib_get_bus(pci); 1111 pcib = device_get_parent(pci); 1112 PCIB_WRITE_CONFIG(pcib, 1113 b, 1114 io->pi_sel.pc_dev, 1115 io->pi_sel.pc_func, 1116 io->pi_reg, 1117 io->pi_data, 1118 io->pi_width); 1119 error = 0; 1120 } else { 1121 error = ENODEV; 1122 } 1123 break; 1124 default: 1125 error = ENODEV; 1126 break; 1127 } 1128 break; 1129 1130 default: 1131 error = ENOTTY; 1132 break; 1133 } 1134 1135 return (error); 1136 } 1137 1138 #define PCI_CDEV 78 1139 1140 static struct cdevsw pcicdev = { 1141 /* name */ "pci", 1142 /* maj */ PCI_CDEV, 1143 /* flags */ 0, 1144 /* port */ NULL, 1145 /* autoq */ 0, 1146 1147 /* open */ pci_open, 1148 /* close */ pci_close, 1149 /* read */ noread, 1150 /* write */ nowrite, 1151 /* ioctl */ pci_ioctl, 1152 /* poll */ nopoll, 1153 /* mmap */ nommap, 1154 /* strategy */ nostrategy, 1155 /* dump */ nodump, 1156 /* psize */ nopsize 1157 }; 1158 1159 #include "pci_if.h" 1160 1161 /* 1162 * New style pci driver. Parent device is either a pci-host-bridge or a 1163 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1164 */ 1165 1166 void 1167 pci_print_verbose(struct pci_devinfo *dinfo) 1168 { 1169 if (bootverbose) { 1170 pcicfgregs *cfg = &dinfo->cfg; 1171 1172 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1173 cfg->vendor, cfg->device, cfg->revid); 1174 printf("\tbus=%d, slot=%d, func=%d\n", 1175 cfg->bus, cfg->slot, cfg->func); 1176 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1177 cfg->baseclass, cfg->subclass, cfg->progif, 1178 cfg->hdrtype, cfg->mfdev); 1179 printf("\tsubordinatebus=%x \tsecondarybus=%x\n", 1180 cfg->subordinatebus, cfg->secondarybus); 1181 #ifdef PCI_DEBUG 1182 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1183 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1184 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1185 cfg->lattimer, cfg->lattimer * 30, 1186 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1187 #endif /* PCI_DEBUG */ 1188 if (cfg->intpin > 0) 1189 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 1190 } 1191 } 1192 1193 static int 1194 pci_porten(device_t pcib, int b, int s, int f) 1195 { 1196 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1197 & PCIM_CMD_PORTEN) != 0; 1198 } 1199 1200 static int 1201 pci_memen(device_t pcib, int b, int s, int f) 1202 { 1203 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1204 & PCIM_CMD_MEMEN) != 0; 1205 } 1206 1207 /* 1208 * Add a resource based on a pci map register. Return 1 if the map 1209 * register is a 32bit map register or 2 if it is a 64bit register. 1210 */ 1211 static int 1212 pci_add_map(device_t pcib, int b, int s, int f, int reg, 1213 struct resource_list *rl) 1214 { 1215 u_int32_t map; 1216 u_int64_t base; 1217 u_int8_t ln2size; 1218 u_int8_t ln2range; 1219 u_int32_t testval; 1220 1221 1222 #ifdef PCI_ENABLE_IO_MODES 1223 u_int16_t cmd; 1224 #endif 1225 int type; 1226 1227 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1228 1229 if (map == 0 || map == 0xffffffff) 1230 return 1; /* skip invalid entry */ 1231 1232 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1233 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1234 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1235 1236 base = pci_mapbase(map); 1237 if (pci_maptype(map) & PCI_MAPMEM) 1238 type = SYS_RES_MEMORY; 1239 else 1240 type = SYS_RES_IOPORT; 1241 ln2size = pci_mapsize(testval); 1242 ln2range = pci_maprange(testval); 1243 if (ln2range == 64) { 1244 /* Read the other half of a 64bit map register */ 1245 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4); 1246 } 1247 1248 /* 1249 * This code theoretically does the right thing, but has 1250 * undesirable side effects in some cases where 1251 * peripherals respond oddly to having these bits 1252 * enabled. Leave them alone by default. 1253 */ 1254 #ifdef PCI_ENABLE_IO_MODES 1255 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1256 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1257 cmd |= PCIM_CMD_PORTEN; 1258 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1259 } 1260 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1261 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1262 cmd |= PCIM_CMD_MEMEN; 1263 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1264 } 1265 #else 1266 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1267 return 1; 1268 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1269 return 1; 1270 #endif 1271 1272 resource_list_add(rl, type, reg, 1273 base, base + (1 << ln2size) - 1, 1274 (1 << ln2size)); 1275 1276 if (bootverbose) { 1277 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n", 1278 reg, pci_maptype(base), ln2range, 1279 (unsigned int) base, ln2size); 1280 } 1281 1282 return (ln2range == 64) ? 2 : 1; 1283 } 1284 1285 static void 1286 pci_add_resources(device_t pcib, device_t bus, device_t dev) 1287 { 1288 struct pci_devinfo *dinfo = device_get_ivars(dev); 1289 pcicfgregs *cfg = &dinfo->cfg; 1290 struct resource_list *rl = &dinfo->resources; 1291 struct pci_quirk *q; 1292 int b, i, f, s; 1293 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */ 1294 int irq; 1295 #endif 1296 1297 b = cfg->bus; 1298 s = cfg->slot; 1299 f = cfg->func; 1300 for (i = 0; i < cfg->nummaps;) { 1301 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl); 1302 } 1303 1304 for (q = &pci_quirks[0]; q->devid; q++) { 1305 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1306 && q->type == PCI_QUIRK_MAP_REG) 1307 pci_add_map(pcib, b, s, f, q->arg1, rl); 1308 } 1309 1310 if (cfg->intpin > 0 && cfg->intline != 255) 1311 resource_list_add(rl, SYS_RES_IRQ, 0, 1312 cfg->intline, cfg->intline, 1); 1313 } 1314 1315 void 1316 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1317 { 1318 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1319 device_t pcib = device_get_parent(dev); 1320 struct pci_devinfo *dinfo; 1321 int maxslots; 1322 int s, f, pcifunchigh; 1323 uint8_t hdrtype; 1324 1325 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo)); 1326 1327 maxslots = PCIB_MAXSLOTS(pcib); 1328 1329 for (s = 0; s <= maxslots; s++) { 1330 pcifunchigh = 0; 1331 f = 0; 1332 hdrtype = REG(PCIR_HDRTYPE, 1); 1333 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1334 continue; 1335 if (hdrtype & PCIM_MFDEV) 1336 pcifunchigh = PCI_FUNCMAX; 1337 for (f = 0; f <= pcifunchigh; f++) { 1338 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1339 if (dinfo != NULL) { 1340 pci_add_child(dev, dinfo); 1341 } 1342 } 1343 } 1344 #undef REG 1345 } 1346 1347 void 1348 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1349 { 1350 device_t pcib; 1351 1352 pcib = device_get_parent(bus); 1353 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1354 device_set_ivars(dinfo->cfg.dev, dinfo); 1355 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1356 pci_print_verbose(dinfo); 1357 } 1358 1359 /* 1360 * Probe the PCI bus. Note: probe code is not supposed to add children 1361 * or call attach. 1362 */ 1363 static int 1364 pci_probe(device_t dev) 1365 { 1366 device_set_desc(dev, "PCI bus"); 1367 1368 /* Allow other subclasses to override this driver */ 1369 return(-1000); 1370 } 1371 1372 static int 1373 pci_attach(device_t dev) 1374 { 1375 int busno; 1376 1377 /* 1378 * Since there can be multiple independantly numbered PCI 1379 * busses on some large alpha systems, we can't use the unit 1380 * number to decide what bus we are probing. We ask the parent 1381 * pcib what our bus number is. 1382 */ 1383 busno = pcib_get_bus(dev); 1384 if (bootverbose) 1385 device_printf(dev, "physical bus=%d\n", busno); 1386 1387 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1388 1389 return (bus_generic_attach(dev)); 1390 } 1391 1392 static int 1393 pci_print_resources(struct resource_list *rl, const char *name, int type, 1394 const char *format) 1395 { 1396 struct resource_list_entry *rle; 1397 int printed, retval; 1398 1399 printed = 0; 1400 retval = 0; 1401 /* Yes, this is kinda cheating */ 1402 SLIST_FOREACH(rle, rl, link) { 1403 if (rle->type == type) { 1404 if (printed == 0) 1405 retval += printf(" %s ", name); 1406 else if (printed > 0) 1407 retval += printf(","); 1408 printed++; 1409 retval += printf(format, rle->start); 1410 if (rle->count > 1) { 1411 retval += printf("-"); 1412 retval += printf(format, rle->start + 1413 rle->count - 1); 1414 } 1415 } 1416 } 1417 return retval; 1418 } 1419 1420 int 1421 pci_print_child(device_t dev, device_t child) 1422 { 1423 struct pci_devinfo *dinfo; 1424 struct resource_list *rl; 1425 pcicfgregs *cfg; 1426 int retval = 0; 1427 1428 dinfo = device_get_ivars(child); 1429 cfg = &dinfo->cfg; 1430 rl = &dinfo->resources; 1431 1432 retval += bus_print_child_header(dev, child); 1433 1434 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 1435 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1436 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 1437 if (device_get_flags(dev)) 1438 retval += printf(" flags %#x", device_get_flags(dev)); 1439 1440 retval += printf(" at device %d.%d", pci_get_slot(child), 1441 pci_get_function(child)); 1442 1443 retval += bus_print_child_footer(dev, child); 1444 1445 return (retval); 1446 } 1447 1448 void 1449 pci_probe_nomatch(device_t dev, device_t child) 1450 { 1451 struct pci_devinfo *dinfo; 1452 pcicfgregs *cfg; 1453 const char *desc; 1454 int unknown; 1455 1456 unknown = 0; 1457 dinfo = device_get_ivars(child); 1458 cfg = &dinfo->cfg; 1459 desc = pci_ata_match(child); 1460 if (!desc) desc = pci_usb_match(child); 1461 if (!desc) desc = pci_vga_match(child); 1462 if (!desc) desc = pci_chip_match(child); 1463 if (!desc) { 1464 desc = "unknown card"; 1465 unknown++; 1466 } 1467 device_printf(dev, "<%s>", desc); 1468 if (bootverbose || unknown) { 1469 printf(" (vendor=0x%04x, dev=0x%04x)", 1470 cfg->vendor, 1471 cfg->device); 1472 } 1473 printf(" at %d.%d", 1474 pci_get_slot(child), 1475 pci_get_function(child)); 1476 if (cfg->intpin > 0 && cfg->intline != 255) { 1477 printf(" irq %d", cfg->intline); 1478 } 1479 printf("\n"); 1480 1481 return; 1482 } 1483 1484 int 1485 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1486 { 1487 struct pci_devinfo *dinfo; 1488 pcicfgregs *cfg; 1489 1490 dinfo = device_get_ivars(child); 1491 cfg = &dinfo->cfg; 1492 1493 switch (which) { 1494 case PCI_IVAR_SUBVENDOR: 1495 *result = cfg->subvendor; 1496 break; 1497 case PCI_IVAR_SUBDEVICE: 1498 *result = cfg->subdevice; 1499 break; 1500 case PCI_IVAR_VENDOR: 1501 *result = cfg->vendor; 1502 break; 1503 case PCI_IVAR_DEVICE: 1504 *result = cfg->device; 1505 break; 1506 case PCI_IVAR_DEVID: 1507 *result = (cfg->device << 16) | cfg->vendor; 1508 break; 1509 case PCI_IVAR_CLASS: 1510 *result = cfg->baseclass; 1511 break; 1512 case PCI_IVAR_SUBCLASS: 1513 *result = cfg->subclass; 1514 break; 1515 case PCI_IVAR_PROGIF: 1516 *result = cfg->progif; 1517 break; 1518 case PCI_IVAR_REVID: 1519 *result = cfg->revid; 1520 break; 1521 case PCI_IVAR_INTPIN: 1522 *result = cfg->intpin; 1523 break; 1524 case PCI_IVAR_IRQ: 1525 *result = cfg->intline; 1526 break; 1527 case PCI_IVAR_BUS: 1528 *result = cfg->bus; 1529 break; 1530 case PCI_IVAR_SLOT: 1531 *result = cfg->slot; 1532 break; 1533 case PCI_IVAR_FUNCTION: 1534 *result = cfg->func; 1535 break; 1536 case PCI_IVAR_SECONDARYBUS: 1537 *result = cfg->secondarybus; 1538 break; 1539 case PCI_IVAR_SUBORDINATEBUS: 1540 *result = cfg->subordinatebus; 1541 break; 1542 case PCI_IVAR_ETHADDR: 1543 /* 1544 * The generic accessor doesn't deal with failure, so 1545 * we set the return value, then return an error. 1546 */ 1547 *result = NULL; 1548 return (EINVAL); 1549 default: 1550 return ENOENT; 1551 } 1552 return 0; 1553 } 1554 1555 int 1556 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1557 { 1558 struct pci_devinfo *dinfo; 1559 pcicfgregs *cfg; 1560 1561 dinfo = device_get_ivars(child); 1562 cfg = &dinfo->cfg; 1563 1564 switch (which) { 1565 case PCI_IVAR_SUBVENDOR: 1566 case PCI_IVAR_SUBDEVICE: 1567 case PCI_IVAR_VENDOR: 1568 case PCI_IVAR_DEVICE: 1569 case PCI_IVAR_DEVID: 1570 case PCI_IVAR_CLASS: 1571 case PCI_IVAR_SUBCLASS: 1572 case PCI_IVAR_PROGIF: 1573 case PCI_IVAR_REVID: 1574 case PCI_IVAR_INTPIN: 1575 case PCI_IVAR_IRQ: 1576 case PCI_IVAR_BUS: 1577 case PCI_IVAR_SLOT: 1578 case PCI_IVAR_FUNCTION: 1579 case PCI_IVAR_ETHADDR: 1580 return EINVAL; /* disallow for now */ 1581 1582 case PCI_IVAR_SECONDARYBUS: 1583 cfg->secondarybus = value; 1584 break; 1585 case PCI_IVAR_SUBORDINATEBUS: 1586 cfg->subordinatebus = value; 1587 break; 1588 default: 1589 return ENOENT; 1590 } 1591 return 0; 1592 } 1593 1594 static struct resource * 1595 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1596 u_long start, u_long end, u_long count, u_int flags) 1597 { 1598 struct pci_devinfo *dinfo = device_get_ivars(child); 1599 struct resource_list *rl = &dinfo->resources; 1600 1601 #ifdef __i386__ 1602 pcicfgregs *cfg = &dinfo->cfg; 1603 /* 1604 * Perform lazy resource allocation 1605 * 1606 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1607 */ 1608 if (device_get_parent(child) == dev) { 1609 /* 1610 * If device doesn't have an interrupt routed, and is 1611 * deserving of an interrupt, try to assign it one. 1612 */ 1613 if ((type == SYS_RES_IRQ) && 1614 (cfg->intline == 255 || cfg->intline == 0) && 1615 (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) { 1616 cfg->intline = PCIB_ROUTE_INTERRUPT( 1617 device_get_parent(dev), child, 1618 cfg->intpin); 1619 if (cfg->intline != 255) { 1620 pci_write_config(child, PCIR_INTLINE, 1621 cfg->intline, 1); 1622 resource_list_add(rl, SYS_RES_IRQ, 0, 1623 cfg->intline, cfg->intline, 1); 1624 } 1625 } 1626 } 1627 #endif 1628 return resource_list_alloc(rl, dev, child, type, rid, 1629 start, end, count, flags); 1630 } 1631 1632 static int 1633 pci_release_resource(device_t dev, device_t child, int type, int rid, 1634 struct resource *r) 1635 { 1636 struct pci_devinfo *dinfo = device_get_ivars(child); 1637 struct resource_list *rl = &dinfo->resources; 1638 1639 return resource_list_release(rl, dev, child, type, rid, r); 1640 } 1641 1642 static int 1643 pci_set_resource(device_t dev, device_t child, int type, int rid, 1644 u_long start, u_long count) 1645 { 1646 struct pci_devinfo *dinfo = device_get_ivars(child); 1647 struct resource_list *rl = &dinfo->resources; 1648 1649 resource_list_add(rl, type, rid, start, start + count - 1, count); 1650 return 0; 1651 } 1652 1653 static int 1654 pci_get_resource(device_t dev, device_t child, int type, int rid, 1655 u_long *startp, u_long *countp) 1656 { 1657 struct pci_devinfo *dinfo = device_get_ivars(child); 1658 struct resource_list *rl = &dinfo->resources; 1659 struct resource_list_entry *rle; 1660 1661 rle = resource_list_find(rl, type, rid); 1662 if (!rle) 1663 return ENOENT; 1664 1665 if (startp) 1666 *startp = rle->start; 1667 if (countp) 1668 *countp = rle->count; 1669 1670 return 0; 1671 } 1672 1673 void 1674 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1675 { 1676 printf("pci_delete_resource: PCI resources can not be deleted\n"); 1677 } 1678 1679 struct resource_list * 1680 pci_get_resource_list (device_t dev, device_t child) 1681 { 1682 struct pci_devinfo * dinfo = device_get_ivars(child); 1683 struct resource_list * rl = &dinfo->resources; 1684 1685 if (!rl) 1686 return (NULL); 1687 1688 return (rl); 1689 } 1690 1691 u_int32_t 1692 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1693 { 1694 struct pci_devinfo *dinfo = device_get_ivars(child); 1695 pcicfgregs *cfg = &dinfo->cfg; 1696 1697 return PCIB_READ_CONFIG(device_get_parent(dev), 1698 cfg->bus, cfg->slot, cfg->func, 1699 reg, width); 1700 } 1701 1702 void 1703 pci_write_config_method(device_t dev, device_t child, int reg, 1704 u_int32_t val, int width) 1705 { 1706 struct pci_devinfo *dinfo = device_get_ivars(child); 1707 pcicfgregs *cfg = &dinfo->cfg; 1708 1709 PCIB_WRITE_CONFIG(device_get_parent(dev), 1710 cfg->bus, cfg->slot, cfg->func, 1711 reg, val, width); 1712 } 1713 1714 int 1715 pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 1716 size_t buflen) 1717 { 1718 struct pci_devinfo *dinfo; 1719 1720 dinfo = device_get_ivars(child); 1721 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1722 pci_get_function(child)); 1723 return (0); 1724 } 1725 1726 int 1727 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 1728 size_t buflen) 1729 { 1730 struct pci_devinfo *dinfo; 1731 pcicfgregs *cfg; 1732 1733 dinfo = device_get_ivars(child); 1734 cfg = &dinfo->cfg; 1735 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1736 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1737 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1738 cfg->progif); 1739 return (0); 1740 } 1741 1742 int 1743 pci_assign_interrupt_method(device_t dev, device_t child) 1744 { 1745 struct pci_devinfo *dinfo = device_get_ivars(child); 1746 pcicfgregs *cfg = &dinfo->cfg; 1747 1748 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1749 cfg->intpin)); 1750 } 1751 1752 static int 1753 pci_modevent(module_t mod, int what, void *arg) 1754 { 1755 static dev_t pci_cdev; 1756 1757 switch (what) { 1758 case MOD_LOAD: 1759 STAILQ_INIT(&pci_devq); 1760 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1761 "pci"); 1762 break; 1763 1764 case MOD_UNLOAD: 1765 destroy_dev(pci_cdev); 1766 break; 1767 } 1768 1769 return 0; 1770 } 1771 1772 int 1773 pci_resume(device_t dev) 1774 { 1775 int numdevs; 1776 int i; 1777 device_t *children; 1778 device_t child; 1779 struct pci_devinfo *dinfo; 1780 pcicfgregs *cfg; 1781 1782 device_get_children(dev, &children, &numdevs); 1783 1784 for (i = 0; i < numdevs; i++) { 1785 child = children[i]; 1786 1787 dinfo = device_get_ivars(child); 1788 cfg = &dinfo->cfg; 1789 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1790 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1791 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1792 pci_write_config(child, PCIR_INTLINE, 1793 cfg->intline, 1); 1794 } 1795 } 1796 } 1797 1798 free(children, M_TEMP); 1799 1800 return (bus_generic_resume(dev)); 1801 } 1802 1803 static device_method_t pci_methods[] = { 1804 /* Device interface */ 1805 DEVMETHOD(device_probe, pci_probe), 1806 DEVMETHOD(device_attach, pci_attach), 1807 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1808 DEVMETHOD(device_suspend, bus_generic_suspend), 1809 DEVMETHOD(device_resume, pci_resume), 1810 1811 /* Bus interface */ 1812 DEVMETHOD(bus_print_child, pci_print_child), 1813 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 1814 DEVMETHOD(bus_read_ivar, pci_read_ivar), 1815 DEVMETHOD(bus_write_ivar, pci_write_ivar), 1816 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1817 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1818 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1819 1820 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 1821 DEVMETHOD(bus_set_resource, pci_set_resource), 1822 DEVMETHOD(bus_get_resource, pci_get_resource), 1823 DEVMETHOD(bus_delete_resource, pci_delete_resource), 1824 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 1825 DEVMETHOD(bus_release_resource, pci_release_resource), 1826 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1827 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1828 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 1829 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 1830 1831 /* PCI interface */ 1832 DEVMETHOD(pci_read_config, pci_read_config_method), 1833 DEVMETHOD(pci_write_config, pci_write_config_method), 1834 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 1835 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 1836 DEVMETHOD(pci_enable_io, pci_enable_io_method), 1837 DEVMETHOD(pci_disable_io, pci_disable_io_method), 1838 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 1839 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 1840 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 1841 1842 { 0, 0 } 1843 }; 1844 1845 static driver_t pci_driver = { 1846 "pci", 1847 pci_methods, 1848 1, /* no softc */ 1849 }; 1850 1851 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 1852