1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $ 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.58 2008/11/16 18:44:00 swildner Exp $ 28 * 29 */ 30 31 #include "opt_bus.h" 32 #include "opt_pci.h" 33 34 #include "opt_compat_oldpci.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/fcntl.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/queue.h> 44 #include <sys/types.h> 45 #include <sys/sysctl.h> 46 #include <sys/buf.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 #include <vm/vm_extern.h> 51 52 #include <sys/bus.h> 53 #include <sys/rman.h> 54 #include <machine/smp.h> 55 #include "pci_cfgreg.h" 56 57 #include <sys/pciio.h> 58 #include "pcireg.h" 59 #include "pcivar.h" 60 #include "pci_private.h" 61 62 #include "pcib_if.h" 63 64 devclass_t pci_devclass; 65 const char *pcib_owner; 66 67 static void pci_read_capabilities(device_t dev, pcicfgregs *cfg); 68 static int pcie_slotimpl(const pcicfgregs *); 69 70 struct pci_quirk { 71 u_int32_t devid; /* Vendor/device of the card */ 72 int type; 73 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 74 int arg1; 75 int arg2; 76 }; 77 78 struct pci_quirk pci_quirks[] = { 79 /* 80 * The Intel 82371AB and 82443MX has a map register at offset 0x90. 81 */ 82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 84 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 86 87 { 0 } 88 }; 89 90 /* map register information */ 91 #define PCI_MAPMEM 0x01 /* memory map */ 92 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 93 #define PCI_MAPPORT 0x04 /* port map */ 94 95 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 96 u_int32_t pci_numdevs = 0; 97 static u_int32_t pci_generation = 0; 98 99 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "pci parameters"); 100 static int pci_do_power_nodriver = 0; 101 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 102 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 103 &pci_do_power_nodriver, 0, 104 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 105 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 106 aggressively place devices into D3 state. 3 means put absolutely everything\n\ 107 in D3 state."); 108 109 device_t 110 pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func) 111 { 112 struct pci_devinfo *dinfo; 113 114 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 115 if ((dinfo->cfg.bus == bus) && 116 (dinfo->cfg.slot == slot) && 117 (dinfo->cfg.func == func)) { 118 return (dinfo->cfg.dev); 119 } 120 } 121 122 return (NULL); 123 } 124 125 device_t 126 pci_find_device(u_int16_t vendor, u_int16_t device) 127 { 128 struct pci_devinfo *dinfo; 129 130 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 131 if ((dinfo->cfg.vendor == vendor) && 132 (dinfo->cfg.device == device)) { 133 return (dinfo->cfg.dev); 134 } 135 } 136 137 return (NULL); 138 } 139 140 int 141 pcie_slot_implemented(device_t dev) 142 { 143 struct pci_devinfo *dinfo = device_get_ivars(dev); 144 145 return pcie_slotimpl(&dinfo->cfg); 146 } 147 148 void 149 pcie_set_max_readrq(device_t dev, uint16_t rqsize) 150 { 151 uint8_t expr_ptr; 152 uint16_t val; 153 154 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK; 155 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) { 156 panic("%s: invalid max read request size 0x%02x\n", 157 device_get_nameunit(dev), rqsize); 158 } 159 160 expr_ptr = pci_get_pciecap_ptr(dev); 161 if (!expr_ptr) 162 panic("%s: not PCIe device\n", device_get_nameunit(dev)); 163 164 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2); 165 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) { 166 if (bootverbose) 167 device_printf(dev, "adjust device control 0x%04x", val); 168 169 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK; 170 val |= rqsize; 171 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2); 172 173 if (bootverbose) 174 kprintf(" -> 0x%04x\n", val); 175 } 176 } 177 178 /* return base address of memory or port map */ 179 180 static u_int32_t 181 pci_mapbase(unsigned mapreg) 182 { 183 int mask = 0x03; 184 if ((mapreg & 0x01) == 0) 185 mask = 0x0f; 186 return (mapreg & ~mask); 187 } 188 189 /* return map type of memory or port map */ 190 191 static int 192 pci_maptype(unsigned mapreg) 193 { 194 static u_int8_t maptype[0x10] = { 195 PCI_MAPMEM, PCI_MAPPORT, 196 PCI_MAPMEM, 0, 197 PCI_MAPMEM, PCI_MAPPORT, 198 0, 0, 199 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 200 PCI_MAPMEM|PCI_MAPMEMP, 0, 201 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 202 0, 0, 203 }; 204 205 return maptype[mapreg & 0x0f]; 206 } 207 208 /* return log2 of map size decoded for memory or port map */ 209 210 static int 211 pci_mapsize(unsigned testval) 212 { 213 int ln2size; 214 215 testval = pci_mapbase(testval); 216 ln2size = 0; 217 if (testval != 0) { 218 while ((testval & 1) == 0) 219 { 220 ln2size++; 221 testval >>= 1; 222 } 223 } 224 return (ln2size); 225 } 226 227 /* return log2 of address range supported by map register */ 228 229 static int 230 pci_maprange(unsigned mapreg) 231 { 232 int ln2range = 0; 233 switch (mapreg & 0x07) { 234 case 0x00: 235 case 0x01: 236 case 0x05: 237 ln2range = 32; 238 break; 239 case 0x02: 240 ln2range = 20; 241 break; 242 case 0x04: 243 ln2range = 64; 244 break; 245 } 246 return (ln2range); 247 } 248 249 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 250 251 static void 252 pci_fixancient(pcicfgregs *cfg) 253 { 254 if (cfg->hdrtype != 0) 255 return; 256 257 /* PCI to PCI bridges use header type 1 */ 258 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 259 cfg->hdrtype = 1; 260 } 261 262 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 263 264 static void * 265 pci_readppb(device_t pcib, int b, int s, int f) 266 { 267 pcih1cfgregs *p; 268 269 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 270 271 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2); 272 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2); 273 274 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1); 275 276 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f, 277 PCIR_IOBASEH_1, 2), 278 PCIB_READ_CONFIG(pcib, b, s, f, 279 PCIR_IOBASEL_1, 1)); 280 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f, 281 PCIR_IOLIMITH_1, 2), 282 PCIB_READ_CONFIG(pcib, b, s, f, 283 PCIR_IOLIMITL_1, 1)); 284 285 p->membase = PCI_PPBMEMBASE (0, 286 PCIB_READ_CONFIG(pcib, b, s, f, 287 PCIR_MEMBASE_1, 2)); 288 p->memlimit = PCI_PPBMEMLIMIT (0, 289 PCIB_READ_CONFIG(pcib, b, s, f, 290 PCIR_MEMLIMIT_1, 2)); 291 292 p->pmembase = PCI_PPBMEMBASE ( 293 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4), 294 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2)); 295 296 p->pmemlimit = PCI_PPBMEMLIMIT ( 297 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, 298 PCIR_PMLIMITH_1, 4), 299 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2)); 300 301 return (p); 302 } 303 304 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 305 306 static void * 307 pci_readpcb(device_t pcib, int b, int s, int f) 308 { 309 pcih2cfgregs *p; 310 311 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 312 313 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2); 314 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2); 315 316 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1); 317 318 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4); 319 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4); 320 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4); 321 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4); 322 323 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4); 324 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4); 325 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4); 326 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4); 327 328 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4); 329 return p; 330 } 331 332 /* extract header type specific config data */ 333 334 static void 335 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 336 { 337 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 338 switch (cfg->hdrtype) { 339 case 0: 340 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 341 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 342 cfg->nummaps = PCI_MAXMAPS_0; 343 break; 344 case 1: 345 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 346 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 347 cfg->secondarybus = REG(PCIR_SECBUS_1, 1); 348 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1); 349 cfg->nummaps = PCI_MAXMAPS_1; 350 cfg->hdrspec = pci_readppb(pcib, b, s, f); 351 break; 352 case 2: 353 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 354 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 355 cfg->secondarybus = REG(PCIR_SECBUS_2, 1); 356 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1); 357 cfg->nummaps = PCI_MAXMAPS_2; 358 cfg->hdrspec = pci_readpcb(pcib, b, s, f); 359 break; 360 } 361 #undef REG 362 } 363 364 /* read configuration header into pcicfgrect structure */ 365 366 struct pci_devinfo * 367 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 368 { 369 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 370 371 pcicfgregs *cfg = NULL; 372 struct pci_devinfo *devlist_entry; 373 struct devlist *devlist_head; 374 375 devlist_head = &pci_devq; 376 377 devlist_entry = NULL; 378 379 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 380 381 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 382 383 cfg = &devlist_entry->cfg; 384 385 cfg->bus = b; 386 cfg->slot = s; 387 cfg->func = f; 388 cfg->vendor = REG(PCIR_VENDOR, 2); 389 cfg->device = REG(PCIR_DEVICE, 2); 390 cfg->cmdreg = REG(PCIR_COMMAND, 2); 391 cfg->statreg = REG(PCIR_STATUS, 2); 392 cfg->baseclass = REG(PCIR_CLASS, 1); 393 cfg->subclass = REG(PCIR_SUBCLASS, 1); 394 cfg->progif = REG(PCIR_PROGIF, 1); 395 cfg->revid = REG(PCIR_REVID, 1); 396 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 397 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 398 cfg->lattimer = REG(PCIR_LATTIMER, 1); 399 cfg->intpin = REG(PCIR_INTPIN, 1); 400 cfg->intline = REG(PCIR_INTLINE, 1); 401 402 #ifdef APIC_IO 403 /* 404 * If using the APIC the intpin is probably wrong, since it 405 * is often setup by the BIOS with the PIC in mind. 406 */ 407 if (cfg->intpin != 0) { 408 int airq; 409 410 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 411 if (airq >= 0) { 412 /* PCI specific entry found in MP table */ 413 if (airq != cfg->intline) { 414 undirect_pci_irq(cfg->intline); 415 cfg->intline = airq; 416 } 417 } else { 418 /* 419 * PCI interrupts might be redirected to the 420 * ISA bus according to some MP tables. Use the 421 * same methods as used by the ISA devices 422 * devices to find the proper IOAPIC int pin. 423 */ 424 airq = isa_apic_irq(cfg->intline); 425 if ((airq >= 0) && (airq != cfg->intline)) { 426 /* XXX: undirect_pci_irq() ? */ 427 undirect_isa_irq(cfg->intline); 428 cfg->intline = airq; 429 } 430 } 431 } 432 #endif /* APIC_IO */ 433 434 cfg->mingnt = REG(PCIR_MINGNT, 1); 435 cfg->maxlat = REG(PCIR_MAXLAT, 1); 436 437 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 438 cfg->hdrtype &= ~PCIM_MFDEV; 439 440 pci_fixancient(cfg); 441 pci_hdrtypedata(pcib, b, s, f, cfg); 442 pci_read_capabilities(pcib, cfg); 443 444 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 445 446 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 447 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 448 devlist_entry->conf.pc_sel.pc_func = cfg->func; 449 devlist_entry->conf.pc_hdr = cfg->hdrtype; 450 451 devlist_entry->conf.pc_subvendor = cfg->subvendor; 452 devlist_entry->conf.pc_subdevice = cfg->subdevice; 453 devlist_entry->conf.pc_vendor = cfg->vendor; 454 devlist_entry->conf.pc_device = cfg->device; 455 456 devlist_entry->conf.pc_class = cfg->baseclass; 457 devlist_entry->conf.pc_subclass = cfg->subclass; 458 devlist_entry->conf.pc_progif = cfg->progif; 459 devlist_entry->conf.pc_revid = cfg->revid; 460 461 pci_numdevs++; 462 pci_generation++; 463 } 464 return (devlist_entry); 465 #undef REG 466 } 467 468 static int 469 pci_fixup_nextptr(int *nextptr0) 470 { 471 int nextptr = *nextptr0; 472 473 /* "Next pointer" is only one byte */ 474 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr)); 475 476 if (nextptr & 0x3) { 477 /* 478 * PCI local bus spec 3.0: 479 * 480 * "... The bottom two bits of all pointers are reserved 481 * and must be implemented as 00b although software must 482 * mask them to allow for future uses of these bits ..." 483 */ 484 if (bootverbose) { 485 kprintf("Illegal PCI extended capability " 486 "offset, fixup 0x%02x -> 0x%02x\n", 487 nextptr, nextptr & ~0x3); 488 } 489 nextptr &= ~0x3; 490 } 491 *nextptr0 = nextptr; 492 493 if (nextptr < 0x40) { 494 if (nextptr != 0) { 495 kprintf("Illegal PCI extended capability " 496 "offset 0x%02x", nextptr); 497 } 498 return 0; 499 } 500 return 1; 501 } 502 503 static void 504 pci_read_cap_pmgt(device_t pcib, int ptr, pcicfgregs *cfg) 505 { 506 #define REG(n, w) \ 507 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 508 509 struct pcicfg_pmgt *pmgt = &cfg->pmgt; 510 511 if (pmgt->pp_cap) 512 return; 513 514 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 515 pmgt->pp_status = ptr + PCIR_POWER_STATUS; 516 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 517 /* 518 * XXX 519 * Following way may be used to to test whether 520 * 'data' register exists: 521 * if 'data_select' register of 522 * PCIR_POWER_STATUS(bits[12,9]) is read-only 523 * then 'data' register is _not_ implemented. 524 */ 525 pmgt->pp_data = 0; 526 527 #undef REG 528 } 529 530 static int 531 pcie_slotimpl(const pcicfgregs *cfg) 532 { 533 const struct pcicfg_expr *expr = &cfg->expr; 534 uint16_t port_type; 535 536 /* 537 * Only version 1 can be parsed currently 538 */ 539 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1) 540 return 0; 541 542 /* 543 * - Slot implemented bit is meaningful iff current port is 544 * root port or down stream port. 545 * - Testing for root port or down stream port is meanningful 546 * iff PCI configure has type 1 header. 547 */ 548 549 if (cfg->hdrtype != 1) 550 return 0; 551 552 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE; 553 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT) 554 return 0; 555 556 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL)) 557 return 0; 558 559 return 1; 560 } 561 562 static void 563 pci_read_cap_expr(device_t pcib, int ptr, pcicfgregs *cfg) 564 { 565 #define REG(n, w) \ 566 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 567 568 struct pcicfg_expr *expr = &cfg->expr; 569 570 expr->expr_ptr = ptr; 571 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2); 572 573 /* 574 * Only version 1 can be parsed currently 575 */ 576 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1) 577 return; 578 579 /* 580 * Read slot capabilities. Slot capabilities exists iff 581 * current port's slot is implemented 582 */ 583 if (pcie_slotimpl(cfg)) 584 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4); 585 586 #undef REG 587 } 588 589 static void 590 pci_read_capabilities(device_t pcib, pcicfgregs *cfg) 591 { 592 #define REG(n, w) \ 593 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 594 595 int nextptr, ptrptr; 596 597 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) { 598 /* No capabilities */ 599 return; 600 } 601 602 switch (cfg->hdrtype) { 603 case 0: 604 case 1: 605 ptrptr = PCIR_CAP_PTR; 606 break; 607 case 2: 608 ptrptr = PCIR_CAP_PTR_2; 609 break; 610 default: 611 return; /* No capabilities support */ 612 } 613 nextptr = REG(ptrptr, 1); 614 615 /* 616 * Read capability entries. 617 */ 618 while (pci_fixup_nextptr(&nextptr)) { 619 int ptr = nextptr; 620 621 /* Process this entry */ 622 switch (REG(ptr, 1)) { 623 case PCIY_PMG: /* PCI power management */ 624 pci_read_cap_pmgt(pcib, ptr, cfg); 625 break; 626 case PCIY_PCIX: /* PCI-X */ 627 cfg->pcixcap_ptr = ptr; 628 break; 629 case PCIY_EXPRESS: /* PCI Express */ 630 pci_read_cap_expr(pcib, ptr, cfg); 631 break; 632 default: 633 break; 634 } 635 636 /* Find the next entry */ 637 nextptr = REG(ptr + 1, 1); 638 } 639 640 #undef REG 641 } 642 643 /* free pcicfgregs structure and all depending data structures */ 644 645 int 646 pci_freecfg(struct pci_devinfo *dinfo) 647 { 648 struct devlist *devlist_head; 649 650 devlist_head = &pci_devq; 651 652 if (dinfo->cfg.hdrspec != NULL) 653 kfree(dinfo->cfg.hdrspec, M_DEVBUF); 654 /* XXX this hasn't been tested */ 655 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 656 kfree(dinfo, M_DEVBUF); 657 658 /* increment the generation count */ 659 pci_generation++; 660 661 /* we're losing one device */ 662 pci_numdevs--; 663 return (0); 664 } 665 666 667 /* 668 * PCI power manangement 669 */ 670 int 671 pci_set_powerstate_method(device_t dev, device_t child, int state) 672 { 673 struct pci_devinfo *dinfo = device_get_ivars(child); 674 pcicfgregs *cfg = &dinfo->cfg; 675 uint16_t status; 676 int result, oldstate, highest, delay; 677 678 if (cfg->pmgt.pp_cap == 0) 679 return (EOPNOTSUPP); 680 681 /* 682 * Optimize a no state change request away. While it would be OK to 683 * write to the hardware in theory, some devices have shown odd 684 * behavior when going from D3 -> D3. 685 */ 686 oldstate = pci_get_powerstate(child); 687 if (oldstate == state) 688 return (0); 689 690 /* 691 * The PCI power management specification states that after a state 692 * transition between PCI power states, system software must 693 * guarantee a minimal delay before the function accesses the device. 694 * Compute the worst case delay that we need to guarantee before we 695 * access the device. Many devices will be responsive much more 696 * quickly than this delay, but there are some that don't respond 697 * instantly to state changes. Transitions to/from D3 state require 698 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 699 * is done below with DELAY rather than a sleeper function because 700 * this function can be called from contexts where we cannot sleep. 701 */ 702 highest = (oldstate > state) ? oldstate : state; 703 if (highest == PCI_POWERSTATE_D3) 704 delay = 10000; 705 else if (highest == PCI_POWERSTATE_D2) 706 delay = 200; 707 else 708 delay = 0; 709 status = PCI_READ_CONFIG(dev, child, cfg->pmgt.pp_status, 2) 710 & ~PCIM_PSTAT_DMASK; 711 result = 0; 712 switch (state) { 713 case PCI_POWERSTATE_D0: 714 status |= PCIM_PSTAT_D0; 715 break; 716 case PCI_POWERSTATE_D1: 717 if ((cfg->pmgt.pp_cap & PCIM_PCAP_D1SUPP) == 0) 718 return (EOPNOTSUPP); 719 status |= PCIM_PSTAT_D1; 720 break; 721 case PCI_POWERSTATE_D2: 722 if ((cfg->pmgt.pp_cap & PCIM_PCAP_D2SUPP) == 0) 723 return (EOPNOTSUPP); 724 status |= PCIM_PSTAT_D2; 725 break; 726 case PCI_POWERSTATE_D3: 727 status |= PCIM_PSTAT_D3; 728 break; 729 default: 730 return (EINVAL); 731 } 732 733 if (bootverbose) 734 kprintf( 735 "pci%d:%d:%d: Transition from D%d to D%d\n", 736 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 737 oldstate, state); 738 739 PCI_WRITE_CONFIG(dev, child, cfg->pmgt.pp_status, status, 2); 740 if (delay) 741 DELAY(delay); 742 return (0); 743 } 744 745 int 746 pci_get_powerstate_method(device_t dev, device_t child) 747 { 748 struct pci_devinfo *dinfo = device_get_ivars(child); 749 pcicfgregs *cfg = &dinfo->cfg; 750 uint16_t status; 751 int result; 752 753 if (cfg->pmgt.pp_cap != 0) { 754 status = PCI_READ_CONFIG(dev, child, cfg->pmgt.pp_status, 2); 755 switch (status & PCIM_PSTAT_DMASK) { 756 case PCIM_PSTAT_D0: 757 result = PCI_POWERSTATE_D0; 758 break; 759 case PCIM_PSTAT_D1: 760 result = PCI_POWERSTATE_D1; 761 break; 762 case PCIM_PSTAT_D2: 763 result = PCI_POWERSTATE_D2; 764 break; 765 case PCIM_PSTAT_D3: 766 result = PCI_POWERSTATE_D3; 767 break; 768 default: 769 result = PCI_POWERSTATE_UNKNOWN; 770 break; 771 } 772 } else { 773 /* No support, device is always at D0 */ 774 result = PCI_POWERSTATE_D0; 775 } 776 return (result); 777 } 778 779 /* 780 * Some convenience functions for PCI device drivers. 781 */ 782 783 static __inline void 784 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 785 { 786 u_int16_t command; 787 788 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 789 command |= bit; 790 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 791 } 792 793 static __inline void 794 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 795 { 796 u_int16_t command; 797 798 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 799 command &= ~bit; 800 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 801 } 802 803 int 804 pci_enable_busmaster_method(device_t dev, device_t child) 805 { 806 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 807 return(0); 808 } 809 810 int 811 pci_disable_busmaster_method(device_t dev, device_t child) 812 { 813 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 814 return(0); 815 } 816 817 int 818 pci_enable_io_method(device_t dev, device_t child, int space) 819 { 820 uint16_t command; 821 uint16_t bit; 822 char *error; 823 824 bit = 0; 825 error = NULL; 826 827 switch(space) { 828 case SYS_RES_IOPORT: 829 bit = PCIM_CMD_PORTEN; 830 error = "port"; 831 break; 832 case SYS_RES_MEMORY: 833 bit = PCIM_CMD_MEMEN; 834 error = "memory"; 835 break; 836 default: 837 return(EINVAL); 838 } 839 pci_set_command_bit(dev, child, bit); 840 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 841 if (command & bit) 842 return(0); 843 device_printf(child, "failed to enable %s mapping!\n", error); 844 return(ENXIO); 845 } 846 847 int 848 pci_disable_io_method(device_t dev, device_t child, int space) 849 { 850 uint16_t command; 851 uint16_t bit; 852 char *error; 853 854 bit = 0; 855 error = NULL; 856 857 switch(space) { 858 case SYS_RES_IOPORT: 859 bit = PCIM_CMD_PORTEN; 860 error = "port"; 861 break; 862 case SYS_RES_MEMORY: 863 bit = PCIM_CMD_MEMEN; 864 error = "memory"; 865 break; 866 default: 867 return (EINVAL); 868 } 869 pci_clear_command_bit(dev, child, bit); 870 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 871 if (command & bit) { 872 device_printf(child, "failed to disable %s mapping!\n", error); 873 return (ENXIO); 874 } 875 return (0); 876 } 877 878 /* 879 * This is the user interface to PCI configuration space. 880 */ 881 882 static int 883 pci_open(struct dev_open_args *ap) 884 { 885 if ((ap->a_oflags & FWRITE) && securelevel > 0) { 886 return EPERM; 887 } 888 return 0; 889 } 890 891 static int 892 pci_close(struct dev_close_args *ap) 893 { 894 return 0; 895 } 896 897 /* 898 * Match a single pci_conf structure against an array of pci_match_conf 899 * structures. The first argument, 'matches', is an array of num_matches 900 * pci_match_conf structures. match_buf is a pointer to the pci_conf 901 * structure that will be compared to every entry in the matches array. 902 * This function returns 1 on failure, 0 on success. 903 */ 904 static int 905 pci_conf_match(struct pci_match_conf *matches, int num_matches, 906 struct pci_conf *match_buf) 907 { 908 int i; 909 910 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 911 return(1); 912 913 for (i = 0; i < num_matches; i++) { 914 /* 915 * I'm not sure why someone would do this...but... 916 */ 917 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 918 continue; 919 920 /* 921 * Look at each of the match flags. If it's set, do the 922 * comparison. If the comparison fails, we don't have a 923 * match, go on to the next item if there is one. 924 */ 925 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 926 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 927 continue; 928 929 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 930 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 931 continue; 932 933 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 934 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 935 continue; 936 937 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 938 && (match_buf->pc_vendor != matches[i].pc_vendor)) 939 continue; 940 941 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 942 && (match_buf->pc_device != matches[i].pc_device)) 943 continue; 944 945 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 946 && (match_buf->pc_class != matches[i].pc_class)) 947 continue; 948 949 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 950 && (match_buf->pd_unit != matches[i].pd_unit)) 951 continue; 952 953 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 954 && (strncmp(matches[i].pd_name, match_buf->pd_name, 955 sizeof(match_buf->pd_name)) != 0)) 956 continue; 957 958 return(0); 959 } 960 961 return(1); 962 } 963 964 /* 965 * Locate the parent of a PCI device by scanning the PCI devlist 966 * and return the entry for the parent. 967 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 968 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 969 */ 970 971 pcicfgregs * 972 pci_devlist_get_parent(pcicfgregs *cfg) 973 { 974 struct devlist *devlist_head; 975 struct pci_devinfo *dinfo; 976 pcicfgregs *bridge_cfg; 977 int i; 978 979 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 980 981 /* If the device is on PCI bus 0, look for the host */ 982 if (cfg->bus == 0) { 983 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 984 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 985 bridge_cfg = &dinfo->cfg; 986 if (bridge_cfg->baseclass == PCIC_BRIDGE 987 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 988 && bridge_cfg->bus == cfg->bus) { 989 return bridge_cfg; 990 } 991 } 992 } 993 994 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 995 if (cfg->bus > 0) { 996 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 997 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 998 bridge_cfg = &dinfo->cfg; 999 if (bridge_cfg->baseclass == PCIC_BRIDGE 1000 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 1001 && bridge_cfg->secondarybus == cfg->bus) { 1002 return bridge_cfg; 1003 } 1004 } 1005 } 1006 1007 return NULL; 1008 } 1009 1010 static int 1011 pci_ioctl(struct dev_ioctl_args *ap) 1012 { 1013 device_t pci, pcib; 1014 struct pci_io *io; 1015 const char *name; 1016 int error; 1017 1018 if (!(ap->a_fflag & FWRITE)) 1019 return EPERM; 1020 1021 switch(ap->a_cmd) { 1022 case PCIOCGETCONF: 1023 { 1024 struct pci_devinfo *dinfo; 1025 struct pci_conf_io *cio; 1026 struct devlist *devlist_head; 1027 struct pci_match_conf *pattern_buf; 1028 int num_patterns; 1029 size_t iolen; 1030 int ionum, i; 1031 1032 cio = (struct pci_conf_io *)ap->a_data; 1033 1034 num_patterns = 0; 1035 dinfo = NULL; 1036 1037 /* 1038 * Hopefully the user won't pass in a null pointer, but it 1039 * can't hurt to check. 1040 */ 1041 if (cio == NULL) { 1042 error = EINVAL; 1043 break; 1044 } 1045 1046 /* 1047 * If the user specified an offset into the device list, 1048 * but the list has changed since they last called this 1049 * ioctl, tell them that the list has changed. They will 1050 * have to get the list from the beginning. 1051 */ 1052 if ((cio->offset != 0) 1053 && (cio->generation != pci_generation)){ 1054 cio->num_matches = 0; 1055 cio->status = PCI_GETCONF_LIST_CHANGED; 1056 error = 0; 1057 break; 1058 } 1059 1060 /* 1061 * Check to see whether the user has asked for an offset 1062 * past the end of our list. 1063 */ 1064 if (cio->offset >= pci_numdevs) { 1065 cio->num_matches = 0; 1066 cio->status = PCI_GETCONF_LAST_DEVICE; 1067 error = 0; 1068 break; 1069 } 1070 1071 /* get the head of the device queue */ 1072 devlist_head = &pci_devq; 1073 1074 /* 1075 * Determine how much room we have for pci_conf structures. 1076 * Round the user's buffer size down to the nearest 1077 * multiple of sizeof(struct pci_conf) in case the user 1078 * didn't specify a multiple of that size. 1079 */ 1080 iolen = min(cio->match_buf_len - 1081 (cio->match_buf_len % sizeof(struct pci_conf)), 1082 pci_numdevs * sizeof(struct pci_conf)); 1083 1084 /* 1085 * Since we know that iolen is a multiple of the size of 1086 * the pciconf union, it's okay to do this. 1087 */ 1088 ionum = iolen / sizeof(struct pci_conf); 1089 1090 /* 1091 * If this test is true, the user wants the pci_conf 1092 * structures returned to match the supplied entries. 1093 */ 1094 if ((cio->num_patterns > 0) 1095 && (cio->pat_buf_len > 0)) { 1096 /* 1097 * pat_buf_len needs to be: 1098 * num_patterns * sizeof(struct pci_match_conf) 1099 * While it is certainly possible the user just 1100 * allocated a large buffer, but set the number of 1101 * matches correctly, it is far more likely that 1102 * their kernel doesn't match the userland utility 1103 * they're using. It's also possible that the user 1104 * forgot to initialize some variables. Yes, this 1105 * may be overly picky, but I hazard to guess that 1106 * it's far more likely to just catch folks that 1107 * updated their kernel but not their userland. 1108 */ 1109 if ((cio->num_patterns * 1110 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 1111 /* The user made a mistake, return an error*/ 1112 cio->status = PCI_GETCONF_ERROR; 1113 kprintf("pci_ioctl: pat_buf_len %d != " 1114 "num_patterns (%d) * sizeof(struct " 1115 "pci_match_conf) (%d)\npci_ioctl: " 1116 "pat_buf_len should be = %d\n", 1117 cio->pat_buf_len, cio->num_patterns, 1118 (int)sizeof(struct pci_match_conf), 1119 (int)sizeof(struct pci_match_conf) * 1120 cio->num_patterns); 1121 kprintf("pci_ioctl: do your headers match your " 1122 "kernel?\n"); 1123 cio->num_matches = 0; 1124 error = EINVAL; 1125 break; 1126 } 1127 1128 /* 1129 * Check the user's buffer to make sure it's readable. 1130 */ 1131 if (!useracc((caddr_t)cio->patterns, 1132 cio->pat_buf_len, VM_PROT_READ)) { 1133 kprintf("pci_ioctl: pattern buffer %p, " 1134 "length %u isn't user accessible for" 1135 " READ\n", cio->patterns, 1136 cio->pat_buf_len); 1137 error = EACCES; 1138 break; 1139 } 1140 /* 1141 * Allocate a buffer to hold the patterns. 1142 */ 1143 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP, 1144 M_WAITOK); 1145 error = copyin(cio->patterns, pattern_buf, 1146 cio->pat_buf_len); 1147 if (error != 0) 1148 break; 1149 num_patterns = cio->num_patterns; 1150 1151 } else if ((cio->num_patterns > 0) 1152 || (cio->pat_buf_len > 0)) { 1153 /* 1154 * The user made a mistake, spit out an error. 1155 */ 1156 cio->status = PCI_GETCONF_ERROR; 1157 cio->num_matches = 0; 1158 kprintf("pci_ioctl: invalid GETCONF arguments\n"); 1159 error = EINVAL; 1160 break; 1161 } else 1162 pattern_buf = NULL; 1163 1164 /* 1165 * Make sure we can write to the match buffer. 1166 */ 1167 if (!useracc((caddr_t)cio->matches, 1168 cio->match_buf_len, VM_PROT_WRITE)) { 1169 kprintf("pci_ioctl: match buffer %p, length %u " 1170 "isn't user accessible for WRITE\n", 1171 cio->matches, cio->match_buf_len); 1172 error = EACCES; 1173 break; 1174 } 1175 1176 /* 1177 * Go through the list of devices and copy out the devices 1178 * that match the user's criteria. 1179 */ 1180 for (cio->num_matches = 0, error = 0, i = 0, 1181 dinfo = STAILQ_FIRST(devlist_head); 1182 (dinfo != NULL) && (cio->num_matches < ionum) 1183 && (error == 0) && (i < pci_numdevs); 1184 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1185 1186 if (i < cio->offset) 1187 continue; 1188 1189 /* Populate pd_name and pd_unit */ 1190 name = NULL; 1191 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 1192 name = device_get_name(dinfo->cfg.dev); 1193 if (name) { 1194 strncpy(dinfo->conf.pd_name, name, 1195 sizeof(dinfo->conf.pd_name)); 1196 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 1197 dinfo->conf.pd_unit = 1198 device_get_unit(dinfo->cfg.dev); 1199 } 1200 1201 if ((pattern_buf == NULL) || 1202 (pci_conf_match(pattern_buf, num_patterns, 1203 &dinfo->conf) == 0)) { 1204 1205 /* 1206 * If we've filled up the user's buffer, 1207 * break out at this point. Since we've 1208 * got a match here, we'll pick right back 1209 * up at the matching entry. We can also 1210 * tell the user that there are more matches 1211 * left. 1212 */ 1213 if (cio->num_matches >= ionum) 1214 break; 1215 1216 error = copyout(&dinfo->conf, 1217 &cio->matches[cio->num_matches], 1218 sizeof(struct pci_conf)); 1219 cio->num_matches++; 1220 } 1221 } 1222 1223 /* 1224 * Set the pointer into the list, so if the user is getting 1225 * n records at a time, where n < pci_numdevs, 1226 */ 1227 cio->offset = i; 1228 1229 /* 1230 * Set the generation, the user will need this if they make 1231 * another ioctl call with offset != 0. 1232 */ 1233 cio->generation = pci_generation; 1234 1235 /* 1236 * If this is the last device, inform the user so he won't 1237 * bother asking for more devices. If dinfo isn't NULL, we 1238 * know that there are more matches in the list because of 1239 * the way the traversal is done. 1240 */ 1241 if (dinfo == NULL) 1242 cio->status = PCI_GETCONF_LAST_DEVICE; 1243 else 1244 cio->status = PCI_GETCONF_MORE_DEVS; 1245 1246 if (pattern_buf != NULL) 1247 kfree(pattern_buf, M_TEMP); 1248 1249 break; 1250 } 1251 case PCIOCREAD: 1252 io = (struct pci_io *)ap->a_data; 1253 switch(io->pi_width) { 1254 case 4: 1255 case 2: 1256 case 1: 1257 /* 1258 * Assume that the user-level bus number is 1259 * actually the pciN instance number. We map 1260 * from that to the real pcib+bus combination. 1261 */ 1262 pci = devclass_get_device(pci_devclass, 1263 io->pi_sel.pc_bus); 1264 if (pci) { 1265 /* 1266 * pci is the pci device and may contain 1267 * several children (for each function code). 1268 * The governing pci bus is the parent to 1269 * the pci device. 1270 */ 1271 int b; 1272 1273 pcib = device_get_parent(pci); 1274 b = pcib_get_bus(pcib); 1275 io->pi_data = 1276 PCIB_READ_CONFIG(pcib, 1277 b, 1278 io->pi_sel.pc_dev, 1279 io->pi_sel.pc_func, 1280 io->pi_reg, 1281 io->pi_width); 1282 error = 0; 1283 } else { 1284 error = ENODEV; 1285 } 1286 break; 1287 default: 1288 error = ENODEV; 1289 break; 1290 } 1291 break; 1292 1293 case PCIOCWRITE: 1294 io = (struct pci_io *)ap->a_data; 1295 switch(io->pi_width) { 1296 case 4: 1297 case 2: 1298 case 1: 1299 /* 1300 * Assume that the user-level bus number is 1301 * actually the pciN instance number. We map 1302 * from that to the real pcib+bus combination. 1303 */ 1304 pci = devclass_get_device(pci_devclass, 1305 io->pi_sel.pc_bus); 1306 if (pci) { 1307 /* 1308 * pci is the pci device and may contain 1309 * several children (for each function code). 1310 * The governing pci bus is the parent to 1311 * the pci device. 1312 */ 1313 int b; 1314 1315 pcib = device_get_parent(pci); 1316 b = pcib_get_bus(pcib); 1317 PCIB_WRITE_CONFIG(pcib, 1318 b, 1319 io->pi_sel.pc_dev, 1320 io->pi_sel.pc_func, 1321 io->pi_reg, 1322 io->pi_data, 1323 io->pi_width); 1324 error = 0; 1325 } else { 1326 error = ENODEV; 1327 } 1328 break; 1329 default: 1330 error = ENODEV; 1331 break; 1332 } 1333 break; 1334 1335 default: 1336 error = ENOTTY; 1337 break; 1338 } 1339 1340 return (error); 1341 } 1342 1343 #define PCI_CDEV 78 1344 1345 static struct dev_ops pcic_ops = { 1346 { "pci", PCI_CDEV, 0 }, 1347 .d_open = pci_open, 1348 .d_close = pci_close, 1349 .d_ioctl = pci_ioctl, 1350 }; 1351 1352 #include "pci_if.h" 1353 1354 /* 1355 * New style pci driver. Parent device is either a pci-host-bridge or a 1356 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1357 */ 1358 const char * 1359 pci_class_to_string(int baseclass) 1360 { 1361 const char *name; 1362 1363 switch(baseclass) { 1364 case PCIC_OLD: 1365 name = "OLD"; 1366 break; 1367 case PCIC_STORAGE: 1368 name = "STORAGE"; 1369 break; 1370 case PCIC_NETWORK: 1371 name = "NETWORK"; 1372 break; 1373 case PCIC_DISPLAY: 1374 name = "DISPLAY"; 1375 break; 1376 case PCIC_MULTIMEDIA: 1377 name = "MULTIMEDIA"; 1378 break; 1379 case PCIC_MEMORY: 1380 name = "MEMORY"; 1381 break; 1382 case PCIC_BRIDGE: 1383 name = "BRIDGE"; 1384 break; 1385 case PCIC_SIMPLECOMM: 1386 name = "SIMPLECOMM"; 1387 break; 1388 case PCIC_BASEPERIPH: 1389 name = "BASEPERIPH"; 1390 break; 1391 case PCIC_INPUTDEV: 1392 name = "INPUTDEV"; 1393 break; 1394 case PCIC_DOCKING: 1395 name = "DOCKING"; 1396 break; 1397 case PCIC_PROCESSOR: 1398 name = "PROCESSOR"; 1399 break; 1400 case PCIC_SERIALBUS: 1401 name = "SERIALBUS"; 1402 break; 1403 case PCIC_WIRELESS: 1404 name = "WIRELESS"; 1405 break; 1406 case PCIC_I2O: 1407 name = "I20"; 1408 break; 1409 case PCIC_SATELLITE: 1410 name = "SATELLITE"; 1411 break; 1412 case PCIC_CRYPTO: 1413 name = "CRYPTO"; 1414 break; 1415 case PCIC_SIGPROC: 1416 name = "SIGPROC"; 1417 break; 1418 case PCIC_OTHER: 1419 name = "OTHER"; 1420 break; 1421 default: 1422 name = "?"; 1423 break; 1424 } 1425 return(name); 1426 } 1427 1428 static void 1429 pci_print_verbose_expr(const pcicfgregs *cfg) 1430 { 1431 const struct pcicfg_expr *expr = &cfg->expr; 1432 const char *port_name; 1433 uint16_t port_type; 1434 1435 if (!bootverbose) 1436 return; 1437 1438 if (expr->expr_ptr == 0) /* No PCI Express capability */ 1439 return; 1440 1441 kprintf("\tPCI Express ver.%d cap=0x%04x", 1442 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap); 1443 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1) 1444 goto back; 1445 1446 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE; 1447 1448 switch (port_type) { 1449 case PCIE_END_POINT: 1450 port_name = "DEVICE"; 1451 break; 1452 case PCIE_LEG_END_POINT: 1453 port_name = "LEGDEV"; 1454 break; 1455 case PCIE_ROOT_PORT: 1456 port_name = "ROOT"; 1457 break; 1458 case PCIE_UP_STREAM_PORT: 1459 port_name = "UPSTREAM"; 1460 break; 1461 case PCIE_DOWN_STREAM_PORT: 1462 port_name = "DOWNSTRM"; 1463 break; 1464 case PCIE_PCIE2PCI_BRIDGE: 1465 port_name = "PCIE2PCI"; 1466 break; 1467 case PCIE_PCI2PCIE_BRIDGE: 1468 port_name = "PCI2PCIE"; 1469 break; 1470 default: 1471 port_name = NULL; 1472 break; 1473 } 1474 if ((port_type == PCIE_ROOT_PORT || 1475 port_type == PCIE_DOWN_STREAM_PORT) && 1476 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL)) 1477 port_name = NULL; 1478 if (port_name != NULL) 1479 kprintf("[%s]", port_name); 1480 1481 if (pcie_slotimpl(cfg)) { 1482 kprintf(", slotcap=0x%08x", expr->expr_slotcap); 1483 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP) 1484 kprintf("[HOTPLUG]"); 1485 } 1486 back: 1487 kprintf("\n"); 1488 } 1489 1490 void 1491 pci_print_verbose(struct pci_devinfo *dinfo) 1492 { 1493 if (bootverbose) { 1494 pcicfgregs *cfg = &dinfo->cfg; 1495 1496 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1497 cfg->vendor, cfg->device, cfg->revid); 1498 kprintf("\tbus=%d, slot=%d, func=%d\n", 1499 cfg->bus, cfg->slot, cfg->func); 1500 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1501 pci_class_to_string(cfg->baseclass), 1502 cfg->baseclass, cfg->subclass, cfg->progif, 1503 cfg->hdrtype, cfg->mfdev); 1504 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n", 1505 cfg->subordinatebus, cfg->secondarybus); 1506 #ifdef PCI_DEBUG 1507 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1508 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1509 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1510 cfg->lattimer, cfg->lattimer * 30, 1511 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1512 #endif /* PCI_DEBUG */ 1513 if (cfg->intpin > 0) 1514 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 1515 1516 pci_print_verbose_expr(cfg); 1517 } 1518 } 1519 1520 static int 1521 pci_porten(device_t pcib, int b, int s, int f) 1522 { 1523 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1524 & PCIM_CMD_PORTEN) != 0; 1525 } 1526 1527 static int 1528 pci_memen(device_t pcib, int b, int s, int f) 1529 { 1530 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1531 & PCIM_CMD_MEMEN) != 0; 1532 } 1533 1534 /* 1535 * Add a resource based on a pci map register. Return 1 if the map 1536 * register is a 32bit map register or 2 if it is a 64bit register. 1537 */ 1538 static int 1539 pci_add_map(device_t pcib, int b, int s, int f, int reg, 1540 struct resource_list *rl) 1541 { 1542 u_int32_t map; 1543 u_int64_t base; 1544 u_int8_t ln2size; 1545 u_int8_t ln2range; 1546 u_int32_t testval; 1547 1548 1549 #ifdef PCI_ENABLE_IO_MODES 1550 u_int16_t cmd; 1551 #endif 1552 int type; 1553 1554 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1555 1556 if (map == 0 || map == 0xffffffff) 1557 return 1; /* skip invalid entry */ 1558 1559 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1560 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1561 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1562 1563 base = pci_mapbase(map); 1564 if (pci_maptype(map) & PCI_MAPMEM) 1565 type = SYS_RES_MEMORY; 1566 else 1567 type = SYS_RES_IOPORT; 1568 ln2size = pci_mapsize(testval); 1569 ln2range = pci_maprange(testval); 1570 if (ln2range == 64) { 1571 /* Read the other half of a 64bit map register */ 1572 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4); 1573 } 1574 1575 /* 1576 * This code theoretically does the right thing, but has 1577 * undesirable side effects in some cases where 1578 * peripherals respond oddly to having these bits 1579 * enabled. Leave them alone by default. 1580 */ 1581 #ifdef PCI_ENABLE_IO_MODES 1582 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1583 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1584 cmd |= PCIM_CMD_PORTEN; 1585 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1586 } 1587 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1588 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1589 cmd |= PCIM_CMD_MEMEN; 1590 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1591 } 1592 #else 1593 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1594 return 1; 1595 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1596 return 1; 1597 #endif 1598 1599 resource_list_add(rl, type, reg, 1600 base, base + (1 << ln2size) - 1, 1601 (1 << ln2size)); 1602 1603 if (bootverbose) { 1604 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n", 1605 reg, pci_maptype(base), ln2range, 1606 (unsigned int) base, ln2size); 1607 } 1608 1609 return (ln2range == 64) ? 2 : 1; 1610 } 1611 1612 #ifdef PCI_MAP_FIXUP 1613 /* 1614 * For ATA devices we need to decide early on what addressing mode to use. 1615 * Legacy demands that the primary and secondary ATA ports sits on the 1616 * same addresses that old ISA hardware did. This dictates that we use 1617 * those addresses and ignore the BARs if we cannot set PCI native 1618 * addressing mode. 1619 */ 1620 static void 1621 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f, 1622 struct resource_list *rl) 1623 { 1624 int rid, type, progif; 1625 #if 0 1626 /* if this device supports PCI native addressing use it */ 1627 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1628 if ((progif &0x8a) == 0x8a) { 1629 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 1630 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 1631 kprintf("Trying ATA native PCI addressing mode\n"); 1632 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 1633 } 1634 } 1635 #endif 1636 /* 1637 * Because we return any preallocated resources for lazy 1638 * allocation for PCI devices in pci_alloc_resource(), we can 1639 * allocate our legacy resources here. 1640 */ 1641 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1642 type = SYS_RES_IOPORT; 1643 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 1644 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl); 1645 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl); 1646 } else { 1647 rid = PCIR_BAR(0); 1648 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 1649 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 1650 0); 1651 rid = PCIR_BAR(1); 1652 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 1653 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 1654 0); 1655 } 1656 if (progif & PCIP_STORAGE_IDE_MODESEC) { 1657 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl); 1658 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl); 1659 } else { 1660 rid = PCIR_BAR(2); 1661 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 1662 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 1663 0); 1664 rid = PCIR_BAR(3); 1665 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1666 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1667 0); 1668 } 1669 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl); 1670 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl); 1671 } 1672 #endif /* PCI_MAP_FIXUP */ 1673 1674 static void 1675 pci_add_resources(device_t pcib, device_t bus, device_t dev) 1676 { 1677 struct pci_devinfo *dinfo = device_get_ivars(dev); 1678 pcicfgregs *cfg = &dinfo->cfg; 1679 struct resource_list *rl = &dinfo->resources; 1680 struct pci_quirk *q; 1681 int b, i, f, s; 1682 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */ 1683 int irq; 1684 #endif 1685 1686 b = cfg->bus; 1687 s = cfg->slot; 1688 f = cfg->func; 1689 #ifdef PCI_MAP_FIXUP 1690 /* atapci devices in legacy mode need special map treatment */ 1691 if ((pci_get_class(dev) == PCIC_STORAGE) && 1692 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1693 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 1694 (!pci_read_config(dev, PCIR_BAR(0), 4) && 1695 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 1696 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 1697 else 1698 #endif /* PCI_MAP_FIXUP */ 1699 for (i = 0; i < cfg->nummaps;) { 1700 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl); 1701 } 1702 1703 for (q = &pci_quirks[0]; q->devid; q++) { 1704 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1705 && q->type == PCI_QUIRK_MAP_REG) 1706 pci_add_map(pcib, b, s, f, q->arg1, rl); 1707 } 1708 1709 if (cfg->intpin > 0 && cfg->intline != 255) 1710 resource_list_add(rl, SYS_RES_IRQ, 0, 1711 cfg->intline, cfg->intline, 1); 1712 } 1713 1714 void 1715 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1716 { 1717 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1718 device_t pcib = device_get_parent(dev); 1719 struct pci_devinfo *dinfo; 1720 int maxslots; 1721 int s, f, pcifunchigh; 1722 uint8_t hdrtype; 1723 1724 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo)); 1725 1726 maxslots = PCIB_MAXSLOTS(pcib); 1727 1728 for (s = 0; s <= maxslots; s++) { 1729 pcifunchigh = 0; 1730 f = 0; 1731 hdrtype = REG(PCIR_HDRTYPE, 1); 1732 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1733 continue; 1734 if (hdrtype & PCIM_MFDEV) 1735 pcifunchigh = PCI_FUNCMAX; 1736 for (f = 0; f <= pcifunchigh; f++) { 1737 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1738 if (dinfo != NULL) { 1739 pci_add_child(dev, dinfo); 1740 } 1741 } 1742 } 1743 #undef REG 1744 } 1745 1746 /* 1747 * The actual PCI child that we add has a NULL driver whos parent 1748 * device will be "pci". The child contains the ivars, not the parent. 1749 */ 1750 void 1751 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1752 { 1753 device_t pcib; 1754 1755 pcib = device_get_parent(bus); 1756 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1757 device_set_ivars(dinfo->cfg.dev, dinfo); 1758 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1759 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1760 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1761 pci_print_verbose(dinfo); 1762 } 1763 1764 /* 1765 * Probe the PCI bus. Note: probe code is not supposed to add children 1766 * or call attach. 1767 */ 1768 static int 1769 pci_probe(device_t dev) 1770 { 1771 device_set_desc(dev, "PCI bus"); 1772 1773 /* Allow other subclasses to override this driver */ 1774 return(-1000); 1775 } 1776 1777 static int 1778 pci_attach(device_t dev) 1779 { 1780 int busno; 1781 int lunit = device_get_unit(dev); 1782 1783 dev_ops_add(&pcic_ops, -1, lunit); 1784 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit); 1785 1786 /* 1787 * Since there can be multiple independantly numbered PCI 1788 * busses on some large alpha systems, we can't use the unit 1789 * number to decide what bus we are probing. We ask the parent 1790 * pcib what our bus number is. 1791 * 1792 * pcib_get_bus() must act on the pci bus device, not on the pci 1793 * device, because it uses badly hacked nexus-based ivars to 1794 * store and retrieve the physical bus number. XXX 1795 */ 1796 busno = pcib_get_bus(device_get_parent(dev)); 1797 if (bootverbose) 1798 device_printf(dev, "pci_attach() physical bus=%d\n", busno); 1799 1800 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1801 1802 return (bus_generic_attach(dev)); 1803 } 1804 1805 static int 1806 pci_print_resources(struct resource_list *rl, const char *name, int type, 1807 const char *format) 1808 { 1809 struct resource_list_entry *rle; 1810 int printed, retval; 1811 1812 printed = 0; 1813 retval = 0; 1814 /* Yes, this is kinda cheating */ 1815 SLIST_FOREACH(rle, rl, link) { 1816 if (rle->type == type) { 1817 if (printed == 0) 1818 retval += kprintf(" %s ", name); 1819 else if (printed > 0) 1820 retval += kprintf(","); 1821 printed++; 1822 retval += kprintf(format, rle->start); 1823 if (rle->count > 1) { 1824 retval += kprintf("-"); 1825 retval += kprintf(format, rle->start + 1826 rle->count - 1); 1827 } 1828 } 1829 } 1830 return retval; 1831 } 1832 1833 int 1834 pci_print_child(device_t dev, device_t child) 1835 { 1836 struct pci_devinfo *dinfo; 1837 struct resource_list *rl; 1838 pcicfgregs *cfg; 1839 int retval = 0; 1840 1841 dinfo = device_get_ivars(child); 1842 cfg = &dinfo->cfg; 1843 rl = &dinfo->resources; 1844 1845 retval += bus_print_child_header(dev, child); 1846 1847 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 1848 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1849 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 1850 if (device_get_flags(dev)) 1851 retval += kprintf(" flags %#x", device_get_flags(dev)); 1852 1853 retval += kprintf(" at device %d.%d", pci_get_slot(child), 1854 pci_get_function(child)); 1855 1856 retval += bus_print_child_footer(dev, child); 1857 1858 return (retval); 1859 } 1860 1861 void 1862 pci_probe_nomatch(device_t dev, device_t child) 1863 { 1864 struct pci_devinfo *dinfo; 1865 pcicfgregs *cfg; 1866 const char *desc; 1867 int unknown; 1868 1869 unknown = 0; 1870 dinfo = device_get_ivars(child); 1871 cfg = &dinfo->cfg; 1872 desc = pci_ata_match(child); 1873 if (!desc) desc = pci_usb_match(child); 1874 if (!desc) desc = pci_vga_match(child); 1875 if (!desc) desc = pci_chip_match(child); 1876 if (!desc) { 1877 desc = "unknown card"; 1878 unknown++; 1879 } 1880 device_printf(dev, "<%s>", desc); 1881 if (bootverbose || unknown) { 1882 kprintf(" (vendor=0x%04x, dev=0x%04x)", 1883 cfg->vendor, 1884 cfg->device); 1885 } 1886 kprintf(" at %d.%d", 1887 pci_get_slot(child), 1888 pci_get_function(child)); 1889 if (cfg->intpin > 0 && cfg->intline != 255) { 1890 kprintf(" irq %d", cfg->intline); 1891 } 1892 kprintf("\n"); 1893 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1); 1894 1895 return; 1896 } 1897 1898 int 1899 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1900 { 1901 struct pci_devinfo *dinfo; 1902 pcicfgregs *cfg; 1903 1904 dinfo = device_get_ivars(child); 1905 cfg = &dinfo->cfg; 1906 1907 switch (which) { 1908 case PCI_IVAR_SUBVENDOR: 1909 *result = cfg->subvendor; 1910 break; 1911 case PCI_IVAR_SUBDEVICE: 1912 *result = cfg->subdevice; 1913 break; 1914 case PCI_IVAR_VENDOR: 1915 *result = cfg->vendor; 1916 break; 1917 case PCI_IVAR_DEVICE: 1918 *result = cfg->device; 1919 break; 1920 case PCI_IVAR_DEVID: 1921 *result = (cfg->device << 16) | cfg->vendor; 1922 break; 1923 case PCI_IVAR_CLASS: 1924 *result = cfg->baseclass; 1925 break; 1926 case PCI_IVAR_SUBCLASS: 1927 *result = cfg->subclass; 1928 break; 1929 case PCI_IVAR_PROGIF: 1930 *result = cfg->progif; 1931 break; 1932 case PCI_IVAR_REVID: 1933 *result = cfg->revid; 1934 break; 1935 case PCI_IVAR_INTPIN: 1936 *result = cfg->intpin; 1937 break; 1938 case PCI_IVAR_IRQ: 1939 *result = cfg->intline; 1940 break; 1941 case PCI_IVAR_BUS: 1942 *result = cfg->bus; 1943 break; 1944 case PCI_IVAR_SLOT: 1945 *result = cfg->slot; 1946 break; 1947 case PCI_IVAR_FUNCTION: 1948 *result = cfg->func; 1949 break; 1950 case PCI_IVAR_SECONDARYBUS: 1951 *result = cfg->secondarybus; 1952 break; 1953 case PCI_IVAR_SUBORDINATEBUS: 1954 *result = cfg->subordinatebus; 1955 break; 1956 case PCI_IVAR_ETHADDR: 1957 /* 1958 * The generic accessor doesn't deal with failure, so 1959 * we set the return value, then return an error. 1960 */ 1961 *result = 0; 1962 return (EINVAL); 1963 case PCI_IVAR_PCIXCAP_PTR: 1964 *result = cfg->pcixcap_ptr; 1965 break; 1966 case PCI_IVAR_PCIECAP_PTR: 1967 *result = cfg->expr.expr_ptr; 1968 break; 1969 default: 1970 return ENOENT; 1971 } 1972 return 0; 1973 } 1974 1975 int 1976 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1977 { 1978 struct pci_devinfo *dinfo; 1979 pcicfgregs *cfg; 1980 1981 dinfo = device_get_ivars(child); 1982 cfg = &dinfo->cfg; 1983 1984 switch (which) { 1985 case PCI_IVAR_SUBVENDOR: 1986 case PCI_IVAR_SUBDEVICE: 1987 case PCI_IVAR_VENDOR: 1988 case PCI_IVAR_DEVICE: 1989 case PCI_IVAR_DEVID: 1990 case PCI_IVAR_CLASS: 1991 case PCI_IVAR_SUBCLASS: 1992 case PCI_IVAR_PROGIF: 1993 case PCI_IVAR_REVID: 1994 case PCI_IVAR_INTPIN: 1995 case PCI_IVAR_IRQ: 1996 case PCI_IVAR_BUS: 1997 case PCI_IVAR_SLOT: 1998 case PCI_IVAR_FUNCTION: 1999 case PCI_IVAR_ETHADDR: 2000 case PCI_IVAR_PCIXCAP_PTR: 2001 case PCI_IVAR_PCIECAP_PTR: 2002 return EINVAL; /* disallow for now */ 2003 2004 case PCI_IVAR_SECONDARYBUS: 2005 cfg->secondarybus = value; 2006 break; 2007 case PCI_IVAR_SUBORDINATEBUS: 2008 cfg->subordinatebus = value; 2009 break; 2010 default: 2011 return ENOENT; 2012 } 2013 return 0; 2014 } 2015 2016 #ifdef PCI_MAP_FIXUP 2017 static struct resource * 2018 pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start, 2019 u_long end, u_long count, u_int flags) 2020 { 2021 struct pci_devinfo *dinfo = device_get_ivars(child); 2022 struct resource_list *rl = &dinfo->resources; 2023 struct resource_list_entry *rle; 2024 struct resource *res; 2025 uint32_t map, testval; 2026 int mapsize; 2027 2028 /* 2029 * Weed out the bogons, and figure out how large the BAR/map 2030 * is. BARs that read back 0 here are bogus and unimplemented. 2031 * 2032 * Note: atapci in legacy mode are special and handled elsewhere 2033 * in the code. If you have an atapci device in legacy mode and 2034 * it fails here, that other code is broken. 2035 */ 2036 res = NULL; 2037 map = pci_read_config(child, *rid, 4); 2038 pci_write_config(child, *rid, 0xffffffff, 4); 2039 testval = pci_read_config(child, *rid, 4); 2040 if (pci_mapbase(testval) == 0) 2041 goto out; 2042 if (pci_maptype(testval) & PCI_MAPMEM) { 2043 if (type != SYS_RES_MEMORY) { 2044 if (bootverbose) 2045 device_printf(dev, "child %s requested type %d" 2046 " for rid %#x, but the BAR says " 2047 "it is a memio\n", 2048 device_get_nameunit(child), type, 2049 *rid); 2050 goto out; 2051 } 2052 } else { 2053 if (type != SYS_RES_IOPORT) { 2054 if (bootverbose) 2055 device_printf(dev, "child %s requested type %d" 2056 " for rid %#x, but the BAR says " 2057 "it is an ioport\n", 2058 device_get_nameunit(child), type, 2059 *rid); 2060 goto out; 2061 } 2062 } 2063 /* 2064 * For real BARs, we need to override the size that 2065 * the driver requests, because that's what the BAR 2066 * actually uses and we would otherwise have a 2067 * situation where we might allocate the excess to 2068 * another driver, which won't work. 2069 */ 2070 mapsize = pci_mapsize(testval); 2071 count = 1 << mapsize; 2072 if (RF_ALIGNMENT(flags) < mapsize) 2073 flags = (flags & ~RF_ALIGNMENT_MASK) | 2074 RF_ALIGNMENT_LOG2(mapsize); 2075 /* 2076 * Allocate enough resource, and then write back the 2077 * appropriate BAR for that resource. 2078 */ 2079 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 2080 start, end, count, flags); 2081 if (res == NULL) { 2082 device_printf(child, "%#lx bytes at rid %#x res %d failed " 2083 "(%#lx, %#lx)\n", count, *rid, type, start, end); 2084 goto out; 2085 } 2086 resource_list_add(rl, type, *rid, start, end, count); 2087 rle = resource_list_find(rl, type, *rid); 2088 if (rle == NULL) 2089 panic("pci_alloc_map: unexpectedly can't find resource."); 2090 rle->res = res; 2091 rle->start = rman_get_start(res); 2092 rle->end = rman_get_end(res); 2093 rle->count = count; 2094 if (bootverbose) 2095 device_printf(child, "lazy allocation of %#lx bytes rid %#x " 2096 "type %d at %#lx\n", count, *rid, type, 2097 rman_get_start(res)); 2098 map = rman_get_start(res); 2099 out:; 2100 pci_write_config(child, *rid, map, 4); 2101 return res; 2102 } 2103 #endif /* PCI_MAP_FIXUP */ 2104 2105 struct resource * 2106 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 2107 u_long start, u_long end, u_long count, u_int flags) 2108 { 2109 struct pci_devinfo *dinfo = device_get_ivars(child); 2110 struct resource_list *rl = &dinfo->resources; 2111 #ifdef PCI_MAP_FIXUP 2112 struct resource_list_entry *rle; 2113 #endif /* PCI_MAP_FIXUP */ 2114 pcicfgregs *cfg = &dinfo->cfg; 2115 2116 /* 2117 * Perform lazy resource allocation 2118 */ 2119 if (device_get_parent(child) == dev) { 2120 switch (type) { 2121 case SYS_RES_IRQ: 2122 #ifdef __i386__ 2123 /* 2124 * If device doesn't have an interrupt routed, and is 2125 * deserving of an interrupt, try to assign it one. 2126 */ 2127 if ((cfg->intline == 255 || cfg->intline == 0) && 2128 (cfg->intpin != 0) && 2129 (start == 0) && (end == ~0UL)) { 2130 cfg->intline = PCIB_ROUTE_INTERRUPT( 2131 device_get_parent(dev), child, 2132 cfg->intpin); 2133 if (cfg->intline != 255) { 2134 pci_write_config(child, PCIR_INTLINE, 2135 cfg->intline, 1); 2136 resource_list_add(rl, SYS_RES_IRQ, 0, 2137 cfg->intline, cfg->intline, 1); 2138 } 2139 } 2140 break; 2141 #endif 2142 case SYS_RES_IOPORT: 2143 /* FALLTHROUGH */ 2144 case SYS_RES_MEMORY: 2145 if (*rid < PCIR_BAR(cfg->nummaps)) { 2146 /* 2147 * Enable the I/O mode. We should 2148 * also be assigning resources too 2149 * when none are present. The 2150 * resource_list_alloc kind of sorta does 2151 * this... 2152 */ 2153 if (PCI_ENABLE_IO(dev, child, type)) 2154 return (NULL); 2155 } 2156 #ifdef PCI_MAP_FIXUP 2157 rle = resource_list_find(rl, type, *rid); 2158 if (rle == NULL) 2159 return pci_alloc_map(dev, child, type, rid, 2160 start, end, count, flags); 2161 #endif /* PCI_MAP_FIXUP */ 2162 break; 2163 } 2164 #ifdef PCI_MAP_FIXUP 2165 /* 2166 * If we've already allocated the resource, then 2167 * return it now. But first we may need to activate 2168 * it, since we don't allocate the resource as active 2169 * above. Normally this would be done down in the 2170 * nexus, but since we short-circuit that path we have 2171 * to do its job here. Not sure if we should free the 2172 * resource if it fails to activate. 2173 * 2174 * Note: this also finds and returns resources for 2175 * atapci devices in legacy mode as allocated in 2176 * pci_ata_maps(). 2177 */ 2178 rle = resource_list_find(rl, type, *rid); 2179 if (rle != NULL && rle->res != NULL) { 2180 if (bootverbose) 2181 device_printf(child, "reserved %#lx bytes for " 2182 "rid %#x type %d at %#lx\n", 2183 rman_get_size(rle->res), *rid, 2184 type, rman_get_start(rle->res)); 2185 if ((flags & RF_ACTIVE) && 2186 bus_generic_activate_resource(dev, child, type, 2187 *rid, rle->res) != 0) 2188 return NULL; 2189 return rle->res; 2190 } 2191 #endif /* PCI_MAP_FIXUP */ 2192 } 2193 return resource_list_alloc(rl, dev, child, type, rid, 2194 start, end, count, flags); 2195 } 2196 2197 static int 2198 pci_release_resource(device_t dev, device_t child, int type, int rid, 2199 struct resource *r) 2200 { 2201 struct pci_devinfo *dinfo = device_get_ivars(child); 2202 struct resource_list *rl = &dinfo->resources; 2203 2204 return resource_list_release(rl, dev, child, type, rid, r); 2205 } 2206 2207 static int 2208 pci_set_resource(device_t dev, device_t child, int type, int rid, 2209 u_long start, u_long count) 2210 { 2211 struct pci_devinfo *dinfo = device_get_ivars(child); 2212 struct resource_list *rl = &dinfo->resources; 2213 2214 resource_list_add(rl, type, rid, start, start + count - 1, count); 2215 return 0; 2216 } 2217 2218 static int 2219 pci_get_resource(device_t dev, device_t child, int type, int rid, 2220 u_long *startp, u_long *countp) 2221 { 2222 struct pci_devinfo *dinfo = device_get_ivars(child); 2223 struct resource_list *rl = &dinfo->resources; 2224 struct resource_list_entry *rle; 2225 2226 rle = resource_list_find(rl, type, rid); 2227 if (!rle) 2228 return ENOENT; 2229 2230 if (startp) 2231 *startp = rle->start; 2232 if (countp) 2233 *countp = rle->count; 2234 2235 return 0; 2236 } 2237 2238 void 2239 pci_delete_resource(device_t dev, device_t child, int type, int rid) 2240 { 2241 kprintf("pci_delete_resource: PCI resources can not be deleted\n"); 2242 } 2243 2244 struct resource_list * 2245 pci_get_resource_list (device_t dev, device_t child) 2246 { 2247 struct pci_devinfo *dinfo = device_get_ivars(child); 2248 2249 if (dinfo == NULL) 2250 return (NULL); 2251 return (&dinfo->resources); 2252 } 2253 2254 u_int32_t 2255 pci_read_config_method(device_t dev, device_t child, int reg, int width) 2256 { 2257 struct pci_devinfo *dinfo = device_get_ivars(child); 2258 pcicfgregs *cfg = &dinfo->cfg; 2259 2260 return PCIB_READ_CONFIG(device_get_parent(dev), 2261 cfg->bus, cfg->slot, cfg->func, 2262 reg, width); 2263 } 2264 2265 void 2266 pci_write_config_method(device_t dev, device_t child, int reg, 2267 u_int32_t val, int width) 2268 { 2269 struct pci_devinfo *dinfo = device_get_ivars(child); 2270 pcicfgregs *cfg = &dinfo->cfg; 2271 2272 PCIB_WRITE_CONFIG(device_get_parent(dev), 2273 cfg->bus, cfg->slot, cfg->func, 2274 reg, val, width); 2275 } 2276 2277 int 2278 pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 2279 size_t buflen) 2280 { 2281 struct pci_devinfo *dinfo; 2282 2283 dinfo = device_get_ivars(child); 2284 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 2285 pci_get_function(child)); 2286 return (0); 2287 } 2288 2289 int 2290 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 2291 size_t buflen) 2292 { 2293 struct pci_devinfo *dinfo; 2294 pcicfgregs *cfg; 2295 2296 dinfo = device_get_ivars(child); 2297 cfg = &dinfo->cfg; 2298 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 2299 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 2300 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 2301 cfg->progif); 2302 return (0); 2303 } 2304 2305 int 2306 pci_assign_interrupt_method(device_t dev, device_t child) 2307 { 2308 struct pci_devinfo *dinfo = device_get_ivars(child); 2309 pcicfgregs *cfg = &dinfo->cfg; 2310 2311 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2312 cfg->intpin)); 2313 } 2314 2315 static int 2316 pci_modevent(module_t mod, int what, void *arg) 2317 { 2318 switch (what) { 2319 case MOD_LOAD: 2320 STAILQ_INIT(&pci_devq); 2321 break; 2322 case MOD_UNLOAD: 2323 break; 2324 } 2325 2326 return 0; 2327 } 2328 2329 void 2330 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 2331 { 2332 int i; 2333 2334 /* 2335 * Only do header type 0 devices. Type 1 devices are bridges, 2336 * which we know need special treatment. Type 2 devices are 2337 * cardbus bridges which also require special treatment. 2338 * Other types are unknown, and we err on the side of safety 2339 * by ignoring them. 2340 */ 2341 if (dinfo->cfg.hdrtype != 0) 2342 return; 2343 2344 /* 2345 * Restore the device to full power mode. We must do this 2346 * before we restore the registers because moving from D3 to 2347 * D0 will cause the chip's BARs and some other registers to 2348 * be reset to some unknown power on reset values. Cut down 2349 * the noise on boot by doing nothing if we are already in 2350 * state D0. 2351 */ 2352 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2353 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2354 } 2355 for (i = 0; i < dinfo->cfg.nummaps; i++) 2356 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 2357 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 2358 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 2359 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 2360 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 2361 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 2362 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 2363 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 2364 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 2365 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 2366 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 2367 #if 0 2368 /* Restore MSI and MSI-X configurations if they are present. */ 2369 if (dinfo->cfg.msi.msi_location != 0) 2370 pci_resume_msi(dev); 2371 if (dinfo->cfg.msix.msix_location != 0) 2372 pci_resume_msix(dev); 2373 #endif 2374 } 2375 2376 void 2377 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 2378 { 2379 int i; 2380 uint32_t cls; 2381 int ps; 2382 2383 /* 2384 * Only do header type 0 devices. Type 1 devices are bridges, which 2385 * we know need special treatment. Type 2 devices are cardbus bridges 2386 * which also require special treatment. Other types are unknown, and 2387 * we err on the side of safety by ignoring them. Powering down 2388 * bridges should not be undertaken lightly. 2389 */ 2390 if (dinfo->cfg.hdrtype != 0) 2391 return; 2392 for (i = 0; i < dinfo->cfg.nummaps; i++) 2393 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2394 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2395 2396 /* 2397 * Some drivers apparently write to these registers w/o updating our 2398 * cached copy. No harm happens if we update the copy, so do so here 2399 * so we can restore them. The COMMAND register is modified by the 2400 * bus w/o updating the cache. This should represent the normally 2401 * writable portion of the 'defined' part of type 0 headers. In 2402 * theory we also need to save/restore the PCI capability structures 2403 * we know about, but apart from power we don't know any that are 2404 * writable. 2405 */ 2406 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2407 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2408 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 2409 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 2410 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 2411 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 2412 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 2413 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 2414 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 2415 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2416 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2417 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2418 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2419 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2420 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2421 2422 /* 2423 * don't set the state for display devices, base peripherals and 2424 * memory devices since bad things happen when they are powered down. 2425 * We should (a) have drivers that can easily detach and (b) use 2426 * generic drivers for these devices so that some device actually 2427 * attaches. We need to make sure that when we implement (a) we don't 2428 * power the device down on a reattach. 2429 */ 2430 cls = pci_get_class(dev); 2431 if (!setstate) 2432 return; 2433 2434 switch (pci_do_power_nodriver) 2435 { 2436 case 0: /* NO powerdown at all */ 2437 return; 2438 case 1: /* Conservative about what to power down */ 2439 if (cls == PCIC_STORAGE) 2440 return; 2441 /*FALLTHROUGH*/ 2442 case 2: /* Agressive about what to power down */ 2443 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2444 cls == PCIC_BASEPERIPH) 2445 return; 2446 /*FALLTHROUGH*/ 2447 case 3: /* Power down everything */ 2448 break; 2449 } 2450 2451 if (cls == PCIC_STORAGE) 2452 return; 2453 2454 /* 2455 * PCI spec says we can only go into D3 state from D0 state. 2456 * Transition from D[12] into D0 before going to D3 state. 2457 */ 2458 ps = pci_get_powerstate(dev); 2459 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2460 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2461 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2462 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2463 } 2464 2465 int 2466 pci_resume(device_t dev) 2467 { 2468 int numdevs; 2469 int i; 2470 device_t *children; 2471 device_t child; 2472 struct pci_devinfo *dinfo; 2473 pcicfgregs *cfg; 2474 2475 device_get_children(dev, &children, &numdevs); 2476 2477 for (i = 0; i < numdevs; i++) { 2478 child = children[i]; 2479 2480 dinfo = device_get_ivars(child); 2481 cfg = &dinfo->cfg; 2482 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 2483 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 2484 if (PCI_INTERRUPT_VALID(cfg->intline)) { 2485 pci_write_config(child, PCIR_INTLINE, 2486 cfg->intline, 1); 2487 } 2488 } 2489 } 2490 2491 kfree(children, M_TEMP); 2492 2493 return (bus_generic_resume(dev)); 2494 } 2495 2496 void 2497 pci_driver_added(device_t dev, driver_t *driver) 2498 { 2499 int numdevs; 2500 device_t *devlist; 2501 device_t child; 2502 struct pci_devinfo *dinfo; 2503 int i; 2504 2505 if (bootverbose) 2506 device_printf(dev, "driver added\n"); 2507 DEVICE_IDENTIFY(driver, dev); 2508 device_get_children(dev, &devlist, &numdevs); 2509 for (i = 0; i < numdevs; i++) { 2510 child = devlist[i]; 2511 if (device_get_state(child) != DS_NOTPRESENT) 2512 continue; 2513 dinfo = device_get_ivars(child); 2514 pci_print_verbose(dinfo); 2515 if (bootverbose) 2516 kprintf("pci%d:%d:%d: reprobing on driver added\n", 2517 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 2518 pci_cfg_restore(child, dinfo); 2519 if (device_probe_and_attach(child) != 0) 2520 pci_cfg_save(child, dinfo, 1); 2521 } 2522 kfree(devlist, M_TEMP); 2523 } 2524 2525 static void 2526 pci_child_detached(device_t parent __unused, device_t child) { 2527 /* Turn child's power off */ 2528 pci_cfg_save(child, device_get_ivars(child), 1); 2529 } 2530 2531 static device_method_t pci_methods[] = { 2532 /* Device interface */ 2533 DEVMETHOD(device_probe, pci_probe), 2534 DEVMETHOD(device_attach, pci_attach), 2535 DEVMETHOD(device_shutdown, bus_generic_shutdown), 2536 DEVMETHOD(device_suspend, bus_generic_suspend), 2537 DEVMETHOD(device_resume, pci_resume), 2538 2539 /* Bus interface */ 2540 DEVMETHOD(bus_print_child, pci_print_child), 2541 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 2542 DEVMETHOD(bus_read_ivar, pci_read_ivar), 2543 DEVMETHOD(bus_write_ivar, pci_write_ivar), 2544 DEVMETHOD(bus_driver_added, pci_driver_added), 2545 DEVMETHOD(bus_child_detached, pci_child_detached), 2546 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 2547 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 2548 2549 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 2550 DEVMETHOD(bus_set_resource, pci_set_resource), 2551 DEVMETHOD(bus_get_resource, pci_get_resource), 2552 DEVMETHOD(bus_delete_resource, pci_delete_resource), 2553 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 2554 DEVMETHOD(bus_release_resource, pci_release_resource), 2555 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 2556 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 2557 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 2558 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 2559 2560 /* PCI interface */ 2561 DEVMETHOD(pci_read_config, pci_read_config_method), 2562 DEVMETHOD(pci_write_config, pci_write_config_method), 2563 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 2564 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 2565 DEVMETHOD(pci_enable_io, pci_enable_io_method), 2566 DEVMETHOD(pci_disable_io, pci_disable_io_method), 2567 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 2568 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 2569 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 2570 2571 { 0, 0 } 2572 }; 2573 2574 driver_t pci_driver = { 2575 "pci", 2576 pci_methods, 2577 1, /* no softc */ 2578 }; 2579 2580 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 2581 MODULE_VERSION(pci, 1); 2582