1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $ 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.37 2007/02/11 01:51:28 swildner Exp $ 28 * 29 */ 30 31 #include "opt_bus.h" 32 #include "opt_pci.h" 33 34 #include "opt_compat_oldpci.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/fcntl.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/queue.h> 44 #include <sys/types.h> 45 #include <sys/buf.h> 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 #include <vm/vm_extern.h> 50 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <machine/smp.h> 54 #ifdef __i386__ 55 #include <bus/pci/i386/pci_cfgreg.h> 56 #endif 57 58 #include <sys/pciio.h> 59 #include "pcireg.h" 60 #include "pcivar.h" 61 #include "pci_private.h" 62 63 #include "pcib_if.h" 64 65 devclass_t pci_devclass; 66 const char *pcib_owner; 67 68 static void pci_read_extcap(device_t dev, pcicfgregs *cfg); 69 70 struct pci_quirk { 71 u_int32_t devid; /* Vendor/device of the card */ 72 int type; 73 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 74 int arg1; 75 int arg2; 76 }; 77 78 struct pci_quirk pci_quirks[] = { 79 /* 80 * The Intel 82371AB and 82443MX has a map register at offset 0x90. 81 */ 82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 84 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 86 87 { 0 } 88 }; 89 90 /* map register information */ 91 #define PCI_MAPMEM 0x01 /* memory map */ 92 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 93 #define PCI_MAPPORT 0x04 /* port map */ 94 95 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 96 u_int32_t pci_numdevs = 0; 97 static u_int32_t pci_generation = 0; 98 99 device_t 100 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func) 101 { 102 struct pci_devinfo *dinfo; 103 104 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 105 if ((dinfo->cfg.bus == bus) && 106 (dinfo->cfg.slot == slot) && 107 (dinfo->cfg.func == func)) { 108 return (dinfo->cfg.dev); 109 } 110 } 111 112 return (NULL); 113 } 114 115 device_t 116 pci_find_device (u_int16_t vendor, u_int16_t device) 117 { 118 struct pci_devinfo *dinfo; 119 120 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 121 if ((dinfo->cfg.vendor == vendor) && 122 (dinfo->cfg.device == device)) { 123 return (dinfo->cfg.dev); 124 } 125 } 126 127 return (NULL); 128 } 129 130 /* return base address of memory or port map */ 131 132 static u_int32_t 133 pci_mapbase(unsigned mapreg) 134 { 135 int mask = 0x03; 136 if ((mapreg & 0x01) == 0) 137 mask = 0x0f; 138 return (mapreg & ~mask); 139 } 140 141 /* return map type of memory or port map */ 142 143 static int 144 pci_maptype(unsigned mapreg) 145 { 146 static u_int8_t maptype[0x10] = { 147 PCI_MAPMEM, PCI_MAPPORT, 148 PCI_MAPMEM, 0, 149 PCI_MAPMEM, PCI_MAPPORT, 150 0, 0, 151 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 152 PCI_MAPMEM|PCI_MAPMEMP, 0, 153 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 154 0, 0, 155 }; 156 157 return maptype[mapreg & 0x0f]; 158 } 159 160 /* return log2 of map size decoded for memory or port map */ 161 162 static int 163 pci_mapsize(unsigned testval) 164 { 165 int ln2size; 166 167 testval = pci_mapbase(testval); 168 ln2size = 0; 169 if (testval != 0) { 170 while ((testval & 1) == 0) 171 { 172 ln2size++; 173 testval >>= 1; 174 } 175 } 176 return (ln2size); 177 } 178 179 /* return log2 of address range supported by map register */ 180 181 static int 182 pci_maprange(unsigned mapreg) 183 { 184 int ln2range = 0; 185 switch (mapreg & 0x07) { 186 case 0x00: 187 case 0x01: 188 case 0x05: 189 ln2range = 32; 190 break; 191 case 0x02: 192 ln2range = 20; 193 break; 194 case 0x04: 195 ln2range = 64; 196 break; 197 } 198 return (ln2range); 199 } 200 201 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 202 203 static void 204 pci_fixancient(pcicfgregs *cfg) 205 { 206 if (cfg->hdrtype != 0) 207 return; 208 209 /* PCI to PCI bridges use header type 1 */ 210 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 211 cfg->hdrtype = 1; 212 } 213 214 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 215 216 static void * 217 pci_readppb(device_t pcib, int b, int s, int f) 218 { 219 pcih1cfgregs *p; 220 221 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 222 if (p == NULL) 223 return (NULL); 224 225 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2); 226 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2); 227 228 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1); 229 230 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f, 231 PCIR_IOBASEH_1, 2), 232 PCIB_READ_CONFIG(pcib, b, s, f, 233 PCIR_IOBASEL_1, 1)); 234 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f, 235 PCIR_IOLIMITH_1, 2), 236 PCIB_READ_CONFIG(pcib, b, s, f, 237 PCIR_IOLIMITL_1, 1)); 238 239 p->membase = PCI_PPBMEMBASE (0, 240 PCIB_READ_CONFIG(pcib, b, s, f, 241 PCIR_MEMBASE_1, 2)); 242 p->memlimit = PCI_PPBMEMLIMIT (0, 243 PCIB_READ_CONFIG(pcib, b, s, f, 244 PCIR_MEMLIMIT_1, 2)); 245 246 p->pmembase = PCI_PPBMEMBASE ( 247 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4), 248 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2)); 249 250 p->pmemlimit = PCI_PPBMEMLIMIT ( 251 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, 252 PCIR_PMLIMITH_1, 4), 253 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2)); 254 255 return (p); 256 } 257 258 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 259 260 static void * 261 pci_readpcb(device_t pcib, int b, int s, int f) 262 { 263 pcih2cfgregs *p; 264 265 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 266 if (p == NULL) 267 return (NULL); 268 269 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2); 270 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2); 271 272 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1); 273 274 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4); 275 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4); 276 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4); 277 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4); 278 279 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4); 280 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4); 281 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4); 282 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4); 283 284 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4); 285 return p; 286 } 287 288 /* extract header type specific config data */ 289 290 static void 291 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 292 { 293 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 294 switch (cfg->hdrtype) { 295 case 0: 296 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 297 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 298 cfg->nummaps = PCI_MAXMAPS_0; 299 break; 300 case 1: 301 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 302 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 303 cfg->secondarybus = REG(PCIR_SECBUS_1, 1); 304 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1); 305 cfg->nummaps = PCI_MAXMAPS_1; 306 cfg->hdrspec = pci_readppb(pcib, b, s, f); 307 break; 308 case 2: 309 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 310 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 311 cfg->secondarybus = REG(PCIR_SECBUS_2, 1); 312 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1); 313 cfg->nummaps = PCI_MAXMAPS_2; 314 cfg->hdrspec = pci_readpcb(pcib, b, s, f); 315 break; 316 } 317 #undef REG 318 } 319 320 /* read configuration header into pcicfgrect structure */ 321 322 struct pci_devinfo * 323 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 324 { 325 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 326 327 pcicfgregs *cfg = NULL; 328 struct pci_devinfo *devlist_entry; 329 struct devlist *devlist_head; 330 331 devlist_head = &pci_devq; 332 333 devlist_entry = NULL; 334 335 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 336 337 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 338 if (devlist_entry == NULL) 339 return (NULL); 340 341 cfg = &devlist_entry->cfg; 342 343 cfg->bus = b; 344 cfg->slot = s; 345 cfg->func = f; 346 cfg->vendor = REG(PCIR_VENDOR, 2); 347 cfg->device = REG(PCIR_DEVICE, 2); 348 cfg->cmdreg = REG(PCIR_COMMAND, 2); 349 cfg->statreg = REG(PCIR_STATUS, 2); 350 cfg->baseclass = REG(PCIR_CLASS, 1); 351 cfg->subclass = REG(PCIR_SUBCLASS, 1); 352 cfg->progif = REG(PCIR_PROGIF, 1); 353 cfg->revid = REG(PCIR_REVID, 1); 354 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 355 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 356 cfg->lattimer = REG(PCIR_LATTIMER, 1); 357 cfg->intpin = REG(PCIR_INTPIN, 1); 358 cfg->intline = REG(PCIR_INTLINE, 1); 359 360 #ifdef APIC_IO 361 /* 362 * If using the APIC the intpin is probably wrong, since it 363 * is often setup by the BIOS with the PIC in mind. 364 */ 365 if (cfg->intpin != 0) { 366 int airq; 367 368 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 369 if (airq >= 0) { 370 /* PCI specific entry found in MP table */ 371 if (airq != cfg->intline) { 372 undirect_pci_irq(cfg->intline); 373 cfg->intline = airq; 374 } 375 } else { 376 /* 377 * PCI interrupts might be redirected to the 378 * ISA bus according to some MP tables. Use the 379 * same methods as used by the ISA devices 380 * devices to find the proper IOAPIC int pin. 381 */ 382 airq = isa_apic_irq(cfg->intline); 383 if ((airq >= 0) && (airq != cfg->intline)) { 384 /* XXX: undirect_pci_irq() ? */ 385 undirect_isa_irq(cfg->intline); 386 cfg->intline = airq; 387 } 388 } 389 } 390 #endif /* APIC_IO */ 391 392 cfg->mingnt = REG(PCIR_MINGNT, 1); 393 cfg->maxlat = REG(PCIR_MAXLAT, 1); 394 395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 396 cfg->hdrtype &= ~PCIM_MFDEV; 397 398 pci_fixancient(cfg); 399 pci_hdrtypedata(pcib, b, s, f, cfg); 400 401 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 402 pci_read_extcap(pcib, cfg); 403 404 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 405 406 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 407 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 408 devlist_entry->conf.pc_sel.pc_func = cfg->func; 409 devlist_entry->conf.pc_hdr = cfg->hdrtype; 410 411 devlist_entry->conf.pc_subvendor = cfg->subvendor; 412 devlist_entry->conf.pc_subdevice = cfg->subdevice; 413 devlist_entry->conf.pc_vendor = cfg->vendor; 414 devlist_entry->conf.pc_device = cfg->device; 415 416 devlist_entry->conf.pc_class = cfg->baseclass; 417 devlist_entry->conf.pc_subclass = cfg->subclass; 418 devlist_entry->conf.pc_progif = cfg->progif; 419 devlist_entry->conf.pc_revid = cfg->revid; 420 421 pci_numdevs++; 422 pci_generation++; 423 } 424 return (devlist_entry); 425 #undef REG 426 } 427 428 static void 429 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 430 { 431 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 432 int ptr, nextptr, ptrptr; 433 434 switch (cfg->hdrtype) { 435 case 0: 436 ptrptr = 0x34; 437 break; 438 case 2: 439 ptrptr = 0x14; 440 break; 441 default: 442 return; /* no extended capabilities support */ 443 } 444 nextptr = REG(ptrptr, 1); /* sanity check? */ 445 446 /* 447 * Read capability entries. 448 */ 449 while (nextptr != 0) { 450 /* Sanity check */ 451 if (nextptr > 255) { 452 kprintf("illegal PCI extended capability offset %d\n", 453 nextptr); 454 return; 455 } 456 /* Find the next entry */ 457 ptr = nextptr; 458 nextptr = REG(ptr + 1, 1); 459 460 /* Process this entry */ 461 switch (REG(ptr, 1)) { 462 case 0x01: /* PCI power management */ 463 if (cfg->pp_cap == 0) { 464 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 465 cfg->pp_status = ptr + PCIR_POWER_STATUS; 466 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 467 if ((nextptr - ptr) > PCIR_POWER_DATA) 468 cfg->pp_data = ptr + PCIR_POWER_DATA; 469 } 470 break; 471 default: 472 break; 473 } 474 } 475 #undef REG 476 } 477 478 /* free pcicfgregs structure and all depending data structures */ 479 480 int 481 pci_freecfg(struct pci_devinfo *dinfo) 482 { 483 struct devlist *devlist_head; 484 485 devlist_head = &pci_devq; 486 487 if (dinfo->cfg.hdrspec != NULL) 488 kfree(dinfo->cfg.hdrspec, M_DEVBUF); 489 /* XXX this hasn't been tested */ 490 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 491 kfree(dinfo, M_DEVBUF); 492 493 /* increment the generation count */ 494 pci_generation++; 495 496 /* we're losing one device */ 497 pci_numdevs--; 498 return (0); 499 } 500 501 502 /* 503 * PCI power manangement 504 */ 505 int 506 pci_set_powerstate_method(device_t dev, device_t child, int state) 507 { 508 struct pci_devinfo *dinfo = device_get_ivars(child); 509 pcicfgregs *cfg = &dinfo->cfg; 510 u_int16_t status; 511 int result; 512 513 if (cfg->pp_cap != 0) { 514 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 515 result = 0; 516 switch (state) { 517 case PCI_POWERSTATE_D0: 518 status |= PCIM_PSTAT_D0; 519 break; 520 case PCI_POWERSTATE_D1: 521 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 522 status |= PCIM_PSTAT_D1; 523 } else { 524 result = EOPNOTSUPP; 525 } 526 break; 527 case PCI_POWERSTATE_D2: 528 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 529 status |= PCIM_PSTAT_D2; 530 } else { 531 result = EOPNOTSUPP; 532 } 533 break; 534 case PCI_POWERSTATE_D3: 535 status |= PCIM_PSTAT_D3; 536 break; 537 default: 538 result = EINVAL; 539 } 540 if (result == 0) 541 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 542 } else { 543 result = ENXIO; 544 } 545 return(result); 546 } 547 548 int 549 pci_get_powerstate_method(device_t dev, device_t child) 550 { 551 struct pci_devinfo *dinfo = device_get_ivars(child); 552 pcicfgregs *cfg = &dinfo->cfg; 553 u_int16_t status; 554 int result; 555 556 if (cfg->pp_cap != 0) { 557 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 558 switch (status & PCIM_PSTAT_DMASK) { 559 case PCIM_PSTAT_D0: 560 result = PCI_POWERSTATE_D0; 561 break; 562 case PCIM_PSTAT_D1: 563 result = PCI_POWERSTATE_D1; 564 break; 565 case PCIM_PSTAT_D2: 566 result = PCI_POWERSTATE_D2; 567 break; 568 case PCIM_PSTAT_D3: 569 result = PCI_POWERSTATE_D3; 570 break; 571 default: 572 result = PCI_POWERSTATE_UNKNOWN; 573 break; 574 } 575 } else { 576 /* No support, device is always at D0 */ 577 result = PCI_POWERSTATE_D0; 578 } 579 return(result); 580 } 581 582 /* 583 * Some convenience functions for PCI device drivers. 584 */ 585 586 static __inline void 587 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 588 { 589 u_int16_t command; 590 591 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 592 command |= bit; 593 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 594 } 595 596 static __inline void 597 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 598 { 599 u_int16_t command; 600 601 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 602 command &= ~bit; 603 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 604 } 605 606 int 607 pci_enable_busmaster_method(device_t dev, device_t child) 608 { 609 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 610 return(0); 611 } 612 613 int 614 pci_disable_busmaster_method(device_t dev, device_t child) 615 { 616 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 617 return(0); 618 } 619 620 int 621 pci_enable_io_method(device_t dev, device_t child, int space) 622 { 623 uint16_t command; 624 uint16_t bit; 625 char *error; 626 627 bit = 0; 628 error = NULL; 629 630 switch(space) { 631 case SYS_RES_IOPORT: 632 bit = PCIM_CMD_PORTEN; 633 error = "port"; 634 break; 635 case SYS_RES_MEMORY: 636 bit = PCIM_CMD_MEMEN; 637 error = "memory"; 638 break; 639 default: 640 return(EINVAL); 641 } 642 pci_set_command_bit(dev, child, bit); 643 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 644 if (command & bit) 645 return(0); 646 device_printf(child, "failed to enable %s mapping!\n", error); 647 return(ENXIO); 648 } 649 650 int 651 pci_disable_io_method(device_t dev, device_t child, int space) 652 { 653 uint16_t command; 654 uint16_t bit; 655 char *error; 656 657 bit = 0; 658 error = NULL; 659 660 switch(space) { 661 case SYS_RES_IOPORT: 662 bit = PCIM_CMD_PORTEN; 663 error = "port"; 664 break; 665 case SYS_RES_MEMORY: 666 bit = PCIM_CMD_MEMEN; 667 error = "memory"; 668 break; 669 default: 670 return (EINVAL); 671 } 672 pci_clear_command_bit(dev, child, bit); 673 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 674 if (command & bit) { 675 device_printf(child, "failed to disable %s mapping!\n", error); 676 return (ENXIO); 677 } 678 return (0); 679 } 680 681 /* 682 * This is the user interface to PCI configuration space. 683 */ 684 685 static int 686 pci_open(struct dev_open_args *ap) 687 { 688 if ((ap->a_oflags & FWRITE) && securelevel > 0) { 689 return EPERM; 690 } 691 return 0; 692 } 693 694 static int 695 pci_close(struct dev_close_args *ap) 696 { 697 return 0; 698 } 699 700 /* 701 * Match a single pci_conf structure against an array of pci_match_conf 702 * structures. The first argument, 'matches', is an array of num_matches 703 * pci_match_conf structures. match_buf is a pointer to the pci_conf 704 * structure that will be compared to every entry in the matches array. 705 * This function returns 1 on failure, 0 on success. 706 */ 707 static int 708 pci_conf_match(struct pci_match_conf *matches, int num_matches, 709 struct pci_conf *match_buf) 710 { 711 int i; 712 713 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 714 return(1); 715 716 for (i = 0; i < num_matches; i++) { 717 /* 718 * I'm not sure why someone would do this...but... 719 */ 720 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 721 continue; 722 723 /* 724 * Look at each of the match flags. If it's set, do the 725 * comparison. If the comparison fails, we don't have a 726 * match, go on to the next item if there is one. 727 */ 728 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 729 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 730 continue; 731 732 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 733 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 734 continue; 735 736 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 737 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 738 continue; 739 740 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 741 && (match_buf->pc_vendor != matches[i].pc_vendor)) 742 continue; 743 744 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 745 && (match_buf->pc_device != matches[i].pc_device)) 746 continue; 747 748 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 749 && (match_buf->pc_class != matches[i].pc_class)) 750 continue; 751 752 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 753 && (match_buf->pd_unit != matches[i].pd_unit)) 754 continue; 755 756 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 757 && (strncmp(matches[i].pd_name, match_buf->pd_name, 758 sizeof(match_buf->pd_name)) != 0)) 759 continue; 760 761 return(0); 762 } 763 764 return(1); 765 } 766 767 /* 768 * Locate the parent of a PCI device by scanning the PCI devlist 769 * and return the entry for the parent. 770 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 771 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 772 */ 773 774 pcicfgregs * 775 pci_devlist_get_parent(pcicfgregs *cfg) 776 { 777 struct devlist *devlist_head; 778 struct pci_devinfo *dinfo; 779 pcicfgregs *bridge_cfg; 780 int i; 781 782 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 783 784 /* If the device is on PCI bus 0, look for the host */ 785 if (cfg->bus == 0) { 786 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 787 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 788 bridge_cfg = &dinfo->cfg; 789 if (bridge_cfg->baseclass == PCIC_BRIDGE 790 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 791 && bridge_cfg->bus == cfg->bus) { 792 return bridge_cfg; 793 } 794 } 795 } 796 797 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 798 if (cfg->bus > 0) { 799 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 800 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 801 bridge_cfg = &dinfo->cfg; 802 if (bridge_cfg->baseclass == PCIC_BRIDGE 803 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 804 && bridge_cfg->secondarybus == cfg->bus) { 805 return bridge_cfg; 806 } 807 } 808 } 809 810 return NULL; 811 } 812 813 static int 814 pci_ioctl(struct dev_ioctl_args *ap) 815 { 816 device_t pci, pcib; 817 struct pci_io *io; 818 const char *name; 819 int error; 820 821 if (!(ap->a_fflag & FWRITE)) 822 return EPERM; 823 824 switch(ap->a_cmd) { 825 case PCIOCGETCONF: 826 { 827 struct pci_devinfo *dinfo; 828 struct pci_conf_io *cio; 829 struct devlist *devlist_head; 830 struct pci_match_conf *pattern_buf; 831 int num_patterns; 832 size_t iolen; 833 int ionum, i; 834 835 cio = (struct pci_conf_io *)ap->a_data; 836 837 num_patterns = 0; 838 dinfo = NULL; 839 840 /* 841 * Hopefully the user won't pass in a null pointer, but it 842 * can't hurt to check. 843 */ 844 if (cio == NULL) { 845 error = EINVAL; 846 break; 847 } 848 849 /* 850 * If the user specified an offset into the device list, 851 * but the list has changed since they last called this 852 * ioctl, tell them that the list has changed. They will 853 * have to get the list from the beginning. 854 */ 855 if ((cio->offset != 0) 856 && (cio->generation != pci_generation)){ 857 cio->num_matches = 0; 858 cio->status = PCI_GETCONF_LIST_CHANGED; 859 error = 0; 860 break; 861 } 862 863 /* 864 * Check to see whether the user has asked for an offset 865 * past the end of our list. 866 */ 867 if (cio->offset >= pci_numdevs) { 868 cio->num_matches = 0; 869 cio->status = PCI_GETCONF_LAST_DEVICE; 870 error = 0; 871 break; 872 } 873 874 /* get the head of the device queue */ 875 devlist_head = &pci_devq; 876 877 /* 878 * Determine how much room we have for pci_conf structures. 879 * Round the user's buffer size down to the nearest 880 * multiple of sizeof(struct pci_conf) in case the user 881 * didn't specify a multiple of that size. 882 */ 883 iolen = min(cio->match_buf_len - 884 (cio->match_buf_len % sizeof(struct pci_conf)), 885 pci_numdevs * sizeof(struct pci_conf)); 886 887 /* 888 * Since we know that iolen is a multiple of the size of 889 * the pciconf union, it's okay to do this. 890 */ 891 ionum = iolen / sizeof(struct pci_conf); 892 893 /* 894 * If this test is true, the user wants the pci_conf 895 * structures returned to match the supplied entries. 896 */ 897 if ((cio->num_patterns > 0) 898 && (cio->pat_buf_len > 0)) { 899 /* 900 * pat_buf_len needs to be: 901 * num_patterns * sizeof(struct pci_match_conf) 902 * While it is certainly possible the user just 903 * allocated a large buffer, but set the number of 904 * matches correctly, it is far more likely that 905 * their kernel doesn't match the userland utility 906 * they're using. It's also possible that the user 907 * forgot to initialize some variables. Yes, this 908 * may be overly picky, but I hazard to guess that 909 * it's far more likely to just catch folks that 910 * updated their kernel but not their userland. 911 */ 912 if ((cio->num_patterns * 913 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 914 /* The user made a mistake, return an error*/ 915 cio->status = PCI_GETCONF_ERROR; 916 kprintf("pci_ioctl: pat_buf_len %d != " 917 "num_patterns (%d) * sizeof(struct " 918 "pci_match_conf) (%d)\npci_ioctl: " 919 "pat_buf_len should be = %d\n", 920 cio->pat_buf_len, cio->num_patterns, 921 (int)sizeof(struct pci_match_conf), 922 (int)sizeof(struct pci_match_conf) * 923 cio->num_patterns); 924 kprintf("pci_ioctl: do your headers match your " 925 "kernel?\n"); 926 cio->num_matches = 0; 927 error = EINVAL; 928 break; 929 } 930 931 /* 932 * Check the user's buffer to make sure it's readable. 933 */ 934 if (!useracc((caddr_t)cio->patterns, 935 cio->pat_buf_len, VM_PROT_READ)) { 936 kprintf("pci_ioctl: pattern buffer %p, " 937 "length %u isn't user accessible for" 938 " READ\n", cio->patterns, 939 cio->pat_buf_len); 940 error = EACCES; 941 break; 942 } 943 /* 944 * Allocate a buffer to hold the patterns. 945 */ 946 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP, 947 M_WAITOK); 948 error = copyin(cio->patterns, pattern_buf, 949 cio->pat_buf_len); 950 if (error != 0) 951 break; 952 num_patterns = cio->num_patterns; 953 954 } else if ((cio->num_patterns > 0) 955 || (cio->pat_buf_len > 0)) { 956 /* 957 * The user made a mistake, spit out an error. 958 */ 959 cio->status = PCI_GETCONF_ERROR; 960 cio->num_matches = 0; 961 kprintf("pci_ioctl: invalid GETCONF arguments\n"); 962 error = EINVAL; 963 break; 964 } else 965 pattern_buf = NULL; 966 967 /* 968 * Make sure we can write to the match buffer. 969 */ 970 if (!useracc((caddr_t)cio->matches, 971 cio->match_buf_len, VM_PROT_WRITE)) { 972 kprintf("pci_ioctl: match buffer %p, length %u " 973 "isn't user accessible for WRITE\n", 974 cio->matches, cio->match_buf_len); 975 error = EACCES; 976 break; 977 } 978 979 /* 980 * Go through the list of devices and copy out the devices 981 * that match the user's criteria. 982 */ 983 for (cio->num_matches = 0, error = 0, i = 0, 984 dinfo = STAILQ_FIRST(devlist_head); 985 (dinfo != NULL) && (cio->num_matches < ionum) 986 && (error == 0) && (i < pci_numdevs); 987 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 988 989 if (i < cio->offset) 990 continue; 991 992 /* Populate pd_name and pd_unit */ 993 name = NULL; 994 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 995 name = device_get_name(dinfo->cfg.dev); 996 if (name) { 997 strncpy(dinfo->conf.pd_name, name, 998 sizeof(dinfo->conf.pd_name)); 999 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 1000 dinfo->conf.pd_unit = 1001 device_get_unit(dinfo->cfg.dev); 1002 } 1003 1004 if ((pattern_buf == NULL) || 1005 (pci_conf_match(pattern_buf, num_patterns, 1006 &dinfo->conf) == 0)) { 1007 1008 /* 1009 * If we've filled up the user's buffer, 1010 * break out at this point. Since we've 1011 * got a match here, we'll pick right back 1012 * up at the matching entry. We can also 1013 * tell the user that there are more matches 1014 * left. 1015 */ 1016 if (cio->num_matches >= ionum) 1017 break; 1018 1019 error = copyout(&dinfo->conf, 1020 &cio->matches[cio->num_matches], 1021 sizeof(struct pci_conf)); 1022 cio->num_matches++; 1023 } 1024 } 1025 1026 /* 1027 * Set the pointer into the list, so if the user is getting 1028 * n records at a time, where n < pci_numdevs, 1029 */ 1030 cio->offset = i; 1031 1032 /* 1033 * Set the generation, the user will need this if they make 1034 * another ioctl call with offset != 0. 1035 */ 1036 cio->generation = pci_generation; 1037 1038 /* 1039 * If this is the last device, inform the user so he won't 1040 * bother asking for more devices. If dinfo isn't NULL, we 1041 * know that there are more matches in the list because of 1042 * the way the traversal is done. 1043 */ 1044 if (dinfo == NULL) 1045 cio->status = PCI_GETCONF_LAST_DEVICE; 1046 else 1047 cio->status = PCI_GETCONF_MORE_DEVS; 1048 1049 if (pattern_buf != NULL) 1050 kfree(pattern_buf, M_TEMP); 1051 1052 break; 1053 } 1054 case PCIOCREAD: 1055 io = (struct pci_io *)ap->a_data; 1056 switch(io->pi_width) { 1057 case 4: 1058 case 2: 1059 case 1: 1060 /* 1061 * Assume that the user-level bus number is 1062 * actually the pciN instance number. We map 1063 * from that to the real pcib+bus combination. 1064 */ 1065 pci = devclass_get_device(pci_devclass, 1066 io->pi_sel.pc_bus); 1067 if (pci) { 1068 /* 1069 * pci is the pci device and may contain 1070 * several children (for each function code). 1071 * The governing pci bus is the parent to 1072 * the pci device. 1073 */ 1074 int b; 1075 1076 pcib = device_get_parent(pci); 1077 b = pcib_get_bus(pcib); 1078 io->pi_data = 1079 PCIB_READ_CONFIG(pcib, 1080 b, 1081 io->pi_sel.pc_dev, 1082 io->pi_sel.pc_func, 1083 io->pi_reg, 1084 io->pi_width); 1085 error = 0; 1086 } else { 1087 error = ENODEV; 1088 } 1089 break; 1090 default: 1091 error = ENODEV; 1092 break; 1093 } 1094 break; 1095 1096 case PCIOCWRITE: 1097 io = (struct pci_io *)ap->a_data; 1098 switch(io->pi_width) { 1099 case 4: 1100 case 2: 1101 case 1: 1102 /* 1103 * Assume that the user-level bus number is 1104 * actually the pciN instance number. We map 1105 * from that to the real pcib+bus combination. 1106 */ 1107 pci = devclass_get_device(pci_devclass, 1108 io->pi_sel.pc_bus); 1109 if (pci) { 1110 /* 1111 * pci is the pci device and may contain 1112 * several children (for each function code). 1113 * The governing pci bus is the parent to 1114 * the pci device. 1115 */ 1116 int b; 1117 1118 pcib = device_get_parent(pci); 1119 b = pcib_get_bus(pcib); 1120 PCIB_WRITE_CONFIG(pcib, 1121 b, 1122 io->pi_sel.pc_dev, 1123 io->pi_sel.pc_func, 1124 io->pi_reg, 1125 io->pi_data, 1126 io->pi_width); 1127 error = 0; 1128 } else { 1129 error = ENODEV; 1130 } 1131 break; 1132 default: 1133 error = ENODEV; 1134 break; 1135 } 1136 break; 1137 1138 default: 1139 error = ENOTTY; 1140 break; 1141 } 1142 1143 return (error); 1144 } 1145 1146 #define PCI_CDEV 78 1147 1148 static struct dev_ops pcic_ops = { 1149 { "pci", PCI_CDEV, 0 }, 1150 .d_open = pci_open, 1151 .d_close = pci_close, 1152 .d_ioctl = pci_ioctl, 1153 }; 1154 1155 #include "pci_if.h" 1156 1157 /* 1158 * New style pci driver. Parent device is either a pci-host-bridge or a 1159 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1160 */ 1161 const char * 1162 pci_class_to_string(int baseclass) 1163 { 1164 const char *name; 1165 1166 switch(baseclass) { 1167 case PCIC_OLD: 1168 name = "OLD"; 1169 break; 1170 case PCIC_STORAGE: 1171 name = "STORAGE"; 1172 break; 1173 case PCIC_NETWORK: 1174 name = "NETWORK"; 1175 break; 1176 case PCIC_DISPLAY: 1177 name = "DISPLAY"; 1178 break; 1179 case PCIC_MULTIMEDIA: 1180 name = "MULTIMEDIA"; 1181 break; 1182 case PCIC_MEMORY: 1183 name = "MEMORY"; 1184 break; 1185 case PCIC_BRIDGE: 1186 name = "BRIDGE"; 1187 break; 1188 case PCIC_SIMPLECOMM: 1189 name = "SIMPLECOMM"; 1190 break; 1191 case PCIC_BASEPERIPH: 1192 name = "BASEPERIPH"; 1193 break; 1194 case PCIC_INPUTDEV: 1195 name = "INPUTDEV"; 1196 break; 1197 case PCIC_DOCKING: 1198 name = "DOCKING"; 1199 break; 1200 case PCIC_PROCESSOR: 1201 name = "PROCESSOR"; 1202 break; 1203 case PCIC_SERIALBUS: 1204 name = "SERIALBUS"; 1205 break; 1206 case PCIC_WIRELESS: 1207 name = "WIRELESS"; 1208 break; 1209 case PCIC_I2O: 1210 name = "I20"; 1211 break; 1212 case PCIC_SATELLITE: 1213 name = "SATELLITE"; 1214 break; 1215 case PCIC_CRYPTO: 1216 name = "CRYPTO"; 1217 break; 1218 case PCIC_SIGPROC: 1219 name = "SIGPROC"; 1220 break; 1221 case PCIC_OTHER: 1222 name = "OTHER"; 1223 break; 1224 default: 1225 name = "?"; 1226 break; 1227 } 1228 return(name); 1229 } 1230 1231 void 1232 pci_print_verbose(struct pci_devinfo *dinfo) 1233 { 1234 if (bootverbose) { 1235 pcicfgregs *cfg = &dinfo->cfg; 1236 1237 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1238 cfg->vendor, cfg->device, cfg->revid); 1239 kprintf("\tbus=%d, slot=%d, func=%d\n", 1240 cfg->bus, cfg->slot, cfg->func); 1241 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1242 pci_class_to_string(cfg->baseclass), 1243 cfg->baseclass, cfg->subclass, cfg->progif, 1244 cfg->hdrtype, cfg->mfdev); 1245 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n", 1246 cfg->subordinatebus, cfg->secondarybus); 1247 #ifdef PCI_DEBUG 1248 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1249 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1250 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1251 cfg->lattimer, cfg->lattimer * 30, 1252 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1253 #endif /* PCI_DEBUG */ 1254 if (cfg->intpin > 0) 1255 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 1256 } 1257 } 1258 1259 static int 1260 pci_porten(device_t pcib, int b, int s, int f) 1261 { 1262 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1263 & PCIM_CMD_PORTEN) != 0; 1264 } 1265 1266 static int 1267 pci_memen(device_t pcib, int b, int s, int f) 1268 { 1269 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1270 & PCIM_CMD_MEMEN) != 0; 1271 } 1272 1273 /* 1274 * Add a resource based on a pci map register. Return 1 if the map 1275 * register is a 32bit map register or 2 if it is a 64bit register. 1276 */ 1277 static int 1278 pci_add_map(device_t pcib, int b, int s, int f, int reg, 1279 struct resource_list *rl) 1280 { 1281 u_int32_t map; 1282 u_int64_t base; 1283 u_int8_t ln2size; 1284 u_int8_t ln2range; 1285 u_int32_t testval; 1286 1287 1288 #ifdef PCI_ENABLE_IO_MODES 1289 u_int16_t cmd; 1290 #endif 1291 int type; 1292 1293 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1294 1295 if (map == 0 || map == 0xffffffff) 1296 return 1; /* skip invalid entry */ 1297 1298 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1299 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1300 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1301 1302 base = pci_mapbase(map); 1303 if (pci_maptype(map) & PCI_MAPMEM) 1304 type = SYS_RES_MEMORY; 1305 else 1306 type = SYS_RES_IOPORT; 1307 ln2size = pci_mapsize(testval); 1308 ln2range = pci_maprange(testval); 1309 if (ln2range == 64) { 1310 /* Read the other half of a 64bit map register */ 1311 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4); 1312 } 1313 1314 /* 1315 * This code theoretically does the right thing, but has 1316 * undesirable side effects in some cases where 1317 * peripherals respond oddly to having these bits 1318 * enabled. Leave them alone by default. 1319 */ 1320 #ifdef PCI_ENABLE_IO_MODES 1321 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1322 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1323 cmd |= PCIM_CMD_PORTEN; 1324 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1325 } 1326 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1327 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1328 cmd |= PCIM_CMD_MEMEN; 1329 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1330 } 1331 #else 1332 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1333 return 1; 1334 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1335 return 1; 1336 #endif 1337 1338 resource_list_add(rl, type, reg, 1339 base, base + (1 << ln2size) - 1, 1340 (1 << ln2size)); 1341 1342 if (bootverbose) { 1343 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n", 1344 reg, pci_maptype(base), ln2range, 1345 (unsigned int) base, ln2size); 1346 } 1347 1348 return (ln2range == 64) ? 2 : 1; 1349 } 1350 1351 #ifdef PCI_MAP_FIXUP 1352 /* 1353 * For ATA devices we need to decide early on what addressing mode to use. 1354 * Legacy demands that the primary and secondary ATA ports sits on the 1355 * same addresses that old ISA hardware did. This dictates that we use 1356 * those addresses and ignore the BARs if we cannot set PCI native 1357 * addressing mode. 1358 */ 1359 static void 1360 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f, 1361 struct resource_list *rl) 1362 { 1363 int rid, type, progif; 1364 #if 0 1365 /* if this device supports PCI native addressing use it */ 1366 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1367 if ((progif &0x8a) == 0x8a) { 1368 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 1369 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 1370 kprintf("Trying ATA native PCI addressing mode\n"); 1371 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 1372 } 1373 } 1374 #endif 1375 /* 1376 * Because we return any preallocated resources for lazy 1377 * allocation for PCI devices in pci_alloc_resource(), we can 1378 * allocate our legacy resources here. 1379 */ 1380 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1381 type = SYS_RES_IOPORT; 1382 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 1383 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl); 1384 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl); 1385 } else { 1386 rid = PCIR_BAR(0); 1387 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 1388 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 1389 0); 1390 rid = PCIR_BAR(1); 1391 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 1392 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 1393 0); 1394 } 1395 if (progif & PCIP_STORAGE_IDE_MODESEC) { 1396 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl); 1397 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl); 1398 } else { 1399 rid = PCIR_BAR(2); 1400 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 1401 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 1402 0); 1403 rid = PCIR_BAR(3); 1404 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1405 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1406 0); 1407 } 1408 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl); 1409 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl); 1410 } 1411 #endif /* PCI_MAP_FIXUP */ 1412 1413 static void 1414 pci_add_resources(device_t pcib, device_t bus, device_t dev) 1415 { 1416 struct pci_devinfo *dinfo = device_get_ivars(dev); 1417 pcicfgregs *cfg = &dinfo->cfg; 1418 struct resource_list *rl = &dinfo->resources; 1419 struct pci_quirk *q; 1420 int b, i, f, s; 1421 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */ 1422 int irq; 1423 #endif 1424 1425 b = cfg->bus; 1426 s = cfg->slot; 1427 f = cfg->func; 1428 #ifdef PCI_MAP_FIXUP 1429 /* atapci devices in legacy mode need special map treatment */ 1430 if ((pci_get_class(dev) == PCIC_STORAGE) && 1431 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1432 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1433 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 1434 else 1435 #endif /* PCI_MAP_FIXUP */ 1436 for (i = 0; i < cfg->nummaps;) { 1437 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl); 1438 } 1439 1440 for (q = &pci_quirks[0]; q->devid; q++) { 1441 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1442 && q->type == PCI_QUIRK_MAP_REG) 1443 pci_add_map(pcib, b, s, f, q->arg1, rl); 1444 } 1445 1446 if (cfg->intpin > 0 && cfg->intline != 255) 1447 resource_list_add(rl, SYS_RES_IRQ, 0, 1448 cfg->intline, cfg->intline, 1); 1449 } 1450 1451 void 1452 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1453 { 1454 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1455 device_t pcib = device_get_parent(dev); 1456 struct pci_devinfo *dinfo; 1457 int maxslots; 1458 int s, f, pcifunchigh; 1459 uint8_t hdrtype; 1460 1461 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo)); 1462 1463 maxslots = PCIB_MAXSLOTS(pcib); 1464 1465 for (s = 0; s <= maxslots; s++) { 1466 pcifunchigh = 0; 1467 f = 0; 1468 hdrtype = REG(PCIR_HDRTYPE, 1); 1469 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1470 continue; 1471 if (hdrtype & PCIM_MFDEV) 1472 pcifunchigh = PCI_FUNCMAX; 1473 for (f = 0; f <= pcifunchigh; f++) { 1474 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1475 if (dinfo != NULL) { 1476 pci_add_child(dev, dinfo); 1477 } 1478 } 1479 } 1480 #undef REG 1481 } 1482 1483 /* 1484 * The actual PCI child that we add has a NULL driver whos parent 1485 * device will be "pci". The child contains the ivars, not the parent. 1486 */ 1487 void 1488 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1489 { 1490 device_t pcib; 1491 1492 pcib = device_get_parent(bus); 1493 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1494 device_set_ivars(dinfo->cfg.dev, dinfo); 1495 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1496 pci_print_verbose(dinfo); 1497 } 1498 1499 /* 1500 * Probe the PCI bus. Note: probe code is not supposed to add children 1501 * or call attach. 1502 */ 1503 static int 1504 pci_probe(device_t dev) 1505 { 1506 device_set_desc(dev, "PCI bus"); 1507 1508 /* Allow other subclasses to override this driver */ 1509 return(-1000); 1510 } 1511 1512 static int 1513 pci_attach(device_t dev) 1514 { 1515 int busno; 1516 int lunit = device_get_unit(dev); 1517 1518 dev_ops_add(&pcic_ops, -1, lunit); 1519 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit); 1520 1521 /* 1522 * Since there can be multiple independantly numbered PCI 1523 * busses on some large alpha systems, we can't use the unit 1524 * number to decide what bus we are probing. We ask the parent 1525 * pcib what our bus number is. 1526 * 1527 * pcib_get_bus() must act on the pci bus device, not on the pci 1528 * device, because it uses badly hacked nexus-based ivars to 1529 * store and retrieve the physical bus number. XXX 1530 */ 1531 busno = pcib_get_bus(device_get_parent(dev)); 1532 if (bootverbose) 1533 device_printf(dev, "pci_attach() physical bus=%d\n", busno); 1534 1535 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1536 1537 return (bus_generic_attach(dev)); 1538 } 1539 1540 static int 1541 pci_print_resources(struct resource_list *rl, const char *name, int type, 1542 const char *format) 1543 { 1544 struct resource_list_entry *rle; 1545 int printed, retval; 1546 1547 printed = 0; 1548 retval = 0; 1549 /* Yes, this is kinda cheating */ 1550 SLIST_FOREACH(rle, rl, link) { 1551 if (rle->type == type) { 1552 if (printed == 0) 1553 retval += kprintf(" %s ", name); 1554 else if (printed > 0) 1555 retval += kprintf(","); 1556 printed++; 1557 retval += kprintf(format, rle->start); 1558 if (rle->count > 1) { 1559 retval += kprintf("-"); 1560 retval += kprintf(format, rle->start + 1561 rle->count - 1); 1562 } 1563 } 1564 } 1565 return retval; 1566 } 1567 1568 int 1569 pci_print_child(device_t dev, device_t child) 1570 { 1571 struct pci_devinfo *dinfo; 1572 struct resource_list *rl; 1573 pcicfgregs *cfg; 1574 int retval = 0; 1575 1576 dinfo = device_get_ivars(child); 1577 cfg = &dinfo->cfg; 1578 rl = &dinfo->resources; 1579 1580 retval += bus_print_child_header(dev, child); 1581 1582 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 1583 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1584 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 1585 if (device_get_flags(dev)) 1586 retval += kprintf(" flags %#x", device_get_flags(dev)); 1587 1588 retval += kprintf(" at device %d.%d", pci_get_slot(child), 1589 pci_get_function(child)); 1590 1591 retval += bus_print_child_footer(dev, child); 1592 1593 return (retval); 1594 } 1595 1596 void 1597 pci_probe_nomatch(device_t dev, device_t child) 1598 { 1599 struct pci_devinfo *dinfo; 1600 pcicfgregs *cfg; 1601 const char *desc; 1602 int unknown; 1603 1604 unknown = 0; 1605 dinfo = device_get_ivars(child); 1606 cfg = &dinfo->cfg; 1607 desc = pci_ata_match(child); 1608 if (!desc) desc = pci_usb_match(child); 1609 if (!desc) desc = pci_vga_match(child); 1610 if (!desc) desc = pci_chip_match(child); 1611 if (!desc) { 1612 desc = "unknown card"; 1613 unknown++; 1614 } 1615 device_printf(dev, "<%s>", desc); 1616 if (bootverbose || unknown) { 1617 kprintf(" (vendor=0x%04x, dev=0x%04x)", 1618 cfg->vendor, 1619 cfg->device); 1620 } 1621 kprintf(" at %d.%d", 1622 pci_get_slot(child), 1623 pci_get_function(child)); 1624 if (cfg->intpin > 0 && cfg->intline != 255) { 1625 kprintf(" irq %d", cfg->intline); 1626 } 1627 kprintf("\n"); 1628 1629 return; 1630 } 1631 1632 int 1633 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1634 { 1635 struct pci_devinfo *dinfo; 1636 pcicfgregs *cfg; 1637 1638 dinfo = device_get_ivars(child); 1639 cfg = &dinfo->cfg; 1640 1641 switch (which) { 1642 case PCI_IVAR_SUBVENDOR: 1643 *result = cfg->subvendor; 1644 break; 1645 case PCI_IVAR_SUBDEVICE: 1646 *result = cfg->subdevice; 1647 break; 1648 case PCI_IVAR_VENDOR: 1649 *result = cfg->vendor; 1650 break; 1651 case PCI_IVAR_DEVICE: 1652 *result = cfg->device; 1653 break; 1654 case PCI_IVAR_DEVID: 1655 *result = (cfg->device << 16) | cfg->vendor; 1656 break; 1657 case PCI_IVAR_CLASS: 1658 *result = cfg->baseclass; 1659 break; 1660 case PCI_IVAR_SUBCLASS: 1661 *result = cfg->subclass; 1662 break; 1663 case PCI_IVAR_PROGIF: 1664 *result = cfg->progif; 1665 break; 1666 case PCI_IVAR_REVID: 1667 *result = cfg->revid; 1668 break; 1669 case PCI_IVAR_INTPIN: 1670 *result = cfg->intpin; 1671 break; 1672 case PCI_IVAR_IRQ: 1673 *result = cfg->intline; 1674 break; 1675 case PCI_IVAR_BUS: 1676 *result = cfg->bus; 1677 break; 1678 case PCI_IVAR_SLOT: 1679 *result = cfg->slot; 1680 break; 1681 case PCI_IVAR_FUNCTION: 1682 *result = cfg->func; 1683 break; 1684 case PCI_IVAR_SECONDARYBUS: 1685 *result = cfg->secondarybus; 1686 break; 1687 case PCI_IVAR_SUBORDINATEBUS: 1688 *result = cfg->subordinatebus; 1689 break; 1690 case PCI_IVAR_ETHADDR: 1691 /* 1692 * The generic accessor doesn't deal with failure, so 1693 * we set the return value, then return an error. 1694 */ 1695 *result = NULL; 1696 return (EINVAL); 1697 default: 1698 return ENOENT; 1699 } 1700 return 0; 1701 } 1702 1703 int 1704 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1705 { 1706 struct pci_devinfo *dinfo; 1707 pcicfgregs *cfg; 1708 1709 dinfo = device_get_ivars(child); 1710 cfg = &dinfo->cfg; 1711 1712 switch (which) { 1713 case PCI_IVAR_SUBVENDOR: 1714 case PCI_IVAR_SUBDEVICE: 1715 case PCI_IVAR_VENDOR: 1716 case PCI_IVAR_DEVICE: 1717 case PCI_IVAR_DEVID: 1718 case PCI_IVAR_CLASS: 1719 case PCI_IVAR_SUBCLASS: 1720 case PCI_IVAR_PROGIF: 1721 case PCI_IVAR_REVID: 1722 case PCI_IVAR_INTPIN: 1723 case PCI_IVAR_IRQ: 1724 case PCI_IVAR_BUS: 1725 case PCI_IVAR_SLOT: 1726 case PCI_IVAR_FUNCTION: 1727 case PCI_IVAR_ETHADDR: 1728 return EINVAL; /* disallow for now */ 1729 1730 case PCI_IVAR_SECONDARYBUS: 1731 cfg->secondarybus = value; 1732 break; 1733 case PCI_IVAR_SUBORDINATEBUS: 1734 cfg->subordinatebus = value; 1735 break; 1736 default: 1737 return ENOENT; 1738 } 1739 return 0; 1740 } 1741 1742 #ifdef PCI_MAP_FIXUP 1743 static struct resource * 1744 pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start, 1745 u_long end, u_long count, u_int flags) 1746 { 1747 struct pci_devinfo *dinfo = device_get_ivars(child); 1748 struct resource_list *rl = &dinfo->resources; 1749 struct resource_list_entry *rle; 1750 struct resource *res; 1751 uint32_t map, testval; 1752 int mapsize; 1753 1754 /* 1755 * Weed out the bogons, and figure out how large the BAR/map 1756 * is. BARs that read back 0 here are bogus and unimplemented. 1757 * 1758 * Note: atapci in legacy mode are special and handled elsewhere 1759 * in the code. If you have an atapci device in legacy mode and 1760 * it fails here, that other code is broken. 1761 */ 1762 res = NULL; 1763 map = pci_read_config(child, *rid, 4); 1764 pci_write_config(child, *rid, 0xffffffff, 4); 1765 testval = pci_read_config(child, *rid, 4); 1766 if (pci_mapbase(testval) == 0) 1767 goto out; 1768 if (pci_maptype(testval) & PCI_MAPMEM) { 1769 if (type != SYS_RES_MEMORY) { 1770 if (bootverbose) 1771 device_printf(dev, "child %s requested type %d" 1772 " for rid %#x, but the BAR says " 1773 "it is a memio\n", 1774 device_get_nameunit(child), type, 1775 *rid); 1776 goto out; 1777 } 1778 } else { 1779 if (type != SYS_RES_IOPORT) { 1780 if (bootverbose) 1781 device_printf(dev, "child %s requested type %d" 1782 " for rid %#x, but the BAR says " 1783 "it is an ioport\n", 1784 device_get_nameunit(child), type, 1785 *rid); 1786 goto out; 1787 } 1788 } 1789 /* 1790 * For real BARs, we need to override the size that 1791 * the driver requests, because that's what the BAR 1792 * actually uses and we would otherwise have a 1793 * situation where we might allocate the excess to 1794 * another driver, which won't work. 1795 */ 1796 mapsize = pci_mapsize(testval); 1797 count = 1 << mapsize; 1798 if (RF_ALIGNMENT(flags) < mapsize) 1799 flags = (flags & ~RF_ALIGNMENT_MASK) | 1800 RF_ALIGNMENT_LOG2(mapsize); 1801 /* 1802 * Allocate enough resource, and then write back the 1803 * appropriate BAR for that resource. 1804 */ 1805 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1806 start, end, count, flags); 1807 if (res == NULL) { 1808 device_printf(child, "%#lx bytes at rid %#x res %d failed " 1809 "(%#lx, %#lx)\n", count, *rid, type, start, end); 1810 goto out; 1811 } 1812 resource_list_add(rl, type, *rid, start, end, count); 1813 rle = resource_list_find(rl, type, *rid); 1814 if (rle == NULL) 1815 panic("pci_alloc_map: unexpectedly can't find resource."); 1816 rle->res = res; 1817 rle->start = rman_get_start(res); 1818 rle->end = rman_get_end(res); 1819 rle->count = count; 1820 if (bootverbose) 1821 device_printf(child, "lazy allocation of %#lx bytes rid %#x " 1822 "type %d at %#lx\n", count, *rid, type, 1823 rman_get_start(res)); 1824 map = rman_get_start(res); 1825 out:; 1826 pci_write_config(child, *rid, map, 4); 1827 return res; 1828 } 1829 #endif /* PCI_MAP_FIXUP */ 1830 1831 struct resource * 1832 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1833 u_long start, u_long end, u_long count, u_int flags) 1834 { 1835 struct pci_devinfo *dinfo = device_get_ivars(child); 1836 struct resource_list *rl = &dinfo->resources; 1837 #ifdef PCI_MAP_FIXUP 1838 struct resource_list_entry *rle; 1839 #endif /* PCI_MAP_FIXUP */ 1840 pcicfgregs *cfg = &dinfo->cfg; 1841 1842 /* 1843 * Perform lazy resource allocation 1844 */ 1845 if (device_get_parent(child) == dev) { 1846 switch (type) { 1847 case SYS_RES_IRQ: 1848 #ifdef __i386__ 1849 /* 1850 * If device doesn't have an interrupt routed, and is 1851 * deserving of an interrupt, try to assign it one. 1852 */ 1853 if ((cfg->intline == 255 || cfg->intline == 0) && 1854 (cfg->intpin != 0) && 1855 (start == 0) && (end == ~0UL)) { 1856 cfg->intline = PCIB_ROUTE_INTERRUPT( 1857 device_get_parent(dev), child, 1858 cfg->intpin); 1859 if (cfg->intline != 255) { 1860 pci_write_config(child, PCIR_INTLINE, 1861 cfg->intline, 1); 1862 resource_list_add(rl, SYS_RES_IRQ, 0, 1863 cfg->intline, cfg->intline, 1); 1864 } 1865 } 1866 break; 1867 #endif 1868 case SYS_RES_IOPORT: 1869 /* FALLTHROUGH */ 1870 case SYS_RES_MEMORY: 1871 if (*rid < PCIR_BAR(cfg->nummaps)) { 1872 /* 1873 * Enable the I/O mode. We should 1874 * also be assigning resources too 1875 * when none are present. The 1876 * resource_list_alloc kind of sorta does 1877 * this... 1878 */ 1879 if (PCI_ENABLE_IO(dev, child, type)) 1880 return (NULL); 1881 } 1882 #ifdef PCI_MAP_FIXUP 1883 rle = resource_list_find(rl, type, *rid); 1884 if (rle == NULL) 1885 return pci_alloc_map(dev, child, type, rid, 1886 start, end, count, flags); 1887 #endif /* PCI_MAP_FIXUP */ 1888 break; 1889 } 1890 #ifdef PCI_MAP_FIXUP 1891 /* 1892 * If we've already allocated the resource, then 1893 * return it now. But first we may need to activate 1894 * it, since we don't allocate the resource as active 1895 * above. Normally this would be done down in the 1896 * nexus, but since we short-circuit that path we have 1897 * to do its job here. Not sure if we should free the 1898 * resource if it fails to activate. 1899 * 1900 * Note: this also finds and returns resources for 1901 * atapci devices in legacy mode as allocated in 1902 * pci_ata_maps(). 1903 */ 1904 rle = resource_list_find(rl, type, *rid); 1905 if (rle != NULL && rle->res != NULL) { 1906 if (bootverbose) 1907 device_printf(child, "reserved %#lx bytes for " 1908 "rid %#x type %d at %#lx\n", 1909 rman_get_size(rle->res), *rid, 1910 type, rman_get_start(rle->res)); 1911 if ((flags & RF_ACTIVE) && 1912 bus_generic_activate_resource(dev, child, type, 1913 *rid, rle->res) != 0) 1914 return NULL; 1915 return rle->res; 1916 } 1917 #endif /* PCI_MAP_FIXUP */ 1918 } 1919 return resource_list_alloc(rl, dev, child, type, rid, 1920 start, end, count, flags); 1921 } 1922 1923 static int 1924 pci_release_resource(device_t dev, device_t child, int type, int rid, 1925 struct resource *r) 1926 { 1927 struct pci_devinfo *dinfo = device_get_ivars(child); 1928 struct resource_list *rl = &dinfo->resources; 1929 1930 return resource_list_release(rl, dev, child, type, rid, r); 1931 } 1932 1933 static int 1934 pci_set_resource(device_t dev, device_t child, int type, int rid, 1935 u_long start, u_long count) 1936 { 1937 struct pci_devinfo *dinfo = device_get_ivars(child); 1938 struct resource_list *rl = &dinfo->resources; 1939 1940 resource_list_add(rl, type, rid, start, start + count - 1, count); 1941 return 0; 1942 } 1943 1944 static int 1945 pci_get_resource(device_t dev, device_t child, int type, int rid, 1946 u_long *startp, u_long *countp) 1947 { 1948 struct pci_devinfo *dinfo = device_get_ivars(child); 1949 struct resource_list *rl = &dinfo->resources; 1950 struct resource_list_entry *rle; 1951 1952 rle = resource_list_find(rl, type, rid); 1953 if (!rle) 1954 return ENOENT; 1955 1956 if (startp) 1957 *startp = rle->start; 1958 if (countp) 1959 *countp = rle->count; 1960 1961 return 0; 1962 } 1963 1964 void 1965 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1966 { 1967 kprintf("pci_delete_resource: PCI resources can not be deleted\n"); 1968 } 1969 1970 struct resource_list * 1971 pci_get_resource_list (device_t dev, device_t child) 1972 { 1973 struct pci_devinfo * dinfo = device_get_ivars(child); 1974 struct resource_list * rl = &dinfo->resources; 1975 1976 if (!rl) 1977 return (NULL); 1978 1979 return (rl); 1980 } 1981 1982 u_int32_t 1983 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1984 { 1985 struct pci_devinfo *dinfo = device_get_ivars(child); 1986 pcicfgregs *cfg = &dinfo->cfg; 1987 1988 return PCIB_READ_CONFIG(device_get_parent(dev), 1989 cfg->bus, cfg->slot, cfg->func, 1990 reg, width); 1991 } 1992 1993 void 1994 pci_write_config_method(device_t dev, device_t child, int reg, 1995 u_int32_t val, int width) 1996 { 1997 struct pci_devinfo *dinfo = device_get_ivars(child); 1998 pcicfgregs *cfg = &dinfo->cfg; 1999 2000 PCIB_WRITE_CONFIG(device_get_parent(dev), 2001 cfg->bus, cfg->slot, cfg->func, 2002 reg, val, width); 2003 } 2004 2005 int 2006 pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 2007 size_t buflen) 2008 { 2009 struct pci_devinfo *dinfo; 2010 2011 dinfo = device_get_ivars(child); 2012 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 2013 pci_get_function(child)); 2014 return (0); 2015 } 2016 2017 int 2018 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 2019 size_t buflen) 2020 { 2021 struct pci_devinfo *dinfo; 2022 pcicfgregs *cfg; 2023 2024 dinfo = device_get_ivars(child); 2025 cfg = &dinfo->cfg; 2026 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 2027 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 2028 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 2029 cfg->progif); 2030 return (0); 2031 } 2032 2033 int 2034 pci_assign_interrupt_method(device_t dev, device_t child) 2035 { 2036 struct pci_devinfo *dinfo = device_get_ivars(child); 2037 pcicfgregs *cfg = &dinfo->cfg; 2038 2039 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2040 cfg->intpin)); 2041 } 2042 2043 static int 2044 pci_modevent(module_t mod, int what, void *arg) 2045 { 2046 switch (what) { 2047 case MOD_LOAD: 2048 STAILQ_INIT(&pci_devq); 2049 break; 2050 case MOD_UNLOAD: 2051 break; 2052 } 2053 2054 return 0; 2055 } 2056 2057 int 2058 pci_resume(device_t dev) 2059 { 2060 int numdevs; 2061 int i; 2062 device_t *children; 2063 device_t child; 2064 struct pci_devinfo *dinfo; 2065 pcicfgregs *cfg; 2066 2067 device_get_children(dev, &children, &numdevs); 2068 2069 for (i = 0; i < numdevs; i++) { 2070 child = children[i]; 2071 2072 dinfo = device_get_ivars(child); 2073 cfg = &dinfo->cfg; 2074 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 2075 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 2076 if (PCI_INTERRUPT_VALID(cfg->intline)) { 2077 pci_write_config(child, PCIR_INTLINE, 2078 cfg->intline, 1); 2079 } 2080 } 2081 } 2082 2083 kfree(children, M_TEMP); 2084 2085 return (bus_generic_resume(dev)); 2086 } 2087 2088 static device_method_t pci_methods[] = { 2089 /* Device interface */ 2090 DEVMETHOD(device_probe, pci_probe), 2091 DEVMETHOD(device_attach, pci_attach), 2092 DEVMETHOD(device_shutdown, bus_generic_shutdown), 2093 DEVMETHOD(device_suspend, bus_generic_suspend), 2094 DEVMETHOD(device_resume, pci_resume), 2095 2096 /* Bus interface */ 2097 DEVMETHOD(bus_print_child, pci_print_child), 2098 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 2099 DEVMETHOD(bus_read_ivar, pci_read_ivar), 2100 DEVMETHOD(bus_write_ivar, pci_write_ivar), 2101 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2102 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 2103 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 2104 2105 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 2106 DEVMETHOD(bus_set_resource, pci_set_resource), 2107 DEVMETHOD(bus_get_resource, pci_get_resource), 2108 DEVMETHOD(bus_delete_resource, pci_delete_resource), 2109 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 2110 DEVMETHOD(bus_release_resource, pci_release_resource), 2111 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 2112 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 2113 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 2114 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 2115 2116 /* PCI interface */ 2117 DEVMETHOD(pci_read_config, pci_read_config_method), 2118 DEVMETHOD(pci_write_config, pci_write_config_method), 2119 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 2120 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 2121 DEVMETHOD(pci_enable_io, pci_enable_io_method), 2122 DEVMETHOD(pci_disable_io, pci_disable_io_method), 2123 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 2124 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 2125 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 2126 2127 { 0, 0 } 2128 }; 2129 2130 static driver_t pci_driver = { 2131 "pci", 2132 pci_methods, 2133 1, /* no softc */ 2134 }; 2135 2136 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 2137 MODULE_VERSION(pci, 1); 2138