14d28e78fSSepherosa Ziehau /*-
24d28e78fSSepherosa Ziehau * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
34d28e78fSSepherosa Ziehau * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
44d28e78fSSepherosa Ziehau * Copyright (c) 2000 BSDi
54d28e78fSSepherosa Ziehau * All rights reserved.
64d28e78fSSepherosa Ziehau *
74d28e78fSSepherosa Ziehau * Redistribution and use in source and binary forms, with or without
84d28e78fSSepherosa Ziehau * modification, are permitted provided that the following conditions
94d28e78fSSepherosa Ziehau * are met:
104d28e78fSSepherosa Ziehau * 1. Redistributions of source code must retain the above copyright
114d28e78fSSepherosa Ziehau * notice, this list of conditions and the following disclaimer.
124d28e78fSSepherosa Ziehau * 2. Redistributions in binary form must reproduce the above copyright
134d28e78fSSepherosa Ziehau * notice, this list of conditions and the following disclaimer in the
144d28e78fSSepherosa Ziehau * documentation and/or other materials provided with the distribution.
154d28e78fSSepherosa Ziehau * 3. The name of the author may not be used to endorse or promote products
164d28e78fSSepherosa Ziehau * derived from this software without specific prior written permission.
174d28e78fSSepherosa Ziehau *
184d28e78fSSepherosa Ziehau * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
194d28e78fSSepherosa Ziehau * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
204d28e78fSSepherosa Ziehau * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
214d28e78fSSepherosa Ziehau * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
224d28e78fSSepherosa Ziehau * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
234d28e78fSSepherosa Ziehau * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
244d28e78fSSepherosa Ziehau * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
254d28e78fSSepherosa Ziehau * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
264d28e78fSSepherosa Ziehau * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
274d28e78fSSepherosa Ziehau * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
284d28e78fSSepherosa Ziehau * SUCH DAMAGE.
2983c1faaaSSascha Wildner *
3083c1faaaSSascha Wildner * $FreeBSD: src/sys/dev/pci/pci_pci.c,v 1.50.2.2.4.1 2009/04/15 03:14:26 kensmith Exp $
314d28e78fSSepherosa Ziehau */
324d28e78fSSepherosa Ziehau
334d28e78fSSepherosa Ziehau /*
344d28e78fSSepherosa Ziehau * PCI:PCI bridge support.
354d28e78fSSepherosa Ziehau */
364d28e78fSSepherosa Ziehau
374d28e78fSSepherosa Ziehau #include <sys/param.h>
384d28e78fSSepherosa Ziehau #include <sys/systm.h>
394d28e78fSSepherosa Ziehau #include <sys/kernel.h>
404d28e78fSSepherosa Ziehau #include <sys/module.h>
414d28e78fSSepherosa Ziehau #include <sys/bus.h>
424d28e78fSSepherosa Ziehau #include <sys/rman.h>
434d28e78fSSepherosa Ziehau #include <sys/sysctl.h>
44ed4d621dSSepherosa Ziehau #include <machine_base/apic/ioapic.h>
454d28e78fSSepherosa Ziehau
464d28e78fSSepherosa Ziehau #include <bus/pci/pcivar.h>
474d28e78fSSepherosa Ziehau #include <bus/pci/pcireg.h>
484d28e78fSSepherosa Ziehau #include <bus/pci/pcib_private.h>
494d28e78fSSepherosa Ziehau
504d28e78fSSepherosa Ziehau #include "pcib_if.h"
514d28e78fSSepherosa Ziehau
524d28e78fSSepherosa Ziehau static int pcib_probe(device_t dev);
534d28e78fSSepherosa Ziehau
544d28e78fSSepherosa Ziehau static device_method_t pcib_methods[] = {
554d28e78fSSepherosa Ziehau /* Device interface */
564d28e78fSSepherosa Ziehau DEVMETHOD(device_probe, pcib_probe),
574d28e78fSSepherosa Ziehau DEVMETHOD(device_attach, pcib_attach),
584d28e78fSSepherosa Ziehau DEVMETHOD(device_detach, bus_generic_detach),
594d28e78fSSepherosa Ziehau DEVMETHOD(device_shutdown, bus_generic_shutdown),
604d28e78fSSepherosa Ziehau DEVMETHOD(device_suspend, bus_generic_suspend),
614d28e78fSSepherosa Ziehau DEVMETHOD(device_resume, bus_generic_resume),
624d28e78fSSepherosa Ziehau
634d28e78fSSepherosa Ziehau /* Bus interface */
644d28e78fSSepherosa Ziehau DEVMETHOD(bus_print_child, bus_generic_print_child),
654d28e78fSSepherosa Ziehau DEVMETHOD(bus_read_ivar, pcib_read_ivar),
664d28e78fSSepherosa Ziehau DEVMETHOD(bus_write_ivar, pcib_write_ivar),
674d28e78fSSepherosa Ziehau DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
684d28e78fSSepherosa Ziehau DEVMETHOD(bus_release_resource, bus_generic_release_resource),
694d28e78fSSepherosa Ziehau DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
704d28e78fSSepherosa Ziehau DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
714d28e78fSSepherosa Ziehau DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
724d28e78fSSepherosa Ziehau DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
734d28e78fSSepherosa Ziehau
744d28e78fSSepherosa Ziehau /* pcib interface */
754d28e78fSSepherosa Ziehau DEVMETHOD(pcib_maxslots, pcib_maxslots),
764d28e78fSSepherosa Ziehau DEVMETHOD(pcib_read_config, pcib_read_config),
774d28e78fSSepherosa Ziehau DEVMETHOD(pcib_write_config, pcib_write_config),
784d28e78fSSepherosa Ziehau DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
794d28e78fSSepherosa Ziehau DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
804d28e78fSSepherosa Ziehau DEVMETHOD(pcib_release_msi, pcib_release_msi),
814d28e78fSSepherosa Ziehau DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
824d28e78fSSepherosa Ziehau DEVMETHOD(pcib_release_msix, pcib_release_msix),
834d28e78fSSepherosa Ziehau DEVMETHOD(pcib_map_msi, pcib_map_msi),
844d28e78fSSepherosa Ziehau
85d3c9c58eSSascha Wildner DEVMETHOD_END
864d28e78fSSepherosa Ziehau };
874d28e78fSSepherosa Ziehau
884d28e78fSSepherosa Ziehau static devclass_t pcib_devclass;
894d28e78fSSepherosa Ziehau
904d28e78fSSepherosa Ziehau DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
91aa2b9d05SSascha Wildner DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL);
924d28e78fSSepherosa Ziehau
934d28e78fSSepherosa Ziehau /*
944d28e78fSSepherosa Ziehau * Is the prefetch window open (eg, can we allocate memory in it?)
954d28e78fSSepherosa Ziehau */
964d28e78fSSepherosa Ziehau static int
pcib_is_prefetch_open(struct pcib_softc * sc)974d28e78fSSepherosa Ziehau pcib_is_prefetch_open(struct pcib_softc *sc)
984d28e78fSSepherosa Ziehau {
994d28e78fSSepherosa Ziehau return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
1004d28e78fSSepherosa Ziehau }
1014d28e78fSSepherosa Ziehau
1024d28e78fSSepherosa Ziehau /*
1034d28e78fSSepherosa Ziehau * Is the nonprefetch window open (eg, can we allocate memory in it?)
1044d28e78fSSepherosa Ziehau */
1054d28e78fSSepherosa Ziehau static int
pcib_is_nonprefetch_open(struct pcib_softc * sc)1064d28e78fSSepherosa Ziehau pcib_is_nonprefetch_open(struct pcib_softc *sc)
1074d28e78fSSepherosa Ziehau {
1084d28e78fSSepherosa Ziehau return (sc->membase > 0 && sc->membase < sc->memlimit);
1094d28e78fSSepherosa Ziehau }
1104d28e78fSSepherosa Ziehau
1114d28e78fSSepherosa Ziehau /*
1124d28e78fSSepherosa Ziehau * Is the io window open (eg, can we allocate ports in it?)
1134d28e78fSSepherosa Ziehau */
1144d28e78fSSepherosa Ziehau static int
pcib_is_io_open(struct pcib_softc * sc)1154d28e78fSSepherosa Ziehau pcib_is_io_open(struct pcib_softc *sc)
1164d28e78fSSepherosa Ziehau {
1174d28e78fSSepherosa Ziehau return (sc->iobase > 0 && sc->iobase < sc->iolimit);
1184d28e78fSSepherosa Ziehau }
1194d28e78fSSepherosa Ziehau
1204d28e78fSSepherosa Ziehau /*
1214d28e78fSSepherosa Ziehau * Generic device interface
1224d28e78fSSepherosa Ziehau */
1234d28e78fSSepherosa Ziehau static int
pcib_probe(device_t dev)1244d28e78fSSepherosa Ziehau pcib_probe(device_t dev)
1254d28e78fSSepherosa Ziehau {
1264d28e78fSSepherosa Ziehau if ((pci_get_class(dev) == PCIC_BRIDGE) &&
1274d28e78fSSepherosa Ziehau (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
1284d28e78fSSepherosa Ziehau device_set_desc(dev, "PCI-PCI bridge");
1296ea3b602SSascha Wildner #if defined(__x86_64__)
1309a4bd8f3SSepherosa Ziehau /* PCIBIOS PCI-PCI bridge is -2000 */
1319a4bd8f3SSepherosa Ziehau if (ioapic_enable)
1329a4bd8f3SSepherosa Ziehau return (-1000);
133ed4d621dSSepherosa Ziehau #endif
134c792a8a7SMichael Neumann return (-10000);
1354d28e78fSSepherosa Ziehau }
1364d28e78fSSepherosa Ziehau return(ENXIO);
1374d28e78fSSepherosa Ziehau }
1384d28e78fSSepherosa Ziehau
1394d28e78fSSepherosa Ziehau void
pcib_attach_common(device_t dev)1404d28e78fSSepherosa Ziehau pcib_attach_common(device_t dev)
1414d28e78fSSepherosa Ziehau {
1424d28e78fSSepherosa Ziehau struct pcib_softc *sc;
1434d28e78fSSepherosa Ziehau uint8_t iolow;
1444d28e78fSSepherosa Ziehau
1454d28e78fSSepherosa Ziehau sc = device_get_softc(dev);
1464d28e78fSSepherosa Ziehau sc->dev = dev;
1474d28e78fSSepherosa Ziehau
1484d28e78fSSepherosa Ziehau /*
1494d28e78fSSepherosa Ziehau * Get current bridge configuration.
1504d28e78fSSepherosa Ziehau */
1514d28e78fSSepherosa Ziehau sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
1524d28e78fSSepherosa Ziehau sc->domain = pci_get_domain(dev);
1534d28e78fSSepherosa Ziehau sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
1544d28e78fSSepherosa Ziehau sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1554d28e78fSSepherosa Ziehau sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
1564d28e78fSSepherosa Ziehau sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
1574d28e78fSSepherosa Ziehau sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
1584d28e78fSSepherosa Ziehau
1594d28e78fSSepherosa Ziehau /*
1604d28e78fSSepherosa Ziehau * Determine current I/O decode.
1614d28e78fSSepherosa Ziehau */
1624d28e78fSSepherosa Ziehau if (sc->command & PCIM_CMD_PORTEN) {
1634d28e78fSSepherosa Ziehau iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
1644d28e78fSSepherosa Ziehau if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
1654d28e78fSSepherosa Ziehau sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
1664d28e78fSSepherosa Ziehau pci_read_config(dev, PCIR_IOBASEL_1, 1));
1674d28e78fSSepherosa Ziehau } else {
1684d28e78fSSepherosa Ziehau sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
1694d28e78fSSepherosa Ziehau }
1704d28e78fSSepherosa Ziehau
1714d28e78fSSepherosa Ziehau iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
1724d28e78fSSepherosa Ziehau if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
1734d28e78fSSepherosa Ziehau sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
1744d28e78fSSepherosa Ziehau pci_read_config(dev, PCIR_IOLIMITL_1, 1));
1754d28e78fSSepherosa Ziehau } else {
1764d28e78fSSepherosa Ziehau sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
1774d28e78fSSepherosa Ziehau }
1784d28e78fSSepherosa Ziehau }
1794d28e78fSSepherosa Ziehau
1804d28e78fSSepherosa Ziehau /*
1814d28e78fSSepherosa Ziehau * Determine current memory decode.
1824d28e78fSSepherosa Ziehau */
1834d28e78fSSepherosa Ziehau if (sc->command & PCIM_CMD_MEMEN) {
1844d28e78fSSepherosa Ziehau sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
1854d28e78fSSepherosa Ziehau sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
1864d28e78fSSepherosa Ziehau iolow = pci_read_config(dev, PCIR_PMBASEL_1, 1);
1874d28e78fSSepherosa Ziehau if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
1884d28e78fSSepherosa Ziehau sc->pmembase = PCI_PPBMEMBASE(
1894d28e78fSSepherosa Ziehau pci_read_config(dev, PCIR_PMBASEH_1, 4),
1904d28e78fSSepherosa Ziehau pci_read_config(dev, PCIR_PMBASEL_1, 2));
1914d28e78fSSepherosa Ziehau else
1924d28e78fSSepherosa Ziehau sc->pmembase = PCI_PPBMEMBASE(0,
1934d28e78fSSepherosa Ziehau pci_read_config(dev, PCIR_PMBASEL_1, 2));
1944d28e78fSSepherosa Ziehau iolow = pci_read_config(dev, PCIR_PMLIMITL_1, 1);
1954d28e78fSSepherosa Ziehau if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
1964d28e78fSSepherosa Ziehau sc->pmemlimit = PCI_PPBMEMLIMIT(
1974d28e78fSSepherosa Ziehau pci_read_config(dev, PCIR_PMLIMITH_1, 4),
1984d28e78fSSepherosa Ziehau pci_read_config(dev, PCIR_PMLIMITL_1, 2));
1994d28e78fSSepherosa Ziehau else
2004d28e78fSSepherosa Ziehau sc->pmemlimit = PCI_PPBMEMLIMIT(0,
2014d28e78fSSepherosa Ziehau pci_read_config(dev, PCIR_PMLIMITL_1, 2));
2024d28e78fSSepherosa Ziehau }
2034d28e78fSSepherosa Ziehau
2044d28e78fSSepherosa Ziehau /*
2054d28e78fSSepherosa Ziehau * Quirk handling.
2064d28e78fSSepherosa Ziehau */
2074d28e78fSSepherosa Ziehau switch (pci_get_devid(dev)) {
2084d28e78fSSepherosa Ziehau case 0x12258086: /* Intel 82454KX/GX (Orion) */
2094d28e78fSSepherosa Ziehau {
2104d28e78fSSepherosa Ziehau uint8_t supbus;
2114d28e78fSSepherosa Ziehau
2124d28e78fSSepherosa Ziehau supbus = pci_read_config(dev, 0x41, 1);
2134d28e78fSSepherosa Ziehau if (supbus != 0xff) {
2144d28e78fSSepherosa Ziehau sc->secbus = supbus + 1;
2154d28e78fSSepherosa Ziehau sc->subbus = supbus + 1;
2164d28e78fSSepherosa Ziehau }
2174d28e78fSSepherosa Ziehau break;
2184d28e78fSSepherosa Ziehau }
2194d28e78fSSepherosa Ziehau
2204d28e78fSSepherosa Ziehau /*
2214d28e78fSSepherosa Ziehau * The i82380FB mobile docking controller is a PCI-PCI bridge,
2224d28e78fSSepherosa Ziehau * and it is a subtractive bridge. However, the ProgIf is wrong
2234d28e78fSSepherosa Ziehau * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
2244d28e78fSSepherosa Ziehau * happen. There's also a Toshiba bridge that behaves this
2254d28e78fSSepherosa Ziehau * way.
2264d28e78fSSepherosa Ziehau */
2274d28e78fSSepherosa Ziehau case 0x124b8086: /* Intel 82380FB Mobile */
2284d28e78fSSepherosa Ziehau case 0x060513d7: /* Toshiba ???? */
2294d28e78fSSepherosa Ziehau sc->flags |= PCIB_SUBTRACTIVE;
2304d28e78fSSepherosa Ziehau break;
2314d28e78fSSepherosa Ziehau
2324d28e78fSSepherosa Ziehau /* Compaq R3000 BIOS sets wrong subordinate bus number. */
2334d28e78fSSepherosa Ziehau case 0x00dd10de:
2344d28e78fSSepherosa Ziehau {
2354d28e78fSSepherosa Ziehau char *cp;
2364d28e78fSSepherosa Ziehau
2374d28e78fSSepherosa Ziehau if ((cp = kgetenv("smbios.planar.maker")) == NULL)
2384d28e78fSSepherosa Ziehau break;
2394d28e78fSSepherosa Ziehau if (strncmp(cp, "Compal", 6) != 0) {
2404d28e78fSSepherosa Ziehau kfreeenv(cp);
2414d28e78fSSepherosa Ziehau break;
2424d28e78fSSepherosa Ziehau }
2434d28e78fSSepherosa Ziehau kfreeenv(cp);
2444d28e78fSSepherosa Ziehau if ((cp = kgetenv("smbios.planar.product")) == NULL)
2454d28e78fSSepherosa Ziehau break;
2464d28e78fSSepherosa Ziehau if (strncmp(cp, "08A0", 4) != 0) {
2474d28e78fSSepherosa Ziehau kfreeenv(cp);
2484d28e78fSSepherosa Ziehau break;
2494d28e78fSSepherosa Ziehau }
2504d28e78fSSepherosa Ziehau kfreeenv(cp);
2514d28e78fSSepherosa Ziehau if (sc->subbus < 0xa) {
2524d28e78fSSepherosa Ziehau pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
2534d28e78fSSepherosa Ziehau sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
2544d28e78fSSepherosa Ziehau }
2554d28e78fSSepherosa Ziehau break;
2564d28e78fSSepherosa Ziehau }
2574d28e78fSSepherosa Ziehau }
2584d28e78fSSepherosa Ziehau
2594d28e78fSSepherosa Ziehau if (pci_msi_device_blacklisted(dev))
2604d28e78fSSepherosa Ziehau sc->flags |= PCIB_DISABLE_MSI;
2614d28e78fSSepherosa Ziehau
2624d28e78fSSepherosa Ziehau /*
2634d28e78fSSepherosa Ziehau * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
2644d28e78fSSepherosa Ziehau * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
2654d28e78fSSepherosa Ziehau * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
2664d28e78fSSepherosa Ziehau * This means they act as if they were subtractively decoding
2674d28e78fSSepherosa Ziehau * bridges and pass all transactions. Mark them and real ProgIf 1
2684d28e78fSSepherosa Ziehau * parts as subtractive.
2694d28e78fSSepherosa Ziehau */
2704d28e78fSSepherosa Ziehau if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
2714d28e78fSSepherosa Ziehau pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
2724d28e78fSSepherosa Ziehau sc->flags |= PCIB_SUBTRACTIVE;
2734d28e78fSSepherosa Ziehau
2744d28e78fSSepherosa Ziehau if (bootverbose) {
2754d28e78fSSepherosa Ziehau device_printf(dev, " domain %d\n", sc->domain);
2764d28e78fSSepherosa Ziehau device_printf(dev, " secondary bus %d\n", sc->secbus);
2774d28e78fSSepherosa Ziehau device_printf(dev, " subordinate bus %d\n", sc->subbus);
2784d28e78fSSepherosa Ziehau device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
2794d28e78fSSepherosa Ziehau if (pcib_is_nonprefetch_open(sc))
2804d28e78fSSepherosa Ziehau device_printf(dev, " memory decode 0x%jx-0x%jx\n",
2814d28e78fSSepherosa Ziehau (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
2824d28e78fSSepherosa Ziehau if (pcib_is_prefetch_open(sc))
2834d28e78fSSepherosa Ziehau device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
2844d28e78fSSepherosa Ziehau (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
2854d28e78fSSepherosa Ziehau else
2864d28e78fSSepherosa Ziehau device_printf(dev, " no prefetched decode\n");
2874d28e78fSSepherosa Ziehau if (sc->flags & PCIB_SUBTRACTIVE)
2884d28e78fSSepherosa Ziehau device_printf(dev, " Subtractively decoded bridge.\n");
2894d28e78fSSepherosa Ziehau }
2904d28e78fSSepherosa Ziehau
291d85e7311SSepherosa Ziehau if (pci_is_pcie(dev) && pcie_slot_implemented(dev)) {
292d85e7311SSepherosa Ziehau uint16_t slot_ctrl;
293d85e7311SSepherosa Ziehau uint8_t ptr;
294d85e7311SSepherosa Ziehau
295d85e7311SSepherosa Ziehau /*
296d85e7311SSepherosa Ziehau * XXX
297d85e7311SSepherosa Ziehau * Before proper PCI Express hot-plug support is in place,
298d85e7311SSepherosa Ziehau * disable all hot-plug interrupts on the PCI Express root
299d85e7311SSepherosa Ziehau * port or down stream port for now.
300d85e7311SSepherosa Ziehau */
301d650e218SMatthew Dillon #define HPINTRS (PCIEM_SLOTCTL_HPINTR_MASK | PCIEM_SLOTCTL_HPINTR_EN)
302d85e7311SSepherosa Ziehau
303d85e7311SSepherosa Ziehau ptr = pci_get_pciecap_ptr(dev);
304d650e218SMatthew Dillon slot_ctrl = pci_read_config(dev, ptr + PCIER_SLOTCTL, 2);
305d85e7311SSepherosa Ziehau if (slot_ctrl & HPINTRS) {
306d85e7311SSepherosa Ziehau device_printf(dev, "Disable PCI Express hot-plug "
307d85e7311SSepherosa Ziehau "interrupts(0x%04x)\n", slot_ctrl & HPINTRS);
308d85e7311SSepherosa Ziehau slot_ctrl &= ~HPINTRS;
309d650e218SMatthew Dillon pci_write_config(dev, ptr + PCIER_SLOTCTL, slot_ctrl, 2);
310d85e7311SSepherosa Ziehau }
311d85e7311SSepherosa Ziehau
312d85e7311SSepherosa Ziehau #undef HPINTRS
313d85e7311SSepherosa Ziehau }
314d85e7311SSepherosa Ziehau
3154d28e78fSSepherosa Ziehau /*
3164d28e78fSSepherosa Ziehau * XXX If the secondary bus number is zero, we should assign a bus number
3174d28e78fSSepherosa Ziehau * since the BIOS hasn't, then initialise the bridge.
3184d28e78fSSepherosa Ziehau */
3194d28e78fSSepherosa Ziehau
3204d28e78fSSepherosa Ziehau /*
3214d28e78fSSepherosa Ziehau * XXX If the subordinate bus number is less than the secondary bus number,
3224d28e78fSSepherosa Ziehau * we should pick a better value. One sensible alternative would be to
3234d28e78fSSepherosa Ziehau * pick 255; the only tradeoff here is that configuration transactions
3244d28e78fSSepherosa Ziehau * would be more widely routed than absolutely necessary.
3254d28e78fSSepherosa Ziehau */
326*21cff6ddSMatthew Dillon
327*21cff6ddSMatthew Dillon /*
328*21cff6ddSMatthew Dillon * Always enable busmastering on bridges so that transactions
329*21cff6ddSMatthew Dillon * initiated on the secondary bus are passed through to the
330*21cff6ddSMatthew Dillon * primary bus.
331*21cff6ddSMatthew Dillon */
332*21cff6ddSMatthew Dillon pci_enable_busmaster(dev);
3334d28e78fSSepherosa Ziehau }
3344d28e78fSSepherosa Ziehau
3354d28e78fSSepherosa Ziehau int
pcib_attach(device_t dev)3364d28e78fSSepherosa Ziehau pcib_attach(device_t dev)
3374d28e78fSSepherosa Ziehau {
3384d28e78fSSepherosa Ziehau struct pcib_softc *sc;
3394d28e78fSSepherosa Ziehau device_t child;
3404d28e78fSSepherosa Ziehau
3414d28e78fSSepherosa Ziehau pcib_attach_common(dev);
3424d28e78fSSepherosa Ziehau sc = device_get_softc(dev);
3434d28e78fSSepherosa Ziehau if (sc->secbus != 0) {
3444d28e78fSSepherosa Ziehau child = device_add_child(dev, "pci", sc->secbus);
3454d28e78fSSepherosa Ziehau if (child != NULL)
3464d28e78fSSepherosa Ziehau return(bus_generic_attach(dev));
3474d28e78fSSepherosa Ziehau }
3484d28e78fSSepherosa Ziehau
3494d28e78fSSepherosa Ziehau /* no secondary bus; we should have fixed this */
3504d28e78fSSepherosa Ziehau return(0);
3514d28e78fSSepherosa Ziehau }
3524d28e78fSSepherosa Ziehau
3534d28e78fSSepherosa Ziehau int
pcib_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)3544d28e78fSSepherosa Ziehau pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3554d28e78fSSepherosa Ziehau {
3564d28e78fSSepherosa Ziehau struct pcib_softc *sc = device_get_softc(dev);
3574d28e78fSSepherosa Ziehau
3584d28e78fSSepherosa Ziehau switch (which) {
3594d28e78fSSepherosa Ziehau case PCIB_IVAR_DOMAIN:
3604d28e78fSSepherosa Ziehau *result = sc->domain;
3614d28e78fSSepherosa Ziehau return(0);
3624d28e78fSSepherosa Ziehau case PCIB_IVAR_BUS:
3634d28e78fSSepherosa Ziehau *result = sc->secbus;
3644d28e78fSSepherosa Ziehau return(0);
3654d28e78fSSepherosa Ziehau }
3664d28e78fSSepherosa Ziehau return(ENOENT);
3674d28e78fSSepherosa Ziehau }
3684d28e78fSSepherosa Ziehau
3694d28e78fSSepherosa Ziehau int
pcib_write_ivar(device_t dev,device_t child,int which,uintptr_t value)3704d28e78fSSepherosa Ziehau pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3714d28e78fSSepherosa Ziehau {
3724d28e78fSSepherosa Ziehau struct pcib_softc *sc = device_get_softc(dev);
3734d28e78fSSepherosa Ziehau
3744d28e78fSSepherosa Ziehau switch (which) {
3754d28e78fSSepherosa Ziehau case PCIB_IVAR_DOMAIN:
3764d28e78fSSepherosa Ziehau return(EINVAL);
3774d28e78fSSepherosa Ziehau case PCIB_IVAR_BUS:
3784d28e78fSSepherosa Ziehau sc->secbus = value;
3794d28e78fSSepherosa Ziehau return(0);
3804d28e78fSSepherosa Ziehau }
3814d28e78fSSepherosa Ziehau return(ENOENT);
3824d28e78fSSepherosa Ziehau }
3834d28e78fSSepherosa Ziehau
3844d28e78fSSepherosa Ziehau /*
3854d28e78fSSepherosa Ziehau * We have to trap resource allocation requests and ensure that the bridge
3864d28e78fSSepherosa Ziehau * is set up to, or capable of handling them.
3874d28e78fSSepherosa Ziehau */
3884d28e78fSSepherosa Ziehau struct resource *
pcib_alloc_resource(device_t dev,device_t child,int type,int * rid,u_long start,u_long end,u_long count,u_int flags,int cpuid)3894d28e78fSSepherosa Ziehau pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
3904f7fe8c7SSepherosa Ziehau u_long start, u_long end, u_long count, u_int flags, int cpuid)
3914d28e78fSSepherosa Ziehau {
3924d28e78fSSepherosa Ziehau struct pcib_softc *sc = device_get_softc(dev);
3934d28e78fSSepherosa Ziehau const char *name, *suffix;
3944d28e78fSSepherosa Ziehau int ok;
3954d28e78fSSepherosa Ziehau
3964d28e78fSSepherosa Ziehau /*
3974d28e78fSSepherosa Ziehau * Fail the allocation for this range if it's not supported.
3984d28e78fSSepherosa Ziehau */
3994d28e78fSSepherosa Ziehau name = device_get_nameunit(child);
4004d28e78fSSepherosa Ziehau if (name == NULL) {
4014d28e78fSSepherosa Ziehau name = "";
4024d28e78fSSepherosa Ziehau suffix = "";
4034d28e78fSSepherosa Ziehau } else
4044d28e78fSSepherosa Ziehau suffix = " ";
4054d28e78fSSepherosa Ziehau switch (type) {
4064d28e78fSSepherosa Ziehau case SYS_RES_IOPORT:
4074d28e78fSSepherosa Ziehau ok = 0;
4084d28e78fSSepherosa Ziehau if (!pcib_is_io_open(sc))
4094d28e78fSSepherosa Ziehau break;
4104d28e78fSSepherosa Ziehau ok = (start >= sc->iobase && end <= sc->iolimit);
4114d28e78fSSepherosa Ziehau
4124d28e78fSSepherosa Ziehau /*
4134d28e78fSSepherosa Ziehau * Make sure we allow access to VGA I/O addresses when the
4144d28e78fSSepherosa Ziehau * bridge has the "VGA Enable" bit set.
4154d28e78fSSepherosa Ziehau */
4164d28e78fSSepherosa Ziehau if (!ok && pci_is_vga_ioport_range(start, end))
4174d28e78fSSepherosa Ziehau ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
4184d28e78fSSepherosa Ziehau
4194d28e78fSSepherosa Ziehau if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
4204d28e78fSSepherosa Ziehau if (!ok) {
4214d28e78fSSepherosa Ziehau if (start < sc->iobase)
4224d28e78fSSepherosa Ziehau start = sc->iobase;
4234d28e78fSSepherosa Ziehau if (end > sc->iolimit)
4244d28e78fSSepherosa Ziehau end = sc->iolimit;
4254d28e78fSSepherosa Ziehau if (start < end)
4264d28e78fSSepherosa Ziehau ok = 1;
4274d28e78fSSepherosa Ziehau }
4284d28e78fSSepherosa Ziehau } else {
4294d28e78fSSepherosa Ziehau ok = 1;
4304d28e78fSSepherosa Ziehau #if 1
4314d28e78fSSepherosa Ziehau if (start < sc->iobase && end > sc->iolimit) {
4324d28e78fSSepherosa Ziehau start = sc->iobase;
4334d28e78fSSepherosa Ziehau end = sc->iolimit;
4344d28e78fSSepherosa Ziehau }
4354d28e78fSSepherosa Ziehau #endif
4364d28e78fSSepherosa Ziehau }
4374d28e78fSSepherosa Ziehau if (end < start) {
4384d28e78fSSepherosa Ziehau device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
4394d28e78fSSepherosa Ziehau end, start);
4404d28e78fSSepherosa Ziehau start = 0;
4414d28e78fSSepherosa Ziehau end = 0;
4424d28e78fSSepherosa Ziehau ok = 0;
4434d28e78fSSepherosa Ziehau }
4444d28e78fSSepherosa Ziehau if (!ok) {
4454d28e78fSSepherosa Ziehau device_printf(dev, "%s%srequested unsupported I/O "
4464d28e78fSSepherosa Ziehau "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
4474d28e78fSSepherosa Ziehau name, suffix, start, end, sc->iobase, sc->iolimit);
4484d28e78fSSepherosa Ziehau return (NULL);
4494d28e78fSSepherosa Ziehau }
4504d28e78fSSepherosa Ziehau if (bootverbose)
4514d28e78fSSepherosa Ziehau device_printf(dev,
4524d28e78fSSepherosa Ziehau "%s%srequested I/O range 0x%lx-0x%lx: in range\n",
4534d28e78fSSepherosa Ziehau name, suffix, start, end);
4544d28e78fSSepherosa Ziehau break;
4554d28e78fSSepherosa Ziehau
4564d28e78fSSepherosa Ziehau case SYS_RES_MEMORY:
4574d28e78fSSepherosa Ziehau ok = 0;
4584d28e78fSSepherosa Ziehau if (pcib_is_nonprefetch_open(sc))
4594d28e78fSSepherosa Ziehau ok = ok || (start >= sc->membase && end <= sc->memlimit);
4604d28e78fSSepherosa Ziehau if (pcib_is_prefetch_open(sc))
4614d28e78fSSepherosa Ziehau ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
4624d28e78fSSepherosa Ziehau
4634d28e78fSSepherosa Ziehau /*
4644d28e78fSSepherosa Ziehau * Make sure we allow access to VGA memory addresses when the
4654d28e78fSSepherosa Ziehau * bridge has the "VGA Enable" bit set.
4664d28e78fSSepherosa Ziehau */
4674d28e78fSSepherosa Ziehau if (!ok && pci_is_vga_memory_range(start, end))
4684d28e78fSSepherosa Ziehau ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
4694d28e78fSSepherosa Ziehau
4704d28e78fSSepherosa Ziehau if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
4714d28e78fSSepherosa Ziehau if (!ok) {
4724d28e78fSSepherosa Ziehau ok = 1;
4734d28e78fSSepherosa Ziehau if (flags & RF_PREFETCHABLE) {
4744d28e78fSSepherosa Ziehau if (pcib_is_prefetch_open(sc)) {
4754d28e78fSSepherosa Ziehau if (start < sc->pmembase)
4764d28e78fSSepherosa Ziehau start = sc->pmembase;
4774d28e78fSSepherosa Ziehau if (end > sc->pmemlimit)
4784d28e78fSSepherosa Ziehau end = sc->pmemlimit;
4794d28e78fSSepherosa Ziehau } else {
4804d28e78fSSepherosa Ziehau ok = 0;
4814d28e78fSSepherosa Ziehau }
4824d28e78fSSepherosa Ziehau } else { /* non-prefetchable */
4834d28e78fSSepherosa Ziehau if (pcib_is_nonprefetch_open(sc)) {
4844d28e78fSSepherosa Ziehau if (start < sc->membase)
4854d28e78fSSepherosa Ziehau start = sc->membase;
4864d28e78fSSepherosa Ziehau if (end > sc->memlimit)
4874d28e78fSSepherosa Ziehau end = sc->memlimit;
4884d28e78fSSepherosa Ziehau } else {
4894d28e78fSSepherosa Ziehau ok = 0;
4904d28e78fSSepherosa Ziehau }
4914d28e78fSSepherosa Ziehau }
4924d28e78fSSepherosa Ziehau }
4934d28e78fSSepherosa Ziehau } else if (!ok) {
4944d28e78fSSepherosa Ziehau ok = 1; /* subtractive bridge: always ok */
4954d28e78fSSepherosa Ziehau #if 1
4964d28e78fSSepherosa Ziehau if (pcib_is_nonprefetch_open(sc)) {
4974d28e78fSSepherosa Ziehau if (start < sc->membase && end > sc->memlimit) {
4984d28e78fSSepherosa Ziehau start = sc->membase;
4994d28e78fSSepherosa Ziehau end = sc->memlimit;
5004d28e78fSSepherosa Ziehau }
5014d28e78fSSepherosa Ziehau }
5024d28e78fSSepherosa Ziehau if (pcib_is_prefetch_open(sc)) {
5034d28e78fSSepherosa Ziehau if (start < sc->pmembase && end > sc->pmemlimit) {
5044d28e78fSSepherosa Ziehau start = sc->pmembase;
5054d28e78fSSepherosa Ziehau end = sc->pmemlimit;
5064d28e78fSSepherosa Ziehau }
5074d28e78fSSepherosa Ziehau }
5084d28e78fSSepherosa Ziehau #endif
5094d28e78fSSepherosa Ziehau }
5104d28e78fSSepherosa Ziehau if (end < start) {
5114d28e78fSSepherosa Ziehau device_printf(dev, "memory: end (%lx) < start (%lx)\n",
5124d28e78fSSepherosa Ziehau end, start);
5134d28e78fSSepherosa Ziehau start = 0;
5144d28e78fSSepherosa Ziehau end = 0;
5154d28e78fSSepherosa Ziehau ok = 0;
5164d28e78fSSepherosa Ziehau }
5174d28e78fSSepherosa Ziehau if (!ok && bootverbose)
5184d28e78fSSepherosa Ziehau device_printf(dev,
5194d28e78fSSepherosa Ziehau "%s%srequested unsupported memory range %#lx-%#lx "
5204d28e78fSSepherosa Ziehau "(decoding %#jx-%#jx, %#jx-%#jx)\n",
5214d28e78fSSepherosa Ziehau name, suffix, start, end,
5224d28e78fSSepherosa Ziehau (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
5234d28e78fSSepherosa Ziehau (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
5244d28e78fSSepherosa Ziehau if (!ok)
5254d28e78fSSepherosa Ziehau return (NULL);
5264d28e78fSSepherosa Ziehau if (bootverbose)
5274d28e78fSSepherosa Ziehau device_printf(dev,"%s%srequested memory range "
5284d28e78fSSepherosa Ziehau "0x%lx-0x%lx: good\n",
5294d28e78fSSepherosa Ziehau name, suffix, start, end);
5304d28e78fSSepherosa Ziehau break;
5314d28e78fSSepherosa Ziehau
5324d28e78fSSepherosa Ziehau default:
5334d28e78fSSepherosa Ziehau break;
5344d28e78fSSepherosa Ziehau }
5354d28e78fSSepherosa Ziehau /*
5364d28e78fSSepherosa Ziehau * Bridge is OK decoding this resource, so pass it up.
5374d28e78fSSepherosa Ziehau */
5384d28e78fSSepherosa Ziehau return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
5394f7fe8c7SSepherosa Ziehau count, flags, cpuid));
5404d28e78fSSepherosa Ziehau }
5414d28e78fSSepherosa Ziehau
5424d28e78fSSepherosa Ziehau /*
5434d28e78fSSepherosa Ziehau * PCIB interface.
5444d28e78fSSepherosa Ziehau */
5454d28e78fSSepherosa Ziehau int
pcib_maxslots(device_t dev)5464d28e78fSSepherosa Ziehau pcib_maxslots(device_t dev)
5474d28e78fSSepherosa Ziehau {
5484d28e78fSSepherosa Ziehau return(PCI_SLOTMAX);
5494d28e78fSSepherosa Ziehau }
5504d28e78fSSepherosa Ziehau
5514d28e78fSSepherosa Ziehau /*
5524d28e78fSSepherosa Ziehau * Since we are a child of a PCI bus, its parent must support the pcib interface.
5534d28e78fSSepherosa Ziehau */
5544d28e78fSSepherosa Ziehau uint32_t
pcib_read_config(device_t dev,int b,int s,int f,int reg,int width)5554d28e78fSSepherosa Ziehau pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
5564d28e78fSSepherosa Ziehau {
5574d28e78fSSepherosa Ziehau return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
5584d28e78fSSepherosa Ziehau }
5594d28e78fSSepherosa Ziehau
5604d28e78fSSepherosa Ziehau void
pcib_write_config(device_t dev,int b,int s,int f,int reg,uint32_t val,int width)5614d28e78fSSepherosa Ziehau pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
5624d28e78fSSepherosa Ziehau {
5634d28e78fSSepherosa Ziehau PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
5644d28e78fSSepherosa Ziehau }
5654d28e78fSSepherosa Ziehau
5664d28e78fSSepherosa Ziehau /*
5674d28e78fSSepherosa Ziehau * Route an interrupt across a PCI bridge.
5684d28e78fSSepherosa Ziehau */
5694d28e78fSSepherosa Ziehau int
pcib_route_interrupt(device_t pcib,device_t dev,int pin)5704d28e78fSSepherosa Ziehau pcib_route_interrupt(device_t pcib, device_t dev, int pin)
5714d28e78fSSepherosa Ziehau {
5724d28e78fSSepherosa Ziehau device_t bus;
5734d28e78fSSepherosa Ziehau int parent_intpin;
5744d28e78fSSepherosa Ziehau int intnum;
5754d28e78fSSepherosa Ziehau
5764d28e78fSSepherosa Ziehau /*
5774d28e78fSSepherosa Ziehau *
5784d28e78fSSepherosa Ziehau * The PCI standard defines a swizzle of the child-side device/intpin to
5794d28e78fSSepherosa Ziehau * the parent-side intpin as follows.
5804d28e78fSSepherosa Ziehau *
5814d28e78fSSepherosa Ziehau * device = device on child bus
5824d28e78fSSepherosa Ziehau * child_intpin = intpin on child bus slot (0-3)
5834d28e78fSSepherosa Ziehau * parent_intpin = intpin on parent bus slot (0-3)
5844d28e78fSSepherosa Ziehau *
5854d28e78fSSepherosa Ziehau * parent_intpin = (device + child_intpin) % 4
5864d28e78fSSepherosa Ziehau */
5874d28e78fSSepherosa Ziehau parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
5884d28e78fSSepherosa Ziehau
5894d28e78fSSepherosa Ziehau /*
5904d28e78fSSepherosa Ziehau * Our parent is a PCI bus. Its parent must export the pcib interface
5914d28e78fSSepherosa Ziehau * which includes the ability to route interrupts.
5924d28e78fSSepherosa Ziehau */
5934d28e78fSSepherosa Ziehau bus = device_get_parent(pcib);
5944d28e78fSSepherosa Ziehau intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
5954d28e78fSSepherosa Ziehau if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
5964d28e78fSSepherosa Ziehau device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
5974d28e78fSSepherosa Ziehau pci_get_slot(dev), 'A' + pin - 1, intnum);
5984d28e78fSSepherosa Ziehau }
5994d28e78fSSepherosa Ziehau return(intnum);
6004d28e78fSSepherosa Ziehau }
6014d28e78fSSepherosa Ziehau
6024d28e78fSSepherosa Ziehau /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
6034d28e78fSSepherosa Ziehau int
pcib_alloc_msi(device_t pcib,device_t dev,int count,int maxcount,int * irqs,int cpuid)604803a9933SSepherosa Ziehau pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
605803a9933SSepherosa Ziehau int *irqs, int cpuid)
6064d28e78fSSepherosa Ziehau {
6074d28e78fSSepherosa Ziehau struct pcib_softc *sc = device_get_softc(pcib);
6084d28e78fSSepherosa Ziehau device_t bus;
6094d28e78fSSepherosa Ziehau
6104d28e78fSSepherosa Ziehau if (sc->flags & PCIB_DISABLE_MSI)
6114d28e78fSSepherosa Ziehau return (ENXIO);
6124d28e78fSSepherosa Ziehau bus = device_get_parent(pcib);
6134d28e78fSSepherosa Ziehau return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
614803a9933SSepherosa Ziehau irqs, cpuid));
6154d28e78fSSepherosa Ziehau }
6164d28e78fSSepherosa Ziehau
6174d28e78fSSepherosa Ziehau /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
6184d28e78fSSepherosa Ziehau int
pcib_release_msi(device_t pcib,device_t dev,int count,int * irqs,int cpuid)619975cc3f0SSepherosa Ziehau pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs, int cpuid)
6204d28e78fSSepherosa Ziehau {
6214d28e78fSSepherosa Ziehau device_t bus;
6224d28e78fSSepherosa Ziehau
6234d28e78fSSepherosa Ziehau bus = device_get_parent(pcib);
624975cc3f0SSepherosa Ziehau return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs,
625975cc3f0SSepherosa Ziehau cpuid));
6264d28e78fSSepherosa Ziehau }
6274d28e78fSSepherosa Ziehau
6284d28e78fSSepherosa Ziehau /* Pass request to alloc an MSI-X message up to the parent bridge. */
6294d28e78fSSepherosa Ziehau int
pcib_alloc_msix(device_t pcib,device_t dev,int * irq,int cpuid)6302a1f96b9SSepherosa Ziehau pcib_alloc_msix(device_t pcib, device_t dev, int *irq, int cpuid)
6314d28e78fSSepherosa Ziehau {
6324d28e78fSSepherosa Ziehau struct pcib_softc *sc = device_get_softc(pcib);
6334d28e78fSSepherosa Ziehau device_t bus;
6344d28e78fSSepherosa Ziehau
6354d28e78fSSepherosa Ziehau if (sc->flags & PCIB_DISABLE_MSI)
6364d28e78fSSepherosa Ziehau return (ENXIO);
6374d28e78fSSepherosa Ziehau bus = device_get_parent(pcib);
6382a1f96b9SSepherosa Ziehau return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq, cpuid));
6394d28e78fSSepherosa Ziehau }
6404d28e78fSSepherosa Ziehau
6414d28e78fSSepherosa Ziehau /* Pass request to release an MSI-X message up to the parent bridge. */
6424d28e78fSSepherosa Ziehau int
pcib_release_msix(device_t pcib,device_t dev,int irq,int cpuid)6432a1f96b9SSepherosa Ziehau pcib_release_msix(device_t pcib, device_t dev, int irq, int cpuid)
6444d28e78fSSepherosa Ziehau {
6454d28e78fSSepherosa Ziehau device_t bus;
6464d28e78fSSepherosa Ziehau
6474d28e78fSSepherosa Ziehau bus = device_get_parent(pcib);
6482a1f96b9SSepherosa Ziehau return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq, cpuid));
6494d28e78fSSepherosa Ziehau }
6504d28e78fSSepherosa Ziehau
6514d28e78fSSepherosa Ziehau /* Pass request to map MSI/MSI-X message up to parent bridge. */
6524d28e78fSSepherosa Ziehau int
pcib_map_msi(device_t pcib,device_t dev,int irq,uint64_t * addr,uint32_t * data,int cpuid)6534d28e78fSSepherosa Ziehau pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
6540af900e1SSepherosa Ziehau uint32_t *data, int cpuid)
6554d28e78fSSepherosa Ziehau {
6564d28e78fSSepherosa Ziehau device_t bus;
6574d28e78fSSepherosa Ziehau int error;
6584d28e78fSSepherosa Ziehau
6594d28e78fSSepherosa Ziehau bus = device_get_parent(pcib);
6600af900e1SSepherosa Ziehau error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data,
6610af900e1SSepherosa Ziehau cpuid);
6624d28e78fSSepherosa Ziehau if (error)
6634d28e78fSSepherosa Ziehau return (error);
6644d28e78fSSepherosa Ziehau
6654d28e78fSSepherosa Ziehau pci_ht_map_msi(pcib, *addr);
6664d28e78fSSepherosa Ziehau return (0);
6674d28e78fSSepherosa Ziehau }
6684d28e78fSSepherosa Ziehau
6694d28e78fSSepherosa Ziehau /*
6704d28e78fSSepherosa Ziehau * Try to read the bus number of a host-PCI bridge using appropriate config
6714d28e78fSSepherosa Ziehau * registers.
6724d28e78fSSepherosa Ziehau */
6734d28e78fSSepherosa Ziehau int
host_pcib_get_busno(pci_read_config_fn read_config,int bus,int slot,int func,uint8_t * busnum)6744d28e78fSSepherosa Ziehau host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
6754d28e78fSSepherosa Ziehau uint8_t *busnum)
6764d28e78fSSepherosa Ziehau {
6774d28e78fSSepherosa Ziehau uint32_t id;
6784d28e78fSSepherosa Ziehau
6794d28e78fSSepherosa Ziehau id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
6804d28e78fSSepherosa Ziehau if (id == 0xffffffff)
6814d28e78fSSepherosa Ziehau return (0);
6824d28e78fSSepherosa Ziehau
6834d28e78fSSepherosa Ziehau switch (id) {
6844d28e78fSSepherosa Ziehau case 0x12258086:
6854d28e78fSSepherosa Ziehau /* Intel 824?? */
6864d28e78fSSepherosa Ziehau /* XXX This is a guess */
6874d28e78fSSepherosa Ziehau /* *busnum = read_config(bus, slot, func, 0x41, 1); */
6884d28e78fSSepherosa Ziehau *busnum = bus;
6894d28e78fSSepherosa Ziehau break;
6904d28e78fSSepherosa Ziehau case 0x84c48086:
6914d28e78fSSepherosa Ziehau /* Intel 82454KX/GX (Orion) */
6924d28e78fSSepherosa Ziehau *busnum = read_config(bus, slot, func, 0x4a, 1);
6934d28e78fSSepherosa Ziehau break;
6944d28e78fSSepherosa Ziehau case 0x84ca8086:
6954d28e78fSSepherosa Ziehau /*
6964d28e78fSSepherosa Ziehau * For the 450nx chipset, there is a whole bundle of
6974d28e78fSSepherosa Ziehau * things pretending to be host bridges. The MIOC will
6984d28e78fSSepherosa Ziehau * be seen first and isn't really a pci bridge (the
6994d28e78fSSepherosa Ziehau * actual busses are attached to the PXB's). We need to
7004d28e78fSSepherosa Ziehau * read the registers of the MIOC to figure out the
7014d28e78fSSepherosa Ziehau * bus numbers for the PXB channels.
7024d28e78fSSepherosa Ziehau *
7034d28e78fSSepherosa Ziehau * Since the MIOC doesn't have a pci bus attached, we
7044d28e78fSSepherosa Ziehau * pretend it wasn't there.
7054d28e78fSSepherosa Ziehau */
7064d28e78fSSepherosa Ziehau return (0);
7074d28e78fSSepherosa Ziehau case 0x84cb8086:
7084d28e78fSSepherosa Ziehau switch (slot) {
7094d28e78fSSepherosa Ziehau case 0x12:
7104d28e78fSSepherosa Ziehau /* Intel 82454NX PXB#0, Bus#A */
7114d28e78fSSepherosa Ziehau *busnum = read_config(bus, 0x10, func, 0xd0, 1);
7124d28e78fSSepherosa Ziehau break;
7134d28e78fSSepherosa Ziehau case 0x13:
7144d28e78fSSepherosa Ziehau /* Intel 82454NX PXB#0, Bus#B */
7154d28e78fSSepherosa Ziehau *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
7164d28e78fSSepherosa Ziehau break;
7174d28e78fSSepherosa Ziehau case 0x14:
7184d28e78fSSepherosa Ziehau /* Intel 82454NX PXB#1, Bus#A */
7194d28e78fSSepherosa Ziehau *busnum = read_config(bus, 0x10, func, 0xd3, 1);
7204d28e78fSSepherosa Ziehau break;
7214d28e78fSSepherosa Ziehau case 0x15:
7224d28e78fSSepherosa Ziehau /* Intel 82454NX PXB#1, Bus#B */
7234d28e78fSSepherosa Ziehau *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
7244d28e78fSSepherosa Ziehau break;
7254d28e78fSSepherosa Ziehau }
7264d28e78fSSepherosa Ziehau break;
7274d28e78fSSepherosa Ziehau
7284d28e78fSSepherosa Ziehau /* ServerWorks -- vendor 0x1166 */
7294d28e78fSSepherosa Ziehau case 0x00051166:
7304d28e78fSSepherosa Ziehau case 0x00061166:
7314d28e78fSSepherosa Ziehau case 0x00081166:
7324d28e78fSSepherosa Ziehau case 0x00091166:
7334d28e78fSSepherosa Ziehau case 0x00101166:
7344d28e78fSSepherosa Ziehau case 0x00111166:
7354d28e78fSSepherosa Ziehau case 0x00171166:
7364d28e78fSSepherosa Ziehau case 0x01011166:
7374d28e78fSSepherosa Ziehau case 0x010f1014:
7384d28e78fSSepherosa Ziehau case 0x02011166:
7394d28e78fSSepherosa Ziehau case 0x03021014:
7404d28e78fSSepherosa Ziehau *busnum = read_config(bus, slot, func, 0x44, 1);
7414d28e78fSSepherosa Ziehau break;
7424d28e78fSSepherosa Ziehau
7434d28e78fSSepherosa Ziehau /* Compaq/HP -- vendor 0x0e11 */
7444d28e78fSSepherosa Ziehau case 0x60100e11:
7454d28e78fSSepherosa Ziehau *busnum = read_config(bus, slot, func, 0xc8, 1);
7464d28e78fSSepherosa Ziehau break;
7474d28e78fSSepherosa Ziehau default:
7484d28e78fSSepherosa Ziehau /* Don't know how to read bus number. */
7494d28e78fSSepherosa Ziehau return 0;
7504d28e78fSSepherosa Ziehau }
7514d28e78fSSepherosa Ziehau
7524d28e78fSSepherosa Ziehau return 1;
7534d28e78fSSepherosa Ziehau }
754