1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: src/sys/dev/pci/pci_pci.c,v 1.50.2.2.4.1 2009/04/15 03:14:26 kensmith Exp $ 31 */ 32 33 /* 34 * PCI:PCI bridge support. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/module.h> 41 #include <sys/bus.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <machine_base/apic/ioapic.h> 45 46 #include <bus/pci/pcivar.h> 47 #include <bus/pci/pcireg.h> 48 #include <bus/pci/pcib_private.h> 49 50 #include "pcib_if.h" 51 52 static int pcib_probe(device_t dev); 53 54 static device_method_t pcib_methods[] = { 55 /* Device interface */ 56 DEVMETHOD(device_probe, pcib_probe), 57 DEVMETHOD(device_attach, pcib_attach), 58 DEVMETHOD(device_detach, bus_generic_detach), 59 DEVMETHOD(device_shutdown, bus_generic_shutdown), 60 DEVMETHOD(device_suspend, bus_generic_suspend), 61 DEVMETHOD(device_resume, bus_generic_resume), 62 63 /* Bus interface */ 64 DEVMETHOD(bus_print_child, bus_generic_print_child), 65 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 66 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 67 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 68 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 69 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 70 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 71 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 72 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 73 74 /* pcib interface */ 75 DEVMETHOD(pcib_maxslots, pcib_maxslots), 76 DEVMETHOD(pcib_read_config, pcib_read_config), 77 DEVMETHOD(pcib_write_config, pcib_write_config), 78 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 79 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 80 DEVMETHOD(pcib_release_msi, pcib_release_msi), 81 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 82 DEVMETHOD(pcib_release_msix, pcib_release_msix), 83 DEVMETHOD(pcib_map_msi, pcib_map_msi), 84 85 { 0, 0 } 86 }; 87 88 static devclass_t pcib_devclass; 89 90 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 91 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 92 93 /* 94 * Is the prefetch window open (eg, can we allocate memory in it?) 95 */ 96 static int 97 pcib_is_prefetch_open(struct pcib_softc *sc) 98 { 99 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 100 } 101 102 /* 103 * Is the nonprefetch window open (eg, can we allocate memory in it?) 104 */ 105 static int 106 pcib_is_nonprefetch_open(struct pcib_softc *sc) 107 { 108 return (sc->membase > 0 && sc->membase < sc->memlimit); 109 } 110 111 /* 112 * Is the io window open (eg, can we allocate ports in it?) 113 */ 114 static int 115 pcib_is_io_open(struct pcib_softc *sc) 116 { 117 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 118 } 119 120 /* 121 * Generic device interface 122 */ 123 static int 124 pcib_probe(device_t dev) 125 { 126 if ((pci_get_class(dev) == PCIC_BRIDGE) && 127 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 128 device_set_desc(dev, "PCI-PCI bridge"); 129 #if defined(__i386__) || defined(__x86_64__) 130 #ifdef SMP 131 /* PCIBIOS PCI-PCI bridge is -2000 */ 132 if (ioapic_enable) 133 return (-1000); 134 #endif 135 #endif 136 return (-10000); 137 } 138 return(ENXIO); 139 } 140 141 void 142 pcib_attach_common(device_t dev) 143 { 144 struct pcib_softc *sc; 145 uint8_t iolow; 146 147 sc = device_get_softc(dev); 148 sc->dev = dev; 149 150 /* 151 * Get current bridge configuration. 152 */ 153 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 154 sc->domain = pci_get_domain(dev); 155 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 156 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 157 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 158 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 159 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 160 161 /* 162 * Determine current I/O decode. 163 */ 164 if (sc->command & PCIM_CMD_PORTEN) { 165 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 166 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 167 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 168 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 169 } else { 170 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 171 } 172 173 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 174 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 175 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 176 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 177 } else { 178 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 179 } 180 } 181 182 /* 183 * Determine current memory decode. 184 */ 185 if (sc->command & PCIM_CMD_MEMEN) { 186 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 187 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 188 iolow = pci_read_config(dev, PCIR_PMBASEL_1, 1); 189 if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 190 sc->pmembase = PCI_PPBMEMBASE( 191 pci_read_config(dev, PCIR_PMBASEH_1, 4), 192 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 193 else 194 sc->pmembase = PCI_PPBMEMBASE(0, 195 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 196 iolow = pci_read_config(dev, PCIR_PMLIMITL_1, 1); 197 if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 198 sc->pmemlimit = PCI_PPBMEMLIMIT( 199 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 200 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 201 else 202 sc->pmemlimit = PCI_PPBMEMLIMIT(0, 203 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 204 } 205 206 /* 207 * Quirk handling. 208 */ 209 switch (pci_get_devid(dev)) { 210 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 211 { 212 uint8_t supbus; 213 214 supbus = pci_read_config(dev, 0x41, 1); 215 if (supbus != 0xff) { 216 sc->secbus = supbus + 1; 217 sc->subbus = supbus + 1; 218 } 219 break; 220 } 221 222 /* 223 * The i82380FB mobile docking controller is a PCI-PCI bridge, 224 * and it is a subtractive bridge. However, the ProgIf is wrong 225 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 226 * happen. There's also a Toshiba bridge that behaves this 227 * way. 228 */ 229 case 0x124b8086: /* Intel 82380FB Mobile */ 230 case 0x060513d7: /* Toshiba ???? */ 231 sc->flags |= PCIB_SUBTRACTIVE; 232 break; 233 234 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 235 case 0x00dd10de: 236 { 237 char *cp; 238 239 if ((cp = kgetenv("smbios.planar.maker")) == NULL) 240 break; 241 if (strncmp(cp, "Compal", 6) != 0) { 242 kfreeenv(cp); 243 break; 244 } 245 kfreeenv(cp); 246 if ((cp = kgetenv("smbios.planar.product")) == NULL) 247 break; 248 if (strncmp(cp, "08A0", 4) != 0) { 249 kfreeenv(cp); 250 break; 251 } 252 kfreeenv(cp); 253 if (sc->subbus < 0xa) { 254 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 255 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 256 } 257 break; 258 } 259 } 260 261 if (pci_msi_device_blacklisted(dev)) 262 sc->flags |= PCIB_DISABLE_MSI; 263 264 /* 265 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 266 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 267 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 268 * This means they act as if they were subtractively decoding 269 * bridges and pass all transactions. Mark them and real ProgIf 1 270 * parts as subtractive. 271 */ 272 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 273 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 274 sc->flags |= PCIB_SUBTRACTIVE; 275 276 if (bootverbose) { 277 device_printf(dev, " domain %d\n", sc->domain); 278 device_printf(dev, " secondary bus %d\n", sc->secbus); 279 device_printf(dev, " subordinate bus %d\n", sc->subbus); 280 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 281 if (pcib_is_nonprefetch_open(sc)) 282 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 283 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 284 if (pcib_is_prefetch_open(sc)) 285 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 286 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 287 else 288 device_printf(dev, " no prefetched decode\n"); 289 if (sc->flags & PCIB_SUBTRACTIVE) 290 device_printf(dev, " Subtractively decoded bridge.\n"); 291 } 292 293 if (pci_is_pcie(dev) && pcie_slot_implemented(dev)) { 294 uint16_t slot_ctrl; 295 uint8_t ptr; 296 297 /* 298 * XXX 299 * Before proper PCI Express hot-plug support is in place, 300 * disable all hot-plug interrupts on the PCI Express root 301 * port or down stream port for now. 302 */ 303 #define HPINTRS (PCIEM_SLTCTL_HPINTR_MASK | PCIEM_SLTCTL_HPINTR_EN) 304 305 ptr = pci_get_pciecap_ptr(dev); 306 slot_ctrl = pci_read_config(dev, ptr + PCIER_SLOTCTRL, 2); 307 if (slot_ctrl & HPINTRS) { 308 device_printf(dev, "Disable PCI Express hot-plug " 309 "interrupts(0x%04x)\n", slot_ctrl & HPINTRS); 310 slot_ctrl &= ~HPINTRS; 311 pci_write_config(dev, ptr + PCIER_SLOTCTRL, slot_ctrl, 2); 312 } 313 314 #undef HPINTRS 315 } 316 317 /* 318 * XXX If the secondary bus number is zero, we should assign a bus number 319 * since the BIOS hasn't, then initialise the bridge. 320 */ 321 322 /* 323 * XXX If the subordinate bus number is less than the secondary bus number, 324 * we should pick a better value. One sensible alternative would be to 325 * pick 255; the only tradeoff here is that configuration transactions 326 * would be more widely routed than absolutely necessary. 327 */ 328 } 329 330 int 331 pcib_attach(device_t dev) 332 { 333 struct pcib_softc *sc; 334 device_t child; 335 336 pcib_attach_common(dev); 337 sc = device_get_softc(dev); 338 if (sc->secbus != 0) { 339 child = device_add_child(dev, "pci", sc->secbus); 340 if (child != NULL) 341 return(bus_generic_attach(dev)); 342 } 343 344 /* no secondary bus; we should have fixed this */ 345 return(0); 346 } 347 348 int 349 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 350 { 351 struct pcib_softc *sc = device_get_softc(dev); 352 353 switch (which) { 354 case PCIB_IVAR_DOMAIN: 355 *result = sc->domain; 356 return(0); 357 case PCIB_IVAR_BUS: 358 *result = sc->secbus; 359 return(0); 360 } 361 return(ENOENT); 362 } 363 364 int 365 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 366 { 367 struct pcib_softc *sc = device_get_softc(dev); 368 369 switch (which) { 370 case PCIB_IVAR_DOMAIN: 371 return(EINVAL); 372 case PCIB_IVAR_BUS: 373 sc->secbus = value; 374 return(0); 375 } 376 return(ENOENT); 377 } 378 379 /* 380 * We have to trap resource allocation requests and ensure that the bridge 381 * is set up to, or capable of handling them. 382 */ 383 struct resource * 384 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 385 u_long start, u_long end, u_long count, u_int flags) 386 { 387 struct pcib_softc *sc = device_get_softc(dev); 388 const char *name, *suffix; 389 int ok; 390 391 /* 392 * Fail the allocation for this range if it's not supported. 393 */ 394 name = device_get_nameunit(child); 395 if (name == NULL) { 396 name = ""; 397 suffix = ""; 398 } else 399 suffix = " "; 400 switch (type) { 401 case SYS_RES_IOPORT: 402 ok = 0; 403 if (!pcib_is_io_open(sc)) 404 break; 405 ok = (start >= sc->iobase && end <= sc->iolimit); 406 407 /* 408 * Make sure we allow access to VGA I/O addresses when the 409 * bridge has the "VGA Enable" bit set. 410 */ 411 if (!ok && pci_is_vga_ioport_range(start, end)) 412 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 413 414 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 415 if (!ok) { 416 if (start < sc->iobase) 417 start = sc->iobase; 418 if (end > sc->iolimit) 419 end = sc->iolimit; 420 if (start < end) 421 ok = 1; 422 } 423 } else { 424 ok = 1; 425 #if 1 426 if (start < sc->iobase && end > sc->iolimit) { 427 start = sc->iobase; 428 end = sc->iolimit; 429 } 430 #endif 431 } 432 if (end < start) { 433 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 434 end, start); 435 start = 0; 436 end = 0; 437 ok = 0; 438 } 439 if (!ok) { 440 device_printf(dev, "%s%srequested unsupported I/O " 441 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 442 name, suffix, start, end, sc->iobase, sc->iolimit); 443 return (NULL); 444 } 445 if (bootverbose) 446 device_printf(dev, 447 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 448 name, suffix, start, end); 449 break; 450 451 case SYS_RES_MEMORY: 452 ok = 0; 453 if (pcib_is_nonprefetch_open(sc)) 454 ok = ok || (start >= sc->membase && end <= sc->memlimit); 455 if (pcib_is_prefetch_open(sc)) 456 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 457 458 /* 459 * Make sure we allow access to VGA memory addresses when the 460 * bridge has the "VGA Enable" bit set. 461 */ 462 if (!ok && pci_is_vga_memory_range(start, end)) 463 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 464 465 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 466 if (!ok) { 467 ok = 1; 468 if (flags & RF_PREFETCHABLE) { 469 if (pcib_is_prefetch_open(sc)) { 470 if (start < sc->pmembase) 471 start = sc->pmembase; 472 if (end > sc->pmemlimit) 473 end = sc->pmemlimit; 474 } else { 475 ok = 0; 476 } 477 } else { /* non-prefetchable */ 478 if (pcib_is_nonprefetch_open(sc)) { 479 if (start < sc->membase) 480 start = sc->membase; 481 if (end > sc->memlimit) 482 end = sc->memlimit; 483 } else { 484 ok = 0; 485 } 486 } 487 } 488 } else if (!ok) { 489 ok = 1; /* subtractive bridge: always ok */ 490 #if 1 491 if (pcib_is_nonprefetch_open(sc)) { 492 if (start < sc->membase && end > sc->memlimit) { 493 start = sc->membase; 494 end = sc->memlimit; 495 } 496 } 497 if (pcib_is_prefetch_open(sc)) { 498 if (start < sc->pmembase && end > sc->pmemlimit) { 499 start = sc->pmembase; 500 end = sc->pmemlimit; 501 } 502 } 503 #endif 504 } 505 if (end < start) { 506 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 507 end, start); 508 start = 0; 509 end = 0; 510 ok = 0; 511 } 512 if (!ok && bootverbose) 513 device_printf(dev, 514 "%s%srequested unsupported memory range %#lx-%#lx " 515 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 516 name, suffix, start, end, 517 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 518 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 519 if (!ok) 520 return (NULL); 521 if (bootverbose) 522 device_printf(dev,"%s%srequested memory range " 523 "0x%lx-0x%lx: good\n", 524 name, suffix, start, end); 525 break; 526 527 default: 528 break; 529 } 530 /* 531 * Bridge is OK decoding this resource, so pass it up. 532 */ 533 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 534 count, flags)); 535 } 536 537 /* 538 * PCIB interface. 539 */ 540 int 541 pcib_maxslots(device_t dev) 542 { 543 return(PCI_SLOTMAX); 544 } 545 546 /* 547 * Since we are a child of a PCI bus, its parent must support the pcib interface. 548 */ 549 uint32_t 550 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 551 { 552 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 553 } 554 555 void 556 pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width) 557 { 558 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 559 } 560 561 /* 562 * Route an interrupt across a PCI bridge. 563 */ 564 int 565 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 566 { 567 device_t bus; 568 int parent_intpin; 569 int intnum; 570 571 /* 572 * 573 * The PCI standard defines a swizzle of the child-side device/intpin to 574 * the parent-side intpin as follows. 575 * 576 * device = device on child bus 577 * child_intpin = intpin on child bus slot (0-3) 578 * parent_intpin = intpin on parent bus slot (0-3) 579 * 580 * parent_intpin = (device + child_intpin) % 4 581 */ 582 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 583 584 /* 585 * Our parent is a PCI bus. Its parent must export the pcib interface 586 * which includes the ability to route interrupts. 587 */ 588 bus = device_get_parent(pcib); 589 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 590 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 591 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 592 pci_get_slot(dev), 'A' + pin - 1, intnum); 593 } 594 return(intnum); 595 } 596 597 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 598 int 599 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 600 { 601 struct pcib_softc *sc = device_get_softc(pcib); 602 device_t bus; 603 604 if (sc->flags & PCIB_DISABLE_MSI) 605 return (ENXIO); 606 bus = device_get_parent(pcib); 607 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 608 irqs)); 609 } 610 611 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 612 int 613 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 614 { 615 device_t bus; 616 617 bus = device_get_parent(pcib); 618 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 619 } 620 621 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 622 int 623 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 624 { 625 struct pcib_softc *sc = device_get_softc(pcib); 626 device_t bus; 627 628 if (sc->flags & PCIB_DISABLE_MSI) 629 return (ENXIO); 630 bus = device_get_parent(pcib); 631 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 632 } 633 634 /* Pass request to release an MSI-X message up to the parent bridge. */ 635 int 636 pcib_release_msix(device_t pcib, device_t dev, int irq) 637 { 638 device_t bus; 639 640 bus = device_get_parent(pcib); 641 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 642 } 643 644 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 645 int 646 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 647 uint32_t *data) 648 { 649 device_t bus; 650 int error; 651 652 bus = device_get_parent(pcib); 653 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 654 if (error) 655 return (error); 656 657 pci_ht_map_msi(pcib, *addr); 658 return (0); 659 } 660 661 /* 662 * Try to read the bus number of a host-PCI bridge using appropriate config 663 * registers. 664 */ 665 int 666 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 667 uint8_t *busnum) 668 { 669 uint32_t id; 670 671 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 672 if (id == 0xffffffff) 673 return (0); 674 675 switch (id) { 676 case 0x12258086: 677 /* Intel 824?? */ 678 /* XXX This is a guess */ 679 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 680 *busnum = bus; 681 break; 682 case 0x84c48086: 683 /* Intel 82454KX/GX (Orion) */ 684 *busnum = read_config(bus, slot, func, 0x4a, 1); 685 break; 686 case 0x84ca8086: 687 /* 688 * For the 450nx chipset, there is a whole bundle of 689 * things pretending to be host bridges. The MIOC will 690 * be seen first and isn't really a pci bridge (the 691 * actual busses are attached to the PXB's). We need to 692 * read the registers of the MIOC to figure out the 693 * bus numbers for the PXB channels. 694 * 695 * Since the MIOC doesn't have a pci bus attached, we 696 * pretend it wasn't there. 697 */ 698 return (0); 699 case 0x84cb8086: 700 switch (slot) { 701 case 0x12: 702 /* Intel 82454NX PXB#0, Bus#A */ 703 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 704 break; 705 case 0x13: 706 /* Intel 82454NX PXB#0, Bus#B */ 707 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 708 break; 709 case 0x14: 710 /* Intel 82454NX PXB#1, Bus#A */ 711 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 712 break; 713 case 0x15: 714 /* Intel 82454NX PXB#1, Bus#B */ 715 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 716 break; 717 } 718 break; 719 720 /* ServerWorks -- vendor 0x1166 */ 721 case 0x00051166: 722 case 0x00061166: 723 case 0x00081166: 724 case 0x00091166: 725 case 0x00101166: 726 case 0x00111166: 727 case 0x00171166: 728 case 0x01011166: 729 case 0x010f1014: 730 case 0x02011166: 731 case 0x03021014: 732 *busnum = read_config(bus, slot, func, 0x44, 1); 733 break; 734 735 /* Compaq/HP -- vendor 0x0e11 */ 736 case 0x60100e11: 737 *busnum = read_config(bus, slot, func, 0xc8, 1); 738 break; 739 default: 740 /* Don't know how to read bus number. */ 741 return 0; 742 } 743 744 return 1; 745 } 746