1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/pci/pcireg.h,v 1.64.2.4.2.1 2009/04/15 03:14:26 kensmith Exp $ 27 */ 28 29 #ifndef _PCIREG_H_ 30 #define _PCIREG_H_ 31 32 #ifndef _SYS_TYPES_H_ 33 #include <sys/types.h> 34 #endif 35 36 typedef u_int16_t pci_vendor_id_t; 37 typedef u_int16_t pci_product_id_t; 38 typedef u_int8_t pci_class_t; 39 typedef u_int8_t pci_subclass_t; 40 typedef u_int8_t pci_interface_t; 41 typedef u_int8_t pci_revision_t; 42 typedef u_int8_t pci_intr_pin_t; 43 typedef u_int8_t pci_intr_line_t; 44 typedef u_int32_t pcireg_t; /* ~typical configuration space */ 45 46 /* 47 * PCIM_xxx: mask to locate subfield in register 48 * PCIR_xxx: config register offset 49 * PCIC_xxx: device class 50 * PCIS_xxx: device subclass 51 * PCIP_xxx: device programming interface 52 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 53 * PCID_xxx: device ID 54 * PCIY_xxx: capability identification number 55 * PCIZ_xxx: extended capability identification number 56 */ 57 58 /* some PCI bus constants */ 59 60 #define PCI_BUSMAX 255 61 #define PCI_SLOTMAX 31 62 #define PCI_FUNCMAX 7 63 #define PCI_REGMAX 255 64 #define PCIE_REGMAX 4095 65 #define PCI_MAXHDRTYPE 2 66 67 /* PCI config header registers for all devices */ 68 69 #define PCIR_DEVVENDOR 0x00 70 #define PCIR_VENDOR 0x00 71 #define PCIR_DEVICE 0x02 72 #define PCIR_COMMAND 0x04 73 #define PCIR_CARDBUSCIS 0x28 74 #define PCIM_CMD_PORTEN 0x0001 75 #define PCIM_CMD_MEMEN 0x0002 76 #define PCIM_CMD_BUSMASTEREN 0x0004 77 #define PCIM_CMD_SPECIALEN 0x0008 78 #define PCIM_CMD_MWRICEN 0x0010 79 #define PCIM_CMD_PERRESPEN 0x0040 80 #define PCIM_CMD_SERRESPEN 0x0100 81 #define PCIM_CMD_BACKTOBACK 0x0200 82 #define PCIM_CMD_INTxDIS 0x0400 83 #define PCIR_STATUS 0x06 84 #define PCIM_STATUS_INTxSTATE 0x0008 85 #define PCIM_STATUS_CAPPRESENT 0x0010 86 #define PCIM_STATUS_66CAPABLE 0x0020 87 #define PCIM_STATUS_BACKTOBACK 0x0080 88 #define PCIM_STATUS_PERRREPORT 0x0100 89 #define PCIM_STATUS_SEL_FAST 0x0000 90 #define PCIM_STATUS_SEL_MEDIMUM 0x0200 91 #define PCIM_STATUS_SEL_SLOW 0x0400 92 #define PCIM_STATUS_SEL_MASK 0x0600 93 #define PCIM_STATUS_STABORT 0x0800 94 #define PCIM_STATUS_RTABORT 0x1000 95 #define PCIM_STATUS_RMABORT 0x2000 96 #define PCIM_STATUS_SERR 0x4000 97 #define PCIM_STATUS_PERR 0x8000 98 #define PCIR_REVID 0x08 99 #define PCIR_PROGIF 0x09 100 #define PCIR_SUBCLASS 0x0a 101 #define PCIR_CLASS 0x0b 102 #define PCIR_CACHELNSZ 0x0c 103 #define PCIR_LATTIMER 0x0d 104 #define PCIR_HDRTYPE 0x0e 105 #define PCIM_HDRTYPE 0x7f 106 #define PCIM_HDRTYPE_NORMAL 0x00 107 #define PCIM_HDRTYPE_BRIDGE 0x01 108 #define PCIM_HDRTYPE_CARDBUS 0x02 109 #define PCIM_MFDEV 0x80 110 #define PCIR_BIST 0x0f 111 112 /* Capability Register Offsets */ 113 114 #define PCICAP_ID 0x0 115 #define PCICAP_NEXTPTR 0x1 116 117 /* Capability Identification Numbers */ 118 119 #define PCIY_PMG 0x01 /* PCI Power Management */ 120 #define PCIY_AGP 0x02 /* AGP */ 121 #define PCIY_VPD 0x03 /* Vital Product Data */ 122 #define PCIY_SLOTID 0x04 /* Slot Identification */ 123 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 124 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 125 #define PCIY_PCIX 0x07 /* PCI-X */ 126 #define PCIY_HT 0x08 /* HyperTransport */ 127 #define PCIY_VENDOR 0x09 /* Vendor Unique */ 128 #define PCIY_DEBUG 0x0a /* Debug port */ 129 #define PCIY_CRES 0x0b /* CompactPCI central resource control */ 130 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 131 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 132 #define PCIY_AGP8X 0x0e /* AGP 8x */ 133 #define PCIY_SECDEV 0x0f /* Secure Device */ 134 #define PCIY_EXPRESS 0x10 /* PCI Express */ 135 #define PCIY_MSIX 0x11 /* MSI-X */ 136 #define PCIY_SATA 0x12 /* SATA */ 137 #define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 138 139 /* Extended Capability Register Fields */ 140 141 #define PCIR_EXTCAP 0x100 142 #define PCIM_EXTCAP_ID 0x0000ffff 143 #define PCIM_EXTCAP_VER 0x000f0000 144 #define PCIM_EXTCAP_NEXTPTR 0xfff00000 145 #define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) 146 #define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) 147 #define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) 148 149 /* Extended Capability Identification Numbers */ 150 151 #define PCIZ_AER 0x0001 /* Advanced Error Reporting */ 152 #define PCIZ_VC 0x0002 /* Virtual Channel */ 153 #define PCIZ_SERNUM 0x0003 /* Device Serial Number */ 154 #define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ 155 #define PCIZ_VENDOR 0x000b /* Vendor Unique */ 156 #define PCIZ_ACS 0x000d /* Access Control Services */ 157 #define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ 158 #define PCIZ_ATS 0x000f /* Address Translation Services */ 159 #define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ 160 161 /* config registers for header type 0 devices */ 162 163 #define PCIR_BARS 0x10 164 #define PCIR_MAPS PCIR_BARS 165 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 166 #define PCIR_MAX_BAR_0 5 167 #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 168 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 169 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 170 #define PCIM_BAR_SPACE 0x00000001 171 #define PCIM_BAR_MEM_SPACE 0 172 #define PCIM_BAR_IO_SPACE 1 173 #define PCIM_BAR_MEM_TYPE 0x00000006 174 #define PCIM_BAR_MEM_32 0 175 #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 176 #define PCIM_BAR_MEM_64 4 177 #define PCIM_BAR_MEM_PREFETCH 0x00000008 178 #define PCIM_BAR_MEM_BASE 0xfffffff0 179 #define PCIM_BAR_IO_RESERVED 0x00000002 180 #define PCIM_BAR_IO_BASE 0xfffffffc 181 #define PCIR_CIS 0x28 182 #define PCIM_CIS_ASI_MASK 0x7 183 #define PCIM_CIS_ASI_CONFIG 0 184 #define PCIM_CIS_ASI_BAR0 1 185 #define PCIM_CIS_ASI_BAR1 2 186 #define PCIM_CIS_ASI_BAR2 3 187 #define PCIM_CIS_ASI_BAR3 4 188 #define PCIM_CIS_ASI_BAR4 5 189 #define PCIM_CIS_ASI_BAR5 6 190 #define PCIM_CIS_ASI_ROM 7 191 #define PCIM_CIS_ADDR_MASK 0x0ffffff8 192 #define PCIM_CIS_ROM_MASK 0xf0000000 193 #define PCIM_CIS_CONFIG_MASK 0xff 194 #define PCIR_SUBVEND_0 0x2c 195 #define PCIR_SUBDEV_0 0x2e 196 #define PCIR_BIOS 0x30 197 #define PCIM_BIOS_ENABLE 0x01 198 #define PCIM_BIOS_ADDR_MASK 0xfffff800 199 #define PCIR_CAP_PTR 0x34 200 #define PCIR_INTLINE 0x3c 201 #define PCIR_INTPIN 0x3d 202 #define PCIR_MINGNT 0x3e 203 #define PCIR_MAXLAT 0x3f 204 205 /* config registers for header type 1 (PCI-to-PCI bridge) devices */ 206 207 #define PCIR_MAX_BAR_1 1 208 #define PCIR_SECSTAT_1 0x1e 209 210 #define PCIR_PRIBUS_1 0x18 211 #define PCIR_SECBUS_1 0x19 212 #define PCIR_SUBBUS_1 0x1a 213 #define PCIR_SECLAT_1 0x1b 214 215 #define PCIR_IOBASEL_1 0x1c 216 #define PCIR_IOLIMITL_1 0x1d 217 #define PCIR_IOBASEH_1 0x30 218 #define PCIR_IOLIMITH_1 0x32 219 #define PCIM_BRIO_16 0x0 220 #define PCIM_BRIO_32 0x1 221 #define PCIM_BRIO_MASK 0xf 222 223 #define PCIR_MEMBASE_1 0x20 224 #define PCIR_MEMLIMIT_1 0x22 225 226 #define PCIR_PMBASEL_1 0x24 227 #define PCIR_PMLIMITL_1 0x26 228 #define PCIR_PMBASEH_1 0x28 229 #define PCIR_PMLIMITH_1 0x2c 230 #define PCIM_BRPM_32 0x0 231 #define PCIM_BRPM_64 0x1 232 #define PCIM_BRPM_MASK 0xf 233 234 #define PCIR_BRIDGECTL_1 0x3e 235 236 /* config registers for header type 2 (CardBus) devices */ 237 238 #define PCIR_MAX_BAR_2 0 239 #define PCIR_CAP_PTR_2 0x14 240 #define PCIR_SECSTAT_2 0x16 241 242 #define PCIR_PRIBUS_2 0x18 243 #define PCIR_SECBUS_2 0x19 244 #define PCIR_SUBBUS_2 0x1a 245 #define PCIR_SECLAT_2 0x1b 246 247 #define PCIR_MEMBASE0_2 0x1c 248 #define PCIR_MEMLIMIT0_2 0x20 249 #define PCIR_MEMBASE1_2 0x24 250 #define PCIR_MEMLIMIT1_2 0x28 251 #define PCIR_IOBASE0_2 0x2c 252 #define PCIR_IOLIMIT0_2 0x30 253 #define PCIR_IOBASE1_2 0x34 254 #define PCIR_IOLIMIT1_2 0x38 255 256 #define PCIR_BRIDGECTL_2 0x3e 257 258 #define PCIR_SUBVEND_2 0x40 259 #define PCIR_SUBDEV_2 0x42 260 261 #define PCIR_PCCARDIF_2 0x44 262 263 /* PCI device class, subclass and programming interface definitions */ 264 265 #define PCIC_OLD 0x00 266 #define PCIS_OLD_NONVGA 0x00 267 #define PCIS_OLD_VGA 0x01 268 269 #define PCIC_STORAGE 0x01 270 #define PCIS_STORAGE_SCSI 0x00 271 #define PCIS_STORAGE_IDE 0x01 272 #define PCIP_STORAGE_IDE_MODEPRIM 0x01 273 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 274 #define PCIP_STORAGE_IDE_MODESEC 0x04 275 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 276 #define PCIP_STORAGE_IDE_MASTERDEV 0x80 277 #define PCIS_STORAGE_FLOPPY 0x02 278 #define PCIS_STORAGE_IPI 0x03 279 #define PCIS_STORAGE_RAID 0x04 280 #define PCIS_STORAGE_ATA_ADMA 0x05 281 #define PCIS_STORAGE_SATA 0x06 282 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01 283 #define PCIS_STORAGE_SAS 0x07 284 #define PCIS_STORAGE_NVM 0x08 285 #define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01 286 #define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02 287 #define PCIS_STORAGE_OTHER 0x80 288 289 #define PCIC_NETWORK 0x02 290 #define PCIS_NETWORK_ETHERNET 0x00 291 #define PCIS_NETWORK_TOKENRING 0x01 292 #define PCIS_NETWORK_FDDI 0x02 293 #define PCIS_NETWORK_ATM 0x03 294 #define PCIS_NETWORK_ISDN 0x04 295 #define PCIS_NETWORK_WORLDFIP 0x05 296 #define PCIS_NETWORK_PICMG 0x06 297 #define PCIS_NETWORK_OTHER 0x80 298 299 #define PCIC_DISPLAY 0x03 300 #define PCIS_DISPLAY_VGA 0x00 301 #define PCIS_DISPLAY_XGA 0x01 302 #define PCIS_DISPLAY_3D 0x02 303 #define PCIS_DISPLAY_OTHER 0x80 304 305 #define PCIC_MULTIMEDIA 0x04 306 #define PCIS_MULTIMEDIA_VIDEO 0x00 307 #define PCIS_MULTIMEDIA_AUDIO 0x01 308 #define PCIS_MULTIMEDIA_TELE 0x02 309 #define PCIS_MULTIMEDIA_HDA 0x03 310 #define PCIS_MULTIMEDIA_OTHER 0x80 311 312 #define PCIC_MEMORY 0x05 313 #define PCIS_MEMORY_RAM 0x00 314 #define PCIS_MEMORY_FLASH 0x01 315 #define PCIS_MEMORY_OTHER 0x80 316 317 #define PCIC_BRIDGE 0x06 318 #define PCIS_BRIDGE_HOST 0x00 319 #define PCIS_BRIDGE_ISA 0x01 320 #define PCIS_BRIDGE_EISA 0x02 321 #define PCIS_BRIDGE_MCA 0x03 322 #define PCIS_BRIDGE_PCI 0x04 323 #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 324 #define PCIS_BRIDGE_PCMCIA 0x05 325 #define PCIS_BRIDGE_NUBUS 0x06 326 #define PCIS_BRIDGE_CARDBUS 0x07 327 #define PCIS_BRIDGE_RACEWAY 0x08 328 #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 329 #define PCIS_BRIDGE_INFINIBAND 0x0a 330 #define PCIS_BRIDGE_OTHER 0x80 331 332 #define PCIC_SIMPLECOMM 0x07 333 #define PCIS_SIMPLECOMM_UART 0x00 334 #define PCIP_SIMPLECOMM_UART_8250 0x00 335 #define PCIP_SIMPLECOMM_UART_16450A 0x01 336 #define PCIP_SIMPLECOMM_UART_16550A 0x02 337 #define PCIP_SIMPLECOMM_UART_16650A 0x03 338 #define PCIP_SIMPLECOMM_UART_16750A 0x04 339 #define PCIP_SIMPLECOMM_UART_16850A 0x05 340 #define PCIP_SIMPLECOMM_UART_16950A 0x06 341 #define PCIS_SIMPLECOMM_PAR 0x01 342 #define PCIS_SIMPLECOMM_MULSER 0x02 343 #define PCIS_SIMPLECOMM_MODEM 0x03 344 #define PCIS_SIMPLECOMM_GPIB 0x04 345 #define PCIS_SIMPLECOMM_SMART_CARD 0x05 346 #define PCIS_SIMPLECOMM_OTHER 0x80 347 348 #define PCIC_BASEPERIPH 0x08 349 #define PCIS_BASEPERIPH_PIC 0x00 350 #define PCIP_BASEPERIPH_PIC_8259A 0x00 351 #define PCIP_BASEPERIPH_PIC_ISA 0x01 352 #define PCIP_BASEPERIPH_PIC_EISA 0x02 353 #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 354 #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 355 #define PCIS_BASEPERIPH_DMA 0x01 356 #define PCIS_BASEPERIPH_TIMER 0x02 357 #define PCIS_BASEPERIPH_RTC 0x03 358 #define PCIS_BASEPERIPH_PCIHOT 0x04 359 #define PCIS_BASEPERIPH_SDHC 0x05 360 #define PCIS_BASEPERIPH_OTHER 0x80 361 362 #define PCIC_INPUTDEV 0x09 363 #define PCIS_INPUTDEV_KEYBOARD 0x00 364 #define PCIS_INPUTDEV_DIGITIZER 0x01 365 #define PCIS_INPUTDEV_MOUSE 0x02 366 #define PCIS_INPUTDEV_SCANNER 0x03 367 #define PCIS_INPUTDEV_GAMEPORT 0x04 368 #define PCIS_INPUTDEV_OTHER 0x80 369 370 #define PCIC_DOCKING 0x0a 371 #define PCIS_DOCKING_GENERIC 0x00 372 #define PCIS_DOCKING_OTHER 0x80 373 374 #define PCIC_PROCESSOR 0x0b 375 #define PCIS_PROCESSOR_386 0x00 376 #define PCIS_PROCESSOR_486 0x01 377 #define PCIS_PROCESSOR_PENTIUM 0x02 378 #define PCIS_PROCESSOR_ALPHA 0x10 379 #define PCIS_PROCESSOR_POWERPC 0x20 380 #define PCIS_PROCESSOR_MIPS 0x30 381 #define PCIS_PROCESSOR_COPROC 0x40 382 383 #define PCIC_SERIALBUS 0x0c 384 #define PCIS_SERIALBUS_FW 0x00 385 #define PCIS_SERIALBUS_ACCESS 0x01 386 #define PCIS_SERIALBUS_SSA 0x02 387 #define PCIS_SERIALBUS_USB 0x03 388 #define PCIP_SERIALBUS_USB_UHCI 0x00 389 #define PCIP_SERIALBUS_USB_OHCI 0x10 390 #define PCIP_SERIALBUS_USB_EHCI 0x20 391 #define PCIP_SERIALBUS_USB_XHCI 0x30 392 #define PCIP_SERIALBUS_USB_DEVICE 0xfe 393 #define PCIS_SERIALBUS_FC 0x04 394 #define PCIS_SERIALBUS_SMBUS 0x05 395 #define PCIS_SERIALBUS_INFINIBAND 0x06 396 #define PCIS_SERIALBUS_IPMI 0x07 397 #define PCIP_SERIALBUS_IPMI_SMIC 0x00 398 #define PCIP_SERIALBUS_IPMI_KCS 0x01 399 #define PCIP_SERIALBUS_IPMI_BT 0x02 400 #define PCIS_SERIALBUS_SERCOS 0x08 401 #define PCIS_SERIALBUS_CANBUS 0x09 402 403 #define PCIC_WIRELESS 0x0d 404 #define PCIS_WIRELESS_IRDA 0x00 405 #define PCIS_WIRELESS_IR 0x01 406 #define PCIS_WIRELESS_RF 0x10 407 #define PCIS_WIRELESS_BLUETOOTH 0x11 408 #define PCIS_WIRELESS_BROADBAND 0x12 409 #define PCIS_WIRELESS_80211A 0x20 410 #define PCIS_WIRELESS_80211B 0x21 411 #define PCIS_WIRELESS_OTHER 0x80 412 413 #define PCIC_INTELLIIO 0x0e 414 #define PCIS_INTELLIIO_I2O 0x00 415 416 #define PCIC_SATCOM 0x0f 417 #define PCIS_SATCOM_TV 0x01 418 #define PCIS_SATCOM_AUDIO 0x02 419 #define PCIS_SATCOM_VOICE 0x03 420 #define PCIS_SATCOM_DATA 0x04 421 422 #define PCIC_CRYPTO 0x10 423 #define PCIS_CRYPTO_NETCOMP 0x00 424 #define PCIS_CRYPTO_ENTERTAIN 0x10 425 #define PCIS_CRYPTO_OTHER 0x80 426 427 #define PCIC_DASP 0x11 428 #define PCIS_DASP_DPIO 0x00 429 #define PCIS_DASP_PERFCNTRS 0x01 430 #define PCIS_DASP_COMM_SYNC 0x10 431 #define PCIS_DASP_MGMT_CARD 0x20 432 #define PCIS_DASP_OTHER 0x80 433 434 #define PCIC_OTHER 0xff 435 436 /* Bridge Control Values. */ 437 #define PCIB_BCR_PERR_ENABLE 0x0001 438 #define PCIB_BCR_SERR_ENABLE 0x0002 439 #define PCIB_BCR_ISA_ENABLE 0x0004 440 #define PCIB_BCR_VGA_ENABLE 0x0008 441 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020 442 #define PCIB_BCR_SECBUS_RESET 0x0040 443 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 444 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 445 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 446 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 447 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 448 449 /* PCI power manangement */ 450 #define PCIR_POWER_CAP 0x2 451 #define PCIM_PCAP_SPEC 0x0007 452 #define PCIM_PCAP_PMEREQCLK 0x0008 453 #define PCIM_PCAP_PMEREQPWR 0x0010 454 #define PCIM_PCAP_DEVSPECINIT 0x0020 455 #define PCIM_PCAP_DYNCLOCK 0x0040 456 #define PCIM_PCAP_SECCLOCK 0x00c0 457 #define PCIM_PCAP_CLOCKMASK 0x00c0 458 #define PCIM_PCAP_REQFULLCLOCK 0x0100 459 #define PCIM_PCAP_D1SUPP 0x0200 460 #define PCIM_PCAP_D2SUPP 0x0400 461 #define PCIM_PCAP_D0PME 0x0800 462 #define PCIM_PCAP_D1PME 0x1000 463 #define PCIM_PCAP_D2PME 0x2000 464 #define PCIM_PCAP_D3PME_HOT 0x4000 465 #define PCIM_PCAP_D3PME_COLD 0x8000 466 467 #define PCIR_POWER_STATUS 0x4 468 #define PCIM_PSTAT_D0 0x0000 469 #define PCIM_PSTAT_D1 0x0001 470 #define PCIM_PSTAT_D2 0x0002 471 #define PCIM_PSTAT_D3 0x0003 472 #define PCIM_PSTAT_DMASK 0x0003 473 #define PCIM_PSTAT_REPENABLE 0x0010 474 #define PCIM_PSTAT_PMEENABLE 0x0100 475 #define PCIM_PSTAT_D0POWER 0x0000 476 #define PCIM_PSTAT_D1POWER 0x0200 477 #define PCIM_PSTAT_D2POWER 0x0400 478 #define PCIM_PSTAT_D3POWER 0x0600 479 #define PCIM_PSTAT_D0HEAT 0x0800 480 #define PCIM_PSTAT_D1HEAT 0x1000 481 #define PCIM_PSTAT_D2HEAT 0x1200 482 #define PCIM_PSTAT_D3HEAT 0x1400 483 #define PCIM_PSTAT_DATAUNKN 0x0000 484 #define PCIM_PSTAT_DATADIV10 0x2000 485 #define PCIM_PSTAT_DATADIV100 0x4000 486 #define PCIM_PSTAT_DATADIV1000 0x6000 487 #define PCIM_PSTAT_DATADIVMASK 0x6000 488 #define PCIM_PSTAT_PME 0x8000 489 490 #define PCIR_POWER_PMCSR 0x6 491 #define PCIM_PMCSR_DCLOCK 0x10 492 #define PCIM_PMCSR_B2SUPP 0x20 493 #define PCIM_BMCSR_B3SUPP 0x40 494 #define PCIM_BMCSR_BPCE 0x80 495 496 #define PCIR_POWER_DATA 0x7 497 498 /* VPD capability registers */ 499 #define PCIR_VPD_ADDR 0x2 500 #define PCIR_VPD_DATA 0x4 501 502 /* PCI Message Signalled Interrupts (MSI) */ 503 #define PCIR_MSI_CTRL 0x2 504 #define PCIM_MSICTRL_VECTOR 0x0100 505 #define PCIM_MSICTRL_64BIT 0x0080 506 #define PCIM_MSICTRL_MME_MASK 0x0070 507 #define PCIM_MSICTRL_MME_1 0x0000 508 #define PCIM_MSICTRL_MME_2 0x0010 509 #define PCIM_MSICTRL_MME_4 0x0020 510 #define PCIM_MSICTRL_MME_8 0x0030 511 #define PCIM_MSICTRL_MME_16 0x0040 512 #define PCIM_MSICTRL_MME_32 0x0050 513 #define PCIM_MSICTRL_MMC_MASK 0x000E 514 #define PCIM_MSICTRL_MMC_1 0x0000 515 #define PCIM_MSICTRL_MMC_2 0x0002 516 #define PCIM_MSICTRL_MMC_4 0x0004 517 #define PCIM_MSICTRL_MMC_8 0x0006 518 #define PCIM_MSICTRL_MMC_16 0x0008 519 #define PCIM_MSICTRL_MMC_32 0x000A 520 #define PCIM_MSICTRL_MSI_ENABLE 0x0001 521 #define PCIR_MSI_ADDR 0x4 522 #define PCIR_MSI_ADDR_HIGH 0x8 523 #define PCIR_MSI_DATA 0x8 524 #define PCIR_MSI_DATA_64BIT 0xc 525 #define PCIR_MSI_MASK 0x10 526 #define PCIR_MSI_PENDING 0x14 527 528 /* PCI-X definitions */ 529 530 /* For header type 0 devices */ 531 #define PCIXR_COMMAND 0x2 532 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 533 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 534 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 535 #define PCIXM_COMMAND_MAX_READ_512 0x0000 536 #define PCIXM_COMMAND_MAX_READ_1024 0x0004 537 #define PCIXM_COMMAND_MAX_READ_2048 0x0008 538 #define PCIXM_COMMAND_MAX_READ_4096 0x000c 539 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 540 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 541 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 542 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 543 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 544 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 545 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 546 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 547 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 548 #define PCIXM_COMMAND_VERSION 0x3000 549 #define PCIXR_STATUS 0x4 550 #define PCIXM_STATUS_DEVFN 0x000000FF 551 #define PCIXM_STATUS_BUS 0x0000FF00 552 #define PCIXM_STATUS_64BIT 0x00010000 553 #define PCIXM_STATUS_133CAP 0x00020000 554 #define PCIXM_STATUS_SC_DISCARDED 0x00040000 555 #define PCIXM_STATUS_UNEXP_SC 0x00080000 556 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000 557 #define PCIXM_STATUS_MAX_READ 0x00600000 558 #define PCIXM_STATUS_MAX_READ_512 0x00000000 559 #define PCIXM_STATUS_MAX_READ_1024 0x00200000 560 #define PCIXM_STATUS_MAX_READ_2048 0x00400000 561 #define PCIXM_STATUS_MAX_READ_4096 0x00600000 562 #define PCIXM_STATUS_MAX_SPLITS 0x03800000 563 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 564 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 565 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 566 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 567 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 568 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 569 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 570 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 571 #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 572 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 573 #define PCIXM_STATUS_266CAP 0x40000000 574 #define PCIXM_STATUS_533CAP 0x80000000 575 576 /* For header type 1 devices (PCI-X bridges) */ 577 #define PCIXR_SEC_STATUS 0x2 578 #define PCIXM_SEC_STATUS_64BIT 0x0001 579 #define PCIXM_SEC_STATUS_133CAP 0x0002 580 #define PCIXM_SEC_STATUS_SC_DISC 0x0004 581 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 582 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 583 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 584 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 585 #define PCIXM_SEC_STATUS_VERSION 0x3000 586 #define PCIXM_SEC_STATUS_266CAP 0x4000 587 #define PCIXM_SEC_STATUS_533CAP 0x8000 588 #define PCIXR_BRIDGE_STATUS 0x4 589 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 590 #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 591 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 592 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 593 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 594 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 595 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 596 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 597 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 598 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 599 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 600 601 /* HT (HyperTransport) Capability definitions */ 602 #define PCIR_HT_COMMAND 0x2 603 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 604 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 605 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 606 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 607 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 608 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 609 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 610 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 611 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 612 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 613 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 614 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 615 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 616 #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 617 618 /* HT MSI Mapping Capability definitions. */ 619 #define PCIM_HTCMD_MSI_ENABLE 0x0001 620 #define PCIM_HTCMD_MSI_FIXED 0x0002 621 #define PCIR_HTMSI_ADDRESS_LO 0x4 622 #define PCIR_HTMSI_ADDRESS_HI 0x8 623 624 /* PCI Vendor capability definitions */ 625 #define PCIR_VENDOR_LENGTH 0x2 626 #define PCIR_VENDOR_DATA 0x3 627 628 /* PCI EHCI Debug Port definitions */ 629 #define PCIR_DEBUG_PORT 0x2 630 #define PCIM_DEBUG_PORT_OFFSET 0x1FFF 631 #define PCIM_DEBUG_PORT_BAR 0xe000 632 633 /* PCI-PCI Bridge Subvendor definitions */ 634 #define PCIR_SUBVENDCAP_ID 0x4 635 636 /* MSI-X definitions */ 637 #define PCIR_MSIX_CTRL 0x2 638 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 639 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 640 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 641 #define PCIR_MSIX_TABLE 0x4 642 #define PCIR_MSIX_PBA 0x8 643 #define PCIM_MSIX_BIR_MASK 0x7 644 #define PCIM_MSIX_BIR_BAR_10 0 645 #define PCIM_MSIX_BIR_BAR_14 1 646 #define PCIM_MSIX_BIR_BAR_18 2 647 #define PCIM_MSIX_BIR_BAR_1C 3 648 #define PCIM_MSIX_BIR_BAR_20 4 649 #define PCIM_MSIX_BIR_BAR_24 5 650 #define PCIM_MSIX_VCTRL_MASK 0x1 651 652 /* 653 * PCI Express definitions 654 * According to 655 * PCI Express base specification, REV. 1.0a 656 */ 657 658 /* PCI Express capabilities, 16bits */ 659 #define PCIER_CAPABILITY 0x2 660 #define PCIEM_CAP_VER_MASK 0x000f /* Version */ 661 #define PCIEM_CAP_VER_1 0x0001 662 #define PCIEM_CAP_VER_2 0x0002 663 #define PCIEM_CAP_PORT_TYPE 0x00f0 /* Port type mask */ 664 #define PCIEM_CAP_SLOT_IMPL 0x0100 /* Slot implemented, 665 * valid only for root port and 666 * switch downstream port 667 */ 668 #define PCIEM_CAP_IRQ_MSGNO 0x3e00 669 670 /* PCI Express port types */ 671 #define PCIE_END_POINT 0x0000 /* Endpoint device */ 672 #define PCIE_LEG_END_POINT 0x0010 /* Legacy endpoint device */ 673 #define PCIE_ROOT_PORT 0x0040 /* Root port */ 674 #define PCIE_UP_STREAM_PORT 0x0050 /* Switch upstream port */ 675 #define PCIE_DOWN_STREAM_PORT 0x0060 /* Switch downstream port */ 676 #define PCIE_PCIE2PCI_BRIDGE 0x0070 /* PCI Express to PCI/PCI-X bridge */ 677 #define PCIE_PCI2PCIE_BRIDGE 0x0080 /* PCI/PCI-X to PCI Express bridge */ 678 #define PCIE_ROOT_END_POINT 0x0090 /* Root Complex Integrated Endpoint */ 679 #define PCIE_ROOT_EVT_COLL 0x00a0 /* Root Complex Event Collector */ 680 681 /* PCI Express device capabilities, 32bits */ 682 #define PCIER_DEVCAP 0x04 683 #define PCIEM_DEVCAP_MAX_PAYLOAD 0x0007 684 685 /* PCI Express device control, 16bits */ 686 #define PCIER_DEVCTRL 0x08 687 #define PCIEM_DEVCTL_RELAX_ORDER 0x0010 /* Enable Relaxed Ordering */ 688 #define PCIEM_DEVCTL_MAX_PAYLOAD_MASK 0x00e0 /* Max Payload Size */ 689 #define PCIEM_DEVCTL_MAX_PAYLOAD_128 0x0000 690 #define PCIEM_DEVCTL_MAX_PAYLOAD_256 0x0020 691 #define PCIEM_DEVCTL_MAX_PAYLOAD_512 0x0040 692 #define PCIEM_DEVCTL_MAX_PAYLOAD_1024 0x0060 693 #define PCIEM_DEVCTL_MAX_PAYLOAD_2048 0x0080 694 #define PCIEM_DEVCTL_MAX_PAYLOAD_4096 0x00a0 695 #define PCIEM_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */ 696 #define PCIEM_DEVCTL_MAX_READRQ_MASK 0x7000 /* Max read request size */ 697 #define PCIEM_DEVCTL_MAX_READRQ_128 0x0000 698 #define PCIEM_DEVCTL_MAX_READRQ_256 0x1000 699 #define PCIEM_DEVCTL_MAX_READRQ_512 0x2000 700 #define PCIEM_DEVCTL_MAX_READRQ_1024 0x3000 701 #define PCIEM_DEVCTL_MAX_READRQ_2048 0x4000 702 #define PCIEM_DEVCTL_MAX_READRQ_4096 0x5000 703 704 /* PCI Express device status, 16bits */ 705 #define PCIER_DEVSTS 0x0a 706 #define PCIEM_DEVSTS_CORR_ERR 0x1 /* Correctable Error */ 707 #define PCIEM_DEVSTS_NFATAL_ERR 0x2 /* Non-Fatal Error */ 708 #define PCIEM_DEVSTS_FATAL_ERR 0x4 /* Fatal Error */ 709 #define PCIEM_DEVSTS_UNSUPP_REQ 0x8 /* Unsupported Request */ 710 711 /* PCI Express link capabilities, 32bits */ 712 #define PCIER_LINKCAP 0x0c 713 #define PCIEM_LNKCAP_SPEED_MASK 0x000f /* Supported link speeds */ 714 #define PCIEM_LNKCAP_SPEED_2_5 0x1 /* 2.5GT/s */ 715 #define PCIEM_LNKCAP_SPEED_5 0x2 /* 5.0GT/s and 2.5GT/s */ 716 #define PCIEM_LNKCAP_MAXW_MASK 0x03f0 /* Maximum link width */ 717 #define PCIEM_LNKCAP_MAXW_X1 0x0010 718 #define PCIEM_LNKCAP_MAXW_X2 0x0020 719 #define PCIEM_LNKCAP_MAXW_X4 0x0040 720 #define PCIEM_LNKCAP_MAXW_X8 0x0080 721 #define PCIEM_LNKCAP_MAXW_X12 0x00c0 722 #define PCIEM_LNKCAP_MAXW_X16 0x0100 723 #define PCIEM_LNKCAP_MAXW_X32 0x0200 724 #define PCIEM_LNKCAP_ASPM_MASK 0x0c00 /* ASPM */ 725 #define PCIEM_LNKCAP_ASPM_L0S 0x0400 726 #define PCIEM_LNKCAP_ASPM_L1 0x0c00 727 728 /* PCI Express link control, 32bits */ 729 #define PCIER_LINKCTRL 0x10 730 #define PCIEM_LNKCTL_ASPM_MASK 0x3 /* ASPM */ 731 #define PCIEM_LNKCTL_ASPM_DISABLE 0x0 732 #define PCIEM_LNKCTL_ASPM_L0S 0x1 733 #define PCIEM_LNKCTL_ASPM_L1 0x2 734 #define PCIEM_LNKCTL_RCB 0x8 735 #define PCIEM_LNKCTL_LINK_DIS 0x0010 736 #define PCIEM_LNKCTL_RETRAIN_LINK 0x0020 737 #define PCIEM_LNKCTL_COMMON_CLOCK 0x0040 738 #define PCIEM_LNKCTL_EXTENDED_SYNC 0x0080 739 #define PCIEM_LNKCTL_ECPM 0x0100 740 #define PCIEM_LNKCTL_HAWD 0x0200 741 #define PCIEM_LNKCTL_LBMIE 0x0400 742 #define PCIEM_LNKCTL_LABIE 0x0800 743 744 /* PCI Express link status, 16bits */ 745 #define PCIER_LINKSTAT 0x12 746 #define PCIEM_LNKSTAT_WIDTH 0x03f0 747 748 /* PCI Express slot capabilities, 32bits */ 749 #define PCIER_SLOTCAP 0x14 750 #define PCIEM_SLTCAP_ATTEN_BTN 0x00000001 /* Attention button present */ 751 #define PCIEM_SLTCAP_PWR_CTRL 0x00000002 /* Power controller present */ 752 #define PCIEM_SLTCAP_MRL_SNS 0x00000004 /* MRL sensor present */ 753 #define PCIEM_SLTCAP_ATTEN_IND 0x00000008 /* Attention indicator present */ 754 #define PCIEM_SLTCAP_PWR_IND 0x00000010 /* Power indicator present */ 755 #define PCIEM_SLTCAP_HP_SURP 0x00000020 /* Hot-Plug surprise */ 756 #define PCIEM_SLTCAP_HP_CAP 0x00000040 /* Hot-Plug capable */ 757 #define PCIEM_SLTCAP_HP_MASK 0x0000007f /* Hot-Plug related bits */ 758 759 /* PCI Express slot control, 16bits */ 760 #define PCIER_SLOTCTRL 0x18 761 #define PCIEM_SLTCTL_HPINTR_MASK 0x001f /* Hot-plug interrupts mask */ 762 #define PCIEM_SLTCTL_HPINTR_EN 0x0020 /* Enable hot-plug interrupts */ 763 764 /* PCI Express hot-plug interrupts */ 765 #define PCIE_HPINTR_ATTEN_BTN 0x0001 /* Attention button intr */ 766 #define PCIE_HPINTR_PWR_FAULT 0x0002 /* Power fault intr */ 767 #define PCIE_HPINTR_MRL_SNS 0x0004 /* MRL sensor changed intr */ 768 #define PCIE_HPINTR_PRSN_DETECT 0x0008 /* Presence detect intr */ 769 #define PCIE_HPINTR_CMD_COMPL 0x0010 /* Command completed intr */ 770 771 /* PCI Express device capabilities 2, 32bits */ 772 #define PCIER_DEVCAP2 0x24 773 #define PCIEM_DEVCAP2_COMP_TIMO_RANGES 0x0000000f 774 #define PCIEM_DEVCAP2_COMP_TIMO_RANGE_A 0x00000001 775 #define PCIEM_DEVCAP2_COMP_TIMO_RANGE_B 0x00000002 776 #define PCIEM_DEVCAP2_COMP_TIMO_RANGE_C 0x00000004 777 #define PCIEM_DEVCAP2_COMP_TIMO_RANGE_D 0x00000008 778 #define PCIEM_DEVCAP2_COMP_TIMO_DISABLE 0x00000010 779 #define PCIEM_DEVCAP2_ALT_RID_SUPP 0x00000020 780 #define PCIEM_DEVCAP2_LTR_SUPP 0x00000800 781 782 /* PCI Express device control 2, 16bits */ 783 #define PCIER_DEVCTRL2 0x28 784 #define PCIEM_DEVCTL2_COMP_TIMO_MASK 0x000f 785 #define PCIEM_DEVCTL2_COMP_TIMO_50MS 0x0000 786 #define PCIEM_DEVCTL2_COMP_TIMO_100US 0x0001 787 #define PCIEM_DEVCTL2_COMP_TIMO_10MS 0x0002 788 #define PCIEM_DEVCTL2_COMP_TIMO_55MS 0x0005 789 #define PCIEM_DEVCTL2_COMP_TIMO_210MS 0x0006 790 #define PCIEM_DEVCTL2_COMP_TIMO_900MS 0x0009 791 #define PCIEM_DEVCTL2_COMP_TIMO_3500MS 0x000a 792 #define PCIEM_DEVCTL2_COMP_TIMO_13S 0x000d 793 #define PCIEM_DEVCTL2_COMP_TIMO_64S 0x000e 794 #define PCIEM_DEVCTL2_COMP_TIMO_DISABLE 0x0010 795 #define PCIEM_DEVCTL2_ALT_RID_ENABLE 0x0020 796 #define PCIEM_DEVCTL2_LTR_ENABLE 0x0400 797 798 /* PCI Express link capabilities 2, 32bits */ 799 #define PCIER_LINK_CAP2 0x2c 800 801 /* PCI Advanced Features definitions */ 802 #define PCIR_PCIAF_CAP 0x3 803 #define PCIM_PCIAFCAP_TP 0x01 804 #define PCIM_PCIAFCAP_FLR 0x02 805 #define PCIR_PCIAF_CTRL 0x4 806 #define PCIR_PCIAFCTRL_FLR 0x01 807 #define PCIR_PCIAF_STATUS 0x5 808 #define PCIR_PCIAFSTATUS_TP 0x01 809 810 /* Advanced Error Reporting */ 811 #define PCIR_AER_UC_STATUS 0x04 812 #define PCIM_AER_UC_TRAINING_ERROR 0x00000001 813 #define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 814 #define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 815 #define PCIM_AER_UC_POISONED_TLP 0x00001000 816 #define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 817 #define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 818 #define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 819 #define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 820 #define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 821 #define PCIM_AER_UC_MALFORMED_TLP 0x00040000 822 #define PCIM_AER_UC_ECRC_ERROR 0x00080000 823 #define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 824 #define PCIM_AER_UC_ACS_VIOLATION 0x00200000 825 #define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ 826 #define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ 827 #define PCIR_AER_COR_STATUS 0x10 828 #define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 829 #define PCIM_AER_COR_BAD_TLP 0x00000040 830 #define PCIM_AER_COR_BAD_DLLP 0x00000080 831 #define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 832 #define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 833 #define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 834 #define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ 835 #define PCIR_AER_CAP_CONTROL 0x18 836 #define PCIM_AER_FIRST_ERROR_PTR 0x0000001f 837 #define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 838 #define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 839 #define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 840 #define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 841 #define PCIR_AER_HEADER_LOG 0x1c 842 #define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ 843 #define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 844 #define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 845 #define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 846 #define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ 847 #define PCIM_AER_ROOTERR_COR_ERR 0x00000001 848 #define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 849 #define PCIM_AER_ROOTERR_UC_ERR 0x00000004 850 #define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 851 #define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 852 #define PCIM_AER_ROOTERR_NF_ERR 0x00000020 853 #define PCIM_AER_ROOTERR_F_ERR 0x00000040 854 #define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 855 #define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ 856 #define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ 857 858 /* Virtual Channel definitions */ 859 #define PCIR_VC_CAP1 0x04 860 #define PCIM_VC_CAP1_EXT_COUNT 0x00000007 861 #define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 862 #define PCIR_VC_CAP2 0x08 863 #define PCIR_VC_CONTROL 0x0C 864 #define PCIR_VC_STATUS 0x0E 865 #define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C) 866 #define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C) 867 #define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C) 868 869 /* Serial Number definitions */ 870 #define PCIR_SERIAL_LOW 0x04 871 #define PCIR_SERIAL_HIGH 0x08 872 873 #endif /* _PCIREG_H_ */ 874