1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pcireg.h,v 1.24.2.5 2002/08/31 10:06:51 gibbs Exp $ 27 * $DragonFly: src/sys/bus/pci/pcireg.h,v 1.14 2007/11/23 13:40:58 sephe Exp $ 28 * 29 */ 30 31 /* 32 * PCIM_xxx: mask to locate subfield in register 33 * PCIR_xxx: config register offset 34 * PCIC_xxx: device class 35 * PCIS_xxx: device subclass 36 * PCIP_xxx: device programming interface 37 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 38 * PCID_xxx: device ID 39 * PCIY_xxx: capability identification number 40 */ 41 42 /* some PCI bus constants */ 43 44 #define PCI_BUSMAX 255 45 #define PCI_SLOTMAX 31 46 #define PCI_FUNCMAX 7 47 #define PCI_REGMAX 255 48 #define PCI_MAXHDRTYPE 2 49 50 /* PCI config header registers for all devices */ 51 52 #define PCIR_DEVVENDOR 0x00 53 #define PCIR_VENDOR 0x00 54 #define PCIR_DEVICE 0x02 55 #define PCIR_COMMAND 0x04 56 #define PCIM_CMD_PORTEN 0x0001 57 #define PCIM_CMD_MEMEN 0x0002 58 #define PCIM_CMD_BUSMASTEREN 0x0004 59 #define PCIM_CMD_MWRICEN 0x0010 60 #define PCIM_CMD_PERRESPEN 0x0040 61 #define PCIM_CMD_SERRESPEN 0x0100 62 #define PCIR_STATUS 0x06 63 #define PCIM_STATUS_CAPPRESENT 0x0010 64 #define PCIM_STATUS_66CAPABLE 0x0020 65 #define PCIM_STATUS_BACKTOBACK 0x0080 66 #define PCIM_STATUS_PERRREPORT 0x0100 67 #define PCIM_STATUS_SEL_FAST 0x0000 68 #define PCIM_STATUS_SEL_MEDIMUM 0x0200 69 #define PCIM_STATUS_SEL_SLOW 0x0400 70 #define PCIM_STATUS_SEL_MASK 0x0600 71 #define PCIM_STATUS_STABORT 0x0800 72 #define PCIM_STATUS_RTABORT 0x1000 73 #define PCIM_STATUS_RMABORT 0x2000 74 #define PCIM_STATUS_SERR 0x4000 75 #define PCIM_STATUS_PERR 0x8000 76 #define PCIR_REVID 0x08 77 #define PCIR_PROGIF 0x09 78 #define PCIR_SUBCLASS 0x0a 79 #define PCIR_CLASS 0x0b 80 #define PCIR_CACHELNSZ 0x0c 81 #define PCIR_LATTIMER 0x0d 82 #define PCIR_HDRTYPE 0x0e 83 #define PCIM_HDRTYPE 0x7f 84 #define PCIM_HDRTYPE_NORMAL 0x00 85 #define PCIM_HDRTYPE_BRIDGE 0x01 86 #define PCIM_HDRTYPE_CARDBUS 0x02 87 #define PCIM_MFDEV 0x80 88 #define PCIR_BIST 0x0f 89 90 /* Capability Identification Numbers */ 91 #define PCIY_PMG 0x01 /* PCI Power Management */ 92 #define PCIY_AGP 0x02 /* AGP */ 93 #define PCIY_VPD 0x03 /* Vital Product Data */ 94 #define PCIY_SLOTID 0x04 /* Slot Identification */ 95 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 96 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 97 #define PCIY_PCIX 0x07 /* PCI-X */ 98 #define PCIY_HT 0x08 /* HyperTransport */ 99 #define PCIY_VENDOR 0x09 /* Vendor Unique */ 100 #define PCIY_DEBUG 0x0a /* Debug port */ 101 #define PCIY_CRES 0x0b /* CompactPCI central resource control */ 102 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 103 #define PCIY_AGP8X 0x0e /* AGP 8x */ 104 #define PCIY_SECDEV 0x0f /* Secure Device */ 105 #define PCIY_EXPRESS 0x10 /* PCI Express */ 106 #define PCIY_MSIX 0x11 /* MSI-X */ 107 108 /* config registers for header type 0 devices */ 109 110 #define PCIR_BARS 0x10 111 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 112 #define PCIR_MAPS PCIR_BARS /* DEPRECATED XXX */ 113 #define PCIR_CARDBUSCIS 0x28 114 #define PCIR_SUBVEND_0 0x2c 115 #define PCIR_SUBDEV_0 0x2e 116 #define PCIR_BIOS 0x30 117 #define PCIM_BIOS_ENABLE 0x01 118 #define PCIR_CAP_PTR 0x34 119 #define PCIR_INTLINE 0x3c 120 #define PCIR_INTPIN 0x3d 121 #define PCIR_MINGNT 0x3e 122 #define PCIR_MAXLAT 0x3f 123 124 /* config registers for header type 1 devices */ 125 126 #define PCIR_SECSTAT_1 0x1e 127 128 #define PCIR_PRIBUS_1 0x18 129 #define PCIR_SECBUS_1 0x19 130 #define PCIR_SUBBUS_1 0x1a 131 #define PCIR_SECLAT_1 0x1b 132 133 #define PCIR_IOBASEL_1 0x1c 134 #define PCIR_IOLIMITL_1 0x1d 135 #define PCIR_IOBASEH_1 0x30 136 #define PCIR_IOLIMITH_1 0x32 137 #define PCIM_BRIO_16 0x0 138 #define PCIM_BRIO_32 0x1 139 #define PCIM_BRIO_MASK 0xf 140 141 #define PCIR_MEMBASE_1 0x20 142 #define PCIR_MEMLIMIT_1 0x22 143 144 #define PCIR_PMBASEL_1 0x24 145 #define PCIR_PMLIMITL_1 0x26 146 #define PCIR_PMBASEH_1 0x28 147 #define PCIR_PMLIMITH_1 0x2c 148 149 #define PCIR_BRIDGECTL_1 0x3e 150 151 #define PCIR_SUBVEND_1 0x34 152 #define PCIR_SUBDEV_1 0x36 153 154 /* config registers for header type 2 (Cardbus) devices */ 155 156 #define PCIR_CAP_PTR_2 0x14 157 #define PCIR_SECSTAT_2 0x16 158 159 #define PCIR_PRIBUS_2 0x18 160 #define PCIR_SECBUS_2 0x19 161 #define PCIR_SUBBUS_2 0x1a 162 #define PCIR_SECLAT_2 0x1b 163 164 #define PCIR_MEMBASE0_2 0x1c 165 #define PCIR_MEMLIMIT0_2 0x20 166 #define PCIR_MEMBASE1_2 0x24 167 #define PCIR_MEMLIMIT1_2 0x28 168 #define PCIR_IOBASE0_2 0x2c 169 #define PCIR_IOLIMIT0_2 0x30 170 #define PCIR_IOBASE1_2 0x34 171 #define PCIR_IOLIMIT1_2 0x38 172 173 #define PCIR_BRIDGECTL_2 0x3e 174 175 #define PCIR_SUBVEND_2 0x40 176 #define PCIR_SUBDEV_2 0x42 177 178 #define PCIR_PCCARDIF_2 0x44 179 180 /* PCI device class, subclass and programming interface definitions */ 181 182 #define PCIC_OLD 0x00 183 #define PCIS_OLD_NONVGA 0x00 184 #define PCIS_OLD_VGA 0x01 185 186 #define PCIC_STORAGE 0x01 187 #define PCIS_STORAGE_SCSI 0x00 188 #define PCIS_STORAGE_IDE 0x01 189 #define PCIP_STORAGE_IDE_MODEPRIM 0x01 190 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 191 #define PCIP_STORAGE_IDE_MODESEC 0x04 192 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 193 #define PCIP_STORAGE_IDE_MASTERDEV 0x80 194 #define PCIS_STORAGE_FLOPPY 0x02 195 #define PCIS_STORAGE_IPI 0x03 196 #define PCIS_STORAGE_RAID 0x04 197 #define PCIS_STORAGE_ATA 0x05 198 #define PCIP_STORAGE_ATA_SINGLEDMA 0x20 199 #define PCIP_STORAGE_ATA_CHAINDMA 0x30 200 #define PCIS_STORAGE_SATA 0x06 201 #define PCIP_STORAGE_SATA_AHCI 0x01 202 #define PCIS_STORAGE_SAS 0x07 203 #define PCIP_STORAGE_SAS_VENDOR 0x00 204 #define PCIP_STORAGE_SAS_SSB 0x01 205 #define PCIS_STORAGE_OTHER 0x80 206 207 #define PCIC_NETWORK 0x02 208 #define PCIS_NETWORK_ETHERNET 0x00 209 #define PCIS_NETWORK_TOKENRING 0x01 210 #define PCIS_NETWORK_FDDI 0x02 211 #define PCIS_NETWORK_ATM 0x03 212 #define PCIS_NETWORK_ISDN 0x04 213 #define PCIS_NETWORK_WORLDFIP 0x05 214 #define PCIS_NETWORK_PICMG 0x06 215 #define PCIS_NETWORK_OTHER 0x80 216 217 #define PCIC_DISPLAY 0x03 218 #define PCIS_DISPLAY_VGA 0x00 219 #define PCIP_DISPLAY_VGA_COMP 0x00 220 #define PCIP_DISPLAY_VGA_8514 0x01 221 #define PCIS_DISPLAY_XGA 0x01 222 #define PCIS_DISPLAY_3D 0x02 223 #define PCIS_DISPLAY_OTHER 0x80 224 225 #define PCIC_MULTIMEDIA 0x04 226 #define PCIS_MULTIMEDIA_VIDEO 0x00 227 #define PCIS_MULTIMEDIA_AUDIO 0x01 228 #define PCIS_MULTIMEDIA_TEL 0x02 229 #define PCIS_MULTIMEDIA_OTHER 0x80 230 231 #define PCIC_MEMORY 0x05 232 #define PCIS_MEMORY_RAM 0x00 233 #define PCIS_MEMORY_FLASH 0x01 234 #define PCIS_MEMORY_OTHER 0x80 235 236 #define PCIC_BRIDGE 0x06 237 #define PCIS_BRIDGE_HOST 0x00 238 #define PCIS_BRIDGE_ISA 0x01 239 #define PCIS_BRIDGE_EISA 0x02 240 #define PCIS_BRIDGE_MCA 0x03 241 #define PCIS_BRIDGE_PCI 0x04 242 #define PCIS_BRIDGE_PCMCIA 0x05 243 #define PCIS_BRIDGE_NUBUS 0x06 244 #define PCIS_BRIDGE_CARDBUS 0x07 245 #define PCIS_BRIDGE_RACEWAY 0x08 246 #define PCIS_BRIDGE_SEMITRANS 0x09 247 #define PCIS_BRIDGE_INFINI 0x0a 248 #define PCIS_BRIDGE_OTHER 0x80 249 250 #define PCIC_SIMPLECOMM 0x07 251 #define PCIS_SIMPLECOMM_UART 0x00 252 #define PCIP_SIMPLECOMM_UART_16550A 0x02 253 #define PCIS_SIMPLECOMM_PAR 0x01 254 #define PCIS_SIMPLECOMM_MULTSER 0x02 255 #define PCIS_SIMPLECOMM_MODEM 0x03 256 #define PCIS_SIMPLECOMM_GPIB 0x04 257 #define PCIS_SIMPLECOMM_SMART 0x05 258 #define PCIS_SIMPLECOMM_OTHER 0x80 259 260 #define PCIC_BASEPERIPH 0x08 261 #define PCIS_BASEPERIPH_PIC 0x00 262 #define PCIS_BASEPERIPH_DMA 0x01 263 #define PCIS_BASEPERIPH_TIMER 0x02 264 #define PCIS_BASEPERIPH_RTC 0x03 265 #define PCIS_BASEPERIPH_HOTPLUG 0x04 266 #define PCIS_BASEPERIPH_OTHER 0x80 267 268 #define PCIC_INPUTDEV 0x09 269 #define PCIS_INPUTDEV_KEYBOARD 0x00 270 #define PCIS_INPUTDEV_DIGITIZER 0x01 271 #define PCIS_INPUTDEV_MOUSE 0x02 272 #define PCIS_INPUTDEV_SCANNER 0x03 273 #define PCIS_INPUTDEV_GAMEPORT 0x04 274 #define PCIS_INPUTDEV_OTHER 0x80 275 276 #define PCIC_DOCKING 0x0a 277 #define PCIS_DOCKING_GENERIC 0x00 278 #define PCIS_DOCKING_OTHER 0x80 279 280 #define PCIC_PROCESSOR 0x0b 281 #define PCIS_PROCESSOR_386 0x00 282 #define PCIS_PROCESSOR_486 0x01 283 #define PCIS_PROCESSOR_PENTIUM 0x02 284 #define PCIS_PROCESSOR_ALPHA 0x10 285 #define PCIS_PROCESSOR_POWERPC 0x20 286 #define PCIS_PROCESSOR_MIPS 0x30 287 #define PCIS_PROCESSOR_COPROC 0x40 288 289 #define PCIC_SERIALBUS 0x0c 290 #define PCIS_SERIALBUS_FW 0x00 291 #define PCIS_SERIALBUS_ACCESS 0x01 292 #define PCIS_SERIALBUS_SSA 0x02 293 #define PCIS_SERIALBUS_USB 0x03 294 #define PCIS_SERIALBUS_FC 0x04 295 #define PCIS_SERIALBUS_SMBUS 0x05 296 #define PCIS_SERIALBUS_INFINI 0x06 297 #define PCIS_SERIALBUS_IPMI 0x07 298 #define PCIS_SERIALBUS_SERCOS 0x08 299 #define PCIS_SERIALBUS_CANBUS 0x09 300 301 #define PCIC_WIRELESS 0x0d 302 #define PCIS_WIRELESS_IRDA 0x00 303 #define PCIS_WIRELESS_IR 0x01 304 #define PCIS_WIRELESS_RF 0x10 305 #define PCIS_WIRELESS_BLUETOOTH 0x11 306 #define PCIS_WIRELESS_BROADBAND 0x12 307 #define PCIS_WIRELESS_80211A 0x20 308 #define PCIS_WIRELESS_80211B 0x21 309 #define PCIS_WIRELESS_OTHER 0x80 310 311 #define PCIC_I2O 0x0e 312 #define PCIS_I2O_10 0x00 313 314 #define PCIC_SATELLITE 0x0f 315 #define PCIS_SATELLITE_TV 0x01 316 #define PCIS_SATELLITE_AUDIO 0x02 317 #define PCIS_SATELLITE_VOICE 0x03 318 #define PCIS_SATELLITE_DATA 0x04 319 320 #define PCIC_CRYPTO 0x10 321 #define PCIS_CRYPTO_NETWORK 0x00 322 #define PCIS_CRYPTO_ENTERTAIN 0x10 323 #define PCIS_CRYPTO_OTHER 0x80 324 325 #define PCIC_SIGPROC 0x11 326 #define PCIS_SIGPROC_DPIO 0x00 327 #define PCIS_SIGPROC_PERFCOUNT 0x01 328 #define PCIS_SIGPROC_COMMSYNC 0x10 329 #define PCIS_SIGPROC_MANAGEMENT 0x20 330 #define PCIS_SIGPROC_OTHER 0x80 331 332 #define PCIC_OTHER 0xff 333 334 /* PCI power manangement */ 335 336 #define PCIR_POWER_CAP 0x2 337 #define PCIM_PCAP_SPEC 0x0007 338 #define PCIM_PCAP_PMEREQCLK 0x0008 339 #define PCIM_PCAP_PMEREQPWR 0x0010 340 #define PCIM_PCAP_DEVSPECINIT 0x0020 341 #define PCIM_PCAP_DYNCLOCK 0x0040 342 #define PCIM_PCAP_SECCLOCK 0x00c0 343 #define PCIM_PCAP_CLOCKMASK 0x00c0 344 #define PCIM_PCAP_REQFULLCLOCK 0x0100 345 #define PCIM_PCAP_D1SUPP 0x0200 346 #define PCIM_PCAP_D2SUPP 0x0400 347 #define PCIM_PCAP_D0PME 0x1000 348 #define PCIM_PCAP_D1PME 0x2000 349 #define PCIM_PCAP_D2PME 0x4000 350 351 #define PCIR_POWER_STATUS 0x4 352 #define PCIM_PSTAT_D0 0x0000 353 #define PCIM_PSTAT_D1 0x0001 354 #define PCIM_PSTAT_D2 0x0002 355 #define PCIM_PSTAT_D3 0x0003 356 #define PCIM_PSTAT_DMASK 0x0003 357 #define PCIM_PSTAT_REPENABLE 0x0010 358 #define PCIM_PSTAT_PMEENABLE 0x0100 359 #define PCIM_PSTAT_D0POWER 0x0000 360 #define PCIM_PSTAT_D1POWER 0x0200 361 #define PCIM_PSTAT_D2POWER 0x0400 362 #define PCIM_PSTAT_D3POWER 0x0600 363 #define PCIM_PSTAT_D0HEAT 0x0800 364 #define PCIM_PSTAT_D1HEAT 0x1000 365 #define PCIM_PSTAT_D2HEAT 0x1200 366 #define PCIM_PSTAT_D3HEAT 0x1400 367 #define PCIM_PSTAT_DATAUNKN 0x0000 368 #define PCIM_PSTAT_DATADIV10 0x2000 369 #define PCIM_PSTAT_DATADIV100 0x4000 370 #define PCIM_PSTAT_DATADIV1000 0x6000 371 #define PCIM_PSTAT_DATADIVMASK 0x6000 372 #define PCIM_PSTAT_PME 0x8000 373 374 #define PCIR_POWER_PMCSR 0x6 375 #define PCIM_PMCSR_DCLOCK 0x10 376 #define PCIM_PMCSR_B2SUPP 0x20 377 #define PCIM_BMCSR_B3SUPP 0x40 378 #define PCIM_BMCSR_BPCE 0x80 379 380 #define PCIR_POWER_DATA 0x7 381 382 /* PCI Message Signalled Interrupts (MSI) */ 383 #define PCIR_MSI_CTRL 0x2 384 #define PCIM_MSICTRL_VECTOR 0x0100 385 #define PCIM_MSICTRL_64BIT 0x0080 386 #define PCIM_MSICTRL_MME_MASK 0x0070 387 #define PCIM_MSICTRL_MME_1 0x0000 388 #define PCIM_MSICTRL_MME_2 0x0010 389 #define PCIM_MSICTRL_MME_4 0x0020 390 #define PCIM_MSICTRL_MME_8 0x0030 391 #define PCIM_MSICTRL_MME_16 0x0040 392 #define PCIM_MSICTRL_MME_32 0x0050 393 #define PCIM_MSICTRL_MMC_MASK 0x000E 394 #define PCIM_MSICTRL_MMC_1 0x0000 395 #define PCIM_MSICTRL_MMC_2 0x0002 396 #define PCIM_MSICTRL_MMC_4 0x0004 397 #define PCIM_MSICTRL_MMC_8 0x0006 398 #define PCIM_MSICTRL_MMC_16 0x0008 399 #define PCIM_MSICTRL_MMC_32 0x000A 400 #define PCIM_MSICTRL_MSI_ENABLE 0x0001 401 #define PCIR_MSI_ADDR 0x4 402 #define PCIR_MSI_ADDR_HIGH 0x8 403 #define PCIR_MSI_DATA 0x8 404 #define PCIR_MSI_DATA_64BIT 0xc 405 #define PCIR_MSI_MASK 0x10 406 #define PCIR_MSI_PENDING 0x14 407 408 /* PCI-X definitions */ 409 #define PCIXR_COMMAND 0x96 410 #define PCIXR_DEVADDR 0x98 411 #define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */ 412 #define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */ 413 #define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */ 414 #define PCIXR_STATUS 0x9A 415 #define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */ 416 #define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */ 417 #define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */ 418 #define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */ 419 #define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */ 420 #define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */ 421 #define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */ 422 #define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */ 423 #define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */ 424 425 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ 426 427 #if defined(_KERNEL) && !defined(KLD_MODULE) 428 #include "opt_compat_oldpci.h" 429 #endif 430 431 #ifdef COMPAT_OLDPCI 432 433 #define PCI_ID_REG 0x00 434 #define PCI_COMMAND_STATUS_REG 0x04 435 #define PCI_COMMAND_IO_ENABLE 0x00000001 436 #define PCI_COMMAND_MEM_ENABLE 0x00000002 437 #define PCI_CLASS_REG 0x08 438 #define PCI_CLASS_MASK 0xff000000 439 #define PCI_SUBCLASS_MASK 0x00ff0000 440 #define PCI_REVISION_MASK 0x000000ff 441 #define PCI_CLASS_PREHISTORIC 0x00000000 442 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000 443 #define PCI_CLASS_MASS_STORAGE 0x01000000 444 #define PCI_CLASS_DISPLAY 0x03000000 445 #define PCI_SUBCLASS_DISPLAY_VGA 0x00000000 446 #define PCI_CLASS_BRIDGE 0x06000000 447 #define PCI_MAP_REG_START 0x10 448 #define PCI_MAP_REG_END 0x28 449 #define PCI_MAP_IO 0x00000001 450 #define PCI_INTERRUPT_REG 0x3c 451 452 #endif /* COMPAT_OLDPCI */ 453