1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pcireg.h,v 1.24.2.5 2002/08/31 10:06:51 gibbs Exp $ 27 * $DragonFly: src/sys/bus/pci/pcireg.h,v 1.18 2008/07/06 05:47:14 sephe Exp $ 28 * 29 */ 30 31 #ifndef _BUS_PCI_PCIREG_H_ 32 #define _BUS_PCI_PCIREG_H_ 33 34 #ifndef _SYS_TYPES_H_ 35 #include <sys/types.h> 36 #endif 37 38 typedef u_int16_t pci_vendor_id_t; 39 typedef u_int16_t pci_product_id_t; 40 41 typedef u_int8_t pci_class_t; 42 typedef u_int8_t pci_subclass_t; 43 typedef u_int8_t pci_interface_t; 44 typedef u_int8_t pci_revision_t; 45 46 typedef u_int8_t pci_intr_pin_t; 47 typedef u_int8_t pci_intr_line_t; 48 49 typedef u_int32_t pcireg_t; /* ~typical configuration space */ 50 51 /* 52 * PCIM_xxx: mask to locate subfield in register 53 * PCIR_xxx: config register offset 54 * PCIC_xxx: device class 55 * PCIS_xxx: device subclass 56 * PCIP_xxx: device programming interface 57 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 58 * PCID_xxx: device ID 59 * PCIY_xxx: capability identification number 60 */ 61 62 /* some PCI bus constants */ 63 64 #define PCI_BUSMAX 255 65 #define PCI_SLOTMAX 31 66 #define PCI_FUNCMAX 7 67 #define PCI_REGMAX 255 68 #define PCI_MAXHDRTYPE 2 69 70 /* PCI config header registers for all devices */ 71 72 #define PCIR_DEVVENDOR 0x00 73 #define PCIR_VENDOR 0x00 74 #define PCIR_DEVICE 0x02 75 76 #define PCIR_COMMAND 0x04 77 #define PCIM_CMD_PORTEN 0x0001 78 #define PCIM_CMD_MEMEN 0x0002 79 #define PCIM_CMD_BUSMASTEREN 0x0004 80 #define PCIM_CMD_MWRICEN 0x0010 81 #define PCIM_CMD_PERRESPEN 0x0040 82 #define PCIM_CMD_SERRESPEN 0x0100 83 84 #define PCIR_STATUS 0x06 85 #define PCIM_STATUS_CAPPRESENT 0x0010 86 #define PCIM_STATUS_66CAPABLE 0x0020 87 #define PCIM_STATUS_BACKTOBACK 0x0080 88 #define PCIM_STATUS_PERRREPORT 0x0100 89 #define PCIM_STATUS_SEL_FAST 0x0000 90 #define PCIM_STATUS_SEL_MEDIMUM 0x0200 91 #define PCIM_STATUS_SEL_SLOW 0x0400 92 #define PCIM_STATUS_SEL_MASK 0x0600 93 #define PCIM_STATUS_STABORT 0x0800 94 #define PCIM_STATUS_RTABORT 0x1000 95 #define PCIM_STATUS_RMABORT 0x2000 96 #define PCIM_STATUS_SERR 0x4000 97 #define PCIM_STATUS_PERR 0x8000 98 99 #define PCIR_REVID 0x08 100 #define PCIR_PROGIF 0x09 101 #define PCIR_SUBCLASS 0x0a 102 #define PCIR_CLASS 0x0b 103 #define PCIR_CACHELNSZ 0x0c 104 #define PCIR_LATTIMER 0x0d 105 106 #define PCIR_HDRTYPE 0x0e 107 #define PCIM_HDRTYPE 0x7f 108 #define PCIM_HDRTYPE_NORMAL 0x00 109 #define PCIM_HDRTYPE_BRIDGE 0x01 110 #define PCIM_HDRTYPE_CARDBUS 0x02 111 #define PCIM_MFDEV 0x80 112 113 #define PCIR_BIST 0x0f 114 115 /* Capability Register Offsets */ 116 #define PCICAP_ID 0x0 117 #define PCICAP_NEXTPTR 0x1 118 119 /* Capability Identification Numbers */ 120 #define PCIY_PMG 0x01 /* PCI Power Management */ 121 #define PCIY_AGP 0x02 /* AGP */ 122 #define PCIY_VPD 0x03 /* Vital Product Data */ 123 #define PCIY_SLOTID 0x04 /* Slot Identification */ 124 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 125 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 126 #define PCIY_PCIX 0x07 /* PCI-X */ 127 #define PCIY_HT 0x08 /* HyperTransport */ 128 #define PCIY_VENDOR 0x09 /* Vendor Unique */ 129 #define PCIY_DEBUG 0x0a /* Debug port */ 130 #define PCIY_CRES 0x0b /* CompactPCI central resource control */ 131 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 132 #define PCIY_AGP8X 0x0e /* AGP 8x */ 133 #define PCIY_SECDEV 0x0f /* Secure Device */ 134 #define PCIY_EXPRESS 0x10 /* PCI Express */ 135 #define PCIY_MSIX 0x11 /* MSI-X */ 136 137 /* config registers for header type 0 devices */ 138 139 #define PCIR_BARS 0x10 140 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 141 #define PCIR_MAPS PCIR_BARS /* DEPRECATED XXX */ 142 #define PCIR_CARDBUSCIS 0x28 143 #define PCIR_SUBVEND_0 0x2c 144 #define PCIR_SUBDEV_0 0x2e 145 #define PCIR_BIOS 0x30 146 #define PCIM_BIOS_ENABLE 0x01 147 #define PCIR_CAP_PTR 0x34 148 #define PCIR_INTLINE 0x3c 149 #define PCIR_INTPIN 0x3d 150 #define PCIR_MINGNT 0x3e 151 #define PCIR_MAXLAT 0x3f 152 153 /* config registers for header type 1 devices */ 154 155 #define PCIR_SECSTAT_1 0x1e 156 157 #define PCIR_PRIBUS_1 0x18 158 #define PCIR_SECBUS_1 0x19 159 #define PCIR_SUBBUS_1 0x1a 160 #define PCIR_SECLAT_1 0x1b 161 162 #define PCIR_IOBASEL_1 0x1c 163 #define PCIR_IOLIMITL_1 0x1d 164 #define PCIR_IOBASEH_1 0x30 165 #define PCIR_IOLIMITH_1 0x32 166 #define PCIM_BRIO_16 0x0 167 #define PCIM_BRIO_32 0x1 168 #define PCIM_BRIO_MASK 0xf 169 170 #define PCIR_MEMBASE_1 0x20 171 #define PCIR_MEMLIMIT_1 0x22 172 173 #define PCIR_PMBASEL_1 0x24 174 #define PCIR_PMLIMITL_1 0x26 175 #define PCIR_PMBASEH_1 0x28 176 #define PCIR_PMLIMITH_1 0x2c 177 178 #define PCIR_BRIDGECTL_1 0x3e 179 180 #define PCIR_SUBVEND_1 0x34 181 #define PCIR_SUBDEV_1 0x36 182 183 /* config registers for header type 2 (Cardbus) devices */ 184 185 #define PCIR_CAP_PTR_2 0x14 186 #define PCIR_SECSTAT_2 0x16 187 188 #define PCIR_PRIBUS_2 0x18 189 #define PCIR_SECBUS_2 0x19 190 #define PCIR_SUBBUS_2 0x1a 191 #define PCIR_SECLAT_2 0x1b 192 193 #define PCIR_MEMBASE0_2 0x1c 194 #define PCIR_MEMLIMIT0_2 0x20 195 #define PCIR_MEMBASE1_2 0x24 196 #define PCIR_MEMLIMIT1_2 0x28 197 #define PCIR_IOBASE0_2 0x2c 198 #define PCIR_IOLIMIT0_2 0x30 199 #define PCIR_IOBASE1_2 0x34 200 #define PCIR_IOLIMIT1_2 0x38 201 202 #define PCIR_BRIDGECTL_2 0x3e 203 204 #define PCIR_SUBVEND_2 0x40 205 #define PCIR_SUBDEV_2 0x42 206 207 #define PCIR_PCCARDIF_2 0x44 208 209 /* PCI device class, subclass and programming interface definitions */ 210 211 #define PCIC_OLD 0x00 212 #define PCIS_OLD_NONVGA 0x00 213 #define PCIS_OLD_VGA 0x01 214 215 #define PCIC_STORAGE 0x01 216 #define PCIS_STORAGE_SCSI 0x00 217 #define PCIS_STORAGE_IDE 0x01 218 #define PCIP_STORAGE_IDE_MODEPRIM 0x01 219 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 220 #define PCIP_STORAGE_IDE_MODESEC 0x04 221 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 222 #define PCIP_STORAGE_IDE_MASTERDEV 0x80 223 #define PCIS_STORAGE_FLOPPY 0x02 224 #define PCIS_STORAGE_IPI 0x03 225 #define PCIS_STORAGE_RAID 0x04 226 #define PCIS_STORAGE_ATA 0x05 227 #define PCIP_STORAGE_ATA_SINGLEDMA 0x20 228 #define PCIP_STORAGE_ATA_CHAINDMA 0x30 229 #define PCIS_STORAGE_SATA 0x06 230 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01 231 #define PCIS_STORAGE_SAS 0x07 232 #define PCIP_STORAGE_SAS_VENDOR 0x00 233 #define PCIP_STORAGE_SAS_SSB 0x01 234 #define PCIS_STORAGE_OTHER 0x80 235 236 #define PCIC_NETWORK 0x02 237 #define PCIS_NETWORK_ETHERNET 0x00 238 #define PCIS_NETWORK_TOKENRING 0x01 239 #define PCIS_NETWORK_FDDI 0x02 240 #define PCIS_NETWORK_ATM 0x03 241 #define PCIS_NETWORK_ISDN 0x04 242 #define PCIS_NETWORK_WORLDFIP 0x05 243 #define PCIS_NETWORK_PICMG 0x06 244 #define PCIS_NETWORK_OTHER 0x80 245 246 #define PCIC_DISPLAY 0x03 247 #define PCIS_DISPLAY_VGA 0x00 248 #define PCIP_DISPLAY_VGA_COMP 0x00 249 #define PCIP_DISPLAY_VGA_8514 0x01 250 #define PCIS_DISPLAY_XGA 0x01 251 #define PCIS_DISPLAY_3D 0x02 252 #define PCIS_DISPLAY_OTHER 0x80 253 254 #define PCIC_MULTIMEDIA 0x04 255 #define PCIS_MULTIMEDIA_VIDEO 0x00 256 #define PCIS_MULTIMEDIA_AUDIO 0x01 257 #define PCIS_MULTIMEDIA_TEL 0x02 258 #define PCIS_MULTIMEDIA_OTHER 0x80 259 260 #define PCIC_MEMORY 0x05 261 #define PCIS_MEMORY_RAM 0x00 262 #define PCIS_MEMORY_FLASH 0x01 263 #define PCIS_MEMORY_OTHER 0x80 264 265 #define PCIC_BRIDGE 0x06 266 #define PCIS_BRIDGE_HOST 0x00 267 #define PCIS_BRIDGE_ISA 0x01 268 #define PCIS_BRIDGE_EISA 0x02 269 #define PCIS_BRIDGE_MCA 0x03 270 #define PCIS_BRIDGE_PCI 0x04 271 #define PCIS_BRIDGE_PCMCIA 0x05 272 #define PCIS_BRIDGE_NUBUS 0x06 273 #define PCIS_BRIDGE_CARDBUS 0x07 274 #define PCIS_BRIDGE_RACEWAY 0x08 275 #define PCIS_BRIDGE_SEMITRANS 0x09 276 #define PCIS_BRIDGE_INFINI 0x0a 277 #define PCIS_BRIDGE_OTHER 0x80 278 279 #define PCIC_SIMPLECOMM 0x07 280 #define PCIS_SIMPLECOMM_UART 0x00 281 #define PCIP_SIMPLECOMM_UART_16550A 0x02 282 #define PCIS_SIMPLECOMM_PAR 0x01 283 #define PCIS_SIMPLECOMM_MULTSER 0x02 284 #define PCIS_SIMPLECOMM_MODEM 0x03 285 #define PCIS_SIMPLECOMM_GPIB 0x04 286 #define PCIS_SIMPLECOMM_SMART 0x05 287 #define PCIS_SIMPLECOMM_OTHER 0x80 288 289 #define PCIC_BASEPERIPH 0x08 290 #define PCIS_BASEPERIPH_PIC 0x00 291 #define PCIS_BASEPERIPH_DMA 0x01 292 #define PCIS_BASEPERIPH_TIMER 0x02 293 #define PCIS_BASEPERIPH_RTC 0x03 294 #define PCIS_BASEPERIPH_HOTPLUG 0x04 295 #define PCIS_BASEPERIPH_OTHER 0x80 296 297 #define PCIC_INPUTDEV 0x09 298 #define PCIS_INPUTDEV_KEYBOARD 0x00 299 #define PCIS_INPUTDEV_DIGITIZER 0x01 300 #define PCIS_INPUTDEV_MOUSE 0x02 301 #define PCIS_INPUTDEV_SCANNER 0x03 302 #define PCIS_INPUTDEV_GAMEPORT 0x04 303 #define PCIS_INPUTDEV_OTHER 0x80 304 305 #define PCIC_DOCKING 0x0a 306 #define PCIS_DOCKING_GENERIC 0x00 307 #define PCIS_DOCKING_OTHER 0x80 308 309 #define PCIC_PROCESSOR 0x0b 310 #define PCIS_PROCESSOR_386 0x00 311 #define PCIS_PROCESSOR_486 0x01 312 #define PCIS_PROCESSOR_PENTIUM 0x02 313 #define PCIS_PROCESSOR_ALPHA 0x10 314 #define PCIS_PROCESSOR_POWERPC 0x20 315 #define PCIS_PROCESSOR_MIPS 0x30 316 #define PCIS_PROCESSOR_COPROC 0x40 317 318 #define PCIC_SERIALBUS 0x0c 319 #define PCIS_SERIALBUS_FW 0x00 320 #define PCIS_SERIALBUS_ACCESS 0x01 321 #define PCIS_SERIALBUS_SSA 0x02 322 #define PCIS_SERIALBUS_USB 0x03 323 #define PCIS_SERIALBUS_FC 0x04 324 #define PCIS_SERIALBUS_SMBUS 0x05 325 #define PCIS_SERIALBUS_INFINI 0x06 326 #define PCIS_SERIALBUS_IPMI 0x07 327 #define PCIS_SERIALBUS_SERCOS 0x08 328 #define PCIS_SERIALBUS_CANBUS 0x09 329 330 #define PCIC_WIRELESS 0x0d 331 #define PCIS_WIRELESS_IRDA 0x00 332 #define PCIS_WIRELESS_IR 0x01 333 #define PCIS_WIRELESS_RF 0x10 334 #define PCIS_WIRELESS_BLUETOOTH 0x11 335 #define PCIS_WIRELESS_BROADBAND 0x12 336 #define PCIS_WIRELESS_80211A 0x20 337 #define PCIS_WIRELESS_80211B 0x21 338 #define PCIS_WIRELESS_OTHER 0x80 339 340 #define PCIC_I2O 0x0e 341 #define PCIS_I2O_10 0x00 342 343 #define PCIC_SATELLITE 0x0f 344 #define PCIS_SATELLITE_TV 0x01 345 #define PCIS_SATELLITE_AUDIO 0x02 346 #define PCIS_SATELLITE_VOICE 0x03 347 #define PCIS_SATELLITE_DATA 0x04 348 349 #define PCIC_CRYPTO 0x10 350 #define PCIS_CRYPTO_NETWORK 0x00 351 #define PCIS_CRYPTO_ENTERTAIN 0x10 352 #define PCIS_CRYPTO_OTHER 0x80 353 354 #define PCIC_SIGPROC 0x11 355 #define PCIS_SIGPROC_DPIO 0x00 356 #define PCIS_SIGPROC_PERFCOUNT 0x01 357 #define PCIS_SIGPROC_COMMSYNC 0x10 358 #define PCIS_SIGPROC_MANAGEMENT 0x20 359 #define PCIS_SIGPROC_OTHER 0x80 360 361 #define PCIC_OTHER 0xff 362 363 /* PCI power manangement */ 364 365 #define PCIR_POWER_CAP 0x2 366 #define PCIM_PCAP_SPEC 0x0007 367 #define PCIM_PCAP_PMEREQCLK 0x0008 368 #define PCIM_PCAP_PMEREQPWR 0x0010 369 #define PCIM_PCAP_DEVSPECINIT 0x0020 370 #define PCIM_PCAP_DYNCLOCK 0x0040 371 #define PCIM_PCAP_SECCLOCK 0x00c0 372 #define PCIM_PCAP_CLOCKMASK 0x00c0 373 #define PCIM_PCAP_REQFULLCLOCK 0x0100 374 #define PCIM_PCAP_D1SUPP 0x0200 375 #define PCIM_PCAP_D2SUPP 0x0400 376 #define PCIM_PCAP_D0PME 0x1000 377 #define PCIM_PCAP_D1PME 0x2000 378 #define PCIM_PCAP_D2PME 0x4000 379 380 #define PCIR_POWER_STATUS 0x4 381 #define PCIM_PSTAT_D0 0x0000 382 #define PCIM_PSTAT_D1 0x0001 383 #define PCIM_PSTAT_D2 0x0002 384 #define PCIM_PSTAT_D3 0x0003 385 #define PCIM_PSTAT_DMASK 0x0003 386 #define PCIM_PSTAT_REPENABLE 0x0010 387 #define PCIM_PSTAT_PMEENABLE 0x0100 388 #define PCIM_PSTAT_D0POWER 0x0000 389 #define PCIM_PSTAT_D1POWER 0x0200 390 #define PCIM_PSTAT_D2POWER 0x0400 391 #define PCIM_PSTAT_D3POWER 0x0600 392 #define PCIM_PSTAT_D0HEAT 0x0800 393 #define PCIM_PSTAT_D1HEAT 0x1000 394 #define PCIM_PSTAT_D2HEAT 0x1200 395 #define PCIM_PSTAT_D3HEAT 0x1400 396 #define PCIM_PSTAT_DATAUNKN 0x0000 397 #define PCIM_PSTAT_DATADIV10 0x2000 398 #define PCIM_PSTAT_DATADIV100 0x4000 399 #define PCIM_PSTAT_DATADIV1000 0x6000 400 #define PCIM_PSTAT_DATADIVMASK 0x6000 401 #define PCIM_PSTAT_PME 0x8000 402 403 #define PCIR_POWER_PMCSR 0x6 404 #define PCIM_PMCSR_DCLOCK 0x10 405 #define PCIM_PMCSR_B2SUPP 0x20 406 #define PCIM_BMCSR_B3SUPP 0x40 407 #define PCIM_BMCSR_BPCE 0x80 408 409 #define PCIR_POWER_DATA 0x7 410 411 /* VPD capability registers */ 412 #define PCIR_VPD_ADDR 0x2 413 #define PCIR_VPD_DATA 0x4 414 415 /* PCI Message Signalled Interrupts (MSI) */ 416 #define PCIR_MSI_CTRL 0x2 417 #define PCIM_MSICTRL_VECTOR 0x0100 418 #define PCIM_MSICTRL_64BIT 0x0080 419 #define PCIM_MSICTRL_MME_MASK 0x0070 420 #define PCIM_MSICTRL_MME_1 0x0000 421 #define PCIM_MSICTRL_MME_2 0x0010 422 #define PCIM_MSICTRL_MME_4 0x0020 423 #define PCIM_MSICTRL_MME_8 0x0030 424 #define PCIM_MSICTRL_MME_16 0x0040 425 #define PCIM_MSICTRL_MME_32 0x0050 426 #define PCIM_MSICTRL_MMC_MASK 0x000E 427 #define PCIM_MSICTRL_MMC_1 0x0000 428 #define PCIM_MSICTRL_MMC_2 0x0002 429 #define PCIM_MSICTRL_MMC_4 0x0004 430 #define PCIM_MSICTRL_MMC_8 0x0006 431 #define PCIM_MSICTRL_MMC_16 0x0008 432 #define PCIM_MSICTRL_MMC_32 0x000A 433 #define PCIM_MSICTRL_MSI_ENABLE 0x0001 434 #define PCIR_MSI_ADDR 0x4 435 #define PCIR_MSI_ADDR_HIGH 0x8 436 #define PCIR_MSI_DATA 0x8 437 #define PCIR_MSI_DATA_64BIT 0xc 438 #define PCIR_MSI_MASK 0x10 439 #define PCIR_MSI_PENDING 0x14 440 441 /* PCI-X definitions */ 442 #define PCIXR_COMMAND 0x96 443 #define PCIXR_DEVADDR 0x98 444 #define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */ 445 #define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */ 446 #define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */ 447 #define PCIXR_STATUS 0x9A 448 #define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */ 449 #define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */ 450 #define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */ 451 #define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */ 452 #define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */ 453 #define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */ 454 #define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */ 455 #define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */ 456 #define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */ 457 458 /* 459 * PCI Express definitions 460 * According to 461 * PCI Express base specification, REV. 1.0a 462 */ 463 464 /* PCI Express capabilities, 16bits */ 465 #define PCIER_CAPABILITY 0x2 466 #define PCIEM_CAP_VER_MASK 0x000f /* Version */ 467 #define PCIEM_CAP_VER_1 0x0001 468 #define PCIEM_CAP_PORT_TYPE 0x00f0 /* Port type mask */ 469 #define PCIEM_CAP_SLOT_IMPL 0x0100 /* Slot implemented, 470 * valid only for root port and 471 * switch downstream port 472 */ 473 /* PCI Express port types */ 474 #define PCIE_END_POINT 0x0000 /* Endpoint device */ 475 #define PCIE_LEG_END_POINT 0x0010 /* Legacy endpoint device */ 476 #define PCIE_ROOT_PORT 0x0040 /* Root port */ 477 #define PCIE_UP_STREAM_PORT 0x0050 /* Switch upstream port */ 478 #define PCIE_DOWN_STREAM_PORT 0x0060 /* Switch downstream port */ 479 #define PCIE_PCIE2PCI_BRIDGE 0x0070 /* PCI Express to PCI/PCI-X bridge */ 480 #define PCIE_PCI2PCIE_BRIDGE 0x0080 /* PCI/PCI-X to PCI Express bridge */ 481 482 /* PCI Express device control, 16bits */ 483 #define PCIER_DEVCTRL 0x08 484 #define PCIEM_DEVCTL_MAX_READRQ_MASK 0x7000 /* Max read request size */ 485 #define PCIEM_DEVCTL_MAX_READRQ_128 0x0000 486 #define PCIEM_DEVCTL_MAX_READRQ_256 0x1000 487 #define PCIEM_DEVCTL_MAX_READRQ_512 0x2000 488 #define PCIEM_DEVCTL_MAX_READRQ_1024 0x3000 489 #define PCIEM_DEVCTL_MAX_READRQ_2048 0x4000 490 #define PCIEM_DEVCTL_MAX_READRQ_4096 0x5000 491 492 /* PCI Express slot capabilities, 32bits */ 493 #define PCIER_SLOTCAP 0x14 494 #define PCIEM_SLTCAP_ATTEN_BTN 0x00000001 /* Attention button present */ 495 #define PCIEM_SLTCAP_PWR_CTRL 0x00000002 /* Power controller present */ 496 #define PCIEM_SLTCAP_MRL_SNS 0x00000004 /* MRL sensor present */ 497 #define PCIEM_SLTCAP_ATTEN_IND 0x00000008 /* Attention indicator present */ 498 #define PCIEM_SLTCAP_PWR_IND 0x00000010 /* Power indicator present */ 499 #define PCIEM_SLTCAP_HP_SURP 0x00000020 /* Hot-Plug surprise */ 500 #define PCIEM_SLTCAP_HP_CAP 0x00000040 /* Hot-Plug capable */ 501 #define PCIEM_SLTCAP_HP_MASK 0x0000007f /* Hot-Plug related bits */ 502 503 /* PCI Express slot control, 16bits */ 504 #define PCIER_SLOTCTRL 0x18 505 #define PCIEM_SLTCTL_HPINTR_MASK 0x001f /* Hot-plug interrupts mask */ 506 #define PCIEM_SLTCTL_HPINTR_EN 0x0020 /* Enable hot-plug interrupts */ 507 /* PCI Expres hot-plug interrupts */ 508 #define PCIE_HPINTR_ATTEN_BTN 0x0001 /* Attention button intr */ 509 #define PCIE_HPINTR_PWR_FAULT 0x0002 /* Power fault intr */ 510 #define PCIE_HPINTR_MRL_SNS 0x0004 /* MRL sensor changed intr */ 511 #define PCIE_HPINTR_PRSN_DETECT 0x0008 /* Presence detect intr */ 512 #define PCIE_HPINTR_CMD_COMPL 0x0010 /* Command completed intr */ 513 514 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ 515 516 #if defined(_KERNEL) && !defined(KLD_MODULE) 517 #include "opt_compat_oldpci.h" 518 #endif 519 520 #ifdef COMPAT_OLDPCI 521 522 #define PCI_ID_REG 0x00 523 #define PCI_COMMAND_STATUS_REG 0x04 524 #define PCI_COMMAND_IO_ENABLE 0x00000001 525 #define PCI_COMMAND_MEM_ENABLE 0x00000002 526 #define PCI_CLASS_REG 0x08 527 #define PCI_CLASS_MASK 0xff000000 528 #define PCI_SUBCLASS_MASK 0x00ff0000 529 #define PCI_REVISION_MASK 0x000000ff 530 #define PCI_CLASS_PREHISTORIC 0x00000000 531 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000 532 #define PCI_CLASS_MASS_STORAGE 0x01000000 533 #define PCI_CLASS_DISPLAY 0x03000000 534 #define PCI_SUBCLASS_DISPLAY_VGA 0x00000000 535 #define PCI_CLASS_BRIDGE 0x06000000 536 #define PCI_MAP_REG_START 0x10 537 #define PCI_MAP_REG_END 0x28 538 #define PCI_MAP_IO 0x00000001 539 #define PCI_INTERRUPT_REG 0x3c 540 541 #endif /* COMPAT_OLDPCI */ 542 543 #endif 544