1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pcivar.h,v 1.41.2.2 2002/01/10 12:08:22 mdodd Exp $ 27 * $DragonFly: src/sys/bus/pci/pcivar.h,v 1.5 2004/01/15 20:35:06 joerg Exp $ 28 * 29 */ 30 31 #ifndef _PCIVAR_H_ 32 #define _PCIVAR_H_ 33 34 #include <sys/queue.h> 35 36 /* some PCI bus constants */ 37 38 #define PCI_BUSMAX 255 /* highest supported bus number */ 39 #define PCI_SLOTMAX 31 /* highest supported slot number */ 40 #define PCI_FUNCMAX 7 /* highest supported function number */ 41 #define PCI_REGMAX 255 /* highest supported config register addr. */ 42 43 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 44 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 45 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 46 47 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 48 49 #ifdef PCI_A64 50 typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 51 #else 52 typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 53 #endif 54 55 /* config header information common to all header types */ 56 57 typedef struct pcicfg { 58 struct device *dev; /* device which owns this */ 59 void *hdrspec; /* pointer to header type specific data */ 60 61 u_int16_t subvendor; /* card vendor ID */ 62 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 63 u_int16_t vendor; /* chip vendor ID */ 64 u_int16_t device; /* chip device ID, assigned by chip vendor */ 65 66 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 67 u_int16_t statreg; /* supported PCI features and error state */ 68 69 u_int8_t baseclass; /* chip PCI class */ 70 u_int8_t subclass; /* chip PCI subclass */ 71 u_int8_t progif; /* chip PCI programming interface */ 72 u_int8_t revid; /* chip revision ID */ 73 74 u_int8_t hdrtype; /* chip config header type */ 75 u_int8_t cachelnsz; /* cache line size in 4byte units */ 76 u_int8_t intpin; /* PCI interrupt pin */ 77 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 78 79 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 80 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 81 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 82 83 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 84 u_int8_t nummaps; /* actual number of PCI maps used */ 85 86 u_int8_t bus; /* config space bus address */ 87 u_int8_t slot; /* config space slot address */ 88 u_int8_t func; /* config space function number */ 89 90 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 91 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 92 93 u_int16_t pp_cap; /* PCI power management capabilities */ 94 u_int8_t pp_status; /* config space address of PCI power status reg */ 95 u_int8_t pp_pmcsr; /* config space address of PMCSR reg */ 96 u_int8_t pp_data; /* config space address of PCI power data reg */ 97 } pcicfgregs; 98 99 /* additional type 1 device config header information (PCI to PCI bridge) */ 100 101 #ifdef PCI_A64 102 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 103 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 104 #else 105 #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 106 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 107 #endif /* PCI_A64 */ 108 109 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 110 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 111 112 typedef struct { 113 pci_addr_t pmembase; /* base address of prefetchable memory */ 114 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 115 u_int32_t membase; /* base address of memory window */ 116 u_int32_t memlimit; /* topmost address of memory window */ 117 u_int32_t iobase; /* base address of port window */ 118 u_int32_t iolimit; /* topmost address of port window */ 119 u_int16_t secstat; /* secondary bus status register */ 120 u_int16_t bridgectl; /* bridge control register */ 121 u_int8_t seclat; /* CardBus latency timer */ 122 } pcih1cfgregs; 123 124 /* additional type 2 device config header information (CardBus bridge) */ 125 126 typedef struct { 127 u_int32_t membase0; /* base address of memory window */ 128 u_int32_t memlimit0; /* topmost address of memory window */ 129 u_int32_t membase1; /* base address of memory window */ 130 u_int32_t memlimit1; /* topmost address of memory window */ 131 u_int32_t iobase0; /* base address of port window */ 132 u_int32_t iolimit0; /* topmost address of port window */ 133 u_int32_t iobase1; /* base address of port window */ 134 u_int32_t iolimit1; /* topmost address of port window */ 135 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 136 u_int16_t secstat; /* secondary bus status register */ 137 u_int16_t bridgectl; /* bridge control register */ 138 u_int8_t seclat; /* CardBus latency timer */ 139 } pcih2cfgregs; 140 141 extern u_int32_t pci_numdevs; 142 143 /* Only if the prerequisites are present */ 144 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 145 struct pci_devinfo { 146 STAILQ_ENTRY(pci_devinfo) pci_links; 147 struct resource_list resources; 148 pcicfgregs cfg; 149 struct pci_conf conf; 150 }; 151 #endif 152 153 /* externally visible functions */ 154 155 const char *pci_ata_match(struct device *dev); 156 const char *pci_usb_match(struct device *dev); 157 const char *pci_vga_match(struct device *dev); 158 const char *pci_chip_match(struct device *dev); 159 160 /* low level PCI config register functions provided by pcibus.c */ 161 162 int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 163 void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 164 #ifdef __alpha__ 165 vm_offset_t pci_cvt_to_dense (vm_offset_t); 166 vm_offset_t pci_cvt_to_bwx (vm_offset_t); 167 #endif /* __alpha__ */ 168 169 /* low level devlist operations for the 2.2 compatibility code in pci.c */ 170 pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg); 171 172 #ifdef _SYS_BUS_H_ 173 174 #include "pci_if.h" 175 176 /* 177 * Define pci-specific resource flags for accessing memory via dense 178 * or bwx memory spaces. These flags are ignored on i386. 179 */ 180 #define PCI_RF_DENSE 0x10000 181 #define PCI_RF_BWX 0x20000 182 183 enum pci_device_ivars { 184 PCI_IVAR_SUBVENDOR, 185 PCI_IVAR_SUBDEVICE, 186 PCI_IVAR_VENDOR, 187 PCI_IVAR_DEVICE, 188 PCI_IVAR_DEVID, 189 PCI_IVAR_CLASS, 190 PCI_IVAR_SUBCLASS, 191 PCI_IVAR_PROGIF, 192 PCI_IVAR_REVID, 193 PCI_IVAR_INTPIN, 194 PCI_IVAR_IRQ, 195 PCI_IVAR_BUS, 196 PCI_IVAR_SLOT, 197 PCI_IVAR_FUNCTION, 198 PCI_IVAR_SECONDARYBUS, 199 PCI_IVAR_SUBORDINATEBUS, 200 }; 201 202 /* 203 * Simplified accessors for pci devices 204 */ 205 #define PCI_ACCESSOR(A, B, T) \ 206 \ 207 static __inline T pci_get_ ## A(device_t dev) \ 208 { \ 209 uintptr_t v; \ 210 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 211 return (T) v; \ 212 } \ 213 \ 214 static __inline void pci_set_ ## A(device_t dev, T t) \ 215 { \ 216 uintptr_t v = (uintptr_t) t; \ 217 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 218 } 219 220 PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 221 PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 222 PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 223 PCI_ACCESSOR(device, DEVICE, u_int16_t) 224 PCI_ACCESSOR(devid, DEVID, u_int32_t) 225 PCI_ACCESSOR(class, CLASS, u_int8_t) 226 PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 227 PCI_ACCESSOR(progif, PROGIF, u_int8_t) 228 PCI_ACCESSOR(revid, REVID, u_int8_t) 229 PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 230 PCI_ACCESSOR(irq, IRQ, u_int8_t) 231 PCI_ACCESSOR(bus, BUS, u_int8_t) 232 PCI_ACCESSOR(slot, SLOT, u_int8_t) 233 PCI_ACCESSOR(function, FUNCTION, u_int8_t) 234 PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 235 PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 236 237 #undef PCI_ACCESSOR 238 239 static __inline u_int32_t 240 pci_read_config(device_t dev, int reg, int width) 241 { 242 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 243 } 244 245 static __inline void 246 pci_write_config(device_t dev, int reg, u_int32_t val, int width) 247 { 248 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 249 } 250 251 /* 252 * Convenience functions. 253 * 254 * These should be used in preference to manually manipulating 255 * configuration space. 256 */ 257 static __inline void 258 pci_enable_busmaster(device_t dev) 259 { 260 PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev); 261 } 262 263 static __inline void 264 pci_disable_busmaster(device_t dev) 265 { 266 PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev); 267 } 268 269 static __inline void 270 pci_enable_io(device_t dev, int space) 271 { 272 PCI_ENABLE_IO(device_get_parent(dev), dev, space); 273 } 274 275 static __inline void 276 pci_disable_io(device_t dev, int space) 277 { 278 PCI_DISABLE_IO(device_get_parent(dev), dev, space); 279 } 280 281 /* 282 * PCI power states are as defined by ACPI: 283 * 284 * D0 State in which device is on and running. It is receiving full 285 * power from the system and delivering full functionality to the user. 286 * D1 Class-specific low-power state in which device context may or may not 287 * be lost. Buses in D1 cannot do anything to the bus that would force 288 * devices on that bus to loose context. 289 * D2 Class-specific low-power state in which device context may or may 290 * not be lost. Attains greater power savings than D1. Buses in D2 291 * can cause devices on that bus to loose some context. Devices in D2 292 * must be prepared for the bus to be in D2 or higher. 293 * D3 State in which the device is off and not running. Device context is 294 * lost. Power can be removed from the device. 295 */ 296 #define PCI_POWERSTATE_D0 0 297 #define PCI_POWERSTATE_D1 1 298 #define PCI_POWERSTATE_D2 2 299 #define PCI_POWERSTATE_D3 3 300 #define PCI_POWERSTATE_UNKNOWN -1 301 302 static __inline int 303 pci_set_powerstate(device_t dev, int state) 304 { 305 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 306 } 307 308 static __inline int 309 pci_get_powerstate(device_t dev) 310 { 311 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 312 } 313 314 /* 315 * Ivars for pci bridges. 316 */ 317 318 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 319 enum pcib_device_ivars { 320 PCIB_IVAR_BUS, 321 }; 322 323 #define PCIB_ACCESSOR(A, B, T) \ 324 \ 325 static __inline T pcib_get_ ## A(device_t dev) \ 326 { \ 327 uintptr_t v; \ 328 BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 329 return (T) v; \ 330 } \ 331 \ 332 static __inline void pcib_set_ ## A(device_t dev, T t) \ 333 { \ 334 uintptr_t v = (uintptr_t) t; \ 335 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 336 } 337 338 PCIB_ACCESSOR(bus, BUS, u_int32_t) 339 340 #undef PCIB_ACCESSOR 341 342 device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t); 343 device_t pci_find_device(u_int16_t, u_int16_t); 344 #endif 345 346 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ 347 348 #if defined(_KERNEL) && !defined(KLD_MODULE) 349 #include "opt_compat_oldpci.h" 350 #endif 351 352 #ifdef COMPAT_OLDPCI 353 /* all this is going some day */ 354 355 typedef pcicfgregs *pcici_t; 356 typedef unsigned pcidi_t; 357 typedef void pci_inthand_t(void *arg); 358 359 #define pci_max_burst_len (3) 360 361 /* just copied from old PCI code for now ... */ 362 363 struct pci_device { 364 char* pd_name; 365 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 366 void (*pd_attach) (pcici_t tag, int unit); 367 u_long *pd_count; 368 int (*pd_shutdown) (int, int); 369 }; 370 371 #ifdef __i386__ 372 typedef u_short pci_port_t; 373 #else 374 typedef u_int pci_port_t; 375 #endif 376 377 u_long pci_conf_read (pcici_t tag, u_long reg); 378 void pci_conf_write (pcici_t tag, u_long reg, u_long data); 379 int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 380 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 381 int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg, 382 intrmask_t *maskptr); 383 int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 384 intrmask_t *maskptr, u_int flags); 385 int pci_unmap_int (pcici_t tag); 386 387 pcici_t pci_get_parent_from_tag(pcici_t tag); 388 int pci_get_bus_from_tag(pcici_t tag); 389 390 struct module; 391 int compat_pci_handler (struct module *, int, void *); 392 #define COMPAT_PCI_DRIVER(name, pcidata) \ 393 static moduledata_t name##_mod = { \ 394 #name, \ 395 compat_pci_handler, \ 396 &pcidata \ 397 }; \ 398 DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 399 400 401 #endif /* COMPAT_OLDPCI */ 402 #endif /* _PCIVAR_H_ */ 403