1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/pci/pcivar.h,v 1.80.2.1.4.1 2009/04/15 03:14:26 kensmith Exp $ 27 * 28 */ 29 30 #ifndef _PCIVAR_H_ 31 #define _PCIVAR_H_ 32 33 #ifndef _SYS_QUEUE_H_ 34 #include <sys/queue.h> 35 #endif 36 37 /* some PCI bus constants */ 38 39 #define PCI_DOMAINMAX 65535 /* highest supported domain number */ 40 #define PCI_BUSMAX 255 /* highest supported bus number */ 41 #define PCI_SLOTMAX 31 /* highest supported slot number */ 42 #define PCI_FUNCMAX 7 /* highest supported function number */ 43 #define PCI_REGMAX 255 /* highest supported config register addr. */ 44 45 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 46 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 47 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 48 49 typedef uint64_t pci_addr_t; 50 51 /* Interesting values for PCI power management */ 52 struct pcicfg_pp { 53 uint16_t pp_cap; /* PCI power management capabilities */ 54 uint8_t pp_status; /* config space address of PCI power status reg */ 55 uint8_t pp_pmcsr; /* config space address of PMCSR reg */ 56 uint8_t pp_data; /* config space address of PCI power data reg */ 57 }; 58 59 struct vpd_readonly { 60 char keyword[2]; 61 char *value; 62 }; 63 64 struct vpd_write { 65 char keyword[2]; 66 char *value; 67 int start; 68 int len; 69 }; 70 71 struct pcicfg_vpd { 72 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 73 char vpd_cached; 74 char *vpd_ident; /* string identifier */ 75 int vpd_rocnt; 76 struct vpd_readonly *vpd_ros; 77 int vpd_wcnt; 78 struct vpd_write *vpd_w; 79 }; 80 81 /* Interesting values for PCI MSI */ 82 struct pcicfg_msi { 83 uint16_t msi_ctrl; /* Message Control */ 84 uint8_t msi_location; /* Offset of MSI capability registers. */ 85 uint8_t msi_msgnum; /* Number of messages */ 86 int msi_alloc; /* Number of allocated messages. */ 87 uint64_t msi_addr; /* Contents of address register. */ 88 uint16_t msi_data; /* Contents of data register. */ 89 u_int msi_handlers; 90 }; 91 92 /* Interesting values for PCI MSI-X */ 93 struct msix_vector { 94 uint64_t mv_address; /* Contents of address register. */ 95 uint32_t mv_data; /* Contents of data register. */ 96 int mv_irq; 97 }; 98 99 struct msix_table_entry { 100 u_int mte_vector; /* 1-based index into msix_vectors array. */ 101 u_int mte_handlers; 102 }; 103 104 struct pcicfg_msix { 105 uint16_t msix_ctrl; /* Message Control */ 106 uint16_t msix_msgnum; /* Number of messages */ 107 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 108 uint8_t msix_table_bar; /* BAR containing vector table. */ 109 uint8_t msix_pba_bar; /* BAR containing PBA. */ 110 uint32_t msix_table_offset; 111 uint32_t msix_pba_offset; 112 int msix_alloc; /* Number of allocated vectors. */ 113 int msix_table_len; /* Length of virtual table. */ 114 struct msix_table_entry *msix_table; /* Virtual table. */ 115 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 116 struct resource *msix_table_res; /* Resource containing vector table. */ 117 struct resource *msix_pba_res; /* Resource containing PBA. */ 118 }; 119 120 /* Interesting values for HyperTransport */ 121 struct pcicfg_ht { 122 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 123 uint16_t ht_msictrl; /* MSI mapping control */ 124 uint64_t ht_msiaddr; /* MSI mapping base address */ 125 }; 126 127 /* Interesting values for PCI Express capability */ 128 struct pcicfg_expr { 129 uint8_t expr_ptr; /* capability ptr */ 130 uint16_t expr_cap; /* capabilities */ 131 uint32_t expr_slotcap; /* slot capabilities */ 132 }; 133 134 /* Interesting values for PCI-X */ 135 struct pcicfg_pcix { 136 uint8_t pcix_ptr; 137 }; 138 139 /* config header information common to all header types */ 140 typedef struct pcicfg { 141 struct device *dev; /* device which owns this */ 142 143 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */ 144 uint32_t bios; /* BIOS mapping */ 145 146 uint16_t subvendor; /* card vendor ID */ 147 uint16_t subdevice; /* card device ID, assigned by card vendor */ 148 uint16_t vendor; /* chip vendor ID */ 149 uint16_t device; /* chip device ID, assigned by chip vendor */ 150 151 uint16_t cmdreg; /* disable/enable chip and PCI options */ 152 uint16_t statreg; /* supported PCI features and error state */ 153 154 uint8_t baseclass; /* chip PCI class */ 155 uint8_t subclass; /* chip PCI subclass */ 156 uint8_t progif; /* chip PCI programming interface */ 157 uint8_t revid; /* chip revision ID */ 158 159 uint8_t hdrtype; /* chip config header type */ 160 uint8_t cachelnsz; /* cache line size in 4byte units */ 161 uint8_t intpin; /* PCI interrupt pin */ 162 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 163 164 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 165 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 166 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 167 168 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 169 uint8_t nummaps; /* actual number of PCI maps used */ 170 171 uint32_t domain; /* PCI domain */ 172 uint8_t bus; /* config space bus address */ 173 uint8_t slot; /* config space slot address */ 174 uint8_t func; /* config space function number */ 175 176 #ifdef COMPAT_OLDPCI 177 uint8_t secondarybus; /* bus on secondary side of bridge, if any */ 178 #else 179 uint8_t dummy; 180 #endif 181 182 struct pcicfg_pp pp; /* pci power management */ 183 struct pcicfg_vpd vpd; /* pci vital product data */ 184 struct pcicfg_msi msi; /* pci msi */ 185 struct pcicfg_msix msix; /* pci msi-x */ 186 struct pcicfg_ht ht; /* HyperTransport */ 187 struct pcicfg_expr expr; /* PCI Express */ 188 struct pcicfg_pcix pcix; /* PCI-X */ 189 } pcicfgregs; 190 191 /* additional type 1 device config header information (PCI to PCI bridge) */ 192 193 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 194 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 195 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 196 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 197 198 typedef struct { 199 pci_addr_t pmembase; /* base address of prefetchable memory */ 200 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 201 uint32_t membase; /* base address of memory window */ 202 uint32_t memlimit; /* topmost address of memory window */ 203 uint32_t iobase; /* base address of port window */ 204 uint32_t iolimit; /* topmost address of port window */ 205 uint16_t secstat; /* secondary bus status register */ 206 uint16_t bridgectl; /* bridge control register */ 207 uint8_t seclat; /* CardBus latency timer */ 208 } pcih1cfgregs; 209 210 /* additional type 2 device config header information (CardBus bridge) */ 211 212 typedef struct { 213 uint32_t membase0; /* base address of memory window */ 214 uint32_t memlimit0; /* topmost address of memory window */ 215 uint32_t membase1; /* base address of memory window */ 216 uint32_t memlimit1; /* topmost address of memory window */ 217 uint32_t iobase0; /* base address of port window */ 218 uint32_t iolimit0; /* topmost address of port window */ 219 uint32_t iobase1; /* base address of port window */ 220 uint32_t iolimit1; /* topmost address of port window */ 221 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 222 uint16_t secstat; /* secondary bus status register */ 223 uint16_t bridgectl; /* bridge control register */ 224 uint8_t seclat; /* CardBus latency timer */ 225 } pcih2cfgregs; 226 227 extern uint32_t pci_numdevs; 228 229 /* Only if the prerequisites are present */ 230 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 231 struct pci_devinfo { 232 STAILQ_ENTRY(pci_devinfo) pci_links; 233 struct resource_list resources; 234 pcicfgregs cfg; 235 struct pci_conf conf; 236 }; 237 #endif 238 239 #ifdef _SYS_BUS_H_ 240 241 #include "pci_if.h" 242 243 /* 244 * Define pci-specific resource flags for accessing memory via dense 245 * or bwx memory spaces. These flags are ignored on i386. 246 */ 247 #define PCI_RF_DENSE 0x10000 248 #define PCI_RF_BWX 0x20000 249 250 enum pci_device_ivars { 251 PCI_IVAR_SUBVENDOR, 252 PCI_IVAR_SUBDEVICE, 253 PCI_IVAR_VENDOR, 254 PCI_IVAR_DEVICE, 255 PCI_IVAR_DEVID, 256 PCI_IVAR_CLASS, 257 PCI_IVAR_SUBCLASS, 258 PCI_IVAR_PROGIF, 259 PCI_IVAR_REVID, 260 PCI_IVAR_INTPIN, 261 PCI_IVAR_IRQ, 262 PCI_IVAR_DOMAIN, 263 PCI_IVAR_BUS, 264 PCI_IVAR_SLOT, 265 PCI_IVAR_FUNCTION, 266 PCI_IVAR_ETHADDR, 267 PCI_IVAR_CMDREG, 268 PCI_IVAR_CACHELNSZ, 269 PCI_IVAR_MINGNT, 270 PCI_IVAR_MAXLAT, 271 PCI_IVAR_LATTIMER, 272 PCI_IVAR_PCIXCAP_PTR, 273 PCI_IVAR_PCIECAP_PTR, 274 PCI_IVAR_VPDCAP_PTR 275 }; 276 277 /* 278 * Simplified accessors for pci devices 279 */ 280 #define PCI_ACCESSOR(var, ivar, type) \ 281 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 282 283 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 284 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 285 PCI_ACCESSOR(vendor, VENDOR, uint16_t) 286 PCI_ACCESSOR(device, DEVICE, uint16_t) 287 PCI_ACCESSOR(devid, DEVID, uint32_t) 288 PCI_ACCESSOR(class, CLASS, uint8_t) 289 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 290 PCI_ACCESSOR(progif, PROGIF, uint8_t) 291 PCI_ACCESSOR(revid, REVID, uint8_t) 292 PCI_ACCESSOR(intpin, INTPIN, uint8_t) 293 PCI_ACCESSOR(irq, IRQ, uint8_t) 294 PCI_ACCESSOR(domain, DOMAIN, uint32_t) 295 PCI_ACCESSOR(bus, BUS, uint8_t) 296 PCI_ACCESSOR(slot, SLOT, uint8_t) 297 PCI_ACCESSOR(function, FUNCTION, uint8_t) 298 PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 299 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 300 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 301 PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 302 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 303 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 304 PCI_ACCESSOR(pcixcap_ptr, PCIXCAP_PTR, uint8_t) 305 PCI_ACCESSOR(pciecap_ptr, PCIECAP_PTR, uint8_t) 306 PCI_ACCESSOR(vpdcap_ptr, VPDCAP_PTR, uint8_t) 307 308 #undef PCI_ACCESSOR 309 310 /* 311 * Operations on configuration space. 312 */ 313 static __inline uint32_t 314 pci_read_config(device_t dev, int reg, int width) 315 { 316 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 317 } 318 319 static __inline void 320 pci_write_config(device_t dev, int reg, uint32_t val, int width) 321 { 322 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 323 } 324 325 /* 326 * Ivars for pci bridges. 327 */ 328 329 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 330 enum pcib_device_ivars { 331 PCIB_IVAR_DOMAIN, 332 PCIB_IVAR_BUS 333 }; 334 335 #define PCIB_ACCESSOR(var, ivar, type) \ 336 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 337 338 PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 339 PCIB_ACCESSOR(bus, BUS, uint32_t) 340 341 #undef PCIB_ACCESSOR 342 343 /* 344 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 345 * on i386 or other platforms should be mapped out in the MD pcireadconf 346 * code and not here, since the only MI invalid IRQ is 255. 347 */ 348 #define PCI_INVALID_IRQ 255 349 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 350 351 /* 352 * Convenience functions. 353 * 354 * These should be used in preference to manually manipulating 355 * configuration space. 356 */ 357 static __inline int 358 pci_enable_busmaster(device_t dev) 359 { 360 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 361 } 362 363 static __inline int 364 pci_disable_busmaster(device_t dev) 365 { 366 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 367 } 368 369 static __inline int 370 pci_enable_io(device_t dev, int space) 371 { 372 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 373 } 374 375 static __inline int 376 pci_disable_io(device_t dev, int space) 377 { 378 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 379 } 380 381 static __inline int 382 pci_get_vpd_ident(device_t dev, const char **identptr) 383 { 384 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 385 } 386 387 static __inline int 388 pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 389 { 390 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 391 } 392 393 /* 394 * Check if the address range falls within the VGA defined address range(s) 395 */ 396 static __inline int 397 pci_is_vga_ioport_range(u_long start, u_long end) 398 { 399 400 return (((start >= 0x3b0 && end <= 0x3bb) || 401 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 402 } 403 404 static __inline int 405 pci_is_vga_memory_range(u_long start, u_long end) 406 { 407 408 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 409 } 410 411 int pcie_slot_implemented(device_t); 412 void pcie_set_max_readrq(device_t, uint16_t); 413 uint16_t pcie_get_max_readrq(device_t); 414 415 /* 416 * PCI power states are as defined by ACPI: 417 * 418 * D0 State in which device is on and running. It is receiving full 419 * power from the system and delivering full functionality to the user. 420 * D1 Class-specific low-power state in which device context may or may not 421 * be lost. Buses in D1 cannot do anything to the bus that would force 422 * devices on that bus to lose context. 423 * D2 Class-specific low-power state in which device context may or may 424 * not be lost. Attains greater power savings than D1. Buses in D2 425 * can cause devices on that bus to lose some context. Devices in D2 426 * must be prepared for the bus to be in D2 or higher. 427 * D3 State in which the device is off and not running. Device context is 428 * lost. Power can be removed from the device. 429 */ 430 #define PCI_POWERSTATE_D0 0 431 #define PCI_POWERSTATE_D1 1 432 #define PCI_POWERSTATE_D2 2 433 #define PCI_POWERSTATE_D3 3 434 #define PCI_POWERSTATE_UNKNOWN -1 435 436 static __inline int 437 pci_set_powerstate(device_t dev, int state) 438 { 439 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 440 } 441 442 static __inline int 443 pci_get_powerstate(device_t dev) 444 { 445 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 446 } 447 448 static __inline int 449 pci_find_extcap(device_t dev, int capability, int *capreg) 450 { 451 return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg); 452 } 453 454 static __inline int 455 pci_is_pcie(device_t dev) 456 { 457 return (pci_get_pciecap_ptr(dev) != 0); 458 } 459 460 static __inline int 461 pci_is_pcix(device_t dev) 462 { 463 return (pci_get_pcixcap_ptr(dev) != 0); 464 } 465 466 static __inline int 467 pci_alloc_msi(device_t dev, int *count) 468 { 469 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 470 } 471 472 static __inline int 473 pci_alloc_msix(device_t dev, int *count) 474 { 475 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 476 } 477 478 static __inline int 479 pci_remap_msix(device_t dev, int count, const u_int *vectors) 480 { 481 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 482 } 483 484 static __inline int 485 pci_release_msi(device_t dev) 486 { 487 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 488 } 489 490 static __inline int 491 pci_msi_count(device_t dev) 492 { 493 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 494 } 495 496 static __inline int 497 pci_msix_count(device_t dev) 498 { 499 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 500 } 501 502 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 503 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 504 device_t pci_find_device(uint16_t, uint16_t); 505 506 /* 507 * Can be used by MD code to request the PCI bus to re-map an MSI or 508 * MSI-X message. 509 */ 510 int pci_remap_msi_irq(device_t dev, u_int irq); 511 512 /* Can be used by drivers to manage the MSI-X table. */ 513 int pci_pending_msix(device_t dev, u_int index); 514 515 int pci_msi_device_blacklisted(device_t dev); 516 517 void pci_ht_map_msi(device_t dev, uint64_t addr); 518 519 #endif /* _SYS_BUS_H_ */ 520 521 /* 522 * cdev switch for control device, initialised in generic PCI code 523 */ 524 extern struct cdevsw pcicdev; 525 526 /* 527 * List of all PCI devices, generation count for the list. 528 */ 529 STAILQ_HEAD(devlist, pci_devinfo); 530 531 extern struct devlist pci_devq; 532 extern uint32_t pci_generation; 533 534 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ 535 536 #if defined(_KERNEL) && !defined(KLD_MODULE) 537 #include "opt_compat_oldpci.h" 538 #endif 539 540 #ifdef COMPAT_OLDPCI 541 /* all this is going some day */ 542 543 typedef pcicfgregs *pcici_t; 544 typedef unsigned pcidi_t; 545 typedef void pci_inthand_t(void *arg); 546 547 #define pci_max_burst_len (3) 548 549 /* just copied from old PCI code for now ... */ 550 551 struct pci_device { 552 char* pd_name; 553 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 554 void (*pd_attach) (pcici_t tag, int unit); 555 u_long *pd_count; 556 int (*pd_shutdown) (int, int); 557 }; 558 559 #ifdef __i386__ 560 typedef u_short pci_port_t; 561 #else 562 typedef u_int pci_port_t; 563 #endif 564 565 u_long pci_conf_read (pcici_t tag, u_long reg); 566 void pci_conf_write (pcici_t tag, u_long reg, u_long data); 567 int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 568 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 569 int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg); 570 int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 571 u_int flags); 572 int pci_unmap_int (pcici_t tag); 573 574 void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 575 576 pcici_t pci_get_parent_from_tag(pcici_t tag); 577 int pci_get_bus_from_tag(pcici_t tag); 578 579 pcicfgregs *pci_devlist_get_parent(pcicfgregs *cfg); 580 581 struct module; 582 int compat_pci_handler (struct module *, int, void *); 583 #define COMPAT_PCI_DRIVER(name, pcidata) \ 584 static moduledata_t name##_mod = { \ 585 #name, \ 586 compat_pci_handler, \ 587 &pcidata \ 588 }; \ 589 DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 590 591 #endif /* COMPAT_OLDPCI */ 592 593 #endif /* _PCIVAR_H_ */ 594