1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/pci/pcivar.h,v 1.80.2.1.4.1 2009/04/15 03:14:26 kensmith Exp $ 27 * 28 */ 29 30 #ifndef _PCIVAR_H_ 31 #define _PCIVAR_H_ 32 33 #ifndef _SYS_QUEUE_H_ 34 #include <sys/queue.h> 35 #endif 36 37 /* some PCI bus constants */ 38 39 #define PCI_DOMAINMAX 65535 /* highest supported domain number */ 40 #define PCI_BUSMAX 255 /* highest supported bus number */ 41 #define PCI_SLOTMAX 31 /* highest supported slot number */ 42 #define PCI_FUNCMAX 7 /* highest supported function number */ 43 #define PCI_REGMAX 255 /* highest supported config register addr. */ 44 45 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 46 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 47 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 48 49 typedef uint64_t pci_addr_t; 50 51 /* Interesting values for PCI power management */ 52 struct pcicfg_pp { 53 uint16_t pp_cap; /* PCI power management capabilities */ 54 uint8_t pp_status; /* config space address of PCI power status reg */ 55 uint8_t pp_pmcsr; /* config space address of PMCSR reg */ 56 uint8_t pp_data; /* config space address of PCI power data reg */ 57 }; 58 59 struct vpd_readonly { 60 char keyword[2]; 61 char *value; 62 }; 63 64 struct vpd_write { 65 char keyword[2]; 66 char *value; 67 int start; 68 int len; 69 }; 70 71 struct pcicfg_vpd { 72 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 73 char vpd_cached; 74 char *vpd_ident; /* string identifier */ 75 int vpd_rocnt; 76 struct vpd_readonly *vpd_ros; 77 int vpd_wcnt; 78 struct vpd_write *vpd_w; 79 }; 80 81 /* Interesting values for PCI MSI */ 82 struct pcicfg_msi { 83 uint16_t msi_ctrl; /* Message Control */ 84 uint8_t msi_location; /* Offset of MSI capability registers. */ 85 uint8_t msi_msgnum; /* Number of messages */ 86 int msi_alloc; /* Number of allocated messages. */ 87 uint64_t msi_addr; /* Contents of address register. */ 88 uint16_t msi_data; /* Contents of data register. */ 89 u_int msi_handlers; 90 }; 91 92 /* Interesting values for PCI MSI-X */ 93 struct msix_vector { 94 TAILQ_ENTRY(msix_vector) mv_link; 95 uint64_t mv_address; /* Contents of address register. */ 96 uint32_t mv_data; /* Contents of data register. */ 97 int mv_rid; 98 }; 99 TAILQ_HEAD(msix_vectorlist, msix_vector); 100 101 struct pcicfg_msix { 102 uint16_t msix_ctrl; /* Message Control */ 103 uint16_t msix_msgnum; /* Number of messages */ 104 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 105 uint8_t msix_table_bar; /* BAR containing vector table. */ 106 uint8_t msix_pba_bar; /* BAR containing PBA. */ 107 uint32_t msix_table_offset; 108 uint32_t msix_pba_offset; 109 int msix_alloc; /* Number of allocated vectors. */ 110 struct resource *msix_table_res; /* Resource containing vector table. */ 111 struct resource *msix_pba_res; /* Resource containing PBA. */ 112 struct msix_vectorlist msix_vectors; 113 }; 114 115 /* Interesting values for HyperTransport */ 116 struct pcicfg_ht { 117 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 118 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 119 uint16_t ht_msictrl; /* MSI mapping control */ 120 uint64_t ht_msiaddr; /* MSI mapping base address */ 121 }; 122 123 /* Interesting values for PCI Express capability */ 124 struct pcicfg_expr { 125 uint8_t expr_ptr; /* capability ptr */ 126 uint16_t expr_cap; /* capabilities */ 127 uint32_t expr_slotcap; /* slot capabilities */ 128 }; 129 130 /* Interesting values for PCI-X */ 131 struct pcicfg_pcix { 132 uint8_t pcix_ptr; 133 }; 134 135 /* config header information common to all header types */ 136 typedef struct pcicfg { 137 struct device *dev; /* device which owns this */ 138 139 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */ 140 uint32_t bios; /* BIOS mapping */ 141 142 uint16_t subvendor; /* card vendor ID */ 143 uint16_t subdevice; /* card device ID, assigned by card vendor */ 144 uint16_t vendor; /* chip vendor ID */ 145 uint16_t device; /* chip device ID, assigned by chip vendor */ 146 147 uint16_t cmdreg; /* disable/enable chip and PCI options */ 148 uint16_t statreg; /* supported PCI features and error state */ 149 150 uint8_t baseclass; /* chip PCI class */ 151 uint8_t subclass; /* chip PCI subclass */ 152 uint8_t progif; /* chip PCI programming interface */ 153 uint8_t revid; /* chip revision ID */ 154 155 uint8_t hdrtype; /* chip config header type */ 156 uint8_t cachelnsz; /* cache line size in 4byte units */ 157 uint8_t intpin; /* PCI interrupt pin */ 158 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 159 160 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 161 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 162 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 163 164 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 165 uint8_t nummaps; /* actual number of PCI maps used */ 166 167 uint32_t domain; /* PCI domain */ 168 uint8_t bus; /* config space bus address */ 169 uint8_t slot; /* config space slot address */ 170 uint8_t func; /* config space function number */ 171 172 #ifdef COMPAT_OLDPCI 173 uint8_t secondarybus; /* bus on secondary side of bridge, if any */ 174 #else 175 uint8_t dummy; 176 #endif 177 178 struct pcicfg_pp pp; /* pci power management */ 179 struct pcicfg_vpd vpd; /* pci vital product data */ 180 struct pcicfg_msi msi; /* pci msi */ 181 struct pcicfg_msix msix; /* pci msi-x */ 182 struct pcicfg_ht ht; /* HyperTransport */ 183 struct pcicfg_expr expr; /* PCI Express */ 184 struct pcicfg_pcix pcix; /* PCI-X */ 185 } pcicfgregs; 186 187 /* additional type 1 device config header information (PCI to PCI bridge) */ 188 189 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 190 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 191 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 192 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 193 194 typedef struct { 195 pci_addr_t pmembase; /* base address of prefetchable memory */ 196 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 197 uint32_t membase; /* base address of memory window */ 198 uint32_t memlimit; /* topmost address of memory window */ 199 uint32_t iobase; /* base address of port window */ 200 uint32_t iolimit; /* topmost address of port window */ 201 uint16_t secstat; /* secondary bus status register */ 202 uint16_t bridgectl; /* bridge control register */ 203 uint8_t seclat; /* CardBus latency timer */ 204 } pcih1cfgregs; 205 206 /* additional type 2 device config header information (CardBus bridge) */ 207 208 typedef struct { 209 uint32_t membase0; /* base address of memory window */ 210 uint32_t memlimit0; /* topmost address of memory window */ 211 uint32_t membase1; /* base address of memory window */ 212 uint32_t memlimit1; /* topmost address of memory window */ 213 uint32_t iobase0; /* base address of port window */ 214 uint32_t iolimit0; /* topmost address of port window */ 215 uint32_t iobase1; /* base address of port window */ 216 uint32_t iolimit1; /* topmost address of port window */ 217 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 218 uint16_t secstat; /* secondary bus status register */ 219 uint16_t bridgectl; /* bridge control register */ 220 uint8_t seclat; /* CardBus latency timer */ 221 } pcih2cfgregs; 222 223 extern uint32_t pci_numdevs; 224 225 /* Only if the prerequisites are present */ 226 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 227 struct pci_devinfo { 228 STAILQ_ENTRY(pci_devinfo) pci_links; 229 struct resource_list resources; 230 pcicfgregs cfg; 231 struct pci_conf conf; 232 }; 233 #endif 234 235 #ifdef _SYS_BUS_H_ 236 237 #include "pci_if.h" 238 239 /* 240 * Define pci-specific resource flags for accessing memory via dense 241 * or bwx memory spaces. These flags are ignored on i386. 242 */ 243 #define PCI_RF_DENSE 0x10000 244 #define PCI_RF_BWX 0x20000 245 246 enum pci_device_ivars { 247 PCI_IVAR_SUBVENDOR, 248 PCI_IVAR_SUBDEVICE, 249 PCI_IVAR_VENDOR, 250 PCI_IVAR_DEVICE, 251 PCI_IVAR_DEVID, 252 PCI_IVAR_CLASS, 253 PCI_IVAR_SUBCLASS, 254 PCI_IVAR_PROGIF, 255 PCI_IVAR_REVID, 256 PCI_IVAR_INTPIN, 257 PCI_IVAR_IRQ, 258 PCI_IVAR_DOMAIN, 259 PCI_IVAR_BUS, 260 PCI_IVAR_SLOT, 261 PCI_IVAR_FUNCTION, 262 PCI_IVAR_ETHADDR, 263 PCI_IVAR_CMDREG, 264 PCI_IVAR_CACHELNSZ, 265 PCI_IVAR_MINGNT, 266 PCI_IVAR_MAXLAT, 267 PCI_IVAR_LATTIMER, 268 PCI_IVAR_PCIXCAP_PTR, 269 PCI_IVAR_PCIECAP_PTR, 270 PCI_IVAR_VPDCAP_PTR 271 }; 272 273 /* 274 * Simplified accessors for pci devices 275 */ 276 #define PCI_ACCESSOR(var, ivar, type) \ 277 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 278 279 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 280 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 281 PCI_ACCESSOR(vendor, VENDOR, uint16_t) 282 PCI_ACCESSOR(device, DEVICE, uint16_t) 283 PCI_ACCESSOR(devid, DEVID, uint32_t) 284 PCI_ACCESSOR(class, CLASS, uint8_t) 285 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 286 PCI_ACCESSOR(progif, PROGIF, uint8_t) 287 PCI_ACCESSOR(revid, REVID, uint8_t) 288 PCI_ACCESSOR(intpin, INTPIN, uint8_t) 289 PCI_ACCESSOR(irq, IRQ, uint8_t) 290 PCI_ACCESSOR(domain, DOMAIN, uint32_t) 291 PCI_ACCESSOR(bus, BUS, uint8_t) 292 PCI_ACCESSOR(slot, SLOT, uint8_t) 293 PCI_ACCESSOR(function, FUNCTION, uint8_t) 294 PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 295 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 296 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 297 PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 298 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 299 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 300 PCI_ACCESSOR(pcixcap_ptr, PCIXCAP_PTR, uint8_t) 301 PCI_ACCESSOR(pciecap_ptr, PCIECAP_PTR, uint8_t) 302 PCI_ACCESSOR(vpdcap_ptr, VPDCAP_PTR, uint8_t) 303 304 #undef PCI_ACCESSOR 305 306 /* 307 * Operations on configuration space. 308 */ 309 static __inline uint32_t 310 pci_read_config(device_t dev, int reg, int width) 311 { 312 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 313 } 314 315 static __inline void 316 pci_write_config(device_t dev, int reg, uint32_t val, int width) 317 { 318 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 319 } 320 321 /* 322 * Ivars for pci bridges. 323 */ 324 325 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 326 enum pcib_device_ivars { 327 PCIB_IVAR_DOMAIN, 328 PCIB_IVAR_BUS 329 }; 330 331 #define PCIB_ACCESSOR(var, ivar, type) \ 332 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 333 334 PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 335 PCIB_ACCESSOR(bus, BUS, uint32_t) 336 337 #undef PCIB_ACCESSOR 338 339 /* 340 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 341 * on i386 or other platforms should be mapped out in the MD pcireadconf 342 * code and not here, since the only MI invalid IRQ is 255. 343 */ 344 #define PCI_INVALID_IRQ 255 345 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 346 347 /* 348 * Convenience functions. 349 * 350 * These should be used in preference to manually manipulating 351 * configuration space. 352 */ 353 static __inline int 354 pci_enable_busmaster(device_t dev) 355 { 356 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 357 } 358 359 static __inline int 360 pci_disable_busmaster(device_t dev) 361 { 362 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 363 } 364 365 static __inline int 366 pci_enable_io(device_t dev, int space) 367 { 368 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 369 } 370 371 static __inline int 372 pci_disable_io(device_t dev, int space) 373 { 374 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 375 } 376 377 static __inline int 378 pci_get_vpd_ident(device_t dev, const char **identptr) 379 { 380 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 381 } 382 383 static __inline int 384 pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 385 { 386 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 387 } 388 389 /* 390 * Check if the address range falls within the VGA defined address range(s) 391 */ 392 static __inline int 393 pci_is_vga_ioport_range(u_long start, u_long end) 394 { 395 396 return (((start >= 0x3b0 && end <= 0x3bb) || 397 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 398 } 399 400 static __inline int 401 pci_is_vga_memory_range(u_long start, u_long end) 402 { 403 404 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 405 } 406 407 int pcie_slot_implemented(device_t); 408 void pcie_set_max_readrq(device_t, uint16_t); 409 uint16_t pcie_get_max_readrq(device_t); 410 411 /* 412 * PCI power states are as defined by ACPI: 413 * 414 * D0 State in which device is on and running. It is receiving full 415 * power from the system and delivering full functionality to the user. 416 * D1 Class-specific low-power state in which device context may or may not 417 * be lost. Buses in D1 cannot do anything to the bus that would force 418 * devices on that bus to lose context. 419 * D2 Class-specific low-power state in which device context may or may 420 * not be lost. Attains greater power savings than D1. Buses in D2 421 * can cause devices on that bus to lose some context. Devices in D2 422 * must be prepared for the bus to be in D2 or higher. 423 * D3 State in which the device is off and not running. Device context is 424 * lost. Power can be removed from the device. 425 */ 426 #define PCI_POWERSTATE_D0 0 427 #define PCI_POWERSTATE_D1 1 428 #define PCI_POWERSTATE_D2 2 429 #define PCI_POWERSTATE_D3 3 430 #define PCI_POWERSTATE_UNKNOWN -1 431 432 static __inline int 433 pci_set_powerstate(device_t dev, int state) 434 { 435 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 436 } 437 438 static __inline int 439 pci_get_powerstate(device_t dev) 440 { 441 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 442 } 443 444 static __inline int 445 pci_find_extcap(device_t dev, int capability, int *capreg) 446 { 447 return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg); 448 } 449 450 static __inline int 451 pci_is_pcie(device_t dev) 452 { 453 return (pci_get_pciecap_ptr(dev) != 0); 454 } 455 456 static __inline int 457 pci_is_pcix(device_t dev) 458 { 459 return (pci_get_pcixcap_ptr(dev) != 0); 460 } 461 462 static __inline int 463 pci_alloc_msi(device_t dev, int *rid, int count, int cpuid) 464 { 465 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, rid, count, cpuid)); 466 } 467 468 static __inline int 469 pci_release_msi(device_t dev) 470 { 471 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 472 } 473 474 static __inline int 475 pci_alloc_msix_vector(device_t dev, u_int vector, int *rid, int cpuid) 476 { 477 return (PCI_ALLOC_MSIX_VECTOR(device_get_parent(dev), dev, vector, rid, 478 cpuid)); 479 } 480 481 static __inline int 482 pci_release_msix_vector(device_t dev, int rid) 483 { 484 return PCI_RELEASE_MSIX_VECTOR(device_get_parent(dev), dev, rid); 485 } 486 487 static __inline int 488 pci_msi_count(device_t dev) 489 { 490 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 491 } 492 493 static __inline int 494 pci_msix_count(device_t dev) 495 { 496 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 497 } 498 499 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 500 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 501 device_t pci_find_device(uint16_t, uint16_t); 502 503 /* Can be used by drivers to manage the MSI-X table. */ 504 int pci_pending_msix_vector(device_t dev, u_int index); 505 int pci_setup_msix(device_t dev); 506 void pci_teardown_msix(device_t dev); 507 void pci_enable_msix(device_t dev); 508 void pci_disable_msix(device_t dev); 509 510 int pci_msi_device_blacklisted(device_t dev); 511 512 void pci_ht_map_msi(device_t dev, uint64_t addr); 513 514 /* Returns PCI_INTR_TYPE_ */ 515 int pci_alloc_1intr(device_t dev, int msi_enable, int *rid, u_int *flags); 516 517 #define PCI_INTR_TYPE_LEGACY 0 518 #define PCI_INTR_TYPE_MSI 1 519 #define PCI_INTR_TYPE_MSIX 2 /* not yet */ 520 521 #endif /* _SYS_BUS_H_ */ 522 523 /* 524 * cdev switch for control device, initialised in generic PCI code 525 */ 526 extern struct cdevsw pcicdev; 527 528 /* 529 * List of all PCI devices, generation count for the list. 530 */ 531 STAILQ_HEAD(devlist, pci_devinfo); 532 533 extern struct devlist pci_devq; 534 extern uint32_t pci_generation; 535 536 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ 537 538 #if defined(_KERNEL) && !defined(KLD_MODULE) 539 #include "opt_compat_oldpci.h" 540 #endif 541 542 #ifdef COMPAT_OLDPCI 543 /* all this is going some day */ 544 545 typedef pcicfgregs *pcici_t; 546 typedef unsigned pcidi_t; 547 typedef void pci_inthand_t(void *arg); 548 549 #define pci_max_burst_len (3) 550 551 /* just copied from old PCI code for now ... */ 552 553 struct pci_device { 554 char* pd_name; 555 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 556 void (*pd_attach) (pcici_t tag, int unit); 557 u_long *pd_count; 558 int (*pd_shutdown) (int, int); 559 }; 560 561 #ifdef __i386__ 562 typedef u_short pci_port_t; 563 #else 564 typedef u_int pci_port_t; 565 #endif 566 567 u_long pci_conf_read (pcici_t tag, u_long reg); 568 void pci_conf_write (pcici_t tag, u_long reg, u_long data); 569 int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 570 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 571 int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg); 572 int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 573 u_int flags); 574 int pci_unmap_int (pcici_t tag); 575 576 void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 577 578 pcici_t pci_get_parent_from_tag(pcici_t tag); 579 int pci_get_bus_from_tag(pcici_t tag); 580 581 pcicfgregs *pci_devlist_get_parent(pcicfgregs *cfg); 582 583 struct module; 584 int compat_pci_handler (struct module *, int, void *); 585 #define COMPAT_PCI_DRIVER(name, pcidata) \ 586 static moduledata_t name##_mod = { \ 587 #name, \ 588 compat_pci_handler, \ 589 &pcidata \ 590 }; \ 591 DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 592 593 #endif /* COMPAT_OLDPCI */ 594 595 #endif /* _PCIVAR_H_ */ 596