1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pcivar.h,v 1.48 2000/09/28 00:37:32 peter Exp $ 27 * $DragonFly: src/sys/bus/pci/pcivar.h,v 1.15 2007/11/28 11:35:40 sephe Exp $ 28 * 29 */ 30 31 #ifndef _PCIVAR_H_ 32 #define _PCIVAR_H_ 33 34 #include <sys/queue.h> 35 36 /* some PCI bus constants */ 37 38 #define PCI_BUSMAX 255 /* highest supported bus number */ 39 #define PCI_SLOTMAX 31 /* highest supported slot number */ 40 #define PCI_FUNCMAX 7 /* highest supported function number */ 41 #define PCI_REGMAX 255 /* highest supported config register addr. */ 42 43 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 44 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 45 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 46 47 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 48 49 #ifdef PCI_A64 50 typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 51 #else 52 typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 53 #endif 54 55 /* config values for PCI power management capability */ 56 struct pcicfg_pmgt { 57 u_int16_t pp_cap; /* PCI power management capabilities */ 58 u_int8_t pp_status; /* config space address of PCI power status reg */ 59 u_int8_t pp_pmcsr; /* config space address of PMCSR reg */ 60 u_int8_t pp_data; /* config space address of PCI power data reg */ 61 }; 62 63 /* config values for PCI Express capability */ 64 struct pcicfg_expr { 65 uint8_t expr_ptr; /* capability ptr */ 66 uint16_t expr_cap; /* capabilities */ 67 uint32_t expr_slotcap; /* slot capabilities */ 68 }; 69 70 /* config header information common to all header types */ 71 72 typedef struct pcicfg { 73 struct device *dev; /* device which owns this */ 74 void *hdrspec; /* pointer to header type specific data */ 75 76 u_int16_t subvendor; /* card vendor ID */ 77 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 78 u_int16_t vendor; /* chip vendor ID */ 79 u_int16_t device; /* chip device ID, assigned by chip vendor */ 80 81 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 82 u_int16_t statreg; /* supported PCI features and error state */ 83 84 u_int8_t baseclass; /* chip PCI class */ 85 u_int8_t subclass; /* chip PCI subclass */ 86 u_int8_t progif; /* chip PCI programming interface */ 87 u_int8_t revid; /* chip revision ID */ 88 89 u_int8_t hdrtype; /* chip config header type */ 90 u_int8_t cachelnsz; /* cache line size in 4byte units */ 91 u_int8_t intpin; /* PCI interrupt pin */ 92 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 93 94 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 95 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 96 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 97 98 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 99 u_int8_t nummaps; /* actual number of PCI maps used */ 100 101 u_int8_t bus; /* config space bus address */ 102 u_int8_t slot; /* config space slot address */ 103 u_int8_t func; /* config space function number */ 104 105 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 106 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 107 108 struct pcicfg_pmgt pmgt; /* power management capability */ 109 struct pcicfg_expr expr; /* PCI Express capability */ 110 u_int8_t pcixcap_ptr; /* PCI-X capability PTR */ 111 } pcicfgregs; 112 113 /* additional type 1 device config header information (PCI to PCI bridge) */ 114 115 #ifdef PCI_A64 116 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 117 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 118 #else 119 #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 120 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 121 #endif /* PCI_A64 */ 122 123 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 124 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 125 126 typedef struct { 127 pci_addr_t pmembase; /* base address of prefetchable memory */ 128 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 129 u_int32_t membase; /* base address of memory window */ 130 u_int32_t memlimit; /* topmost address of memory window */ 131 u_int32_t iobase; /* base address of port window */ 132 u_int32_t iolimit; /* topmost address of port window */ 133 u_int16_t secstat; /* secondary bus status register */ 134 u_int16_t bridgectl; /* bridge control register */ 135 u_int8_t seclat; /* CardBus latency timer */ 136 } pcih1cfgregs; 137 138 /* additional type 2 device config header information (CardBus bridge) */ 139 140 typedef struct { 141 u_int32_t membase0; /* base address of memory window */ 142 u_int32_t memlimit0; /* topmost address of memory window */ 143 u_int32_t membase1; /* base address of memory window */ 144 u_int32_t memlimit1; /* topmost address of memory window */ 145 u_int32_t iobase0; /* base address of port window */ 146 u_int32_t iolimit0; /* topmost address of port window */ 147 u_int32_t iobase1; /* base address of port window */ 148 u_int32_t iolimit1; /* topmost address of port window */ 149 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 150 u_int16_t secstat; /* secondary bus status register */ 151 u_int16_t bridgectl; /* bridge control register */ 152 u_int8_t seclat; /* CardBus latency timer */ 153 } pcih2cfgregs; 154 155 extern u_int32_t pci_numdevs; 156 extern const char *pcib_owner; /* arbitrate who owns the pci device arch */ 157 158 /* Only if the prerequisites are present */ 159 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 160 struct pci_devinfo { 161 STAILQ_ENTRY(pci_devinfo) pci_links; 162 struct resource_list resources; 163 pcicfgregs cfg; 164 struct pci_conf conf; 165 }; 166 #endif 167 168 /* externally visible functions */ 169 170 const char *pci_ata_match(struct device *dev); 171 const char *pci_usb_match(struct device *dev); 172 const char *pci_vga_match(struct device *dev); 173 const char *pci_chip_match(struct device *dev); 174 175 /* low level PCI config register functions provided by pcibus.c */ 176 177 int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 178 void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 179 180 /* low level devlist operations for the 2.2 compatibility code in pci.c */ 181 pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg); 182 183 #ifdef _SYS_BUS_H_ 184 185 #include "pci_if.h" 186 187 /* 188 * Define pci-specific resource flags for accessing memory via dense 189 * or bwx memory spaces. These flags are ignored on i386. 190 */ 191 #define PCI_RF_DENSE 0x10000 192 #define PCI_RF_BWX 0x20000 193 194 enum pci_device_ivars { 195 PCI_IVAR_SUBVENDOR, 196 PCI_IVAR_SUBDEVICE, 197 PCI_IVAR_VENDOR, 198 PCI_IVAR_DEVICE, 199 PCI_IVAR_DEVID, 200 PCI_IVAR_CLASS, 201 PCI_IVAR_SUBCLASS, 202 PCI_IVAR_PROGIF, 203 PCI_IVAR_REVID, 204 PCI_IVAR_INTPIN, 205 PCI_IVAR_IRQ, 206 PCI_IVAR_BUS, 207 PCI_IVAR_SLOT, 208 PCI_IVAR_FUNCTION, 209 PCI_IVAR_SECONDARYBUS, 210 PCI_IVAR_SUBORDINATEBUS, 211 PCI_IVAR_ETHADDR, 212 PCI_IVAR_PCIXCAP_PTR, 213 PCI_IVAR_PCIECAP_PTR 214 }; 215 216 /* 217 * Simplified accessors for pci devices 218 * 219 * The PCI device passed in actually represents a PCI function number 220 * for the current slot. The parent of dev is the "pci" slot device. 221 * Each function number has its own set of ivars. 222 */ 223 #define PCI_ACCESSOR(A, B, T) \ 224 \ 225 static __inline T pci_get_ ## A(device_t dev) \ 226 { \ 227 uintptr_t v; \ 228 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 229 return (T) v; \ 230 } \ 231 \ 232 static __inline void pci_set_ ## A(device_t dev, T t) \ 233 { \ 234 uintptr_t v = (uintptr_t) t; \ 235 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 236 } 237 238 PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 239 PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 240 PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 241 PCI_ACCESSOR(device, DEVICE, u_int16_t) 242 PCI_ACCESSOR(devid, DEVID, u_int32_t) 243 PCI_ACCESSOR(class, CLASS, u_int8_t) 244 PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 245 PCI_ACCESSOR(progif, PROGIF, u_int8_t) 246 PCI_ACCESSOR(revid, REVID, u_int8_t) 247 PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 248 PCI_ACCESSOR(irq, IRQ, u_int8_t) 249 PCI_ACCESSOR(bus, BUS, u_int8_t) 250 PCI_ACCESSOR(slot, SLOT, u_int8_t) 251 PCI_ACCESSOR(function, FUNCTION, u_int8_t) 252 PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 253 PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 254 PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 255 PCI_ACCESSOR(pcixcap_ptr, PCIXCAP_PTR, uint8_t) 256 PCI_ACCESSOR(pciecap_ptr, PCIECAP_PTR, uint8_t) 257 258 #undef PCI_ACCESSOR 259 260 static __inline u_int32_t 261 pci_read_config(device_t dev, int reg, int width) 262 { 263 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 264 } 265 266 static __inline void 267 pci_write_config(device_t dev, int reg, u_int32_t val, int width) 268 { 269 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 270 } 271 272 /* 273 * Convenience functions. 274 * 275 * These should be used in preference to manually manipulating 276 * configuration space. 277 */ 278 static __inline void 279 pci_enable_busmaster(device_t dev) 280 { 281 PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev); 282 } 283 284 static __inline void 285 pci_disable_busmaster(device_t dev) 286 { 287 PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev); 288 } 289 290 static __inline void 291 pci_enable_io(device_t dev, int space) 292 { 293 PCI_ENABLE_IO(device_get_parent(dev), dev, space); 294 } 295 296 static __inline void 297 pci_disable_io(device_t dev, int space) 298 { 299 PCI_DISABLE_IO(device_get_parent(dev), dev, space); 300 } 301 302 static __inline int 303 pci_is_pcie(device_t dev) 304 { 305 return (pci_get_pciecap_ptr(dev) != 0); 306 } 307 308 static __inline int 309 pci_is_pcix(device_t dev) 310 { 311 return (pci_get_pcixcap_ptr(dev) != 0); 312 } 313 314 /* 315 * PCI power states are as defined by ACPI: 316 * 317 * D0 State in which device is on and running. It is receiving full 318 * power from the system and delivering full functionality to the user. 319 * D1 Class-specific low-power state in which device context may or may not 320 * be lost. Buses in D1 cannot do anything to the bus that would force 321 * devices on that bus to loose context. 322 * D2 Class-specific low-power state in which device context may or may 323 * not be lost. Attains greater power savings than D1. Buses in D2 324 * can cause devices on that bus to loose some context. Devices in D2 325 * must be prepared for the bus to be in D2 or higher. 326 * D3 State in which the device is off and not running. Device context is 327 * lost. Power can be removed from the device. 328 */ 329 #define PCI_POWERSTATE_D0 0 330 #define PCI_POWERSTATE_D1 1 331 #define PCI_POWERSTATE_D2 2 332 #define PCI_POWERSTATE_D3 3 333 #define PCI_POWERSTATE_UNKNOWN -1 334 335 static __inline int 336 pci_set_powerstate(device_t dev, int state) 337 { 338 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 339 } 340 341 static __inline int 342 pci_get_powerstate(device_t dev) 343 { 344 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 345 } 346 347 /* 348 * Ivars for pci bridges. 349 * 350 * Whereas PCI devices are arranged [pciX]->[pciX.Y] with the pci driver 351 * functions in [pciX] but the individual ivars in [pciX.Y], PCI bridges 352 * are installed in [pciX.Y] and store their ivars in a softc. This 353 * is why the accessor functions for a bridge do not call device_get_parent(). 354 */ 355 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 356 enum pcib_device_ivars { 357 PCIB_IVAR_BUS, 358 }; 359 360 #define PCIB_ACCESSOR(A, B, T) \ 361 \ 362 static __inline T pcib_get_ ## A(device_t dev) \ 363 { \ 364 uintptr_t v; \ 365 BUS_READ_IVAR(dev, dev, PCIB_IVAR_ ## B, &v); \ 366 return (T) v; \ 367 } \ 368 \ 369 static __inline void pcib_set_ ## A(device_t dev, T t) \ 370 { \ 371 uintptr_t v = (uintptr_t) t; \ 372 BUS_WRITE_IVAR(dev, dev, PCIB_IVAR_ ## B, v); \ 373 } 374 375 PCIB_ACCESSOR(bus, BUS, u_int32_t) 376 377 #undef PCIB_ACCESSOR 378 379 device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t); 380 device_t pci_find_device(u_int16_t, u_int16_t); 381 int pcie_slot_implemented(device_t); 382 #endif 383 384 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ 385 386 #if defined(_KERNEL) && !defined(KLD_MODULE) 387 #include "opt_compat_oldpci.h" 388 #endif 389 390 #ifdef COMPAT_OLDPCI 391 /* all this is going some day */ 392 393 typedef pcicfgregs *pcici_t; 394 typedef unsigned pcidi_t; 395 typedef void pci_inthand_t(void *arg); 396 397 #define pci_max_burst_len (3) 398 399 /* just copied from old PCI code for now ... */ 400 401 struct pci_device { 402 char* pd_name; 403 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 404 void (*pd_attach) (pcici_t tag, int unit); 405 u_long *pd_count; 406 int (*pd_shutdown) (int, int); 407 }; 408 409 #ifdef __i386__ 410 typedef u_short pci_port_t; 411 #else 412 typedef u_int pci_port_t; 413 #endif 414 415 u_long pci_conf_read (pcici_t tag, u_long reg); 416 void pci_conf_write (pcici_t tag, u_long reg, u_long data); 417 int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 418 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 419 int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg); 420 int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 421 u_int flags); 422 int pci_unmap_int (pcici_t tag); 423 424 pcici_t pci_get_parent_from_tag(pcici_t tag); 425 int pci_get_bus_from_tag(pcici_t tag); 426 427 struct module; 428 int compat_pci_handler (struct module *, int, void *); 429 #define COMPAT_PCI_DRIVER(name, pcidata) \ 430 static moduledata_t name##_mod = { \ 431 #name, \ 432 compat_pci_handler, \ 433 &pcidata \ 434 }; \ 435 DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 436 437 438 #endif /* COMPAT_OLDPCI */ 439 #endif /* _PCIVAR_H_ */ 440