1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/pci/pcivar.h,v 1.80.2.1.4.1 2009/04/15 03:14:26 kensmith Exp $ 27 * 28 */ 29 30 #ifndef _PCIVAR_H_ 31 #define _PCIVAR_H_ 32 33 #ifndef _SYS_QUEUE_H_ 34 #include <sys/queue.h> 35 #endif 36 37 /* some PCI bus constants */ 38 39 #define PCI_DOMAINMAX 65535 /* highest supported domain number */ 40 #define PCI_BUSMAX 255 /* highest supported bus number */ 41 #define PCI_SLOTMAX 31 /* highest supported slot number */ 42 #define PCI_FUNCMAX 7 /* highest supported function number */ 43 #define PCI_REGMAX 255 /* highest supported config register addr. */ 44 45 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 46 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 47 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 48 49 typedef uint64_t pci_addr_t; 50 51 /* Interesting values for PCI power management */ 52 struct pcicfg_pp { 53 uint16_t pp_cap; /* PCI power management capabilities */ 54 uint8_t pp_status; /* config space address of PCI power status reg */ 55 uint8_t pp_pmcsr; /* config space address of PMCSR reg */ 56 uint8_t pp_data; /* config space address of PCI power data reg */ 57 }; 58 59 struct vpd_readonly { 60 char keyword[2]; 61 char *value; 62 }; 63 64 struct vpd_write { 65 char keyword[2]; 66 char *value; 67 int start; 68 int len; 69 }; 70 71 struct pcicfg_vpd { 72 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 73 char vpd_cached; 74 char *vpd_ident; /* string identifier */ 75 int vpd_rocnt; 76 struct vpd_readonly *vpd_ros; 77 int vpd_wcnt; 78 struct vpd_write *vpd_w; 79 }; 80 81 /* Interesting values for PCI MSI */ 82 struct pcicfg_msi { 83 uint16_t msi_ctrl; /* Message Control */ 84 uint8_t msi_location; /* Offset of MSI capability registers. */ 85 uint8_t msi_msgnum; /* Number of messages */ 86 int msi_alloc; /* Number of allocated messages. */ 87 uint64_t msi_addr; /* Contents of address register. */ 88 uint16_t msi_data; /* Contents of data register. */ 89 u_int msi_handlers; 90 }; 91 92 /* Interesting values for PCI MSI-X */ 93 struct msix_vector { 94 uint64_t mv_address; /* Contents of address register. */ 95 uint32_t mv_data; /* Contents of data register. */ 96 int mv_irq; 97 }; 98 99 struct msix_table_entry { 100 u_int mte_vector; /* 1-based index into msix_vectors array. */ 101 u_int mte_handlers; 102 }; 103 104 struct pcicfg_msix { 105 uint16_t msix_ctrl; /* Message Control */ 106 uint16_t msix_msgnum; /* Number of messages */ 107 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 108 uint8_t msix_table_bar; /* BAR containing vector table. */ 109 uint8_t msix_pba_bar; /* BAR containing PBA. */ 110 uint32_t msix_table_offset; 111 uint32_t msix_pba_offset; 112 int msix_alloc; /* Number of allocated vectors. */ 113 int msix_table_len; /* Length of virtual table. */ 114 struct msix_table_entry *msix_table; /* Virtual table. */ 115 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 116 struct resource *msix_table_res; /* Resource containing vector table. */ 117 struct resource *msix_pba_res; /* Resource containing PBA. */ 118 }; 119 120 /* Interesting values for HyperTransport */ 121 struct pcicfg_ht { 122 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 123 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 124 uint16_t ht_msictrl; /* MSI mapping control */ 125 uint64_t ht_msiaddr; /* MSI mapping base address */ 126 }; 127 128 /* Interesting values for PCI Express capability */ 129 struct pcicfg_expr { 130 uint8_t expr_ptr; /* capability ptr */ 131 uint16_t expr_cap; /* capabilities */ 132 uint32_t expr_slotcap; /* slot capabilities */ 133 }; 134 135 /* Interesting values for PCI-X */ 136 struct pcicfg_pcix { 137 uint8_t pcix_ptr; 138 }; 139 140 /* config header information common to all header types */ 141 typedef struct pcicfg { 142 struct device *dev; /* device which owns this */ 143 144 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */ 145 uint32_t bios; /* BIOS mapping */ 146 147 uint16_t subvendor; /* card vendor ID */ 148 uint16_t subdevice; /* card device ID, assigned by card vendor */ 149 uint16_t vendor; /* chip vendor ID */ 150 uint16_t device; /* chip device ID, assigned by chip vendor */ 151 152 uint16_t cmdreg; /* disable/enable chip and PCI options */ 153 uint16_t statreg; /* supported PCI features and error state */ 154 155 uint8_t baseclass; /* chip PCI class */ 156 uint8_t subclass; /* chip PCI subclass */ 157 uint8_t progif; /* chip PCI programming interface */ 158 uint8_t revid; /* chip revision ID */ 159 160 uint8_t hdrtype; /* chip config header type */ 161 uint8_t cachelnsz; /* cache line size in 4byte units */ 162 uint8_t intpin; /* PCI interrupt pin */ 163 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 164 165 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 166 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 167 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 168 169 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 170 uint8_t nummaps; /* actual number of PCI maps used */ 171 172 uint32_t domain; /* PCI domain */ 173 uint8_t bus; /* config space bus address */ 174 uint8_t slot; /* config space slot address */ 175 uint8_t func; /* config space function number */ 176 177 #ifdef COMPAT_OLDPCI 178 uint8_t secondarybus; /* bus on secondary side of bridge, if any */ 179 #else 180 uint8_t dummy; 181 #endif 182 183 struct pcicfg_pp pp; /* pci power management */ 184 struct pcicfg_vpd vpd; /* pci vital product data */ 185 struct pcicfg_msi msi; /* pci msi */ 186 struct pcicfg_msix msix; /* pci msi-x */ 187 struct pcicfg_ht ht; /* HyperTransport */ 188 struct pcicfg_expr expr; /* PCI Express */ 189 struct pcicfg_pcix pcix; /* PCI-X */ 190 } pcicfgregs; 191 192 /* additional type 1 device config header information (PCI to PCI bridge) */ 193 194 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 195 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 196 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 197 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 198 199 typedef struct { 200 pci_addr_t pmembase; /* base address of prefetchable memory */ 201 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 202 uint32_t membase; /* base address of memory window */ 203 uint32_t memlimit; /* topmost address of memory window */ 204 uint32_t iobase; /* base address of port window */ 205 uint32_t iolimit; /* topmost address of port window */ 206 uint16_t secstat; /* secondary bus status register */ 207 uint16_t bridgectl; /* bridge control register */ 208 uint8_t seclat; /* CardBus latency timer */ 209 } pcih1cfgregs; 210 211 /* additional type 2 device config header information (CardBus bridge) */ 212 213 typedef struct { 214 uint32_t membase0; /* base address of memory window */ 215 uint32_t memlimit0; /* topmost address of memory window */ 216 uint32_t membase1; /* base address of memory window */ 217 uint32_t memlimit1; /* topmost address of memory window */ 218 uint32_t iobase0; /* base address of port window */ 219 uint32_t iolimit0; /* topmost address of port window */ 220 uint32_t iobase1; /* base address of port window */ 221 uint32_t iolimit1; /* topmost address of port window */ 222 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 223 uint16_t secstat; /* secondary bus status register */ 224 uint16_t bridgectl; /* bridge control register */ 225 uint8_t seclat; /* CardBus latency timer */ 226 } pcih2cfgregs; 227 228 extern uint32_t pci_numdevs; 229 230 /* Only if the prerequisites are present */ 231 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 232 struct pci_devinfo { 233 STAILQ_ENTRY(pci_devinfo) pci_links; 234 struct resource_list resources; 235 pcicfgregs cfg; 236 struct pci_conf conf; 237 }; 238 #endif 239 240 #ifdef _SYS_BUS_H_ 241 242 #include "pci_if.h" 243 244 /* 245 * Define pci-specific resource flags for accessing memory via dense 246 * or bwx memory spaces. These flags are ignored on i386. 247 */ 248 #define PCI_RF_DENSE 0x10000 249 #define PCI_RF_BWX 0x20000 250 251 enum pci_device_ivars { 252 PCI_IVAR_SUBVENDOR, 253 PCI_IVAR_SUBDEVICE, 254 PCI_IVAR_VENDOR, 255 PCI_IVAR_DEVICE, 256 PCI_IVAR_DEVID, 257 PCI_IVAR_CLASS, 258 PCI_IVAR_SUBCLASS, 259 PCI_IVAR_PROGIF, 260 PCI_IVAR_REVID, 261 PCI_IVAR_INTPIN, 262 PCI_IVAR_IRQ, 263 PCI_IVAR_DOMAIN, 264 PCI_IVAR_BUS, 265 PCI_IVAR_SLOT, 266 PCI_IVAR_FUNCTION, 267 PCI_IVAR_ETHADDR, 268 PCI_IVAR_CMDREG, 269 PCI_IVAR_CACHELNSZ, 270 PCI_IVAR_MINGNT, 271 PCI_IVAR_MAXLAT, 272 PCI_IVAR_LATTIMER, 273 PCI_IVAR_PCIXCAP_PTR, 274 PCI_IVAR_PCIECAP_PTR, 275 PCI_IVAR_VPDCAP_PTR 276 }; 277 278 /* 279 * Simplified accessors for pci devices 280 */ 281 #define PCI_ACCESSOR(var, ivar, type) \ 282 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 283 284 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 285 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 286 PCI_ACCESSOR(vendor, VENDOR, uint16_t) 287 PCI_ACCESSOR(device, DEVICE, uint16_t) 288 PCI_ACCESSOR(devid, DEVID, uint32_t) 289 PCI_ACCESSOR(class, CLASS, uint8_t) 290 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 291 PCI_ACCESSOR(progif, PROGIF, uint8_t) 292 PCI_ACCESSOR(revid, REVID, uint8_t) 293 PCI_ACCESSOR(intpin, INTPIN, uint8_t) 294 PCI_ACCESSOR(irq, IRQ, uint8_t) 295 PCI_ACCESSOR(domain, DOMAIN, uint32_t) 296 PCI_ACCESSOR(bus, BUS, uint8_t) 297 PCI_ACCESSOR(slot, SLOT, uint8_t) 298 PCI_ACCESSOR(function, FUNCTION, uint8_t) 299 PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 300 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 301 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 302 PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 303 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 304 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 305 PCI_ACCESSOR(pcixcap_ptr, PCIXCAP_PTR, uint8_t) 306 PCI_ACCESSOR(pciecap_ptr, PCIECAP_PTR, uint8_t) 307 PCI_ACCESSOR(vpdcap_ptr, VPDCAP_PTR, uint8_t) 308 309 #undef PCI_ACCESSOR 310 311 /* 312 * Operations on configuration space. 313 */ 314 static __inline uint32_t 315 pci_read_config(device_t dev, int reg, int width) 316 { 317 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 318 } 319 320 static __inline void 321 pci_write_config(device_t dev, int reg, uint32_t val, int width) 322 { 323 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 324 } 325 326 /* 327 * Ivars for pci bridges. 328 */ 329 330 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 331 enum pcib_device_ivars { 332 PCIB_IVAR_DOMAIN, 333 PCIB_IVAR_BUS 334 }; 335 336 #define PCIB_ACCESSOR(var, ivar, type) \ 337 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 338 339 PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 340 PCIB_ACCESSOR(bus, BUS, uint32_t) 341 342 #undef PCIB_ACCESSOR 343 344 /* 345 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 346 * on i386 or other platforms should be mapped out in the MD pcireadconf 347 * code and not here, since the only MI invalid IRQ is 255. 348 */ 349 #define PCI_INVALID_IRQ 255 350 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 351 352 /* 353 * Convenience functions. 354 * 355 * These should be used in preference to manually manipulating 356 * configuration space. 357 */ 358 static __inline int 359 pci_enable_busmaster(device_t dev) 360 { 361 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 362 } 363 364 static __inline int 365 pci_disable_busmaster(device_t dev) 366 { 367 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 368 } 369 370 static __inline int 371 pci_enable_io(device_t dev, int space) 372 { 373 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 374 } 375 376 static __inline int 377 pci_disable_io(device_t dev, int space) 378 { 379 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 380 } 381 382 static __inline int 383 pci_get_vpd_ident(device_t dev, const char **identptr) 384 { 385 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 386 } 387 388 static __inline int 389 pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 390 { 391 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 392 } 393 394 /* 395 * Check if the address range falls within the VGA defined address range(s) 396 */ 397 static __inline int 398 pci_is_vga_ioport_range(u_long start, u_long end) 399 { 400 401 return (((start >= 0x3b0 && end <= 0x3bb) || 402 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 403 } 404 405 static __inline int 406 pci_is_vga_memory_range(u_long start, u_long end) 407 { 408 409 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 410 } 411 412 int pcie_slot_implemented(device_t); 413 void pcie_set_max_readrq(device_t, uint16_t); 414 uint16_t pcie_get_max_readrq(device_t); 415 416 /* 417 * PCI power states are as defined by ACPI: 418 * 419 * D0 State in which device is on and running. It is receiving full 420 * power from the system and delivering full functionality to the user. 421 * D1 Class-specific low-power state in which device context may or may not 422 * be lost. Buses in D1 cannot do anything to the bus that would force 423 * devices on that bus to lose context. 424 * D2 Class-specific low-power state in which device context may or may 425 * not be lost. Attains greater power savings than D1. Buses in D2 426 * can cause devices on that bus to lose some context. Devices in D2 427 * must be prepared for the bus to be in D2 or higher. 428 * D3 State in which the device is off and not running. Device context is 429 * lost. Power can be removed from the device. 430 */ 431 #define PCI_POWERSTATE_D0 0 432 #define PCI_POWERSTATE_D1 1 433 #define PCI_POWERSTATE_D2 2 434 #define PCI_POWERSTATE_D3 3 435 #define PCI_POWERSTATE_UNKNOWN -1 436 437 static __inline int 438 pci_set_powerstate(device_t dev, int state) 439 { 440 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 441 } 442 443 static __inline int 444 pci_get_powerstate(device_t dev) 445 { 446 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 447 } 448 449 static __inline int 450 pci_find_extcap(device_t dev, int capability, int *capreg) 451 { 452 return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg); 453 } 454 455 static __inline int 456 pci_is_pcie(device_t dev) 457 { 458 return (pci_get_pciecap_ptr(dev) != 0); 459 } 460 461 static __inline int 462 pci_is_pcix(device_t dev) 463 { 464 return (pci_get_pcixcap_ptr(dev) != 0); 465 } 466 467 static __inline int 468 pci_alloc_msi(device_t dev, int *rid, int count, int cpuid) 469 { 470 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, rid, count, cpuid)); 471 } 472 473 static __inline int 474 pci_alloc_msix(device_t dev, int *count) 475 { 476 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 477 } 478 479 static __inline int 480 pci_remap_msix(device_t dev, int count, const u_int *vectors) 481 { 482 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 483 } 484 485 static __inline int 486 pci_release_msi(device_t dev) 487 { 488 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 489 } 490 491 static __inline int 492 pci_msi_count(device_t dev) 493 { 494 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 495 } 496 497 static __inline int 498 pci_msix_count(device_t dev) 499 { 500 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 501 } 502 503 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 504 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 505 device_t pci_find_device(uint16_t, uint16_t); 506 507 /* 508 * Can be used by MD code to request the PCI bus to re-map an MSI or 509 * MSI-X message. 510 */ 511 int pci_remap_msi_irq(device_t dev, u_int irq); 512 513 /* Can be used by drivers to manage the MSI-X table. */ 514 int pci_pending_msix(device_t dev, u_int index); 515 516 int pci_msi_device_blacklisted(device_t dev); 517 518 void pci_ht_map_msi(device_t dev, uint64_t addr); 519 520 /* Returns PCI_INTR_TYPE_ */ 521 int pci_alloc_1intr(device_t dev, int msi_enable, int *rid, u_int *flags); 522 523 #define PCI_INTR_TYPE_LEGACY 0 524 #define PCI_INTR_TYPE_MSI 1 525 #define PCI_INTR_TYPE_MSIX 2 /* not yet */ 526 527 #endif /* _SYS_BUS_H_ */ 528 529 /* 530 * cdev switch for control device, initialised in generic PCI code 531 */ 532 extern struct cdevsw pcicdev; 533 534 /* 535 * List of all PCI devices, generation count for the list. 536 */ 537 STAILQ_HEAD(devlist, pci_devinfo); 538 539 extern struct devlist pci_devq; 540 extern uint32_t pci_generation; 541 542 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ 543 544 #if defined(_KERNEL) && !defined(KLD_MODULE) 545 #include "opt_compat_oldpci.h" 546 #endif 547 548 #ifdef COMPAT_OLDPCI 549 /* all this is going some day */ 550 551 typedef pcicfgregs *pcici_t; 552 typedef unsigned pcidi_t; 553 typedef void pci_inthand_t(void *arg); 554 555 #define pci_max_burst_len (3) 556 557 /* just copied from old PCI code for now ... */ 558 559 struct pci_device { 560 char* pd_name; 561 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 562 void (*pd_attach) (pcici_t tag, int unit); 563 u_long *pd_count; 564 int (*pd_shutdown) (int, int); 565 }; 566 567 #ifdef __i386__ 568 typedef u_short pci_port_t; 569 #else 570 typedef u_int pci_port_t; 571 #endif 572 573 u_long pci_conf_read (pcici_t tag, u_long reg); 574 void pci_conf_write (pcici_t tag, u_long reg, u_long data); 575 int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 576 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 577 int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg); 578 int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 579 u_int flags); 580 int pci_unmap_int (pcici_t tag); 581 582 void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 583 584 pcici_t pci_get_parent_from_tag(pcici_t tag); 585 int pci_get_bus_from_tag(pcici_t tag); 586 587 pcicfgregs *pci_devlist_get_parent(pcicfgregs *cfg); 588 589 struct module; 590 int compat_pci_handler (struct module *, int, void *); 591 #define COMPAT_PCI_DRIVER(name, pcidata) \ 592 static moduledata_t name##_mod = { \ 593 #name, \ 594 compat_pci_handler, \ 595 &pcidata \ 596 }; \ 597 DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 598 599 #endif /* COMPAT_OLDPCI */ 600 601 #endif /* _PCIVAR_H_ */ 602