1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org> 4 * Copyright (c) 2000, BSDi 5 * Copyright (c) 2004, Scott Long <scottl@kfreebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/i386/pci/pci_cfgreg.c,v 1.124.2.3 2009/05/04 21:04:29 jhb 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/spinlock.h> 39 #include <sys/spinlock2.h> 40 #include <sys/queue.h> 41 #include <bus/pci/pcivar.h> 42 #include <bus/pci/pcireg.h> 43 #include "pci_cfgreg.h" 44 #include <machine/pc/bios.h> 45 46 #include <vm/vm.h> 47 #include <vm/vm_param.h> 48 #include <vm/vm_kern.h> 49 #include <vm/vm_extern.h> 50 #include <vm/pmap.h> 51 #include <machine/pmap.h> 52 53 enum { 54 CFGMECH_NONE = 0, 55 CFGMECH_1, 56 CFGMECH_PCIE, 57 }; 58 59 static vm_offset_t pcie_base; 60 static int pcie_minbus, pcie_maxbus; 61 static uint32_t pcie_badslots; 62 static int cfgmech; 63 static struct spinlock pcicfg_spin; 64 65 static int mcfg_enable = 1; 66 TUNABLE_INT("hw.pci.mcfg", &mcfg_enable); 67 68 static uint32_t pci_docfgregread(int bus, int slot, int func, int reg, int bytes); 69 70 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes); 71 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, 72 int bytes); 73 74 static int pciereg_cfgread(int bus, unsigned slot, unsigned func, 75 unsigned reg, unsigned bytes); 76 static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func, 77 unsigned reg, int data, unsigned bytes); 78 79 /* 80 * Initialise access to PCI configuration space 81 */ 82 int 83 pci_cfgregopen(void) 84 { 85 static int inited = 0; 86 uint64_t pciebar; 87 uint16_t vid, did; 88 89 if (!inited) { 90 inited = 1; 91 spin_init(&pcicfg_spin, "pcicfg"); 92 } 93 94 if (cfgmech != CFGMECH_NONE) 95 return 1; 96 cfgmech = CFGMECH_1; 97 98 /* 99 * Grope around in the PCI config space to see if this is a 100 * chipset that is capable of doing memory-mapped config cycles. 101 * This also implies that it can do PCIe extended config cycles. 102 */ 103 104 /* Check for supported chipsets */ 105 vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2); 106 did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2); 107 switch (vid) { 108 case 0x8086: 109 switch (did) { 110 case 0x3590: 111 case 0x3592: 112 /* Intel 7520 or 7320 */ 113 pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16; 114 pcie_cfgregopen(pciebar, 0, 255); 115 break; 116 case 0x2580: 117 case 0x2584: 118 case 0x2590: 119 /* Intel 915, 925, or 915GM */ 120 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4); 121 pcie_cfgregopen(pciebar, 0, 255); 122 break; 123 } 124 } 125 return 1; 126 } 127 128 static uint32_t 129 pci_docfgregread(int bus, int slot, int func, int reg, int bytes) 130 { 131 if (cfgmech == CFGMECH_PCIE && 132 (bus >= pcie_minbus && bus <= pcie_maxbus) && 133 (bus != 0 || !(1 << slot & pcie_badslots))) 134 return pciereg_cfgread(bus, slot, func, reg, bytes); 135 else 136 return pcireg_cfgread(bus, slot, func, reg, bytes); 137 } 138 139 /* 140 * Read configuration space register 141 */ 142 uint32_t 143 pci_cfgregread(int bus, int slot, int func, int reg, int bytes) 144 { 145 /* 146 * Some BIOS writers seem to want to ignore the spec and put 147 * 0 in the intline rather than 255 to indicate none. Some use 148 * numbers in the range 128-254 to indicate something strange and 149 * apparently undocumented anywhere. Assume these are completely 150 * bogus and map them to 255, which means "none". 151 */ 152 if (reg == PCIR_INTLINE && bytes == 1) { 153 uint32_t line; 154 155 line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1); 156 if (line == 0 || line >= 128) 157 return (PCI_INVALID_IRQ); 158 return line; 159 } 160 return pci_docfgregread(bus, slot, func, reg, bytes); 161 } 162 163 /* 164 * Write configuration space register 165 */ 166 void 167 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) 168 { 169 if (cfgmech == CFGMECH_PCIE && 170 (bus >= pcie_minbus && bus <= pcie_maxbus) && 171 (bus != 0 || !(1 << slot & pcie_badslots))) 172 pciereg_cfgwrite(bus, slot, func, reg, data, bytes); 173 else 174 pcireg_cfgwrite(bus, slot, func, reg, data, bytes); 175 } 176 177 /* 178 * Configuration space access using direct register operations 179 */ 180 181 /* enable configuration space accesses and return data port address */ 182 static int 183 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes) 184 { 185 int dataport = 0; 186 187 if (bus <= PCI_BUSMAX && 188 slot <= PCI_SLOTMAX && 189 func <= PCI_FUNCMAX && 190 (unsigned)reg <= PCI_REGMAX && 191 bytes != 3 && 192 (unsigned)bytes <= 4 && 193 (reg & (bytes - 1)) == 0) { 194 outl(CONF1_ADDR_PORT, (1 << 31) | (bus << 16) | (slot << 11) | 195 (func << 8) | (reg & ~0x03)); 196 dataport = CONF1_DATA_PORT + (reg & 0x03); 197 } 198 return dataport; 199 } 200 201 /* disable configuration space accesses */ 202 static void 203 pci_cfgdisable(void) 204 { 205 /* 206 * Do nothing. Writing a 0 to the address port can apparently 207 * confuse some bridges and cause spurious access failures. 208 */ 209 } 210 211 static int 212 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes) 213 { 214 int data = -1; 215 int port; 216 217 spin_lock(&pcicfg_spin); 218 port = pci_cfgenable(bus, slot, func, reg, bytes); 219 if (port != 0) { 220 switch (bytes) { 221 case 1: 222 data = inb(port); 223 break; 224 case 2: 225 data = inw(port); 226 break; 227 case 4: 228 data = inl(port); 229 break; 230 } 231 pci_cfgdisable(); 232 } 233 spin_unlock(&pcicfg_spin); 234 return data; 235 } 236 237 static void 238 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) 239 { 240 int port; 241 242 spin_lock(&pcicfg_spin); 243 port = pci_cfgenable(bus, slot, func, reg, bytes); 244 if (port != 0) { 245 switch (bytes) { 246 case 1: 247 outb(port, data); 248 break; 249 case 2: 250 outw(port, data); 251 break; 252 case 4: 253 outl(port, data); 254 break; 255 } 256 pci_cfgdisable(); 257 } 258 spin_unlock(&pcicfg_spin); 259 } 260 261 int 262 pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) 263 { 264 if (bootverbose) { 265 kprintf("PCIe: Memory Mapped configuration base @ 0x%jx, " 266 "bus [%d, %d]\n", (uintmax_t)base, minbus, maxbus); 267 } 268 269 if (!mcfg_enable) 270 return 0; 271 272 if (minbus != 0) 273 return 0; 274 275 if (bootverbose) 276 kprintf("PCIe: Using Memory Mapped configuration\n"); 277 278 pcie_base = (vm_offset_t)pmap_mapdev_uncacheable(base, 279 ((unsigned)maxbus + 1) << 20); 280 pcie_minbus = minbus; 281 pcie_maxbus = maxbus; 282 cfgmech = CFGMECH_PCIE; 283 284 /* 285 * On some AMD systems, some of the devices on bus 0 are 286 * inaccessible using memory-mapped PCI config access. Walk 287 * bus 0 looking for such devices. For these devices, we will 288 * fall back to using type 1 config access instead. 289 */ 290 if (pci_cfgregopen() != 0) { 291 int slot; 292 293 for (slot = 0; slot <= PCI_SLOTMAX; slot++) { 294 uint32_t val1, val2; 295 296 val1 = pcireg_cfgread(0, slot, 0, 0, 4); 297 if (val1 == 0xffffffff) 298 continue; 299 300 val2 = pciereg_cfgread(0, slot, 0, 0, 4); 301 if (val2 != val1) 302 pcie_badslots |= (1 << slot); 303 } 304 } 305 return 1; 306 } 307 308 #define PCIE_VADDR(base, reg, bus, slot, func) \ 309 ((base) + \ 310 ((((bus) & 0xff) << 20) | \ 311 (((slot) & 0x1f) << 15) | \ 312 (((func) & 0x7) << 12) | \ 313 ((reg) & 0xfff))) 314 315 static int 316 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg, 317 unsigned bytes) 318 { 319 volatile vm_offset_t va; 320 int data = -1; 321 322 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX || 323 func > PCI_FUNCMAX || reg > PCIE_REGMAX) 324 return -1; 325 326 va = PCIE_VADDR(pcie_base, reg, bus, slot, func); 327 328 switch (bytes) { 329 case 4: 330 data = *(volatile uint32_t *)(va); 331 break; 332 case 2: 333 data = *(volatile uint16_t *)(va); 334 break; 335 case 1: 336 data = *(volatile uint8_t *)(va); 337 break; 338 } 339 return data; 340 } 341 342 static void 343 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data, 344 unsigned bytes) 345 { 346 volatile vm_offset_t va; 347 348 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX || 349 func > PCI_FUNCMAX || reg > PCIE_REGMAX) 350 return; 351 352 va = PCIE_VADDR(pcie_base, reg, bus, slot, func); 353 354 switch (bytes) { 355 case 4: 356 *(volatile uint32_t *)(va) = data; 357 break; 358 case 2: 359 *(volatile uint16_t *)(va) = data; 360 break; 361 case 1: 362 *(volatile uint8_t *)(va) = data; 363 break; 364 } 365 } 366