1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 /* 35 * Intel 4th generation mobile cpus integrated I2C device, smbus driver. 36 * 37 * See ig4_reg.h for datasheet reference and notes. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/errno.h> 45 #include <sys/lock.h> 46 #include <sys/syslog.h> 47 #include <sys/bus.h> 48 #include <sys/sysctl.h> 49 50 #include <sys/rman.h> 51 52 #include <bus/pci/pcivar.h> 53 #include <bus/pci/pcireg.h> 54 #include <bus/smbus/smbconf.h> 55 56 #include "smbus_if.h" 57 58 #include "ig4_reg.h" 59 #include "ig4_var.h" 60 61 #define TRANS_NORMAL 1 62 #define TRANS_PCALL 2 63 #define TRANS_BLOCK 3 64 65 static void ig4iic_intr(void *cookie); 66 static void ig4iic_dump(ig4iic_softc_t *sc); 67 68 static int ig4_dump; 69 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLTYPE_INT | CTLFLAG_RW, 70 &ig4_dump, 0, ""); 71 72 /* 73 * Low-level inline support functions 74 */ 75 static __inline 76 void 77 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value) 78 { 79 bus_space_write_4(sc->regs_t, sc->regs_h, reg, value); 80 bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4, 81 BUS_SPACE_BARRIER_WRITE); 82 } 83 84 static __inline 85 uint32_t 86 reg_read(ig4iic_softc_t *sc, uint32_t reg) 87 { 88 uint32_t value; 89 90 bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4, 91 BUS_SPACE_BARRIER_READ); 92 value = bus_space_read_4(sc->regs_t, sc->regs_h, reg); 93 return value; 94 } 95 96 /* 97 * Enable or disable the controller and wait for the controller to acknowledge 98 * the state change. 99 */ 100 static 101 int 102 set_controller(ig4iic_softc_t *sc, uint32_t ctl) 103 { 104 int retry; 105 int error; 106 uint32_t v; 107 108 if (ctl & IG4_I2C_ENABLE) { 109 reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET | 110 IG4_INTR_RX_FULL); 111 reg_read(sc, IG4_REG_CLR_INTR); 112 } else { 113 reg_write(sc, IG4_REG_INTR_MASK, 0); 114 } 115 reg_write(sc, IG4_REG_I2C_EN, ctl); 116 error = SMB_ETIMEOUT; 117 118 for (retry = 100; retry > 0; --retry) { 119 v = reg_read(sc, IG4_REG_ENABLE_STATUS); 120 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) { 121 error = 0; 122 break; 123 } 124 tsleep(sc, 0, "i2cslv", 1); 125 } 126 return error; 127 } 128 129 /* 130 * Wait up to 25ms for the requested status using a 25uS polling loop. 131 */ 132 static 133 int 134 wait_status(ig4iic_softc_t *sc, uint32_t status) 135 { 136 uint32_t v; 137 int error; 138 int txlvl = -1; 139 sysclock_t count; 140 sysclock_t limit; 141 142 error = SMB_ETIMEOUT; 143 count = sys_cputimer->count(); 144 limit = sys_cputimer->freq / 40; 145 146 for (;;) { 147 /* 148 * Check requested status 149 */ 150 v = reg_read(sc, IG4_REG_I2C_STA); 151 if (v & status) { 152 error = 0; 153 break; 154 } 155 156 /* 157 * When waiting for receive data break-out if the interrupt 158 * loaded data into the FIFO. 159 */ 160 if (status & IG4_STATUS_RX_NOTEMPTY) { 161 if (sc->rpos != sc->rnext) { 162 error = 0; 163 break; 164 } 165 } 166 167 /* 168 * When waiting for the transmit FIFO to become empty, 169 * reset the timeout if we see a change in the transmit 170 * FIFO level as progress is being made. 171 */ 172 if (status & IG4_STATUS_TX_EMPTY) { 173 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK; 174 if (txlvl != v) { 175 txlvl = v; 176 count = sys_cputimer->count(); 177 } 178 } 179 180 /* 181 * Stop if we've run out of time. 182 */ 183 if (sys_cputimer->count() - count > limit) 184 break; 185 186 /* 187 * When waiting for receive data let the interrupt do its 188 * work, otherwise poll with the lock held. 189 */ 190 if (status & IG4_STATUS_RX_NOTEMPTY) { 191 lksleep(sc, &sc->lk, 0, "i2cwait", (hz + 99) / 100); 192 } else { 193 DELAY(25); 194 } 195 } 196 197 return error; 198 } 199 200 /* 201 * Read I2C data. The data might have already been read by 202 * the interrupt code, otherwise it is sitting in the data 203 * register. 204 */ 205 static 206 uint8_t 207 data_read(ig4iic_softc_t *sc) 208 { 209 uint8_t c; 210 211 if (sc->rpos == sc->rnext) { 212 c = (uint8_t)reg_read(sc, IG4_REG_DATA_CMD); 213 } else { 214 c = sc->rbuf[sc->rpos & IG4_RBUFMASK]; 215 ++sc->rpos; 216 } 217 return c; 218 } 219 220 /* 221 * Set the slave address. The controller must be disabled when 222 * changing the address. 223 * 224 * This operation does not issue anything to the I2C bus but sets 225 * the target address for when the controller later issues a START. 226 */ 227 static 228 void 229 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave, int trans_op) 230 { 231 uint32_t tar; 232 uint32_t ctl; 233 int use_10bit; 234 235 use_10bit = sc->use_10bit; 236 if (trans_op & SMB_TRANS_7BIT) 237 use_10bit = 0; 238 if (trans_op & SMB_TRANS_10BIT) 239 use_10bit = 1; 240 241 if (sc->slave_valid && sc->last_slave == slave && 242 sc->use_10bit == use_10bit) { 243 return; 244 } 245 sc->use_10bit = use_10bit; 246 247 /* 248 * Wait for TXFIFO to drain before disabling the controller. 249 * 250 * If a write message has not been completed it's really a 251 * programming error, but for now in that case issue an extra 252 * byte + STOP. 253 * 254 * If a read message has not been completed it's also a programming 255 * error, for now just ignore it. 256 */ 257 wait_status(sc, IG4_STATUS_TX_NOTFULL); 258 if (sc->write_started) { 259 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP); 260 sc->write_started = 0; 261 } 262 if (sc->read_started) 263 sc->read_started = 0; 264 wait_status(sc, IG4_STATUS_TX_EMPTY); 265 266 set_controller(sc, 0); 267 ctl = reg_read(sc, IG4_REG_CTL); 268 ctl &= ~IG4_CTL_10BIT; 269 ctl |= IG4_CTL_RESTARTEN; 270 271 tar = slave; 272 if (sc->use_10bit) { 273 tar |= IG4_TAR_10BIT; 274 ctl |= IG4_CTL_10BIT; 275 } 276 reg_write(sc, IG4_REG_CTL, ctl); 277 reg_write(sc, IG4_REG_TAR_ADD, tar); 278 set_controller(sc, IG4_I2C_ENABLE); 279 sc->slave_valid = 1; 280 sc->last_slave = slave; 281 } 282 283 /* 284 * Issue START with byte command, possible count, and a variable length 285 * read or write buffer, then possible turn-around read. The read also 286 * has a possible count received. 287 * 288 * For SMBUS - 289 * 290 * Quick: START+ADDR+RD/WR STOP 291 * 292 * Normal: START+ADDR+WR CMD DATA..DATA STOP 293 * 294 * START+ADDR+RD CMD 295 * RESTART+ADDR RDATA..RDATA STOP 296 * (can also be used for I2C transactions) 297 * 298 * Process Call: START+ADDR+WR CMD DATAL DATAH 299 * RESTART+ADDR+RD RDATAL RDATAH STOP 300 * 301 * Block: START+ADDR+RD CMD 302 * RESTART+ADDR+RD RCOUNT DATA... STOP 303 * 304 * START+ADDR+WR CMD 305 * RESTART+ADDR+WR WCOUNT DATA... STOP 306 * 307 * For I2C - basically, no *COUNT fields, possibly no *CMD field. If the 308 * sender needs to issue a 2-byte command it will incorporate it 309 * into the write buffer and also set NOCMD. 310 * 311 * Generally speaking, the START+ADDR / RESTART+ADDR is handled automatically 312 * by the controller at the beginning of a command sequence or on a data 313 * direction turn-around, and we only need to tell it when to issue the STOP. 314 */ 315 static int 316 smb_transaction(ig4iic_softc_t *sc, char cmd, int op, 317 char *wbuf, int wcount, char *rbuf, int rcount, int *actualp) 318 { 319 int error; 320 int unit; 321 uint32_t last; 322 323 /* 324 * Debugging - dump registers 325 */ 326 if (ig4_dump) { 327 unit = device_get_unit(sc->dev); 328 if (ig4_dump & (1 << unit)) { 329 ig4_dump &= ~(1 << unit); 330 ig4iic_dump(sc); 331 } 332 } 333 334 /* 335 * Issue START or RESTART with next data byte, clear any previous 336 * abort condition that may have been holding the txfifo in reset. 337 */ 338 last = IG4_DATA_RESTART; 339 reg_read(sc, IG4_REG_CLR_TX_ABORT); 340 if (actualp) 341 *actualp = 0; 342 343 /* 344 * Issue command if not told otherwise (smbus). 345 */ 346 if ((op & SMB_TRANS_NOCMD) == 0) { 347 error = wait_status(sc, IG4_STATUS_TX_NOTFULL); 348 if (error) 349 goto done; 350 last |= (u_char)cmd; 351 if (wcount == 0 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0) 352 last |= IG4_DATA_STOP; 353 reg_write(sc, IG4_REG_DATA_CMD, last); 354 last = 0; 355 } 356 357 /* 358 * Clean out any previously received data. 359 */ 360 if (sc->rpos != sc->rnext && 361 (op & SMB_TRANS_NOREPORT) == 0) { 362 device_printf(sc->dev, 363 "discarding %d bytes of spurious data\n", 364 sc->rnext - sc->rpos); 365 } 366 sc->rpos = 0; 367 sc->rnext = 0; 368 369 /* 370 * If writing and not told otherwise, issue the write count (smbus). 371 */ 372 if (wcount && (op & SMB_TRANS_NOCNT) == 0) { 373 error = wait_status(sc, IG4_STATUS_TX_NOTFULL); 374 if (error) 375 goto done; 376 last |= (u_char)cmd; 377 reg_write(sc, IG4_REG_DATA_CMD, last); 378 last = 0; 379 } 380 381 /* 382 * Bulk write (i2c) 383 */ 384 while (wcount) { 385 error = wait_status(sc, IG4_STATUS_TX_NOTFULL); 386 if (error) 387 goto done; 388 last |= (u_char)*wbuf; 389 if (wcount == 1 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0) 390 last |= IG4_DATA_STOP; 391 reg_write(sc, IG4_REG_DATA_CMD, last); 392 --wcount; 393 ++wbuf; 394 last = 0; 395 } 396 397 /* 398 * Issue reads to xmit FIFO (strange, I know) to tell the controller 399 * to clock in data. At the moment just issue one read ahead to 400 * pipeline the incoming data. 401 * 402 * NOTE: In the case of NOCMD and wcount == 0 we still issue a 403 * RESTART here, even if the data direction has not changed 404 * from the previous CHAINing call. This we force the RESTART. 405 * (A new START is issued automatically by the controller in 406 * the other nominal cases such as a data direction change or 407 * a previous STOP was issued). 408 * 409 * If this will be the last byte read we must also issue the STOP 410 * at the end of the read. 411 */ 412 if (rcount) { 413 last = IG4_DATA_RESTART | IG4_DATA_COMMAND_RD; 414 if (rcount == 1 && 415 (op & (SMB_TRANS_NOSTOP | SMB_TRANS_NOCNT)) == 416 SMB_TRANS_NOCNT) { 417 last |= IG4_DATA_STOP; 418 } 419 reg_write(sc, IG4_REG_DATA_CMD, last); 420 last = IG4_DATA_COMMAND_RD; 421 } 422 423 /* 424 * Bulk read (i2c) and count field handling (smbus) 425 */ 426 while (rcount) { 427 /* 428 * Maintain a pipeline by queueing the allowance for the next 429 * read before waiting for the current read. 430 */ 431 if (rcount > 1) { 432 if (op & SMB_TRANS_NOCNT) 433 last = (rcount == 2) ? IG4_DATA_STOP : 0; 434 else 435 last = 0; 436 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD | 437 last); 438 } 439 error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY); 440 if (error) { 441 if ((op & SMB_TRANS_NOREPORT) == 0) { 442 device_printf(sc->dev, 443 "rx timeout addr 0x%02x\n", 444 sc->last_slave); 445 } 446 goto done; 447 } 448 last = data_read(sc); 449 450 if (op & SMB_TRANS_NOCNT) { 451 *rbuf = (u_char)last; 452 ++rbuf; 453 --rcount; 454 if (actualp) 455 ++*actualp; 456 } else { 457 /* 458 * Handle count field (smbus), which is not part of 459 * the rcount'ed buffer. The first read data in a 460 * bulk transfer is the count. 461 * 462 * XXX if rcount is loaded as 0 how do I generate a 463 * STOP now without issuing another RD or WR? 464 */ 465 if (rcount > (u_char)last) 466 rcount = (u_char)last; 467 op |= SMB_TRANS_NOCNT; 468 } 469 } 470 error = 0; 471 done: 472 /* XXX wait for xmit buffer to become empty */ 473 last = reg_read(sc, IG4_REG_TX_ABRT_SOURCE); 474 475 return error; 476 } 477 478 /* 479 * SMBUS API FUNCTIONS 480 * 481 * Called from ig4iic_pci_attach/detach() 482 */ 483 int 484 ig4iic_attach(ig4iic_softc_t *sc) 485 { 486 int error; 487 uint32_t v; 488 489 lockmgr(&sc->lk, LK_EXCLUSIVE); 490 491 if (sc->version == IG4_ATOM) { 492 v = reg_read(sc, IG4_REG_COMP_TYPE); 493 kprintf("type %08x", v); 494 } 495 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 496 v = reg_read(sc, IG4_REG_COMP_PARAM1); 497 kprintf(" params %08x", v); 498 v = reg_read(sc, IG4_REG_GENERAL); 499 kprintf(" general %08x", v); 500 /* 501 * The content of IG4_REG_GENERAL is different for each 502 * controller version. 503 */ 504 if (sc->version == IG4_HASWELL && 505 (v & IG4_GENERAL_SWMODE) == 0) { 506 v |= IG4_GENERAL_SWMODE; 507 reg_write(sc, IG4_REG_GENERAL, v); 508 v = reg_read(sc, IG4_REG_GENERAL); 509 kprintf(" (updated %08x)", v); 510 } 511 } 512 513 if (sc->version == IG4_HASWELL) { 514 v = reg_read(sc, IG4_REG_SW_LTR_VALUE); 515 kprintf(" swltr %08x", v); 516 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE); 517 kprintf(" autoltr %08x", v); 518 } else if (sc->version == IG4_SKYLAKE) { 519 v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE); 520 kprintf(" activeltr %08x", v); 521 v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE); 522 kprintf(" idleltr %08x", v); 523 } 524 525 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 526 v = reg_read(sc, IG4_REG_COMP_VER); 527 kprintf(" version %08x\n", v); 528 if (v != IG4_COMP_VER) { 529 error = ENXIO; 530 goto done; 531 } 532 } 533 #if 1 534 v = reg_read(sc, IG4_REG_SS_SCL_HCNT); 535 kprintf("SS_SCL_HCNT=%08x", v); 536 v = reg_read(sc, IG4_REG_SS_SCL_LCNT); 537 kprintf(" LCNT=%08x", v); 538 v = reg_read(sc, IG4_REG_FS_SCL_HCNT); 539 kprintf(" FS_SCL_HCNT=%08x", v); 540 v = reg_read(sc, IG4_REG_FS_SCL_LCNT); 541 kprintf(" LCNT=%08x\n", v); 542 v = reg_read(sc, IG4_REG_SDA_HOLD); 543 kprintf("HOLD %08x\n", v); 544 545 v = reg_read(sc, IG4_REG_SS_SCL_HCNT); 546 reg_write(sc, IG4_REG_FS_SCL_HCNT, v); 547 v = reg_read(sc, IG4_REG_SS_SCL_LCNT); 548 reg_write(sc, IG4_REG_FS_SCL_LCNT, v); 549 #endif 550 /* 551 * Program based on a 25000 Hz clock. This is a bit of a 552 * hack (obviously). The defaults are 400 and 470 for standard 553 * and 60 and 130 for fast. The defaults for standard fail 554 * utterly (presumably cause an abort) because the clock time 555 * is ~18.8ms by default. This brings it down to ~4ms (for now). 556 */ 557 reg_write(sc, IG4_REG_SS_SCL_HCNT, 100); 558 reg_write(sc, IG4_REG_SS_SCL_LCNT, 125); 559 reg_write(sc, IG4_REG_FS_SCL_HCNT, 100); 560 reg_write(sc, IG4_REG_FS_SCL_LCNT, 125); 561 562 /* 563 * Use a threshold of 1 so we get interrupted on each character, 564 * allowing us to use lksleep() in our poll code. Not perfect 565 * but this is better than using DELAY() for receiving data. 566 */ 567 reg_write(sc, IG4_REG_RX_TL, 1); 568 569 reg_write(sc, IG4_REG_CTL, 570 IG4_CTL_MASTER | 571 IG4_CTL_SLAVE_DISABLE | 572 IG4_CTL_RESTARTEN | 573 IG4_CTL_SPEED_STD); 574 /* 575 * When ig4 is attached via ACPI, (child) devices should access the 576 * smbus via I2cSerialBus ACPI resources instead. 577 */ 578 if (strcmp("acpi", device_get_name(device_get_parent(sc->dev))) != 0) { 579 sc->smb = device_add_child(sc->dev, "smbus", -1); 580 if (sc->smb == NULL) { 581 device_printf(sc->dev, "smbus driver not found\n"); 582 error = ENXIO; 583 goto done; 584 } 585 } 586 587 sc->acpismb = device_add_child(sc->dev, "smbacpi", -1); 588 if (sc->acpismb == NULL) { 589 device_printf(sc->dev, "smbacpi driver not found\n"); 590 if (sc->smb == NULL) { 591 error = ENXIO; 592 goto done; 593 } 594 } 595 596 #if 0 597 /* 598 * Don't do this, it blows up the PCI config 599 */ 600 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 601 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW); 602 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW); 603 } else if (sc->version == IG4_SKYLAKE) { 604 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); 605 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); 606 } 607 #endif 608 609 /* 610 * Interrupt on STOP detect or receive character ready 611 */ 612 if (set_controller(sc, 0)) 613 device_printf(sc->dev, "controller error during attach-1\n"); 614 if (set_controller(sc, IG4_I2C_ENABLE)) 615 device_printf(sc->dev, "controller error during attach-2\n"); 616 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE, 617 ig4iic_intr, sc, &sc->intr_handle, NULL); 618 if (error) { 619 device_printf(sc->dev, 620 "Unable to setup irq: error %d\n", error); 621 goto done; 622 } 623 624 /* Attach us to the smbus */ 625 lockmgr(&sc->lk, LK_RELEASE); 626 error = bus_generic_attach(sc->dev); 627 lockmgr(&sc->lk, LK_EXCLUSIVE); 628 if (error) { 629 device_printf(sc->dev, 630 "failed to attach child: error %d\n", error); 631 goto done; 632 } 633 sc->generic_attached = 1; 634 635 done: 636 lockmgr(&sc->lk, LK_RELEASE); 637 return error; 638 } 639 640 int 641 ig4iic_detach(ig4iic_softc_t *sc) 642 { 643 int error; 644 645 lockmgr(&sc->lk, LK_EXCLUSIVE); 646 647 reg_write(sc, IG4_REG_INTR_MASK, 0); 648 set_controller(sc, 0); 649 650 if (sc->generic_attached) { 651 error = bus_generic_detach(sc->dev); 652 if (error) 653 goto done; 654 sc->generic_attached = 0; 655 } 656 if (sc->smb) { 657 device_delete_child(sc->dev, sc->smb); 658 sc->smb = NULL; 659 } 660 if (sc->acpismb) { 661 device_delete_child(sc->dev, sc->acpismb); 662 sc->acpismb = NULL; 663 } 664 if (sc->intr_handle) { 665 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle); 666 sc->intr_handle = NULL; 667 } 668 669 error = 0; 670 done: 671 lockmgr(&sc->lk, LK_RELEASE); 672 return error; 673 } 674 675 int 676 ig4iic_smb_callback(device_t dev, int index, void *data) 677 { 678 ig4iic_softc_t *sc = device_get_softc(dev); 679 int error; 680 681 lockmgr(&sc->lk, LK_EXCLUSIVE); 682 683 switch (index) { 684 case SMB_REQUEST_BUS: 685 error = 0; 686 break; 687 case SMB_RELEASE_BUS: 688 error = 0; 689 break; 690 default: 691 error = SMB_EABORT; 692 break; 693 } 694 695 lockmgr(&sc->lk, LK_RELEASE); 696 697 return error; 698 } 699 700 /* 701 * Quick command. i.e. START + cmd + R/W + STOP and no data. It is 702 * unclear to me how I could implement this with the intel i2c controller 703 * because the controler sends STARTs and STOPs automatically with data. 704 */ 705 int 706 ig4iic_smb_quick(device_t dev, u_char slave, int how) 707 { 708 ig4iic_softc_t *sc = device_get_softc(dev); 709 int error; 710 711 lockmgr(&sc->lk, LK_EXCLUSIVE); 712 713 switch (how) { 714 case SMB_QREAD: 715 error = SMB_ENOTSUPP; 716 break; 717 case SMB_QWRITE: 718 error = SMB_ENOTSUPP; 719 break; 720 default: 721 error = SMB_ENOTSUPP; 722 break; 723 } 724 lockmgr(&sc->lk, LK_RELEASE); 725 726 return error; 727 } 728 729 /* 730 * Incremental send byte without stop (?). It is unclear why the slave 731 * address is specified if this presumably is used in combination with 732 * ig4iic_smb_quick(). 733 * 734 * (Also, how would this work anyway? Issue the last byte with writeb()?) 735 */ 736 int 737 ig4iic_smb_sendb(device_t dev, u_char slave, char byte) 738 { 739 ig4iic_softc_t *sc = device_get_softc(dev); 740 uint32_t cmd; 741 int error; 742 743 lockmgr(&sc->lk, LK_EXCLUSIVE); 744 745 set_slave_addr(sc, slave, 0); 746 cmd = byte; 747 if (wait_status(sc, IG4_STATUS_TX_NOTFULL) == 0) { 748 reg_write(sc, IG4_REG_DATA_CMD, cmd); 749 error = 0; 750 } else { 751 error = SMB_ETIMEOUT; 752 } 753 754 lockmgr(&sc->lk, LK_RELEASE); 755 return error; 756 } 757 758 /* 759 * Incremental receive byte without stop (?). It is unclear why the slave 760 * address is specified if this presumably is used in combination with 761 * ig4iic_smb_quick(). 762 */ 763 int 764 ig4iic_smb_recvb(device_t dev, u_char slave, char *byte) 765 { 766 ig4iic_softc_t *sc = device_get_softc(dev); 767 int error; 768 769 lockmgr(&sc->lk, LK_EXCLUSIVE); 770 771 set_slave_addr(sc, slave, 0); 772 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD); 773 if (wait_status(sc, IG4_STATUS_RX_NOTEMPTY) == 0) { 774 *byte = data_read(sc); 775 error = 0; 776 } else { 777 *byte = 0; 778 error = SMB_ETIMEOUT; 779 } 780 781 lockmgr(&sc->lk, LK_RELEASE); 782 return error; 783 } 784 785 /* 786 * Write command and single byte in transaction. 787 */ 788 int 789 ig4iic_smb_writeb(device_t dev, u_char slave, char cmd, char byte) 790 { 791 ig4iic_softc_t *sc = device_get_softc(dev); 792 int error; 793 794 lockmgr(&sc->lk, LK_EXCLUSIVE); 795 796 set_slave_addr(sc, slave, 0); 797 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 798 &byte, 1, NULL, 0, NULL); 799 800 lockmgr(&sc->lk, LK_RELEASE); 801 return error; 802 } 803 804 /* 805 * Write command and single word in transaction. 806 */ 807 int 808 ig4iic_smb_writew(device_t dev, u_char slave, char cmd, short word) 809 { 810 ig4iic_softc_t *sc = device_get_softc(dev); 811 char buf[2]; 812 int error; 813 814 lockmgr(&sc->lk, LK_EXCLUSIVE); 815 816 set_slave_addr(sc, slave, 0); 817 buf[0] = word & 0xFF; 818 buf[1] = word >> 8; 819 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 820 buf, 2, NULL, 0, NULL); 821 822 lockmgr(&sc->lk, LK_RELEASE); 823 return error; 824 } 825 826 /* 827 * write command and read single byte in transaction. 828 */ 829 int 830 ig4iic_smb_readb(device_t dev, u_char slave, char cmd, char *byte) 831 { 832 ig4iic_softc_t *sc = device_get_softc(dev); 833 int error; 834 835 lockmgr(&sc->lk, LK_EXCLUSIVE); 836 837 set_slave_addr(sc, slave, 0); 838 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 839 NULL, 0, byte, 1, NULL); 840 841 lockmgr(&sc->lk, LK_RELEASE); 842 return error; 843 } 844 845 /* 846 * write command and read word in transaction. 847 */ 848 int 849 ig4iic_smb_readw(device_t dev, u_char slave, char cmd, short *word) 850 { 851 ig4iic_softc_t *sc = device_get_softc(dev); 852 char buf[2]; 853 int error; 854 855 lockmgr(&sc->lk, LK_EXCLUSIVE); 856 857 set_slave_addr(sc, slave, 0); 858 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 859 NULL, 0, buf, 2, NULL)) == 0) { 860 *word = (u_char)buf[0] | ((u_char)buf[1] << 8); 861 } 862 863 lockmgr(&sc->lk, LK_RELEASE); 864 return error; 865 } 866 867 /* 868 * write command and word and read word in transaction 869 */ 870 int 871 ig4iic_smb_pcall(device_t dev, u_char slave, char cmd, 872 short sdata, short *rdata) 873 { 874 ig4iic_softc_t *sc = device_get_softc(dev); 875 char rbuf[2]; 876 char wbuf[2]; 877 int error; 878 879 lockmgr(&sc->lk, LK_EXCLUSIVE); 880 881 set_slave_addr(sc, slave, 0); 882 wbuf[0] = sdata & 0xFF; 883 wbuf[1] = sdata >> 8; 884 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 885 wbuf, 2, rbuf, 2, NULL)) == 0) { 886 *rdata = (u_char)rbuf[0] | ((u_char)rbuf[1] << 8); 887 } 888 889 lockmgr(&sc->lk, LK_RELEASE); 890 return error; 891 } 892 893 int 894 ig4iic_smb_bwrite(device_t dev, u_char slave, char cmd, 895 u_char wcount, char *buf) 896 { 897 ig4iic_softc_t *sc = device_get_softc(dev); 898 int error; 899 900 lockmgr(&sc->lk, LK_EXCLUSIVE); 901 902 set_slave_addr(sc, slave, 0); 903 error = smb_transaction(sc, cmd, 0, 904 buf, wcount, NULL, 0, NULL); 905 906 lockmgr(&sc->lk, LK_RELEASE); 907 return error; 908 } 909 910 int 911 ig4iic_smb_bread(device_t dev, u_char slave, char cmd, 912 u_char *countp_char, char *buf) 913 { 914 ig4iic_softc_t *sc = device_get_softc(dev); 915 int rcount = *countp_char; 916 int error; 917 918 lockmgr(&sc->lk, LK_EXCLUSIVE); 919 920 set_slave_addr(sc, slave, 0); 921 error = smb_transaction(sc, cmd, 0, 922 NULL, 0, buf, rcount, &rcount); 923 *countp_char = rcount; 924 925 lockmgr(&sc->lk, LK_RELEASE); 926 return error; 927 } 928 929 int 930 ig4iic_smb_trans(device_t dev, int slave, char cmd, int op, 931 char *wbuf, int wcount, char *rbuf, int rcount, 932 int *actualp) 933 { 934 ig4iic_softc_t *sc = device_get_softc(dev); 935 int error; 936 937 lockmgr(&sc->lk, LK_EXCLUSIVE); 938 939 set_slave_addr(sc, slave, op); 940 error = smb_transaction(sc, cmd, op, 941 wbuf, wcount, rbuf, rcount, actualp); 942 943 lockmgr(&sc->lk, LK_RELEASE); 944 return error; 945 } 946 947 /* 948 * Interrupt Operation 949 */ 950 static 951 void 952 ig4iic_intr(void *cookie) 953 { 954 ig4iic_softc_t *sc = cookie; 955 uint32_t status; 956 957 lockmgr(&sc->lk, LK_EXCLUSIVE); 958 /* reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET);*/ 959 reg_read(sc, IG4_REG_CLR_INTR); 960 status = reg_read(sc, IG4_REG_I2C_STA); 961 while (status & IG4_STATUS_RX_NOTEMPTY) { 962 sc->rbuf[sc->rnext & IG4_RBUFMASK] = 963 (uint8_t)reg_read(sc, IG4_REG_DATA_CMD); 964 ++sc->rnext; 965 status = reg_read(sc, IG4_REG_I2C_STA); 966 } 967 wakeup(sc); 968 lockmgr(&sc->lk, LK_RELEASE); 969 } 970 971 #define REGDUMP(sc, reg) \ 972 device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg)) 973 974 static 975 void 976 ig4iic_dump(ig4iic_softc_t *sc) 977 { 978 device_printf(sc->dev, "ig4iic register dump:\n"); 979 REGDUMP(sc, IG4_REG_CTL); 980 REGDUMP(sc, IG4_REG_TAR_ADD); 981 REGDUMP(sc, IG4_REG_SS_SCL_HCNT); 982 REGDUMP(sc, IG4_REG_SS_SCL_LCNT); 983 REGDUMP(sc, IG4_REG_FS_SCL_HCNT); 984 REGDUMP(sc, IG4_REG_FS_SCL_LCNT); 985 REGDUMP(sc, IG4_REG_INTR_STAT); 986 REGDUMP(sc, IG4_REG_INTR_MASK); 987 REGDUMP(sc, IG4_REG_RAW_INTR_STAT); 988 REGDUMP(sc, IG4_REG_RX_TL); 989 REGDUMP(sc, IG4_REG_TX_TL); 990 REGDUMP(sc, IG4_REG_I2C_EN); 991 REGDUMP(sc, IG4_REG_I2C_STA); 992 REGDUMP(sc, IG4_REG_TXFLR); 993 REGDUMP(sc, IG4_REG_RXFLR); 994 REGDUMP(sc, IG4_REG_SDA_HOLD); 995 REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE); 996 REGDUMP(sc, IG4_REG_SLV_DATA_NACK); 997 REGDUMP(sc, IG4_REG_DMA_CTRL); 998 REGDUMP(sc, IG4_REG_DMA_TDLR); 999 REGDUMP(sc, IG4_REG_DMA_RDLR); 1000 REGDUMP(sc, IG4_REG_SDA_SETUP); 1001 REGDUMP(sc, IG4_REG_ENABLE_STATUS); 1002 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 1003 REGDUMP(sc, IG4_REG_COMP_PARAM1); 1004 REGDUMP(sc, IG4_REG_COMP_VER); 1005 } 1006 if (sc->version == IG4_ATOM) { 1007 REGDUMP(sc, IG4_REG_COMP_TYPE); 1008 REGDUMP(sc, IG4_REG_CLK_PARMS); 1009 } 1010 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 1011 REGDUMP(sc, IG4_REG_RESETS_HSW); 1012 REGDUMP(sc, IG4_REG_GENERAL); 1013 } else if (sc->version == IG4_SKYLAKE) { 1014 REGDUMP(sc, IG4_REG_RESETS_SKL); 1015 } 1016 if (sc->version == IG4_HASWELL) { 1017 REGDUMP(sc, IG4_REG_SW_LTR_VALUE); 1018 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE); 1019 } else if (sc->version == IG4_SKYLAKE) { 1020 REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE); 1021 REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE); 1022 } 1023 } 1024 #undef REGDUMP 1025 1026 DRIVER_MODULE(smbus, ig4iic, smbus_driver, smbus_devclass, NULL, NULL); 1027