1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 /* 35 * Intel 4th generation mobile cpus integrated I2C device, smbus driver. 36 * 37 * See ig4_reg.h for datasheet reference and notes. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/errno.h> 45 #include <sys/lock.h> 46 #include <sys/syslog.h> 47 #include <sys/bus.h> 48 #include <sys/sysctl.h> 49 50 #include <sys/rman.h> 51 52 #include <bus/pci/pcivar.h> 53 #include <bus/pci/pcireg.h> 54 #include <bus/smbus/smbconf.h> 55 56 #include "smbus_if.h" 57 58 #include "ig4_reg.h" 59 #include "ig4_var.h" 60 61 #define TRANS_NORMAL 1 62 #define TRANS_PCALL 2 63 #define TRANS_BLOCK 3 64 65 static void ig4iic_intr(void *cookie); 66 static void ig4iic_dump(ig4iic_softc_t *sc); 67 68 static int ig4_dump; 69 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLTYPE_INT | CTLFLAG_RW, 70 &ig4_dump, 0, ""); 71 72 /* 73 * Low-level inline support functions 74 */ 75 static __inline 76 void 77 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value) 78 { 79 bus_space_write_4(sc->regs_t, sc->regs_h, reg, value); 80 bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4, 81 BUS_SPACE_BARRIER_WRITE); 82 } 83 84 static __inline 85 uint32_t 86 reg_read(ig4iic_softc_t *sc, uint32_t reg) 87 { 88 uint32_t value; 89 90 bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4, 91 BUS_SPACE_BARRIER_READ); 92 value = bus_space_read_4(sc->regs_t, sc->regs_h, reg); 93 return value; 94 } 95 96 /* 97 * Enable or disable the controller and wait for the controller to acknowledge 98 * the state change. 99 */ 100 static 101 int 102 set_controller(ig4iic_softc_t *sc, uint32_t ctl) 103 { 104 int retry; 105 int error; 106 uint32_t v; 107 108 if (ctl & IG4_I2C_ENABLE) { 109 reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET | 110 IG4_INTR_RX_FULL); 111 reg_read(sc, IG4_REG_CLR_INTR); 112 } else { 113 reg_write(sc, IG4_REG_INTR_MASK, 0); 114 } 115 reg_write(sc, IG4_REG_I2C_EN, ctl); 116 error = SMB_ETIMEOUT; 117 118 for (retry = 100; retry > 0; --retry) { 119 v = reg_read(sc, IG4_REG_ENABLE_STATUS); 120 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) { 121 error = 0; 122 break; 123 } 124 tsleep(sc, 0, "i2cslv", 1); 125 } 126 return error; 127 } 128 129 /* 130 * Wait up to 25ms for the requested status using a 25uS polling loop. 131 */ 132 static 133 int 134 wait_status(ig4iic_softc_t *sc, uint32_t status) 135 { 136 uint32_t v; 137 int error; 138 int txlvl = -1; 139 sysclock_t count; 140 sysclock_t limit; 141 142 error = SMB_ETIMEOUT; 143 count = sys_cputimer->count(); 144 limit = sys_cputimer->freq / 40; 145 146 for (;;) { 147 /* 148 * Check requested status 149 */ 150 v = reg_read(sc, IG4_REG_I2C_STA); 151 if (v & status) { 152 error = 0; 153 break; 154 } 155 156 /* 157 * When waiting for receive data break-out if the interrupt 158 * loaded data into the FIFO. 159 */ 160 if (status & IG4_STATUS_RX_NOTEMPTY) { 161 if (sc->rpos != sc->rnext) { 162 error = 0; 163 break; 164 } 165 } 166 167 /* 168 * When waiting for the transmit FIFO to become empty, 169 * reset the timeout if we see a change in the transmit 170 * FIFO level as progress is being made. 171 */ 172 if (status & IG4_STATUS_TX_EMPTY) { 173 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK; 174 if (txlvl != v) { 175 txlvl = v; 176 count = sys_cputimer->count(); 177 } 178 } 179 180 /* 181 * Stop if we've run out of time. 182 */ 183 if (sys_cputimer->count() - count > limit) 184 break; 185 186 /* 187 * When waiting for receive data let the interrupt do its 188 * work, otherwise poll with the lock held. 189 */ 190 if (status & IG4_STATUS_RX_NOTEMPTY) { 191 lksleep(sc, &sc->lk, 0, "i2cwait", (hz + 99) / 100); 192 } else { 193 DELAY(25); 194 } 195 } 196 197 return error; 198 } 199 200 /* 201 * Read I2C data. The data might have already been read by 202 * the interrupt code, otherwise it is sitting in the data 203 * register. 204 */ 205 static 206 uint8_t 207 data_read(ig4iic_softc_t *sc) 208 { 209 uint8_t c; 210 211 if (sc->rpos == sc->rnext) { 212 c = (uint8_t)reg_read(sc, IG4_REG_DATA_CMD); 213 } else { 214 c = sc->rbuf[sc->rpos & IG4_RBUFMASK]; 215 ++sc->rpos; 216 } 217 return c; 218 } 219 220 /* 221 * Set the slave address. The controller must be disabled when 222 * changing the address. 223 * 224 * This operation does not issue anything to the I2C bus but sets 225 * the target address for when the controller later issues a START. 226 */ 227 static 228 void 229 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave, int trans_op) 230 { 231 uint32_t tar; 232 uint32_t ctl; 233 int use_10bit; 234 235 use_10bit = sc->use_10bit; 236 if (trans_op & SMB_TRANS_7BIT) 237 use_10bit = 0; 238 if (trans_op & SMB_TRANS_10BIT) 239 use_10bit = 1; 240 241 if (sc->slave_valid && sc->last_slave == slave && 242 sc->use_10bit == use_10bit) { 243 return; 244 } 245 sc->use_10bit = use_10bit; 246 247 /* 248 * Wait for TXFIFO to drain before disabling the controller. 249 * 250 * If a write message has not been completed it's really a 251 * programming error, but for now in that case issue an extra 252 * byte + STOP. 253 * 254 * If a read message has not been completed it's also a programming 255 * error, for now just ignore it. 256 */ 257 wait_status(sc, IG4_STATUS_TX_NOTFULL); 258 if (sc->write_started) { 259 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP); 260 sc->write_started = 0; 261 } 262 if (sc->read_started) 263 sc->read_started = 0; 264 wait_status(sc, IG4_STATUS_TX_EMPTY); 265 266 set_controller(sc, 0); 267 ctl = reg_read(sc, IG4_REG_CTL); 268 ctl &= ~IG4_CTL_10BIT; 269 ctl |= IG4_CTL_RESTARTEN; 270 271 tar = slave; 272 if (sc->use_10bit) { 273 tar |= IG4_TAR_10BIT; 274 ctl |= IG4_CTL_10BIT; 275 } 276 reg_write(sc, IG4_REG_CTL, ctl); 277 reg_write(sc, IG4_REG_TAR_ADD, tar); 278 set_controller(sc, IG4_I2C_ENABLE); 279 sc->slave_valid = 1; 280 sc->last_slave = slave; 281 } 282 283 /* 284 * Issue START with byte command, possible count, and a variable length 285 * read or write buffer, then possible turn-around read. The read also 286 * has a possible count received. 287 * 288 * For SMBUS - 289 * 290 * Quick: START+ADDR+RD/WR STOP 291 * 292 * Normal: START+ADDR+WR CMD DATA..DATA STOP 293 * 294 * START+ADDR+RD CMD 295 * RESTART+ADDR RDATA..RDATA STOP 296 * (can also be used for I2C transactions) 297 * 298 * Process Call: START+ADDR+WR CMD DATAL DATAH 299 * RESTART+ADDR+RD RDATAL RDATAH STOP 300 * 301 * Block: START+ADDR+RD CMD 302 * RESTART+ADDR+RD RCOUNT DATA... STOP 303 * 304 * START+ADDR+WR CMD 305 * RESTART+ADDR+WR WCOUNT DATA... STOP 306 * 307 * For I2C - basically, no *COUNT fields, possibly no *CMD field. If the 308 * sender needs to issue a 2-byte command it will incorporate it 309 * into the write buffer and also set NOCMD. 310 * 311 * Generally speaking, the START+ADDR / RESTART+ADDR is handled automatically 312 * by the controller at the beginning of a command sequence or on a data 313 * direction turn-around, and we only need to tell it when to issue the STOP. 314 */ 315 static int 316 smb_transaction(ig4iic_softc_t *sc, char cmd, int op, 317 char *wbuf, int wcount, char *rbuf, int rcount, int *actualp) 318 { 319 int error; 320 int unit; 321 uint32_t last; 322 323 /* 324 * Debugging - dump registers 325 */ 326 if (ig4_dump) { 327 unit = device_get_unit(sc->dev); 328 if (ig4_dump & (1 << unit)) { 329 ig4_dump &= ~(1 << unit); 330 ig4iic_dump(sc); 331 } 332 } 333 334 /* 335 * Issue START or RESTART with next data byte, clear any previous 336 * abort condition that may have been holding the txfifo in reset. 337 */ 338 last = IG4_DATA_RESTART; 339 reg_read(sc, IG4_REG_CLR_TX_ABORT); 340 if (actualp) 341 *actualp = 0; 342 343 /* 344 * Issue command if not told otherwise (smbus). 345 */ 346 if ((op & SMB_TRANS_NOCMD) == 0) { 347 error = wait_status(sc, IG4_STATUS_TX_NOTFULL); 348 if (error) 349 goto done; 350 last |= (u_char)cmd; 351 if (wcount == 0 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0) 352 last |= IG4_DATA_STOP; 353 reg_write(sc, IG4_REG_DATA_CMD, last); 354 last = 0; 355 } 356 357 /* 358 * Clean out any previously received data. 359 */ 360 if (sc->rpos != sc->rnext && 361 (op & SMB_TRANS_NOREPORT) == 0) { 362 device_printf(sc->dev, 363 "discarding %d bytes of spurious data\n", 364 sc->rnext - sc->rpos); 365 } 366 sc->rpos = 0; 367 sc->rnext = 0; 368 369 /* 370 * If writing and not told otherwise, issue the write count (smbus). 371 */ 372 if (wcount && (op & SMB_TRANS_NOCNT) == 0) { 373 error = wait_status(sc, IG4_STATUS_TX_NOTFULL); 374 if (error) 375 goto done; 376 last |= (u_char)cmd; 377 reg_write(sc, IG4_REG_DATA_CMD, last); 378 last = 0; 379 } 380 381 /* 382 * Bulk write (i2c) 383 */ 384 while (wcount) { 385 error = wait_status(sc, IG4_STATUS_TX_NOTFULL); 386 if (error) 387 goto done; 388 last |= (u_char)*wbuf; 389 if (wcount == 1 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0) 390 last |= IG4_DATA_STOP; 391 reg_write(sc, IG4_REG_DATA_CMD, last); 392 --wcount; 393 ++wbuf; 394 last = 0; 395 } 396 397 /* 398 * Issue reads to xmit FIFO (strange, I know) to tell the controller 399 * to clock in data. At the moment just issue one read ahead to 400 * pipeline the incoming data. 401 * 402 * NOTE: In the case of NOCMD and wcount == 0 we still issue a 403 * RESTART here, even if the data direction has not changed 404 * from the previous CHAINing call. This we force the RESTART. 405 * (A new START is issued automatically by the controller in 406 * the other nominal cases such as a data direction change or 407 * a previous STOP was issued). 408 * 409 * If this will be the last byte read we must also issue the STOP 410 * at the end of the read. 411 */ 412 if (rcount) { 413 last = IG4_DATA_RESTART | IG4_DATA_COMMAND_RD; 414 if (rcount == 1 && 415 (op & (SMB_TRANS_NOSTOP | SMB_TRANS_NOCNT)) == 416 SMB_TRANS_NOCNT) { 417 last |= IG4_DATA_STOP; 418 } 419 reg_write(sc, IG4_REG_DATA_CMD, last); 420 last = IG4_DATA_COMMAND_RD; 421 } 422 423 /* 424 * Bulk read (i2c) and count field handling (smbus) 425 */ 426 while (rcount) { 427 /* 428 * Maintain a pipeline by queueing the allowance for the next 429 * read before waiting for the current read. 430 */ 431 if (rcount > 1) { 432 if (op & SMB_TRANS_NOCNT) 433 last = (rcount == 2) ? IG4_DATA_STOP : 0; 434 else 435 last = 0; 436 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD | 437 last); 438 } 439 error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY); 440 if (error) { 441 if ((op & SMB_TRANS_NOREPORT) == 0) { 442 device_printf(sc->dev, 443 "rx timeout addr 0x%02x\n", 444 sc->last_slave); 445 } 446 goto done; 447 } 448 last = data_read(sc); 449 450 if (op & SMB_TRANS_NOCNT) { 451 *rbuf = (u_char)last; 452 ++rbuf; 453 --rcount; 454 if (actualp) 455 ++*actualp; 456 } else { 457 /* 458 * Handle count field (smbus), which is not part of 459 * the rcount'ed buffer. The first read data in a 460 * bulk transfer is the count. 461 * 462 * XXX if rcount is loaded as 0 how do I generate a 463 * STOP now without issuing another RD or WR? 464 */ 465 if (rcount > (u_char)last) 466 rcount = (u_char)last; 467 op |= SMB_TRANS_NOCNT; 468 } 469 } 470 error = 0; 471 done: 472 /* XXX wait for xmit buffer to become empty */ 473 last = reg_read(sc, IG4_REG_TX_ABRT_SOURCE); 474 475 return error; 476 } 477 478 /* 479 * SMBUS API FUNCTIONS 480 * 481 * Called from ig4iic_pci_attach/detach() 482 */ 483 int 484 ig4iic_attach(ig4iic_softc_t *sc) 485 { 486 int error; 487 uint32_t v; 488 489 lockmgr(&sc->lk, LK_EXCLUSIVE); 490 491 if (sc->version == IG4_ATOM) { 492 v = reg_read(sc, IG4_REG_COMP_TYPE); 493 kprintf("type %08x", v); 494 } 495 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 496 v = reg_read(sc, IG4_REG_COMP_PARAM1); 497 kprintf(" params %08x", v); 498 v = reg_read(sc, IG4_REG_GENERAL); 499 kprintf(" general %08x", v); 500 /* 501 * The content of IG4_REG_GENERAL is different for each 502 * controller version. 503 */ 504 if (sc->version == IG4_HASWELL && 505 (v & IG4_GENERAL_SWMODE) == 0) { 506 v |= IG4_GENERAL_SWMODE; 507 reg_write(sc, IG4_REG_GENERAL, v); 508 v = reg_read(sc, IG4_REG_GENERAL); 509 kprintf(" (updated %08x)", v); 510 } 511 } 512 513 if (sc->version == IG4_HASWELL) { 514 v = reg_read(sc, IG4_REG_SW_LTR_VALUE); 515 kprintf(" swltr %08x", v); 516 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE); 517 kprintf(" autoltr %08x", v); 518 } else if (sc->version == IG4_SKYLAKE) { 519 v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE); 520 kprintf(" activeltr %08x", v); 521 v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE); 522 kprintf(" idleltr %08x", v); 523 } 524 525 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 526 v = reg_read(sc, IG4_REG_COMP_VER); 527 kprintf(" version %08x\n", v); 528 if (v != IG4_COMP_VER) { 529 error = ENXIO; 530 goto done; 531 } 532 } 533 #if 1 534 v = reg_read(sc, IG4_REG_SS_SCL_HCNT); 535 kprintf("SS_SCL_HCNT=%08x", v); 536 v = reg_read(sc, IG4_REG_SS_SCL_LCNT); 537 kprintf(" LCNT=%08x", v); 538 v = reg_read(sc, IG4_REG_FS_SCL_HCNT); 539 kprintf(" FS_SCL_HCNT=%08x", v); 540 v = reg_read(sc, IG4_REG_FS_SCL_LCNT); 541 kprintf(" LCNT=%08x\n", v); 542 v = reg_read(sc, IG4_REG_SDA_HOLD); 543 kprintf("HOLD %08x\n", v); 544 545 v = reg_read(sc, IG4_REG_SS_SCL_HCNT); 546 reg_write(sc, IG4_REG_FS_SCL_HCNT, v); 547 v = reg_read(sc, IG4_REG_SS_SCL_LCNT); 548 reg_write(sc, IG4_REG_FS_SCL_LCNT, v); 549 #endif 550 /* 551 * Program based on a 25000 Hz clock. This is a bit of a 552 * hack (obviously). The defaults are 400 and 470 for standard 553 * and 60 and 130 for fast. The defaults for standard fail 554 * utterly (presumably cause an abort) because the clock time 555 * is ~18.8ms by default. This brings it down to ~4ms (for now). 556 */ 557 reg_write(sc, IG4_REG_SS_SCL_HCNT, 100); 558 reg_write(sc, IG4_REG_SS_SCL_LCNT, 125); 559 reg_write(sc, IG4_REG_FS_SCL_HCNT, 100); 560 reg_write(sc, IG4_REG_FS_SCL_LCNT, 125); 561 reg_write(sc, IG4_REG_SDA_HOLD, 1); 562 563 /* 564 * Use a threshold of 1 so we get interrupted on each character, 565 * allowing us to use lksleep() in our poll code. Not perfect 566 * but this is better than using DELAY() for receiving data. 567 */ 568 reg_write(sc, IG4_REG_RX_TL, 1); 569 570 reg_write(sc, IG4_REG_CTL, 571 IG4_CTL_MASTER | 572 IG4_CTL_SLAVE_DISABLE | 573 IG4_CTL_RESTARTEN | 574 IG4_CTL_SPEED_STD); 575 /* 576 * When ig4 is attached via ACPI, (child) devices should access the 577 * smbus via I2cSerialBus ACPI resources instead. 578 */ 579 if (strcmp("acpi", device_get_name(device_get_parent(sc->dev))) != 0) { 580 sc->smb = device_add_child(sc->dev, "smbus", -1); 581 if (sc->smb == NULL) { 582 device_printf(sc->dev, "smbus driver not found\n"); 583 error = ENXIO; 584 goto done; 585 } 586 } 587 588 sc->acpismb = device_add_child(sc->dev, "smbacpi", -1); 589 if (sc->acpismb == NULL) { 590 device_printf(sc->dev, "smbacpi driver not found\n"); 591 if (sc->smb == NULL) { 592 error = ENXIO; 593 goto done; 594 } 595 } 596 597 #if 0 598 /* 599 * Don't do this, it blows up the PCI config 600 */ 601 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 602 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW); 603 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW); 604 } else if (sc->version == IG4_SKYLAKE) { 605 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); 606 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); 607 } 608 #endif 609 610 /* 611 * Interrupt on STOP detect or receive character ready 612 */ 613 if (set_controller(sc, 0)) { 614 device_printf(sc->dev, "controller error during attach-1\n"); 615 error = ENXIO; 616 goto done; 617 } 618 if (set_controller(sc, IG4_I2C_ENABLE)) { 619 device_printf(sc->dev, "controller error during attach-2\n"); 620 error = ENXIO; 621 goto done; 622 } 623 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE, 624 ig4iic_intr, sc, &sc->intr_handle, NULL); 625 if (error) { 626 device_printf(sc->dev, 627 "Unable to setup irq: error %d\n", error); 628 goto done; 629 } 630 631 /* Attach us to the smbus */ 632 lockmgr(&sc->lk, LK_RELEASE); 633 error = bus_generic_attach(sc->dev); 634 lockmgr(&sc->lk, LK_EXCLUSIVE); 635 if (error) { 636 device_printf(sc->dev, 637 "failed to attach child: error %d\n", error); 638 goto done; 639 } 640 sc->generic_attached = 1; 641 642 done: 643 lockmgr(&sc->lk, LK_RELEASE); 644 return error; 645 } 646 647 int 648 ig4iic_detach(ig4iic_softc_t *sc) 649 { 650 int error; 651 652 lockmgr(&sc->lk, LK_EXCLUSIVE); 653 654 reg_write(sc, IG4_REG_INTR_MASK, 0); 655 set_controller(sc, 0); 656 657 if (sc->generic_attached) { 658 error = bus_generic_detach(sc->dev); 659 if (error) 660 goto done; 661 sc->generic_attached = 0; 662 } 663 if (sc->smb) { 664 device_delete_child(sc->dev, sc->smb); 665 sc->smb = NULL; 666 } 667 if (sc->acpismb) { 668 device_delete_child(sc->dev, sc->acpismb); 669 sc->acpismb = NULL; 670 } 671 if (sc->intr_handle) { 672 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle); 673 sc->intr_handle = NULL; 674 } 675 676 error = 0; 677 done: 678 lockmgr(&sc->lk, LK_RELEASE); 679 return error; 680 } 681 682 int 683 ig4iic_smb_callback(device_t dev, int index, void *data) 684 { 685 ig4iic_softc_t *sc = device_get_softc(dev); 686 int error; 687 688 lockmgr(&sc->lk, LK_EXCLUSIVE); 689 690 switch (index) { 691 case SMB_REQUEST_BUS: 692 error = 0; 693 break; 694 case SMB_RELEASE_BUS: 695 error = 0; 696 break; 697 default: 698 error = SMB_EABORT; 699 break; 700 } 701 702 lockmgr(&sc->lk, LK_RELEASE); 703 704 return error; 705 } 706 707 /* 708 * Quick command. i.e. START + cmd + R/W + STOP and no data. It is 709 * unclear to me how I could implement this with the intel i2c controller 710 * because the controler sends STARTs and STOPs automatically with data. 711 */ 712 int 713 ig4iic_smb_quick(device_t dev, u_char slave, int how) 714 { 715 ig4iic_softc_t *sc = device_get_softc(dev); 716 int error; 717 718 lockmgr(&sc->lk, LK_EXCLUSIVE); 719 720 switch (how) { 721 case SMB_QREAD: 722 error = SMB_ENOTSUPP; 723 break; 724 case SMB_QWRITE: 725 error = SMB_ENOTSUPP; 726 break; 727 default: 728 error = SMB_ENOTSUPP; 729 break; 730 } 731 lockmgr(&sc->lk, LK_RELEASE); 732 733 return error; 734 } 735 736 /* 737 * Incremental send byte without stop (?). It is unclear why the slave 738 * address is specified if this presumably is used in combination with 739 * ig4iic_smb_quick(). 740 * 741 * (Also, how would this work anyway? Issue the last byte with writeb()?) 742 */ 743 int 744 ig4iic_smb_sendb(device_t dev, u_char slave, char byte) 745 { 746 ig4iic_softc_t *sc = device_get_softc(dev); 747 uint32_t cmd; 748 int error; 749 750 lockmgr(&sc->lk, LK_EXCLUSIVE); 751 752 set_slave_addr(sc, slave, 0); 753 cmd = byte; 754 if (wait_status(sc, IG4_STATUS_TX_NOTFULL) == 0) { 755 reg_write(sc, IG4_REG_DATA_CMD, cmd); 756 error = 0; 757 } else { 758 error = SMB_ETIMEOUT; 759 } 760 761 lockmgr(&sc->lk, LK_RELEASE); 762 return error; 763 } 764 765 /* 766 * Incremental receive byte without stop (?). It is unclear why the slave 767 * address is specified if this presumably is used in combination with 768 * ig4iic_smb_quick(). 769 */ 770 int 771 ig4iic_smb_recvb(device_t dev, u_char slave, char *byte) 772 { 773 ig4iic_softc_t *sc = device_get_softc(dev); 774 int error; 775 776 lockmgr(&sc->lk, LK_EXCLUSIVE); 777 778 set_slave_addr(sc, slave, 0); 779 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD); 780 if (wait_status(sc, IG4_STATUS_RX_NOTEMPTY) == 0) { 781 *byte = data_read(sc); 782 error = 0; 783 } else { 784 *byte = 0; 785 error = SMB_ETIMEOUT; 786 } 787 788 lockmgr(&sc->lk, LK_RELEASE); 789 return error; 790 } 791 792 /* 793 * Write command and single byte in transaction. 794 */ 795 int 796 ig4iic_smb_writeb(device_t dev, u_char slave, char cmd, char byte) 797 { 798 ig4iic_softc_t *sc = device_get_softc(dev); 799 int error; 800 801 lockmgr(&sc->lk, LK_EXCLUSIVE); 802 803 set_slave_addr(sc, slave, 0); 804 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 805 &byte, 1, NULL, 0, NULL); 806 807 lockmgr(&sc->lk, LK_RELEASE); 808 return error; 809 } 810 811 /* 812 * Write command and single word in transaction. 813 */ 814 int 815 ig4iic_smb_writew(device_t dev, u_char slave, char cmd, short word) 816 { 817 ig4iic_softc_t *sc = device_get_softc(dev); 818 char buf[2]; 819 int error; 820 821 lockmgr(&sc->lk, LK_EXCLUSIVE); 822 823 set_slave_addr(sc, slave, 0); 824 buf[0] = word & 0xFF; 825 buf[1] = word >> 8; 826 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 827 buf, 2, NULL, 0, NULL); 828 829 lockmgr(&sc->lk, LK_RELEASE); 830 return error; 831 } 832 833 /* 834 * write command and read single byte in transaction. 835 */ 836 int 837 ig4iic_smb_readb(device_t dev, u_char slave, char cmd, char *byte) 838 { 839 ig4iic_softc_t *sc = device_get_softc(dev); 840 int error; 841 842 lockmgr(&sc->lk, LK_EXCLUSIVE); 843 844 set_slave_addr(sc, slave, 0); 845 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 846 NULL, 0, byte, 1, NULL); 847 848 lockmgr(&sc->lk, LK_RELEASE); 849 return error; 850 } 851 852 /* 853 * write command and read word in transaction. 854 */ 855 int 856 ig4iic_smb_readw(device_t dev, u_char slave, char cmd, short *word) 857 { 858 ig4iic_softc_t *sc = device_get_softc(dev); 859 char buf[2]; 860 int error; 861 862 lockmgr(&sc->lk, LK_EXCLUSIVE); 863 864 set_slave_addr(sc, slave, 0); 865 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 866 NULL, 0, buf, 2, NULL)) == 0) { 867 *word = (u_char)buf[0] | ((u_char)buf[1] << 8); 868 } 869 870 lockmgr(&sc->lk, LK_RELEASE); 871 return error; 872 } 873 874 /* 875 * write command and word and read word in transaction 876 */ 877 int 878 ig4iic_smb_pcall(device_t dev, u_char slave, char cmd, 879 short sdata, short *rdata) 880 { 881 ig4iic_softc_t *sc = device_get_softc(dev); 882 char rbuf[2]; 883 char wbuf[2]; 884 int error; 885 886 lockmgr(&sc->lk, LK_EXCLUSIVE); 887 888 set_slave_addr(sc, slave, 0); 889 wbuf[0] = sdata & 0xFF; 890 wbuf[1] = sdata >> 8; 891 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 892 wbuf, 2, rbuf, 2, NULL)) == 0) { 893 *rdata = (u_char)rbuf[0] | ((u_char)rbuf[1] << 8); 894 } 895 896 lockmgr(&sc->lk, LK_RELEASE); 897 return error; 898 } 899 900 int 901 ig4iic_smb_bwrite(device_t dev, u_char slave, char cmd, 902 u_char wcount, char *buf) 903 { 904 ig4iic_softc_t *sc = device_get_softc(dev); 905 int error; 906 907 lockmgr(&sc->lk, LK_EXCLUSIVE); 908 909 set_slave_addr(sc, slave, 0); 910 error = smb_transaction(sc, cmd, 0, 911 buf, wcount, NULL, 0, NULL); 912 913 lockmgr(&sc->lk, LK_RELEASE); 914 return error; 915 } 916 917 int 918 ig4iic_smb_bread(device_t dev, u_char slave, char cmd, 919 u_char *countp_char, char *buf) 920 { 921 ig4iic_softc_t *sc = device_get_softc(dev); 922 int rcount = *countp_char; 923 int error; 924 925 lockmgr(&sc->lk, LK_EXCLUSIVE); 926 927 set_slave_addr(sc, slave, 0); 928 error = smb_transaction(sc, cmd, 0, 929 NULL, 0, buf, rcount, &rcount); 930 *countp_char = rcount; 931 932 lockmgr(&sc->lk, LK_RELEASE); 933 return error; 934 } 935 936 int 937 ig4iic_smb_trans(device_t dev, int slave, char cmd, int op, 938 char *wbuf, int wcount, char *rbuf, int rcount, 939 int *actualp) 940 { 941 ig4iic_softc_t *sc = device_get_softc(dev); 942 int error; 943 944 lockmgr(&sc->lk, LK_EXCLUSIVE); 945 946 set_slave_addr(sc, slave, op); 947 error = smb_transaction(sc, cmd, op, 948 wbuf, wcount, rbuf, rcount, actualp); 949 950 lockmgr(&sc->lk, LK_RELEASE); 951 return error; 952 } 953 954 /* 955 * Interrupt Operation 956 */ 957 static 958 void 959 ig4iic_intr(void *cookie) 960 { 961 ig4iic_softc_t *sc = cookie; 962 uint32_t status; 963 964 lockmgr(&sc->lk, LK_EXCLUSIVE); 965 /* reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET);*/ 966 reg_read(sc, IG4_REG_CLR_INTR); 967 status = reg_read(sc, IG4_REG_I2C_STA); 968 while (status & IG4_STATUS_RX_NOTEMPTY) { 969 sc->rbuf[sc->rnext & IG4_RBUFMASK] = 970 (uint8_t)reg_read(sc, IG4_REG_DATA_CMD); 971 ++sc->rnext; 972 status = reg_read(sc, IG4_REG_I2C_STA); 973 } 974 wakeup(sc); 975 lockmgr(&sc->lk, LK_RELEASE); 976 } 977 978 #define REGDUMP(sc, reg) \ 979 device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg)) 980 981 static 982 void 983 ig4iic_dump(ig4iic_softc_t *sc) 984 { 985 device_printf(sc->dev, "ig4iic register dump:\n"); 986 REGDUMP(sc, IG4_REG_CTL); 987 REGDUMP(sc, IG4_REG_TAR_ADD); 988 REGDUMP(sc, IG4_REG_SS_SCL_HCNT); 989 REGDUMP(sc, IG4_REG_SS_SCL_LCNT); 990 REGDUMP(sc, IG4_REG_FS_SCL_HCNT); 991 REGDUMP(sc, IG4_REG_FS_SCL_LCNT); 992 REGDUMP(sc, IG4_REG_INTR_STAT); 993 REGDUMP(sc, IG4_REG_INTR_MASK); 994 REGDUMP(sc, IG4_REG_RAW_INTR_STAT); 995 REGDUMP(sc, IG4_REG_RX_TL); 996 REGDUMP(sc, IG4_REG_TX_TL); 997 REGDUMP(sc, IG4_REG_I2C_EN); 998 REGDUMP(sc, IG4_REG_I2C_STA); 999 REGDUMP(sc, IG4_REG_TXFLR); 1000 REGDUMP(sc, IG4_REG_RXFLR); 1001 REGDUMP(sc, IG4_REG_SDA_HOLD); 1002 REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE); 1003 REGDUMP(sc, IG4_REG_SLV_DATA_NACK); 1004 REGDUMP(sc, IG4_REG_DMA_CTRL); 1005 REGDUMP(sc, IG4_REG_DMA_TDLR); 1006 REGDUMP(sc, IG4_REG_DMA_RDLR); 1007 REGDUMP(sc, IG4_REG_SDA_SETUP); 1008 REGDUMP(sc, IG4_REG_ENABLE_STATUS); 1009 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 1010 REGDUMP(sc, IG4_REG_COMP_PARAM1); 1011 REGDUMP(sc, IG4_REG_COMP_VER); 1012 } 1013 if (sc->version == IG4_ATOM) { 1014 REGDUMP(sc, IG4_REG_COMP_TYPE); 1015 REGDUMP(sc, IG4_REG_CLK_PARMS); 1016 } 1017 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 1018 REGDUMP(sc, IG4_REG_RESETS_HSW); 1019 REGDUMP(sc, IG4_REG_GENERAL); 1020 } else if (sc->version == IG4_SKYLAKE) { 1021 REGDUMP(sc, IG4_REG_RESETS_SKL); 1022 } 1023 if (sc->version == IG4_HASWELL) { 1024 REGDUMP(sc, IG4_REG_SW_LTR_VALUE); 1025 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE); 1026 } else if (sc->version == IG4_SKYLAKE) { 1027 REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE); 1028 REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE); 1029 } 1030 } 1031 #undef REGDUMP 1032 1033 DRIVER_MODULE(smbus, ig4iic, smbus_driver, smbus_devclass, NULL, NULL); 1034