1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 /* 35 * Intel 4th generation mobile cpus integrated I2C device, smbus driver. 36 * 37 * See ig4_reg.h for datasheet reference and notes. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/errno.h> 45 #include <sys/serialize.h> 46 #include <sys/syslog.h> 47 #include <sys/bus.h> 48 #include <sys/sysctl.h> 49 50 #include <sys/rman.h> 51 52 #include <bus/pci/pcivar.h> 53 #include <bus/pci/pcireg.h> 54 #include <bus/smbus/smbconf.h> 55 56 #include "smbus_if.h" 57 58 #include "ig4_reg.h" 59 #include "ig4_var.h" 60 61 #define TRANS_NORMAL 1 62 #define TRANS_PCALL 2 63 #define TRANS_BLOCK 3 64 65 static void ig4iic_intr(void *cookie); 66 static void ig4iic_dump(ig4iic_softc_t *sc); 67 68 static int ig4_dump; 69 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLTYPE_INT | CTLFLAG_RW, 70 &ig4_dump, 0, ""); 71 72 /* 73 * Low-level inline support functions 74 */ 75 static __inline 76 void 77 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value) 78 { 79 bus_space_write_4(sc->regs_t, sc->regs_h, reg, value); 80 bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4, 81 BUS_SPACE_BARRIER_WRITE); 82 } 83 84 static __inline 85 uint32_t 86 reg_read(ig4iic_softc_t *sc, uint32_t reg) 87 { 88 uint32_t value; 89 90 bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4, 91 BUS_SPACE_BARRIER_READ); 92 value = bus_space_read_4(sc->regs_t, sc->regs_h, reg); 93 return value; 94 } 95 96 static 97 void 98 set_intr_mask(ig4iic_softc_t *sc, uint32_t val) 99 { 100 if (sc->intr_mask != val) { 101 reg_write(sc, IG4_REG_INTR_MASK, val); 102 sc->intr_mask = val; 103 } 104 } 105 106 /* 107 * Enable or disable the controller and wait for the controller to acknowledge 108 * the state change. 109 */ 110 static 111 int 112 set_controller(ig4iic_softc_t *sc, uint32_t ctl) 113 { 114 int retry; 115 int error; 116 uint32_t v; 117 118 set_intr_mask(sc, 0); 119 if (ctl & IG4_I2C_ENABLE) 120 reg_read(sc, IG4_REG_CLR_INTR); 121 122 reg_write(sc, IG4_REG_I2C_EN, ctl); 123 error = SMB_ETIMEOUT; 124 125 for (retry = 100; retry > 0; --retry) { 126 v = reg_read(sc, IG4_REG_ENABLE_STATUS); 127 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) { 128 error = 0; 129 break; 130 } 131 tsleep(sc, 0, "i2cslv", 1); 132 } 133 return error; 134 } 135 136 /* 137 * Wait up to 25ms for the requested status using a 25uS polling loop. 138 */ 139 static 140 int 141 wait_status(ig4iic_softc_t *sc, uint32_t status) 142 { 143 uint32_t v; 144 int error; 145 int txlvl = -1; 146 sysclock_t count; 147 sysclock_t limit; 148 149 error = SMB_ETIMEOUT; 150 count = sys_cputimer->count(); 151 limit = sys_cputimer->freq / 40; 152 153 for (;;) { 154 /* 155 * Check requested status 156 */ 157 v = reg_read(sc, IG4_REG_I2C_STA); 158 if (v & status) { 159 error = 0; 160 break; 161 } 162 163 /* 164 * When waiting for receive data break-out if the interrupt 165 * loaded data into the FIFO. 166 */ 167 if (status & IG4_STATUS_RX_NOTEMPTY) { 168 if (sc->rpos != sc->rnext) { 169 error = 0; 170 break; 171 } 172 } 173 174 /* 175 * When waiting for the transmit FIFO to become empty, 176 * reset the timeout if we see a change in the transmit 177 * FIFO level as progress is being made. 178 */ 179 if (status & IG4_STATUS_TX_EMPTY) { 180 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK; 181 if (txlvl != v) { 182 txlvl = v; 183 count = sys_cputimer->count(); 184 } 185 } 186 187 /* 188 * Stop if we've run out of time. 189 */ 190 if (sys_cputimer->count() - count > limit) 191 break; 192 193 /* 194 * When waiting for receive data let the interrupt do its 195 * work, otherwise poll with the serializer held. 196 */ 197 if (status & IG4_STATUS_RX_NOTEMPTY) { 198 set_intr_mask(sc, IG4_INTR_STOP_DET | IG4_INTR_RX_FULL); 199 zsleep(sc, &sc->slz, 0, "i2cwait", (hz + 99) / 100); 200 set_intr_mask(sc, 0); 201 } else { 202 DELAY(25); 203 } 204 } 205 206 return error; 207 } 208 209 /* 210 * Read I2C data. The data might have already been read by 211 * the interrupt code, otherwise it is sitting in the data 212 * register. 213 */ 214 static 215 uint8_t 216 data_read(ig4iic_softc_t *sc) 217 { 218 uint8_t c; 219 220 if (sc->rpos == sc->rnext) { 221 c = (uint8_t)reg_read(sc, IG4_REG_DATA_CMD); 222 } else { 223 c = sc->rbuf[sc->rpos & IG4_RBUFMASK]; 224 ++sc->rpos; 225 } 226 return c; 227 } 228 229 /* 230 * Set the slave address. The controller must be disabled when 231 * changing the address. 232 * 233 * This operation does not issue anything to the I2C bus but sets 234 * the target address for when the controller later issues a START. 235 */ 236 static 237 void 238 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave, int trans_op) 239 { 240 uint32_t tar; 241 uint32_t ctl; 242 int use_10bit; 243 244 use_10bit = sc->use_10bit; 245 if (trans_op & SMB_TRANS_7BIT) 246 use_10bit = 0; 247 if (trans_op & SMB_TRANS_10BIT) 248 use_10bit = 1; 249 250 if (sc->slave_valid && sc->last_slave == slave && 251 sc->use_10bit == use_10bit) { 252 return; 253 } 254 sc->use_10bit = use_10bit; 255 256 /* 257 * Wait for TXFIFO to drain before disabling the controller. 258 * 259 * If a write message has not been completed it's really a 260 * programming error, but for now in that case issue an extra 261 * byte + STOP. 262 * 263 * If a read message has not been completed it's also a programming 264 * error, for now just ignore it. 265 */ 266 wait_status(sc, IG4_STATUS_TX_NOTFULL); 267 if (sc->write_started) { 268 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP); 269 sc->write_started = 0; 270 } 271 if (sc->read_started) 272 sc->read_started = 0; 273 wait_status(sc, IG4_STATUS_TX_EMPTY); 274 275 set_controller(sc, 0); 276 ctl = reg_read(sc, IG4_REG_CTL); 277 ctl &= ~IG4_CTL_10BIT; 278 ctl |= IG4_CTL_RESTARTEN; 279 280 tar = slave; 281 if (sc->use_10bit) { 282 tar |= IG4_TAR_10BIT; 283 ctl |= IG4_CTL_10BIT; 284 } 285 reg_write(sc, IG4_REG_CTL, ctl); 286 reg_write(sc, IG4_REG_TAR_ADD, tar); 287 set_controller(sc, IG4_I2C_ENABLE); 288 sc->slave_valid = 1; 289 sc->last_slave = slave; 290 } 291 292 /* 293 * Issue START with byte command, possible count, and a variable length 294 * read or write buffer, then possible turn-around read. The read also 295 * has a possible count received. 296 * 297 * For SMBUS - 298 * 299 * Quick: START+ADDR+RD/WR STOP 300 * 301 * Normal: START+ADDR+WR CMD DATA..DATA STOP 302 * 303 * START+ADDR+RD CMD 304 * RESTART+ADDR RDATA..RDATA STOP 305 * (can also be used for I2C transactions) 306 * 307 * Process Call: START+ADDR+WR CMD DATAL DATAH 308 * RESTART+ADDR+RD RDATAL RDATAH STOP 309 * 310 * Block: START+ADDR+RD CMD 311 * RESTART+ADDR+RD RCOUNT DATA... STOP 312 * 313 * START+ADDR+WR CMD 314 * RESTART+ADDR+WR WCOUNT DATA... STOP 315 * 316 * For I2C - basically, no *COUNT fields, possibly no *CMD field. If the 317 * sender needs to issue a 2-byte command it will incorporate it 318 * into the write buffer and also set NOCMD. 319 * 320 * Generally speaking, the START+ADDR / RESTART+ADDR is handled automatically 321 * by the controller at the beginning of a command sequence or on a data 322 * direction turn-around, and we only need to tell it when to issue the STOP. 323 */ 324 static int 325 smb_transaction(ig4iic_softc_t *sc, char cmd, int op, 326 char *wbuf, int wcount, char *rbuf, int rcount, int *actualp) 327 { 328 int error; 329 int unit; 330 uint32_t last; 331 332 /* 333 * Debugging - dump registers 334 */ 335 if (ig4_dump) { 336 unit = device_get_unit(sc->dev); 337 if (ig4_dump & (1 << unit)) { 338 ig4_dump &= ~(1 << unit); 339 ig4iic_dump(sc); 340 } 341 } 342 343 /* 344 * Issue START or RESTART with next data byte, clear any previous 345 * abort condition that may have been holding the txfifo in reset. 346 */ 347 last = IG4_DATA_RESTART; 348 reg_read(sc, IG4_REG_CLR_TX_ABORT); 349 if (actualp) 350 *actualp = 0; 351 352 /* 353 * Issue command if not told otherwise (smbus). 354 */ 355 if ((op & SMB_TRANS_NOCMD) == 0) { 356 error = wait_status(sc, IG4_STATUS_TX_NOTFULL); 357 if (error) 358 goto done; 359 last |= (u_char)cmd; 360 if (wcount == 0 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0) 361 last |= IG4_DATA_STOP; 362 reg_write(sc, IG4_REG_DATA_CMD, last); 363 last = 0; 364 } 365 366 /* 367 * Clean out any previously received data. 368 */ 369 if (sc->rpos != sc->rnext && 370 (op & SMB_TRANS_NOREPORT) == 0) { 371 device_printf(sc->dev, 372 "discarding %d bytes of spurious data\n", 373 sc->rnext - sc->rpos); 374 } 375 sc->rpos = 0; 376 sc->rnext = 0; 377 378 /* 379 * If writing and not told otherwise, issue the write count (smbus). 380 */ 381 if (wcount && (op & SMB_TRANS_NOCNT) == 0) { 382 error = wait_status(sc, IG4_STATUS_TX_NOTFULL); 383 if (error) 384 goto done; 385 last |= (u_char)cmd; 386 reg_write(sc, IG4_REG_DATA_CMD, last); 387 last = 0; 388 } 389 390 /* 391 * Bulk write (i2c) 392 */ 393 while (wcount) { 394 error = wait_status(sc, IG4_STATUS_TX_NOTFULL); 395 if (error) 396 goto done; 397 last |= (u_char)*wbuf; 398 if (wcount == 1 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0) 399 last |= IG4_DATA_STOP; 400 reg_write(sc, IG4_REG_DATA_CMD, last); 401 --wcount; 402 ++wbuf; 403 last = 0; 404 } 405 406 /* 407 * Issue reads to xmit FIFO (strange, I know) to tell the controller 408 * to clock in data. At the moment just issue one read ahead to 409 * pipeline the incoming data. 410 * 411 * NOTE: In the case of NOCMD and wcount == 0 we still issue a 412 * RESTART here, even if the data direction has not changed 413 * from the previous CHAINing call. This we force the RESTART. 414 * (A new START is issued automatically by the controller in 415 * the other nominal cases such as a data direction change or 416 * a previous STOP was issued). 417 * 418 * If this will be the last byte read we must also issue the STOP 419 * at the end of the read. 420 */ 421 if (rcount) { 422 last = IG4_DATA_RESTART | IG4_DATA_COMMAND_RD; 423 if (rcount == 1 && 424 (op & (SMB_TRANS_NOSTOP | SMB_TRANS_NOCNT)) == 425 SMB_TRANS_NOCNT) { 426 last |= IG4_DATA_STOP; 427 } 428 reg_write(sc, IG4_REG_DATA_CMD, last); 429 last = IG4_DATA_COMMAND_RD; 430 } 431 432 /* 433 * Bulk read (i2c) and count field handling (smbus) 434 */ 435 while (rcount) { 436 /* 437 * Maintain a pipeline by queueing the allowance for the next 438 * read before waiting for the current read. 439 */ 440 if (rcount > 1) { 441 if (op & SMB_TRANS_NOCNT) 442 last = (rcount == 2) ? IG4_DATA_STOP : 0; 443 else 444 last = 0; 445 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD | 446 last); 447 } 448 error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY); 449 if (error) { 450 if ((op & SMB_TRANS_NOREPORT) == 0) { 451 device_printf(sc->dev, 452 "rx timeout addr 0x%02x\n", 453 sc->last_slave); 454 } 455 goto done; 456 } 457 last = data_read(sc); 458 459 if (op & SMB_TRANS_NOCNT) { 460 *rbuf = (u_char)last; 461 ++rbuf; 462 --rcount; 463 if (actualp) 464 ++*actualp; 465 } else { 466 /* 467 * Handle count field (smbus), which is not part of 468 * the rcount'ed buffer. The first read data in a 469 * bulk transfer is the count. 470 * 471 * XXX if rcount is loaded as 0 how do I generate a 472 * STOP now without issuing another RD or WR? 473 */ 474 if (rcount > (u_char)last) 475 rcount = (u_char)last; 476 op |= SMB_TRANS_NOCNT; 477 } 478 } 479 error = 0; 480 done: 481 set_intr_mask(sc, 0); 482 /* XXX wait for xmit buffer to become empty */ 483 last = reg_read(sc, IG4_REG_TX_ABRT_SOURCE); 484 485 return error; 486 } 487 488 /* 489 * SMBUS API FUNCTIONS 490 * 491 * Called from ig4iic_pci_attach/detach() 492 */ 493 int 494 ig4iic_attach(ig4iic_softc_t *sc) 495 { 496 int error; 497 uint32_t v; 498 499 device_printf(sc->dev, "version %d ", sc->version); 500 if (sc->version == IG4_ATOM) { 501 v = reg_read(sc, IG4_REG_COMP_TYPE); 502 kprintf("type %08x", v); 503 } 504 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 505 v = reg_read(sc, IG4_REG_COMP_PARAM1); 506 kprintf(" params %08x", v); 507 v = reg_read(sc, IG4_REG_GENERAL); 508 kprintf(" general %08x", v); 509 /* 510 * The content of IG4_REG_GENERAL is different for each 511 * controller version. 512 */ 513 if (sc->version == IG4_HASWELL && 514 (v & IG4_GENERAL_SWMODE) == 0) { 515 v |= IG4_GENERAL_SWMODE; 516 reg_write(sc, IG4_REG_GENERAL, v); 517 v = reg_read(sc, IG4_REG_GENERAL); 518 kprintf(" (updated %08x)", v); 519 } 520 } 521 522 if (sc->version == IG4_HASWELL) { 523 v = reg_read(sc, IG4_REG_SW_LTR_VALUE); 524 kprintf(" swltr %08x", v); 525 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE); 526 kprintf(" autoltr %08x", v); 527 } else if (sc->version >= IG4_SKYLAKE) { 528 v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE); 529 kprintf(" activeltr %08x", v); 530 v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE); 531 kprintf(" idleltr %08x", v); 532 } 533 534 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 535 v = reg_read(sc, IG4_REG_COMP_VER); 536 kprintf(" comp_version %08x\n", v); 537 if (v < IG4_COMP_VER) { 538 device_printf(sc->dev, "Compat version too low\n"); 539 error = ENXIO; 540 goto done; 541 } 542 } else { 543 kprintf("\n"); 544 } 545 if (bootverbose) { 546 device_printf(sc->dev, "debug -"); 547 v = reg_read(sc, IG4_REG_SS_SCL_HCNT); 548 kprintf(" SS_SCL_HCNT=%08x", v); 549 v = reg_read(sc, IG4_REG_SS_SCL_LCNT); 550 kprintf(" LCNT=%08x", v); 551 v = reg_read(sc, IG4_REG_FS_SCL_HCNT); 552 kprintf(" FS_SCL_HCNT=%08x", v); 553 v = reg_read(sc, IG4_REG_FS_SCL_LCNT); 554 kprintf(" LCNT=%08x", v); 555 v = reg_read(sc, IG4_REG_SDA_HOLD); 556 kprintf(" HOLD=%08x\n", v); 557 } 558 #if 1 559 v = reg_read(sc, IG4_REG_SS_SCL_HCNT); 560 reg_write(sc, IG4_REG_FS_SCL_HCNT, v); 561 v = reg_read(sc, IG4_REG_SS_SCL_LCNT); 562 reg_write(sc, IG4_REG_FS_SCL_LCNT, v); 563 #endif 564 565 reg_read(sc, IG4_REG_CLR_INTR); 566 reg_write(sc, IG4_REG_INTR_MASK, 0); 567 sc->intr_mask = 0; 568 569 /* 570 * Program based on a 25000 Hz clock. This is a bit of a 571 * hack (obviously). The defaults are 400 and 470 for standard 572 * and 60 and 130 for fast. The defaults for standard fail 573 * utterly (presumably cause an abort) because the clock time 574 * is ~18.8ms by default. This brings it down to ~4ms (for now). 575 */ 576 reg_write(sc, IG4_REG_SS_SCL_HCNT, 100); 577 reg_write(sc, IG4_REG_SS_SCL_LCNT, 125); 578 reg_write(sc, IG4_REG_FS_SCL_HCNT, 100); 579 reg_write(sc, IG4_REG_FS_SCL_LCNT, 125); 580 reg_write(sc, IG4_REG_SDA_HOLD, 1); 581 582 /* 583 * Use a threshold of 1 so we get interrupted on each character, 584 * allowing us to use lksleep() in our poll code. Not perfect 585 * but this is better than using DELAY() for receiving data. 586 */ 587 reg_write(sc, IG4_REG_RX_TL, 0); 588 589 reg_write(sc, IG4_REG_CTL, 590 IG4_CTL_MASTER | 591 IG4_CTL_SLAVE_DISABLE | 592 IG4_CTL_RESTARTEN | 593 IG4_CTL_SPEED_STD); 594 /* 595 * When ig4 is attached via ACPI, (child) devices should access the 596 * smbus via I2cSerialBus ACPI resources instead. 597 */ 598 if (strcmp("acpi", device_get_name(device_get_parent(sc->dev))) != 0) { 599 sc->smb = device_add_child(sc->dev, "smbus", -1); 600 if (sc->smb == NULL) { 601 device_printf(sc->dev, "smbus driver not found\n"); 602 error = ENXIO; 603 goto done; 604 } 605 } 606 607 sc->acpismb = device_add_child(sc->dev, "smbacpi", -1); 608 if (sc->acpismb == NULL) { 609 device_printf(sc->dev, "smbacpi driver not found\n"); 610 if (sc->smb == NULL) { 611 error = ENXIO; 612 goto done; 613 } 614 } 615 616 #if 0 617 /* 618 * Don't do this, it blows up the PCI config 619 */ 620 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 621 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW); 622 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW); 623 } else if (sc->version >= IG4_SKYLAKE) { 624 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); 625 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); 626 } 627 #endif 628 629 /* 630 * Make sure that the I2C controller is at least somewhat functional. 631 */ 632 if (set_controller(sc, 0)) { 633 device_printf(sc->dev, "controller error during attach-1\n"); 634 error = ENXIO; 635 goto done; 636 } 637 if (set_controller(sc, IG4_I2C_ENABLE)) { 638 device_printf(sc->dev, "controller error during attach-2\n"); 639 error = ENXIO; 640 goto done; 641 } 642 if (set_controller(sc, 0)) { 643 device_printf(sc->dev, "controller error during attach-3\n"); 644 error = ENXIO; 645 goto done; 646 } 647 648 lwkt_serialize_enter(&sc->slz); 649 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE, 650 ig4iic_intr, sc, &sc->intr_handle, &sc->slz); 651 if (error) { 652 device_printf(sc->dev, 653 "Unable to setup irq: error %d\n", error); 654 goto done; 655 } 656 657 /* Attach us to the smbus */ 658 lwkt_serialize_exit(&sc->slz); 659 error = bus_generic_attach(sc->dev); 660 if (error) { 661 device_printf(sc->dev, 662 "failed to attach child: error %d\n", error); 663 goto done; 664 } 665 lwkt_serialize_enter(&sc->slz); 666 sc->generic_attached = 1; 667 lwkt_serialize_exit(&sc->slz); 668 669 done: 670 return error; 671 } 672 673 int 674 ig4iic_detach(ig4iic_softc_t *sc) 675 { 676 int error; 677 678 lwkt_serialize_enter(&sc->slz); 679 680 reg_write(sc, IG4_REG_INTR_MASK, 0); 681 set_controller(sc, 0); 682 683 if (sc->generic_attached) { 684 error = bus_generic_detach(sc->dev); 685 if (error) 686 goto done; 687 sc->generic_attached = 0; 688 } 689 if (sc->smb) { 690 device_delete_child(sc->dev, sc->smb); 691 sc->smb = NULL; 692 } 693 if (sc->acpismb) { 694 device_delete_child(sc->dev, sc->acpismb); 695 sc->acpismb = NULL; 696 } 697 if (sc->intr_handle) { 698 lwkt_serialize_handler_disable(&sc->slz); 699 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle); 700 sc->intr_handle = NULL; 701 } 702 703 error = 0; 704 done: 705 lwkt_serialize_exit(&sc->slz); 706 return error; 707 } 708 709 int 710 ig4iic_smb_callback(device_t dev, int index, void *data) 711 { 712 ig4iic_softc_t *sc = device_get_softc(dev); 713 int error; 714 715 lwkt_serialize_enter(&sc->slz); 716 717 switch (index) { 718 case SMB_REQUEST_BUS: 719 error = 0; 720 break; 721 case SMB_RELEASE_BUS: 722 error = 0; 723 break; 724 default: 725 error = SMB_EABORT; 726 break; 727 } 728 729 lwkt_serialize_exit(&sc->slz); 730 return error; 731 } 732 733 /* 734 * Quick command. i.e. START + cmd + R/W + STOP and no data. It is 735 * unclear to me how I could implement this with the intel i2c controller 736 * because the controler sends STARTs and STOPs automatically with data. 737 */ 738 int 739 ig4iic_smb_quick(device_t dev, u_char slave, int how) 740 { 741 ig4iic_softc_t *sc = device_get_softc(dev); 742 int error; 743 744 lwkt_serialize_enter(&sc->slz); 745 746 switch (how) { 747 case SMB_QREAD: 748 error = SMB_ENOTSUPP; 749 break; 750 case SMB_QWRITE: 751 error = SMB_ENOTSUPP; 752 break; 753 default: 754 error = SMB_ENOTSUPP; 755 break; 756 } 757 758 lwkt_serialize_exit(&sc->slz); 759 return error; 760 } 761 762 /* 763 * Incremental send byte without stop (?). It is unclear why the slave 764 * address is specified if this presumably is used in combination with 765 * ig4iic_smb_quick(). 766 * 767 * (Also, how would this work anyway? Issue the last byte with writeb()?) 768 */ 769 int 770 ig4iic_smb_sendb(device_t dev, u_char slave, char byte) 771 { 772 ig4iic_softc_t *sc = device_get_softc(dev); 773 uint32_t cmd; 774 int error; 775 776 lwkt_serialize_enter(&sc->slz); 777 778 set_slave_addr(sc, slave, 0); 779 cmd = byte; 780 if (wait_status(sc, IG4_STATUS_TX_NOTFULL) == 0) { 781 reg_write(sc, IG4_REG_DATA_CMD, cmd); 782 error = 0; 783 } else { 784 error = SMB_ETIMEOUT; 785 } 786 787 lwkt_serialize_exit(&sc->slz); 788 return error; 789 } 790 791 /* 792 * Incremental receive byte without stop (?). It is unclear why the slave 793 * address is specified if this presumably is used in combination with 794 * ig4iic_smb_quick(). 795 */ 796 int 797 ig4iic_smb_recvb(device_t dev, u_char slave, char *byte) 798 { 799 ig4iic_softc_t *sc = device_get_softc(dev); 800 int error; 801 802 lwkt_serialize_enter(&sc->slz); 803 804 set_slave_addr(sc, slave, 0); 805 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD); 806 if (wait_status(sc, IG4_STATUS_RX_NOTEMPTY) == 0) { 807 *byte = data_read(sc); 808 error = 0; 809 } else { 810 *byte = 0; 811 error = SMB_ETIMEOUT; 812 } 813 814 lwkt_serialize_exit(&sc->slz); 815 return error; 816 } 817 818 /* 819 * Write command and single byte in transaction. 820 */ 821 int 822 ig4iic_smb_writeb(device_t dev, u_char slave, char cmd, char byte) 823 { 824 ig4iic_softc_t *sc = device_get_softc(dev); 825 int error; 826 827 lwkt_serialize_enter(&sc->slz); 828 829 set_slave_addr(sc, slave, 0); 830 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 831 &byte, 1, NULL, 0, NULL); 832 833 lwkt_serialize_exit(&sc->slz); 834 return error; 835 } 836 837 /* 838 * Write command and single word in transaction. 839 */ 840 int 841 ig4iic_smb_writew(device_t dev, u_char slave, char cmd, short word) 842 { 843 ig4iic_softc_t *sc = device_get_softc(dev); 844 char buf[2]; 845 int error; 846 847 lwkt_serialize_enter(&sc->slz); 848 849 set_slave_addr(sc, slave, 0); 850 buf[0] = word & 0xFF; 851 buf[1] = word >> 8; 852 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 853 buf, 2, NULL, 0, NULL); 854 855 lwkt_serialize_exit(&sc->slz); 856 return error; 857 } 858 859 /* 860 * write command and read single byte in transaction. 861 */ 862 int 863 ig4iic_smb_readb(device_t dev, u_char slave, char cmd, char *byte) 864 { 865 ig4iic_softc_t *sc = device_get_softc(dev); 866 int error; 867 868 lwkt_serialize_enter(&sc->slz); 869 870 set_slave_addr(sc, slave, 0); 871 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 872 NULL, 0, byte, 1, NULL); 873 874 lwkt_serialize_exit(&sc->slz); 875 return error; 876 } 877 878 /* 879 * write command and read word in transaction. 880 */ 881 int 882 ig4iic_smb_readw(device_t dev, u_char slave, char cmd, short *word) 883 { 884 ig4iic_softc_t *sc = device_get_softc(dev); 885 char buf[2]; 886 int error; 887 888 lwkt_serialize_enter(&sc->slz); 889 890 set_slave_addr(sc, slave, 0); 891 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 892 NULL, 0, buf, 2, NULL)) == 0) { 893 *word = (u_char)buf[0] | ((u_char)buf[1] << 8); 894 } 895 896 lwkt_serialize_exit(&sc->slz); 897 return error; 898 } 899 900 /* 901 * write command and word and read word in transaction 902 */ 903 int 904 ig4iic_smb_pcall(device_t dev, u_char slave, char cmd, 905 short sdata, short *rdata) 906 { 907 ig4iic_softc_t *sc = device_get_softc(dev); 908 char rbuf[2]; 909 char wbuf[2]; 910 int error; 911 912 lwkt_serialize_enter(&sc->slz); 913 914 set_slave_addr(sc, slave, 0); 915 wbuf[0] = sdata & 0xFF; 916 wbuf[1] = sdata >> 8; 917 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, 918 wbuf, 2, rbuf, 2, NULL)) == 0) { 919 *rdata = (u_char)rbuf[0] | ((u_char)rbuf[1] << 8); 920 } 921 922 lwkt_serialize_exit(&sc->slz); 923 return error; 924 } 925 926 int 927 ig4iic_smb_bwrite(device_t dev, u_char slave, char cmd, 928 u_char wcount, char *buf) 929 { 930 ig4iic_softc_t *sc = device_get_softc(dev); 931 int error; 932 933 lwkt_serialize_enter(&sc->slz); 934 935 set_slave_addr(sc, slave, 0); 936 error = smb_transaction(sc, cmd, 0, 937 buf, wcount, NULL, 0, NULL); 938 939 lwkt_serialize_exit(&sc->slz); 940 return error; 941 } 942 943 int 944 ig4iic_smb_bread(device_t dev, u_char slave, char cmd, 945 u_char *countp_char, char *buf) 946 { 947 ig4iic_softc_t *sc = device_get_softc(dev); 948 int rcount = *countp_char; 949 int error; 950 951 lwkt_serialize_enter(&sc->slz); 952 953 set_slave_addr(sc, slave, 0); 954 error = smb_transaction(sc, cmd, 0, 955 NULL, 0, buf, rcount, &rcount); 956 *countp_char = rcount; 957 958 lwkt_serialize_exit(&sc->slz); 959 return error; 960 } 961 962 int 963 ig4iic_smb_trans(device_t dev, int slave, char cmd, int op, 964 char *wbuf, int wcount, char *rbuf, int rcount, 965 int *actualp) 966 { 967 ig4iic_softc_t *sc = device_get_softc(dev); 968 int error; 969 970 lwkt_serialize_enter(&sc->slz); 971 972 set_slave_addr(sc, slave, op); 973 error = smb_transaction(sc, cmd, op, 974 wbuf, wcount, rbuf, rcount, actualp); 975 976 lwkt_serialize_exit(&sc->slz); 977 return error; 978 } 979 980 /* 981 * Interrupt Operation 982 */ 983 static 984 void 985 ig4iic_intr(void *cookie) 986 { 987 ig4iic_softc_t *sc = cookie; 988 uint32_t status; 989 990 set_intr_mask(sc, 0); 991 reg_read(sc, IG4_REG_CLR_INTR); 992 status = reg_read(sc, IG4_REG_I2C_STA); 993 while (status & IG4_STATUS_RX_NOTEMPTY) { 994 sc->rbuf[sc->rnext & IG4_RBUFMASK] = 995 (uint8_t)reg_read(sc, IG4_REG_DATA_CMD); 996 ++sc->rnext; 997 status = reg_read(sc, IG4_REG_I2C_STA); 998 } 999 wakeup(sc); 1000 } 1001 1002 #define REGDUMP(sc, reg) \ 1003 device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg)) 1004 1005 static 1006 void 1007 ig4iic_dump(ig4iic_softc_t *sc) 1008 { 1009 device_printf(sc->dev, "ig4iic register dump:\n"); 1010 REGDUMP(sc, IG4_REG_CTL); 1011 REGDUMP(sc, IG4_REG_TAR_ADD); 1012 REGDUMP(sc, IG4_REG_SS_SCL_HCNT); 1013 REGDUMP(sc, IG4_REG_SS_SCL_LCNT); 1014 REGDUMP(sc, IG4_REG_FS_SCL_HCNT); 1015 REGDUMP(sc, IG4_REG_FS_SCL_LCNT); 1016 REGDUMP(sc, IG4_REG_INTR_STAT); 1017 REGDUMP(sc, IG4_REG_INTR_MASK); 1018 REGDUMP(sc, IG4_REG_RAW_INTR_STAT); 1019 REGDUMP(sc, IG4_REG_RX_TL); 1020 REGDUMP(sc, IG4_REG_TX_TL); 1021 REGDUMP(sc, IG4_REG_I2C_EN); 1022 REGDUMP(sc, IG4_REG_I2C_STA); 1023 REGDUMP(sc, IG4_REG_TXFLR); 1024 REGDUMP(sc, IG4_REG_RXFLR); 1025 REGDUMP(sc, IG4_REG_SDA_HOLD); 1026 REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE); 1027 REGDUMP(sc, IG4_REG_SLV_DATA_NACK); 1028 REGDUMP(sc, IG4_REG_DMA_CTRL); 1029 REGDUMP(sc, IG4_REG_DMA_TDLR); 1030 REGDUMP(sc, IG4_REG_DMA_RDLR); 1031 REGDUMP(sc, IG4_REG_SDA_SETUP); 1032 REGDUMP(sc, IG4_REG_ENABLE_STATUS); 1033 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 1034 REGDUMP(sc, IG4_REG_COMP_PARAM1); 1035 REGDUMP(sc, IG4_REG_COMP_VER); 1036 } 1037 if (sc->version == IG4_ATOM) { 1038 REGDUMP(sc, IG4_REG_COMP_TYPE); 1039 REGDUMP(sc, IG4_REG_CLK_PARMS); 1040 } 1041 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { 1042 REGDUMP(sc, IG4_REG_RESETS_HSW); 1043 REGDUMP(sc, IG4_REG_GENERAL); 1044 } else if (sc->version == IG4_SKYLAKE) { 1045 REGDUMP(sc, IG4_REG_RESETS_SKL); 1046 } 1047 if (sc->version == IG4_HASWELL) { 1048 REGDUMP(sc, IG4_REG_SW_LTR_VALUE); 1049 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE); 1050 } else if (sc->version >= IG4_SKYLAKE) { 1051 REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE); 1052 REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE); 1053 } 1054 } 1055 #undef REGDUMP 1056 1057 DRIVER_MODULE(smbus, ig4iic, smbus_driver, smbus_devclass, NULL, NULL); 1058