1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 /* 35 * Intel 4th generation mobile cpus integrated I2C device. 36 * 37 * Datasheet reference: Section 22. 38 * 39 * http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html?wapkw=datasheets+4th+generation 40 * 41 * This is a from-scratch driver under the BSD license using the Intel data 42 * sheet and the linux driver for reference. All code is freshly written 43 * without referencing the linux driver code. However, during testing 44 * I am also using the linux driver code as a reference to help resolve any 45 * issues that come. These will be specifically documented in the code. 46 * 47 * Please see protocol notes in section 5.21. This controller is an I2C 48 * master only and cannot act as a slave. The IO voltage should be set by 49 * the BIOS. Standard (100Kb/s) and Fast (400Kb/s) and fast mode plus 50 * (1MB/s) is supported. High speed mode (3.4 MB/s) is NOT supported. 51 */ 52 53 #ifndef _BUS_SMBUS_INTELGEN4_IG4_REG_H_ 54 #define _BUS_SMBUS_INTELGEN4_IG4_REG_H_ 55 56 /* 57 * 22.2 MMIO registers can be accessed through BAR0 in PCI mode or through 58 * BAR1 when in ACPI mode. 59 * 60 * Register width is 32-bits 61 * 62 * 22.2 Default Values on device reset are 0 except as specified here: 63 * TAR_ADD 0x00000055 64 * SS_SCL_HCNT 0x00000264 65 * SS_SCL_LCNT 0x000002C2 66 * FS_SCL_HCNT 0x0000006E 67 * FS_SCL_LCNT 0x000000CF 68 * INTR_MASK 0x000008FF 69 * I2C_STA 0x00000006 70 * SDA_HOLD 0x00000001 71 * SDA_SETUP 0x00000064 72 * COMP_PARAM1 0x00FFFF6E 73 * COMP_VER 0x3131352A 74 */ 75 76 #define IG4_REG_CTL 0x0000 /* RW Control Register */ 77 #define IG4_REG_TAR_ADD 0x0004 /* RW Target Address */ 78 #define IG4_REG_DATA_CMD 0x0010 /* RW Data Buffer and Command */ 79 #define IG4_REG_SS_SCL_HCNT 0x0014 /* RW Std Speed clock High Count */ 80 #define IG4_REG_SS_SCL_LCNT 0x0018 /* RW Std Speed clock Low Count */ 81 #define IG4_REG_FS_SCL_HCNT 0x001C /* RW Fast Speed clock High Count */ 82 #define IG4_REG_FS_SCL_LCNT 0x0020 /* RW Fast Speed clock Low Count */ 83 #define IG4_REG_INTR_STAT 0x002C /* RO Interrupt Status */ 84 #define IG4_REG_INTR_MASK 0x0030 /* RW Interrupt Mask */ 85 #define IG4_REG_RAW_INTR_STAT 0x0034 /* RO Raw Interrupt Status */ 86 #define IG4_REG_RX_TL 0x0038 /* RW Receive FIFO Threshold */ 87 #define IG4_REG_TX_TL 0x003C /* RW Transmit FIFO Threshold */ 88 #define IG4_REG_CLR_INTR 0x0040 /* RO Clear Interrupt */ 89 #define IG4_REG_CLR_RX_UNDER 0x0044 /* RO Clear RX_Under Interrupt */ 90 #define IG4_REG_CLR_RX_OVER 0x0048 /* RO Clear RX_Over Interrupt */ 91 #define IG4_REG_CLR_TX_OVER 0x004C /* RO Clear TX_Over Interrupt */ 92 #define IG4_REG_CLR_TX_ABORT 0x0054 /* RO Clear TX_Abort Interrupt */ 93 #define IG4_REG_CLR_ACTIVITY 0x005C /* RO Clear Activity Interrupt */ 94 #define IG4_REG_CLR_STOP_DET 0x0060 /* RO Clear STOP Detection Int */ 95 #define IG4_REG_CLR_START_DET 0x0064 /* RO Clear START Detection Int */ 96 #define IG4_REG_CLR_GEN_CALL 0x0068 /* RO Clear General Call Interrupt */ 97 #define IG4_REG_I2C_EN 0x006C /* RW I2C Enable */ 98 #define IG4_REG_I2C_STA 0x0070 /* RO I2C Status */ 99 #define IG4_REG_TXFLR 0x0074 /* RO Transmit FIFO Level */ 100 #define IG4_REG_RXFLR 0x0078 /* RO Receive FIFO Level */ 101 #define IG4_REG_SDA_HOLD 0x007C /* RW SDA Hold Time Length */ 102 #define IG4_REG_TX_ABRT_SOURCE 0x0080 /* RO Transmit Abort Source */ 103 #define IG4_REG_SLV_DATA_NACK 0x0084 /* RW General Slave Data NACK */ 104 #define IG4_REG_DMA_CTRL 0x0088 /* RW DMA Control */ 105 #define IG4_REG_DMA_TDLR 0x008C /* RW DMA Transmit Data Level */ 106 #define IG4_REG_DMA_RDLR 0x0090 /* RW DMA Receive Data Level */ 107 #define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */ 108 #define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */ 109 #define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */ 110 #define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */ 111 #define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */ 112 #define IG4_REG_CLK_PARMS 0x0800 /* RW Clock Parameters */ 113 #define IG4_REG_RESETS 0x0804 /* RW Reset Register */ 114 #define IG4_REG_GENERAL 0x0808 /* RW General Register */ 115 #define IG4_REG_SW_LTR_VALUE 0x0810 /* RW SW LTR Value */ 116 #define IG4_REG_AUTO_LTR_VALUE 0x0814 /* RW Auto LTR Value */ 117 118 /* 119 * CTL - Control Register 22.2.1 120 * Default Value: 0x0000007F. 121 * 122 * RESTARTEN - RW Restart Enable 123 * 10BIT - RW Controller operates in 10-bit mode, else 7-bit 124 * 125 * NOTE: When restart is disabled the controller is incapable of 126 * performing the following functions: 127 * 128 * Sending a START Byte 129 * Performing any high-speed mode op 130 * Performing direction changes in combined format mode 131 * Performing a read operation with a 10-bit address 132 * 133 * Attempting to perform the above operations will result in the 134 * TX_ABORT bit being set in RAW_INTR_STAT. 135 */ 136 #define IG4_CTL_SLAVE_DISABLE 0x0040 /* snarfed from linux */ 137 #define IG4_CTL_RESTARTEN 0x0020 /* Allow Restart when master */ 138 #define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */ 139 #define IG4_CTL_SPEED_FAST 0x0004 /* snarfed from linux */ 140 #define IG4_CTL_SPEED_STD 0x0002 /* snarfed from linux */ 141 #define IG4_CTL_MASTER 0x0001 /* snarfed from linux */ 142 143 /* 144 * TAR_ADD - Target Address Register 22.2.2 145 * Default Value: 0x00000055F 146 * 147 * 10BIT - RW controller starts its transfers in 10-bit 148 * address mode, else 7-bit. 149 * 150 * SPECIAL - RW Indicates whether software performs a General Call 151 * or START BYTE command. 152 * 153 * 0 Ignore GC_OR_START and use TAR address. 154 * 155 * 1 Perform special I2C Command based on GC_OR_START. 156 * 157 * GC_OR_START - RW (only if SPECIAL is set) 158 * 159 * 0 General Call Address. After issuing a General Call, 160 * only writes may be performed. Attempting to issue 161 * a read command results in IX_ABRT in RAW_INTR_STAT. 162 * The controller remains in General Call mode until 163 * bit 11 (SPECIAL) is cleared. 164 * 165 * 1 START BYTE. 166 * 167 * 168 * IC_TAR - RW when transmitting a general call, these bits are 169 * ignored. To generate a START BYTE, the address 170 * needs to be written into these bits once. 171 * 172 * This register should only be updated when the IIC is disabled (I2C_ENABLE=0) 173 */ 174 #define IG4_TAR_10BIT 0x1000 /* start xfer in 10-bit mode */ 175 #define IG4_TAR_SPECIAL 0x0800 /* Perform special command */ 176 #define IG4_TAR_GC_OR_START 0x0400 /* General Call or Start */ 177 #define IG4_TAR_ADDR_MASK 0x03FF /* Target address */ 178 179 /* 180 * TAR_DATA_CMD - Data Buffer and Command Register 22.2.3 181 * 182 * RESTART - RW This bit controls whether a forced RESTART is 183 * issued before the byte is sent or received. 184 * 185 * 0 If not set a RESTART is only issued if the tranfer 186 * direction is changing from the previous command. 187 * 188 * 1 A RESTART is issued before the byte is sent or 189 * received, regardless of whether or not the transfer 190 * direction is changing from the previous command. 191 * 192 * STOP - RW This bit controls whether a STOP is issued after 193 * the byte is sent or received. 194 * 195 * 0 STOP is not issued after this byte, regardless 196 * of whether or not the Tx FIFO is empty. 197 * 198 * 1 STOP is issued after this byte, regardless of 199 * whether or not the Tx FIFO is empty. If the 200 * Tx FIFO is not empty the master immediately tries 201 * to start a new transfer by issuing a START and 202 * arbitrating for the bus. 203 * 204 * i.e. the STOP is issued along with this byte, 205 * within the write stream. 206 * 207 * COMMAND - RW Control whether a read or write is performed. 208 * 209 * 0 WRITE 210 * 211 * 1 READ 212 * 213 * DATA (7:0) - RW Contains the data to be transmitted or received 214 * on the I2C bus. 215 * 216 * NOTE: Writing to this register causes a START + slave + RW to be 217 * issued if the direction has changed or the last data byte was 218 * sent with a STOP. 219 * 220 * NOTE: We control termination? so this register must be written 221 * for each byte we wish to receive. We can then drain the 222 * receive FIFO. 223 */ 224 225 #define IG4_DATA_RESTART 0x0400 /* Force RESTART */ 226 #define IG4_DATA_STOP 0x0200 /* Force STOP[+START] */ 227 #define IG4_DATA_COMMAND_RD 0x0100 /* bus direction 0=write 1=read */ 228 #define IG4_DATA_MASK 0x00FF 229 230 /* 231 * SS_SCL_HCNT - Standard Speed Clock High Count Register 22.2.4 232 * SS_SCL_LCNT - Standard Speed Clock Low Count Register 22.2.5 233 * FS_SCL_HCNT - Fast Speed Clock High Count Register 22.2.6 234 * FS_SCL_LCNT - Fast Speed Clock Low Count Register 22.2.7 235 * 236 * COUNT (15:0) - Set the period count to a value between 6 and 237 * 65525. 238 */ 239 #define IG4_SCL_CLOCK_MASK 0xFFFFU /* count bits in register */ 240 241 /* 242 * INTR_STAT - (RO) Interrupt Status Register 22.2.8 243 * INTR_MASK - (RW) Interrupt Mask Register 22.2.9 244 * RAW_INTR_STAT- (RO) Raw Interrupt Status Register 22.2.10 245 * 246 * GEN_CALL Set only when a general call (broadcast) address 247 * is received and acknowleged, stays set until 248 * cleared by reading CLR_GEN_CALL. 249 * 250 * START_DET Set when a START or RESTART condition has occurred 251 * on the interface. 252 * 253 * STOP_DET Set when a STOP condition has occurred on the 254 * interface. 255 * 256 * ACTIVITY Set by any activity on the interface. Cleared 257 * by reading CLR_ACTIVITY or CLR_INTR. 258 * 259 * TX_ABRT Indicates the controller as a transmitter is 260 * unable to complete the intended action. When set, 261 * the controller will hold the TX FIFO in a reset 262 * state (flushed) until CLR_TX_ABORT is read to 263 * clear the condition. Once cleared, the TX FIFO 264 * will be available again. 265 * 266 * TX_EMPTY Indicates that the transmitter is at or below 267 * the specified TX_TL threshold. Automatically 268 * cleared by HW when the buffer level goes above 269 * the threshold. 270 * 271 * TX_OVER Indicates that the processer attempted to write 272 * to the TX FIFO while the TX FIFO was full. Cleared 273 * by reading CLR_TX_OVER. 274 * 275 * RX_FULL Indicates that the receive FIFO has reached or 276 * exceeded the specified RX_TL threshold. Cleared 277 * by HW when the cpu drains the FIFO to below the 278 * threshold. 279 * 280 * RX_OVER Indicates that the receive FIFO was unable to 281 * accept new data and data was lost. Cleared by 282 * reading CLR_RX_OVER. 283 * 284 * RX_UNDER Indicates that the cpu attempted to read data 285 * from the receive buffer while the RX FIFO was 286 * empty. Cleared by reading CLR_RX_UNDER. 287 * 288 * NOTES ON RAW_INTR_STAT: 289 * 290 * This register can be used to monitor the GEN_CALL, START_DET, 291 * STOP_DET, ACTIVITY, TX_ABRT, TX_EMPTY, TX_OVER, RX_FULL, RX_OVER, 292 * and RX_UNDER bits. The documentation is a bit unclear but presumably 293 * this is the unlatched version. 294 * 295 * Code should test FIFO conditions using the I2C_STA (status) register, 296 * not the interrupt status registers. 297 */ 298 299 #define IG4_INTR_GEN_CALL 0x0800 300 #define IG4_INTR_START_DET 0x0400 301 #define IG4_INTR_STOP_DET 0x0200 302 #define IG4_INTR_ACTIVITY 0x0100 303 #define IG4_INTR_TX_ABRT 0x0040 304 #define IG4_INTR_TX_EMPTY 0x0010 305 #define IG4_INTR_TX_OVER 0x0008 306 #define IG4_INTR_RX_FULL 0x0004 307 #define IG4_INTR_RX_OVER 0x0002 308 #define IG4_INTR_RX_UNDER 0x0001 309 310 /* 311 * RX_TL - (RW) Receive FIFO Threshold Register 22.2.11 312 * TX_TL - (RW) Transmit FIFO Threshold Register 22.2.12 313 * 314 * Specify the receive and transmit FIFO threshold register. The 315 * FIFOs have 16 elements. The valid range is 0-15. Setting a 316 * value greater than 15 causes the actual value to be the maximum 317 * depth of the FIFO. 318 * 319 * Generally speaking since everything is messaged, we can use a 320 * mid-level setting for both parameters and (e.g.) fully drain the 321 * receive FIFO on the STOP_DET condition to handle loose ends. 322 */ 323 #define IG4_FIFO_MASK 0x00FF 324 #define IG4_FIFO_LIMIT 16 325 326 /* 327 * CLR_INTR - (RO) Clear Interrupt Register 22.2.13 328 * CLR_RX_UNDER - (RO) Clear Interrupt Register (specific) 22.2.14 329 * CLR_RX_OVER - (RO) Clear Interrupt Register (specific) 22.2.15 330 * CLR_TX_OVER - (RO) Clear Interrupt Register (specific) 22.2.16 331 * CLR_TX_ABORT - (RO) Clear Interrupt Register (specific) 22.2.17 332 * CLR_ACTIVITY - (RO) Clear Interrupt Register (specific) 22.2.18 333 * CLR_STOP_DET - (RO) Clear Interrupt Register (specific) 22.2.19 334 * CLR_START_DET- (RO) Clear Interrupt Register (specific) 22.2.20 335 * CLR_GEN_CALL - (RO) Clear Interrupt Register (specific) 22.2.21 336 * 337 * CLR_* specific operations clear the appropriate bit in the 338 * RAW_INTR_STAT register. Intel does not really document whether 339 * these operations clear the normal interrupt status register. 340 * 341 * CLR_INTR clears bits in the normal interrupt status register and 342 * presumably also the raw(?) register? Intel is again unclear. 343 * 344 * NOTE: CLR_INTR only clears software-clearable interrupts. Hardware 345 * clearable interrupts are controlled entirely by the hardware. 346 * CLR_INTR also clears the TX_ABRT_SOURCE register. 347 * 348 * NOTE: CLR_TX_ABORT also clears the TX_ABRT_SOURCE register and releases 349 * the TX FIFO from its flushed/reset state, allowing more writes 350 * to the TX FIFO. 351 * 352 * NOTE: CLR_ACTIVITY has no effect if the I2C bus is still active. 353 * Intel documents that the bit is automatically cleared when 354 * there is no further activity on the bus. 355 */ 356 #define IG4_CLR_BIT 0x0001 /* Reflects source */ 357 358 /* 359 * I2C_EN - (RW) I2C Enable Register 22.2.22 360 * 361 * ABORT Software can abort an I2C transfer by setting this 362 * bit. Hardware will clear the bit once the STOP has 363 * been detected. This bit can only be set while the 364 * I2C interface is enabled. 365 * 366 * I2C_ENABLE Enable the controller, else disable it. 367 * (Use I2C_ENABLE_STATUS to poll enable status 368 * & wait for changes) 369 */ 370 #define IG4_I2C_ABORT 0x0002 371 #define IG4_I2C_ENABLE 0x0001 372 373 /* 374 * I2C_STA - (RO) I2C Status Register 22.2.23 375 */ 376 #define IG4_STATUS_ACTIVITY 0x0020 /* Controller is active */ 377 #define IG4_STATUS_RX_FULL 0x0010 /* RX FIFO completely full */ 378 #define IG4_STATUS_RX_NOTEMPTY 0x0008 /* RX FIFO not empty */ 379 #define IG4_STATUS_TX_EMPTY 0x0004 /* TX FIFO completely empty */ 380 #define IG4_STATUS_TX_NOTFULL 0x0002 /* TX FIFO not full */ 381 #define IG4_STATUS_I2C_ACTIVE 0x0001 /* I2C bus is active */ 382 383 /* 384 * TXFLR - (RO) Transmit FIFO Level Register 22.2.24 385 * RXFLR - (RO) Receive FIFO Level Register 22.2.25 386 * 387 * Read the number of entries currently in the Transmit or Receive 388 * FIFOs. Note that for some reason the mask is 9 bits instead of 389 * the 8 bits the fill level controls. 390 */ 391 #define IG4_FIFOLVL_MASK 0x001F 392 393 /* 394 * SDA_HOLD - (RW) SDA Hold Time Length Register 22.2.26 395 * 396 * Set the SDA hold time length register in I2C clocks. 397 */ 398 #define IG4_SDA_HOLD_MASK 0x00FF 399 400 /* 401 * TX_ABRT_SOURCE- (RO) Transmit Abort Source Register 22.2.27 402 * 403 * Indicates the cause of a transmit abort. This can indicate a 404 * software programming error or a device expected address width 405 * mismatch or other issues. The NORESTART conditions and GENCALL_NOACK 406 * can only occur if a programming error was made in the driver software. 407 * 408 * In particular, it should be possible to detect whether any devices 409 * are on the bus by observing the GENCALL_READ status, and it might 410 * be possible to detect ADDR7 vs ADDR10 mismatches. 411 */ 412 #define IG4_ABRTSRC_TRANSFER 0x00010000 /* Abort initiated by user */ 413 #define IG4_ABRTSRC_ARBLOST 0x00001000 /* Arbitration lost */ 414 #define IG4_ABRTSRC_NORESTART_10 0x00000400 /* RESTART disabled */ 415 #define IG4_ABRTSRC_NORESTART_START 0x00000200 /* RESTART disabled */ 416 #define IG4_ABRTSRC_ACKED_START 0x00000080 /* Improper acked START */ 417 #define IG4_ABRTSRC_GENCALL_NOACK 0x00000020 /* Improper GENCALL */ 418 #define IG4_ABRTSRC_GENCALL_READ 0x00000010 /* Nobody acked GENCALL */ 419 #define IG4_ABRTSRC_TXNOACK_DATA 0x00000008 /* data phase no ACK */ 420 #define IG4_ABRTSRC_TXNOACK_ADDR10_2 0x00000004 /* addr10/1 phase no ACK */ 421 #define IG4_ABRTSRC_TXNOACK_ADDR10_1 0x00000002 /* addr10/2 phase no ACK */ 422 #define IG4_ABRTSRC_TXNOACK_ADDR7 0x00000001 /* addr7 phase no ACK */ 423 424 /* 425 * SLV_DATA_NACK - (RW) Generate Slave DATA NACK Register 22.2.28 426 * 427 * When the controller is a receiver a NACK can be generated on 428 * receipt of data. 429 * 430 * NACK_GENERATE Set to 0 for normal NACK/ACK generation. 431 * Set to 1 to generate a NACK after next data 432 * byte received. 433 * 434 */ 435 #define IG4_NACK_GENERATE 0x0001 436 437 /* 438 * DMA_CTRL - (RW) DMA Control Register 22.2.29 439 * 440 * Enables DMA on the transmit and/or receive DMA channel. 441 */ 442 #define IG4_TX_DMA_ENABLE 0x0002 443 #define IG4_RX_DMA_ENABLE 0x0001 444 445 /* 446 * DMA_TDLR - (RW) DMA Transmit Data Level Register 22.2.30 447 * DMA_RDLR - (RW) DMA Receive Data Level Register 22.2.31 448 * 449 * Similar to RX_TL and TX_TL but controls when a DMA burst occurs 450 * to empty or fill the FIFOs. Use the same IG4_FIFO_MASK and 451 * IG4_FIFO_LIMIT defines for RX_RL and TX_TL. 452 */ 453 /* empty */ 454 455 /* 456 * SDA_SETUP - (RW) SDA Setup Time Length Register 22.2.32 457 * 458 * Set the SDA setup time length register in I2C clocks. 459 * The register must be programmed with a value >=2. 460 * (Defaults to 0x64). 461 */ 462 #define IG4_SDA_SETUP_MASK 0x00FF 463 464 /* 465 * ACK_GEN_CALL - (RW) ACK General Call Register 22.2.33 466 * 467 * Control whether the controller responds with a ACK or NACK when 468 * it receives an I2C General Call address. 469 * 470 * If set to 0 a NACK is generated and a General Call interrupt is 471 * NOT generated. Otherwise an ACK + interrupt is generated. 472 */ 473 #define IG4_ACKGC_ACK 0x0001 474 475 /* 476 * ENABLE_STATUS - (RO) Enable Status Registger 22.2.34 477 * 478 * DATA_LOST - Indicates that a slave receiver operation has 479 * been aborted with at least one data byte received 480 * from a transfer due to the I2C controller being 481 * disabled (IG4_I2C_ENABLE -> 0) 482 * 483 * ENABLED - Intel documentation is lacking but I assume this 484 * is a reflection of the IG4_I2C_ENABLE bit in the 485 * I2C_EN register. 486 * 487 */ 488 #define IG4_ENASTAT_DATA_LOST 0x0004 489 #define IG4_ENASTAT_ENABLED 0x0001 490 491 /* 492 * COMP_PARAM1 - (RO) Component Parameter Register 22.2.35 493 * Default Value 0x00FFFF6E 494 * 495 * VALID - Intel documentation is unclear but I believe this 496 * must be read as a 1 to indicate that the rest of 497 * the bits in the register are valid. 498 * 499 * HASDMA - Indicates that the chip is DMA-capable. Presumably 500 * in certain virtualization cases the chip might be 501 * set to not be DMA-capable. 502 * 503 * INTR_IO - Indicates that all interrupts are combined to 504 * generate one interrupt. If not set, interrupts 505 * are individual (more virtualization stuff?) 506 * 507 * HCCNT_RO - Indicates that the clock timing registers are 508 * RW. If not set, the registers are RO. 509 * (more virtualization stuff). 510 * 511 * MAXSPEED - Indicates the maximum speed supported. 512 * 513 * DATAW - Indicates the internal bus width in bits. 514 */ 515 #define IG4_PARAM1_TXFIFO_DEPTH(v) (((v) >> 16) & 0xFF) 516 #define IG4_PARAM1_RXFIFO_DEPTH(v) (((v) >> 8) & 0xFF) 517 #define IG4_PARAM1_CONFIG_VALID 0x00000080 518 #define IG4_PARAM1_CONFIG_HASDMA 0x00000040 519 #define IG4_PARAM1_CONFIG_INTR_IO 0x00000020 520 #define IG4_PARAM1_CONFIG_HCCNT_RO 0x00000010 521 #define IG4_PARAM1_CONFIG_MAXSPEED_MASK 0x0000000C 522 #define IG4_PARAM1_CONFIG_DATAW_MASK 0x00000003 523 524 #define IG4_CONFIG_MAXSPEED_RESERVED00 0x00000000 525 #define IG4_CONFIG_MAXSPEED_STANDARD 0x00000004 526 #define IG4_CONFIG_MAXSPEED_FAST 0x00000008 527 #define IG4_CONFIG_MAXSPEED_HIGH 0x0000000C 528 529 #define IG4_CONFIG_DATAW_8 0x00000000 530 #define IG4_CONFIG_DATAW_16 0x00000001 531 #define IG4_CONFIG_DATAW_32 0x00000002 532 #define IG4_CONFIG_DATAW_RESERVED11 0x00000003 533 534 /* 535 * COMP_VER - (RO) Component Version Register 22.2.36 536 * Default Value 0x3131352A 537 * 538 * Contains the chip version number. All 32 bits. 539 */ 540 #define IG4_COMP_VER 0x3131352A 541 542 /* 543 * COMP_TYPE - (RO) (linux) Endian and bus width probe 544 * 545 * Read32 from this register and test against IG4_COMP_TYPE 546 * to determine the bus width. e.g. 01404457 = endian-reversed, 547 * and 00000140 or 00004457 means internal 16-bit bus (?). 548 * 549 * This register is not in the intel documentation, I pulled it 550 * from the linux driver i2c-designware-core.c. 551 */ 552 #define IG4_COMP_TYPE 0x44570140 553 554 /* 555 * RESETS - (RW) Resets Register 22.2.37 556 * 557 * Used to reset the I2C host controller by SW. There is no timing 558 * requirement, software can assert and de-assert in back-to-back 559 * transactions. 560 * 561 * 00 I2C host controller is NOT in reset. 562 * 01 (reserved) 563 * 10 (reserved) 564 * 11 I2C host controller is in reset. 565 */ 566 #define IG4_RESETS_ASSERT 0x0003 567 #define IG4_RESETS_DEASSERT 0x0000 568 569 /* 570 * GENERAL - (RW) General Reigster 22.2.38 571 * 572 * IOVOLT 0=1.8V 1=3.3V 573 * 574 * LTR 0=Auto 1=SW 575 * 576 * In Auto mode the BIOS will write to the host controller's 577 * AUTO LTR Value register (offset 0x0814) with the active 578 * state LTR value, and will write to the SW LTR Value register 579 * (offset 0x0810) with the idle state LTR value. 580 * 581 * In SW mode the SW will write to the host controller SW LTR 582 * value (offset 0x0810). It is the SW responsibility to update 583 * the LTR with the appropriate value. 584 */ 585 #define IG4_GENERAL_IOVOLT3_3 0x0008 586 #define IG4_GENERAL_SWMODE 0x0004 587 588 /* 589 * SW_LTR_VALUE - (RW) SW LTR Value Register 22.2.39 590 * AUTO_LTR_VALUE - (RW) SW LTR Value Register 22.2.40 591 * 592 * Default value is 0x00000800 which means the best possible 593 * service/response time. 594 * 595 * It isn't quite clear how the snooping works. There are two scale 596 * bits for both sets but two of the four codes are reserved. The 597 * *SNOOP_VALUE() is specified as a 10-bit latency value. If 0, it 598 * indicates that the device cannot tolerate any delay and needs the 599 * best possible service/response time. 600 * 601 * I think this is for snooping (testing) the I2C bus. The lowest 602 * delay (0) probably runs the controller polling at a high, power hungry 603 * rate. But I dunno. 604 */ 605 #define IG4_SWLTR_NSNOOP_REQ 0x80000000 /* (ro) */ 606 #define IG4_SWLTR_NSNOOP_SCALE_MASK 0x1C000000 /* (ro) */ 607 #define IG4_SWLTR_NSNOOP_SCALE_1US 0x08000000 /* (ro) */ 608 #define IG4_SWLTR_NSNOOP_SCALE_32US 0x0C000000 /* (ro) */ 609 #define IG4_SWLTR_NSNOOP_VALUE_DECODE(v) (((v) >> 16) & 0x3F) 610 #define IG4_SWLTR_NSNOOP_VALUE_ENCODE(v) (((v) & 0x3F) << 16) 611 612 #define IG4_SWLTR_SNOOP_REQ 0x00008000 /* (rw) */ 613 #define IG4_SWLTR_SNOOP_SCALE_MASK 0x00001C00 /* (rw) */ 614 #define IG4_SWLTR_SNOOP_SCALE_1US 0x00000800 /* (rw) */ 615 #define IG4_SWLTR_SNOOP_SCALE_32US 0x00000C00 /* (rw) */ 616 #define IG4_SWLTR_SNOOP_VALUE_DECODE(v) ((v) & 0x3F) 617 #define IG4_SWLTR_SNOOP_VALUE_ENCODE(v) ((v) & 0x3F) 618 619 #endif 620