1 /*- 2 * ichsmb_pci.c 3 * 4 * Author: Archie Cobbs <archie@freebsd.org> 5 * Copyright (c) 2000 Whistle Communications, Inc. 6 * All rights reserved. 7 * Author: Archie Cobbs <archie@freebsd.org> 8 * 9 * Subject to the following obligations and disclaimer of warranty, use and 10 * redistribution of this software, in source or object code forms, with or 11 * without modifications are expressly permitted by Whistle Communications; 12 * provided, however, that: 13 * 1. Any and all reproductions of the source or object code must include the 14 * copyright notice above and the following disclaimer of warranties; and 15 * 2. No rights are granted, in any manner or form, to use Whistle 16 * Communications, Inc. trademarks, including the mark "WHISTLE 17 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as 18 * such appears in the above copyright notice or in the software. 19 * 20 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND 21 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO 22 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE, 23 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 25 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY 26 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS 27 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE. 28 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES 29 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING 30 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 31 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY 36 * OF SUCH DAMAGE. 37 * 38 * $FreeBSD: src/sys/dev/ichsmb/ichsmb_pci.c,v 1.25 2009/12/16 12:25:27 avg Exp $ 39 */ 40 41 /* 42 * Support for the SMBus controller logical device which is part of the 43 * Intel 81801AA/AB/BA/CA/DC/EB (ICH/ICH[02345]) I/O controller hub chips. 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/errno.h> 51 #include <sys/lock.h> 52 #include <sys/mutex.h> 53 #include <sys/syslog.h> 54 #include <sys/bus.h> 55 56 #include <sys/rman.h> 57 58 #include <bus/pci/pcivar.h> 59 #include <bus/pci/pcireg.h> 60 61 #include <bus/smbus/smbconf.h> 62 63 #include "ichsmb_var.h" 64 #include "ichsmb_reg.h" 65 66 /* PCI unique identifiers */ 67 #define PCI_VENDOR_INTEL 0x8086 68 #define ID_82801AA 0x2413 69 #define ID_82801AB 0x2423 70 #define ID_82801BA 0x2443 71 #define ID_82801CA 0x2483 72 #define ID_82801DC 0x24C3 73 #define ID_82801E 0x2453 74 #define ID_82801EB 0x24D3 75 #define ID_82801FB 0x266A 76 #define ID_82801GB 0x27da 77 #define ID_82801H 0x283e 78 #define ID_82801I 0x2930 79 #define ID_EP80579 0x5032 80 #define ID_82801JI 0x3a30 81 #define ID_82801JD 0x3a60 82 #define ID_PCH 0x3b30 83 #define ID_6300ESB 0x25a4 84 #define ID_631xESB 0x269b 85 #define ID_DH89XXCC 0x2330 86 #define ID_PATSBURG 0x1d22 87 #define ID_CPT 0x1c22 88 #define ID_PPT 0x1e22 89 #define ID_AVOTON 0x1f3c 90 #define ID_COLETOCRK 0x23B0 91 #define ID_LPT 0x8c22 92 #define ID_LPTLP 0x9c22 93 #define ID_WCPT 0x8ca2 94 #define ID_WCPTLP 0x9ca2 95 #define ID_BAYTRAIL 0x0f12 96 #define ID_BRASWELL 0x2292 97 #define ID_WELLSBURG 0x8d22 98 #define ID_SRPT 0xa123 99 #define ID_SRPTLP 0x9d23 100 #define ID_DENVERTON 0x19df 101 #define ID_BROXTON 0x5ad4 102 #define ID_LEWISBURG 0xa1a3 103 #define ID_LEWISBURG2 0xa223 104 #define ID_KABYLAKE 0xa2a3 105 106 static const struct ichsmb_device { 107 uint16_t id; 108 const char *name; 109 } ichsmb_devices[] = { 110 { ID_82801AA, "Intel 82801AA (ICH) SMBus controller" }, 111 { ID_82801AB, "Intel 82801AB (ICH0) SMBus controller" }, 112 { ID_82801BA, "Intel 82801BA (ICH2) SMBus controller" }, 113 { ID_82801CA, "Intel 82801CA (ICH3) SMBus controller" }, 114 { ID_82801DC, "Intel 82801DC (ICH4) SMBus controller" }, 115 { ID_82801EB, "Intel 82801EB (ICH5) SMBus controller" }, 116 { ID_82801FB, "Intel 82801FB (ICH6) SMBus controller" }, 117 { ID_82801GB, "Intel 82801GB (ICH7) SMBus controller" }, 118 { ID_82801H, "Intel 82801H (ICH8) SMBus controller" }, 119 { ID_82801I, "Intel 82801I (ICH9) SMBus controller" }, 120 { ID_82801GB, "Intel 82801GB (ICH7) SMBus controller" }, 121 { ID_82801H, "Intel 82801H (ICH8) SMBus controller" }, 122 { ID_82801I, "Intel 82801I (ICH9) SMBus controller" }, 123 { ID_EP80579, "Intel EP80579 SMBus controller" }, 124 { ID_82801JI, "Intel 82801JI (ICH10) SMBus controller" }, 125 { ID_82801JD, "Intel 82801JD (ICH10) SMBus controller" }, 126 { ID_PCH, "Intel PCH SMBus controller" }, 127 { ID_6300ESB, "Intel 6300ESB (ICH) SMBus controller" }, 128 { ID_631xESB, "Intel 631xESB/6321ESB (ESB2) SMBus controller" }, 129 { ID_DH89XXCC, "Intel DH89xxCC SMBus controller" }, 130 { ID_PATSBURG, "Intel Patsburg SMBus controller" }, 131 { ID_CPT, "Intel Cougar Point SMBus controller" }, 132 { ID_PPT, "Intel Panther Point SMBus controller" }, 133 { ID_AVOTON, "Intel Avoton SMBus controller" }, 134 { ID_LPT, "Intel Lynx Point SMBus controller" }, 135 { ID_LPTLP, "Intel Lynx Point-LP SMBus controller" }, 136 { ID_WCPT, "Intel Wildcat Point SMBus controller" }, 137 { ID_WCPTLP, "Intel Wildcat Point-LP SMBus controller" }, 138 { ID_BAYTRAIL, "Intel Baytrail SMBus controller" }, 139 { ID_BRASWELL, "Intel Braswell SMBus controller" }, 140 { ID_COLETOCRK, "Intel Coleto Creek SMBus controller" }, 141 { ID_WELLSBURG, "Intel Wellsburg SMBus controller" }, 142 { ID_SRPT, "Intel Sunrise Point-H SMBus controller" }, 143 { ID_SRPTLP, "Intel Sunrise Point-LP SMBus controller" }, 144 { ID_DENVERTON, "Intel Denverton SMBus controller" }, 145 { ID_BROXTON, "Intel Broxton SMBus controller" }, 146 { ID_LEWISBURG, "Intel Lewisburg SMBus controller" }, 147 { ID_LEWISBURG2,"Intel Lewisburg SMBus controller" }, 148 { ID_KABYLAKE, "Intel Kaby Lake SMBus controller" }, 149 { 0, NULL }, 150 }; 151 152 #define PCIS_SERIALBUS_SMBUS_PROGIF 0x00 153 154 /* Internal functions */ 155 static int ichsmb_pci_probe(device_t dev); 156 static int ichsmb_pci_attach(device_t dev); 157 /*Use generic one for now*/ 158 #if 0 159 static int ichsmb_pci_detach(device_t dev); 160 #endif 161 162 /* Device methods */ 163 static device_method_t ichsmb_pci_methods[] = { 164 /* Device interface */ 165 DEVMETHOD(device_probe, ichsmb_pci_probe), 166 DEVMETHOD(device_attach, ichsmb_pci_attach), 167 DEVMETHOD(device_detach, ichsmb_detach), 168 169 /* Bus methods */ 170 DEVMETHOD(bus_print_child, bus_generic_print_child), 171 172 /* SMBus methods */ 173 DEVMETHOD(smbus_callback, ichsmb_callback), 174 DEVMETHOD(smbus_quick, ichsmb_quick), 175 DEVMETHOD(smbus_sendb, ichsmb_sendb), 176 DEVMETHOD(smbus_recvb, ichsmb_recvb), 177 DEVMETHOD(smbus_writeb, ichsmb_writeb), 178 DEVMETHOD(smbus_writew, ichsmb_writew), 179 DEVMETHOD(smbus_readb, ichsmb_readb), 180 DEVMETHOD(smbus_readw, ichsmb_readw), 181 DEVMETHOD(smbus_pcall, ichsmb_pcall), 182 DEVMETHOD(smbus_bwrite, ichsmb_bwrite), 183 DEVMETHOD(smbus_bread, ichsmb_bread), 184 DEVMETHOD_END 185 }; 186 187 static driver_t ichsmb_pci_driver = { 188 "ichsmb", 189 ichsmb_pci_methods, 190 sizeof(struct ichsmb_softc) 191 }; 192 193 static devclass_t ichsmb_pci_devclass; 194 195 DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, ichsmb_pci_devclass, NULL, NULL); 196 197 static int 198 ichsmb_pci_probe(device_t dev) 199 { 200 const struct ichsmb_device *device; 201 202 for (device = ichsmb_devices; device->name != NULL; device++) { 203 if (pci_get_device(dev) == device->id) { 204 device_set_desc(dev, device->name); 205 return (ichsmb_probe(dev)); 206 } 207 } 208 209 return (ENXIO); 210 } 211 212 static int 213 ichsmb_pci_attach(device_t dev) 214 { 215 const sc_p sc = device_get_softc(dev); 216 int error; 217 218 /* Initialize private state */ 219 bzero(sc, sizeof(*sc)); 220 sc->ich_cmd = -1; 221 sc->dev = dev; 222 223 /* Allocate an I/O range */ 224 sc->io_rid = ICH_SMB_BASE; 225 sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT, 226 &sc->io_rid, 0, ~0, 16, RF_ACTIVE); 227 if (sc->io_res == NULL) 228 sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT, 229 &sc->io_rid, 0ul, ~0ul, 32, RF_ACTIVE); 230 if (sc->io_res == NULL) { 231 device_printf(dev, "can't map I/O\n"); 232 error = ENXIO; 233 goto fail; 234 } 235 236 /* Allocate interrupt */ 237 sc->irq_rid = 0; 238 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 239 &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE); 240 if (sc->irq_res == NULL) { 241 device_printf(dev, "can't get IRQ\n"); 242 error = ENXIO; 243 goto fail; 244 } 245 246 /* Enable device */ 247 pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1); 248 249 /* Done */ 250 error = ichsmb_attach(dev); 251 if (error) 252 goto fail; 253 return (0); 254 255 fail: 256 /* Attach failed, release resources */ 257 ichsmb_release_resources(sc); 258 return (error); 259 } 260 261 262 MODULE_DEPEND(ichsmb, pci, 1, 1, 1); 263 MODULE_DEPEND(ichsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); 264 MODULE_VERSION(ichsmb, 1); 265