xref: /dragonfly/sys/bus/smbus/ichsmb/ichsmb_pci.c (revision ef2687d4)
1 /*-
2  * ichsmb_pci.c
3  *
4  * Author: Archie Cobbs <archie@freebsd.org>
5  * Copyright (c) 2000 Whistle Communications, Inc.
6  * All rights reserved.
7  * Author: Archie Cobbs <archie@freebsd.org>
8  *
9  * Subject to the following obligations and disclaimer of warranty, use and
10  * redistribution of this software, in source or object code forms, with or
11  * without modifications are expressly permitted by Whistle Communications;
12  * provided, however, that:
13  * 1. Any and all reproductions of the source or object code must include the
14  *    copyright notice above and the following disclaimer of warranties; and
15  * 2. No rights are granted, in any manner or form, to use Whistle
16  *    Communications, Inc. trademarks, including the mark "WHISTLE
17  *    COMMUNICATIONS" on advertising, endorsements, or otherwise except as
18  *    such appears in the above copyright notice or in the software.
19  *
20  * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND
21  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO
22  * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE,
23  * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF
24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
25  * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
26  * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS
27  * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE.
28  * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES
29  * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING
30  * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
31  * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR
32  * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
35  * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY
36  * OF SUCH DAMAGE.
37  *
38  * $FreeBSD: src/sys/dev/ichsmb/ichsmb_pci.c,v 1.25 2009/12/16 12:25:27 avg Exp $
39  */
40 
41 /*
42  * Support for the SMBus controller logical device which is part of the
43  * Intel 81801AA/AB/BA/CA/DC/EB (ICH/ICH[02345]) I/O controller hub chips.
44  */
45 
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/errno.h>
51 #include <sys/lock.h>
52 #include <sys/mutex.h>
53 #include <sys/syslog.h>
54 #include <sys/bus.h>
55 
56 #include <sys/rman.h>
57 
58 #include <bus/pci/pcivar.h>
59 #include <bus/pci/pcireg.h>
60 
61 #include <bus/smbus/smbconf.h>
62 
63 #include "ichsmb_var.h"
64 #include "ichsmb_reg.h"
65 
66 /* PCI unique identifiers */
67 #define ID_82801AA			0x24138086
68 #define ID_82801AB			0x24238086
69 #define ID_82801BA			0x24438086
70 #define ID_82801CA			0x24838086
71 #define ID_82801DC			0x24C38086
72 #define ID_82801E			0x24538086
73 #define ID_82801EB			0x24D38086
74 #define ID_82801FB			0x266A8086
75 #define ID_82801GB			0x27da8086
76 #define ID_82801H			0x283e8086
77 #define ID_82801I			0x29308086
78 #define ID_82801JI			0x3a308086
79 #define ID_PCH				0x3b308086
80 #define ID_6300ESB			0x25a48086
81 #define	ID_631xESB			0x269b8086
82 #define ID_DH89XXCC			0x23308086
83 #define ID_PATSBURG			0x1d228086
84 #define ID_CPT				0x1c228086
85 #define ID_PPT				0x1e228086
86 #define ID_AVOTON			0x1f3c8086
87 #define ID_COLETOCRK			0x23B08086
88 #define ID_LPT				0x8c228086
89 #define ID_LPT_LP			0x9c228086
90 
91 #define PCIS_SERIALBUS_SMBUS_PROGIF	0x00
92 
93 /* Internal functions */
94 static int	ichsmb_pci_probe(device_t dev);
95 static int	ichsmb_pci_attach(device_t dev);
96 /*Use generic one for now*/
97 #if 0
98 static int	ichsmb_pci_detach(device_t dev);
99 #endif
100 
101 /* Device methods */
102 static device_method_t ichsmb_pci_methods[] = {
103 	/* Device interface */
104         DEVMETHOD(device_probe, ichsmb_pci_probe),
105         DEVMETHOD(device_attach, ichsmb_pci_attach),
106         DEVMETHOD(device_detach, ichsmb_detach),
107 
108 	/* Bus methods */
109         DEVMETHOD(bus_print_child, bus_generic_print_child),
110 
111 	/* SMBus methods */
112         DEVMETHOD(smbus_callback, ichsmb_callback),
113         DEVMETHOD(smbus_quick, ichsmb_quick),
114         DEVMETHOD(smbus_sendb, ichsmb_sendb),
115         DEVMETHOD(smbus_recvb, ichsmb_recvb),
116         DEVMETHOD(smbus_writeb, ichsmb_writeb),
117         DEVMETHOD(smbus_writew, ichsmb_writew),
118         DEVMETHOD(smbus_readb, ichsmb_readb),
119         DEVMETHOD(smbus_readw, ichsmb_readw),
120         DEVMETHOD(smbus_pcall, ichsmb_pcall),
121         DEVMETHOD(smbus_bwrite, ichsmb_bwrite),
122         DEVMETHOD(smbus_bread, ichsmb_bread),
123 	DEVMETHOD_END
124 };
125 
126 static driver_t ichsmb_pci_driver = {
127 	"ichsmb",
128 	ichsmb_pci_methods,
129 	sizeof(struct ichsmb_softc)
130 };
131 
132 static devclass_t ichsmb_pci_devclass;
133 
134 DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, ichsmb_pci_devclass, NULL, NULL);
135 
136 static int
137 ichsmb_pci_probe(device_t dev)
138 {
139 	/* Check PCI identifier */
140 	switch (pci_get_devid(dev)) {
141 	case ID_82801AA:
142 		device_set_desc(dev, "Intel 82801AA (ICH) SMBus controller");
143 		break;
144 	case ID_82801AB:
145 		device_set_desc(dev, "Intel 82801AB (ICH0) SMBus controller");
146 		break;
147 	case ID_82801BA:
148 		device_set_desc(dev, "Intel 82801BA (ICH2) SMBus controller");
149 		break;
150 	case ID_82801CA:
151 		device_set_desc(dev, "Intel 82801CA (ICH3) SMBus controller");
152 		break;
153 	case ID_82801DC:
154 		device_set_desc(dev, "Intel 82801DC (ICH4) SMBus controller");
155 		break;
156 	case ID_82801E:
157 		device_set_desc(dev, "Intel 82801E (C-ICH) SMBus controller");
158 		break;
159 	case ID_82801EB:
160 		device_set_desc(dev, "Intel 82801EB (ICH5) SMBus controller");
161 		break;
162 	case ID_82801FB:
163 		device_set_desc(dev, "Intel 82801FB (ICH6) SMBus controller");
164 		break;
165 	case ID_82801GB:
166 		device_set_desc(dev, "Intel 82801GB (ICH7) SMBus controller");
167 		break;
168 	case ID_82801H:
169 		device_set_desc(dev, "Intel 82801H (ICH8) SMBus controller");
170 		break;
171 	case ID_82801I:
172 		device_set_desc(dev, "Intel 82801I (ICH9) SMBus controller");
173 		break;
174 	case ID_82801JI:
175 		device_set_desc(dev, "Intel 82801JI (ICH10) SMBus controller");
176 		break;
177 	case ID_PCH:
178 		device_set_desc(dev, "Intel PCH SMBus controller");
179 		break;
180 	case ID_6300ESB:
181 		device_set_desc(dev, "Intel 6300ESB (ICH) SMBus controller");
182 		break;
183 	case ID_631xESB:
184 		device_set_desc(dev, "Intel 631xESB/6321ESB (ESB2) SMBus controller");
185 		break;
186 	case ID_DH89XXCC:
187 		device_set_desc(dev, "Intel DH89xxCC SMBus controller");
188 		break;
189 	case ID_PATSBURG:
190 		device_set_desc(dev, "Intel Patsburg SMBus controller");
191 		break;
192 	case ID_CPT:
193 		device_set_desc(dev, "Intel Cougar Point SMBus controller");
194 		break;
195 	case ID_PPT:
196 		device_set_desc(dev, "Intel Panther Point SMBus controller");
197 		break;
198 	case ID_AVOTON:
199 		device_set_desc(dev, "Intel Avoton SMBus controller");
200 		break;
201 	case ID_COLETOCRK:
202 		device_set_desc(dev, "Intel Coleto Creek SMBus controller");
203 		break;
204 	case ID_LPT:
205 		device_set_desc(dev, "Intel Lynx Point SMBus controller");
206 		break;
207 	case ID_LPT_LP:
208 		device_set_desc(dev, "Intel Lynx Point-LP SMBus controller-0");
209 		break;
210 	default:
211 		return (ENXIO);
212 	}
213 
214 	/* Done */
215 	return (ichsmb_probe(dev));
216 }
217 
218 static int
219 ichsmb_pci_attach(device_t dev)
220 {
221 	const sc_p sc = device_get_softc(dev);
222 	int error;
223 
224 	/* Initialize private state */
225 	bzero(sc, sizeof(*sc));
226 	sc->ich_cmd = -1;
227 	sc->dev = dev;
228 
229 	/* Allocate an I/O range */
230 	sc->io_rid = ICH_SMB_BASE;
231 	sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
232 	    &sc->io_rid, 0, ~0, 16, RF_ACTIVE);
233 	if (sc->io_res == NULL)
234 		sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
235 		    &sc->io_rid, 0ul, ~0ul, 32, RF_ACTIVE);
236 	if (sc->io_res == NULL) {
237 		device_printf(dev, "can't map I/O\n");
238 		error = ENXIO;
239 		goto fail;
240 	}
241 
242 	/* Allocate interrupt */
243 	sc->irq_rid = 0;
244 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
245 	    &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE);
246 	if (sc->irq_res == NULL) {
247 		device_printf(dev, "can't get IRQ\n");
248 		error = ENXIO;
249 		goto fail;
250 	}
251 
252 	/* Enable device */
253 	pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1);
254 
255 	/* Done */
256 	error = ichsmb_attach(dev);
257 	if (error)
258 		goto fail;
259 	return (0);
260 
261 fail:
262 	/* Attach failed, release resources */
263 	ichsmb_release_resources(sc);
264 	return (error);
265 }
266 
267 
268 MODULE_DEPEND(ichsmb, pci, 1, 1, 1);
269 MODULE_DEPEND(ichsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
270 MODULE_VERSION(ichsmb, 1);
271