1 /* $FreeBSD: head/sys/dev/usb/controller/ehci.c 269569 2014-08-05 08:24:41Z n_hibma $ */ 2 /*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 5 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 6 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 32 * 33 * The EHCI 0.96 spec can be found at 34 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 35 * The EHCI 1.0 spec can be found at 36 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 37 * and the USB 2.0 spec at 38 * http://www.usb.org/developers/docs/usb_20.zip 39 * 40 */ 41 42 /* 43 * TODO: 44 * 1) command failures are not recovered correctly 45 */ 46 47 #include <sys/stdint.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/condvar.h> 57 #include <sys/sysctl.h> 58 #include <sys/unistd.h> 59 #include <sys/callout.h> 60 #include <sys/malloc.h> 61 #include <sys/priv.h> 62 63 #include <bus/u4b/usb.h> 64 #include <bus/u4b/usbdi.h> 65 66 #define USB_DEBUG_VAR ehcidebug 67 68 #include <bus/u4b/usb_core.h> 69 #include <bus/u4b/usb_debug.h> 70 #include <bus/u4b/usb_busdma.h> 71 #include <bus/u4b/usb_process.h> 72 #include <bus/u4b/usb_transfer.h> 73 #include <bus/u4b/usb_device.h> 74 #include <bus/u4b/usb_hub.h> 75 #include <bus/u4b/usb_util.h> 76 77 #include <bus/u4b/usb_controller.h> 78 #include <bus/u4b/usb_bus.h> 79 #include <bus/u4b/controller/ehci.h> 80 #include <bus/u4b/controller/ehcireg.h> 81 82 #define EHCI_BUS2SC(bus) \ 83 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 84 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 85 86 #ifdef USB_DEBUG 87 static int ehcidebug = 0; 88 static int ehcinohighspeed = 0; 89 static int ehciiaadbug = 0; 90 static int ehcilostintrbug = 0; 91 92 static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 93 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW, 94 &ehcidebug, 0, "Debug level"); 95 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 96 &ehcinohighspeed, 0, "Disable High Speed USB"); 97 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW, 98 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 99 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW, 100 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 101 102 TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug); 103 TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed); 104 TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug); 105 TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug); 106 107 static void ehci_dump_regs(ehci_softc_t *sc); 108 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 109 110 #endif 111 112 #define EHCI_INTR_ENDPT 1 113 114 static const struct usb_bus_methods ehci_bus_methods; 115 static const struct usb_pipe_methods ehci_device_bulk_methods; 116 static const struct usb_pipe_methods ehci_device_ctrl_methods; 117 static const struct usb_pipe_methods ehci_device_intr_methods; 118 static const struct usb_pipe_methods ehci_device_isoc_fs_methods; 119 static const struct usb_pipe_methods ehci_device_isoc_hs_methods; 120 121 static void ehci_do_poll(struct usb_bus *); 122 static void ehci_device_done(struct usb_xfer *, usb_error_t); 123 static uint8_t ehci_check_transfer(struct usb_xfer *xfer, int finish); 124 static void ehci_timeout(void *); 125 static void ehci_poll_timeout(void *); 126 127 static void ehci_root_intr(ehci_softc_t *sc); 128 129 struct ehci_std_temp { 130 ehci_softc_t *sc; 131 struct usb_page_cache *pc; 132 ehci_qtd_t *td; 133 ehci_qtd_t *td_next; 134 uint32_t average; 135 uint32_t qtd_status; 136 uint32_t len; 137 uint16_t max_frame_size; 138 uint8_t shortpkt; 139 uint8_t auto_data_toggle; 140 uint8_t setup_alt_next; 141 uint8_t last_frame; 142 }; 143 144 void 145 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 146 { 147 ehci_softc_t *sc = EHCI_BUS2SC(bus); 148 uint32_t i; 149 150 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 151 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 152 153 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 154 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 155 156 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 157 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 158 159 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 160 cb(bus, sc->sc_hw.intr_start_pc + i, 161 sc->sc_hw.intr_start_pg + i, 162 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 163 } 164 165 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 166 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 167 sc->sc_hw.isoc_hs_start_pg + i, 168 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 169 } 170 171 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 172 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 173 sc->sc_hw.isoc_fs_start_pg + i, 174 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 175 } 176 } 177 178 usb_error_t 179 ehci_reset(ehci_softc_t *sc) 180 { 181 uint32_t hcr; 182 int i; 183 184 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 185 for (i = 0; i < 100; i++) { 186 usb_pause_mtx(NULL, hz / 128); 187 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 188 if (!hcr) { 189 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) { 190 /* 191 * Force USBMODE as requested. Controllers 192 * may have multiple operating modes. 193 */ 194 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE); 195 if (sc->sc_flags & EHCI_SCFLG_SETMODE) { 196 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST; 197 device_printf(sc->sc_bus.bdev, 198 "set host controller mode\n"); 199 } 200 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) { 201 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE; 202 device_printf(sc->sc_bus.bdev, 203 "set big-endian mode\n"); 204 } 205 EOWRITE4(sc, EHCI_USBMODE, usbmode); 206 } 207 return (0); 208 } 209 } 210 device_printf(sc->sc_bus.bdev, "Reset timeout\n"); 211 return (USB_ERR_IOERROR); 212 } 213 214 static usb_error_t 215 ehci_hcreset(ehci_softc_t *sc) 216 { 217 uint32_t hcr; 218 int i; 219 220 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 221 for (i = 0; i < 100; i++) { 222 usb_pause_mtx(NULL, hz / 128); 223 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 224 if (hcr) 225 break; 226 } 227 if (!hcr) 228 /* 229 * Fall through and try reset anyway even though 230 * Table 2-9 in the EHCI spec says this will result 231 * in undefined behavior. 232 */ 233 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 234 235 return (ehci_reset(sc)); 236 } 237 238 static int 239 ehci_init_sub(struct ehci_softc *sc) 240 { 241 struct usb_page_search buf_res; 242 uint32_t cparams; 243 uint32_t hcr; 244 uint8_t i; 245 246 cparams = EREAD4(sc, EHCI_HCCPARAMS); 247 248 DPRINTF("cparams=0x%x\n", cparams); 249 250 if (EHCI_HCC_64BIT(cparams)) { 251 DPRINTF("HCC uses 64-bit structures\n"); 252 253 /* MUST clear segment register if 64 bit capable */ 254 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 255 } 256 257 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 258 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 259 260 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 261 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 262 263 /* enable interrupts */ 264 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 265 266 /* turn on controller */ 267 EOWRITE4(sc, EHCI_USBCMD, 268 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 269 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 270 EHCI_CMD_ASPME | EHCI_CMD_ASPMC | 271 EHCI_CMD_ASE | 272 EHCI_CMD_PSE | 273 EHCI_CMD_RS); 274 275 /* Take over port ownership */ 276 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 277 278 for (i = 0; i < 100; i++) { 279 usb_pause_mtx(NULL, hz / 128); 280 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 281 if (!hcr) { 282 break; 283 } 284 } 285 if (hcr) { 286 device_printf(sc->sc_bus.bdev, "Run timeout\n"); 287 return (USB_ERR_IOERROR); 288 } 289 return (USB_ERR_NORMAL_COMPLETION); 290 } 291 292 usb_error_t 293 ehci_init(ehci_softc_t *sc) 294 { 295 struct usb_page_search buf_res; 296 uint32_t version; 297 uint32_t sparams; 298 uint16_t i; 299 uint16_t x; 300 uint16_t y; 301 uint16_t bit; 302 usb_error_t err = 0; 303 304 DPRINTF("start\n"); 305 306 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_lock, 0); 307 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_lock, 0); 308 309 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 310 311 #ifdef USB_DEBUG 312 if (ehciiaadbug) 313 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 314 if (ehcilostintrbug) 315 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 316 if (ehcidebug > 2) { 317 ehci_dump_regs(sc); 318 } 319 #endif 320 321 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 322 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 323 version >> 8, version & 0xff); 324 325 sparams = EREAD4(sc, EHCI_HCSPARAMS); 326 DPRINTF("sparams=0x%x\n", sparams); 327 328 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 329 sc->sc_bus.usbrev = USB_REV_2_0; 330 331 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) { 332 /* Reset the controller */ 333 DPRINTF("%s: resetting\n", 334 device_get_nameunit(sc->sc_bus.bdev)); 335 336 err = ehci_hcreset(sc); 337 if (err) { 338 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 339 return (err); 340 } 341 } 342 343 /* 344 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 345 * bytes 2: 256*4 bytes 3: unknown 346 */ 347 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 348 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 349 return (USB_ERR_IOERROR); 350 } 351 /* set up the bus struct */ 352 sc->sc_bus.methods = &ehci_bus_methods; 353 354 sc->sc_eintrs = EHCI_NORMAL_INTRS; 355 356 if (1) { 357 struct ehci_qh_sub *qh; 358 359 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 360 361 qh = buf_res.buffer; 362 363 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 364 365 /* init terminate TD */ 366 qh->qtd_next = 367 htohc32(sc, EHCI_LINK_TERMINATE); 368 qh->qtd_altnext = 369 htohc32(sc, EHCI_LINK_TERMINATE); 370 qh->qtd_status = 371 htohc32(sc, EHCI_QTD_HALTED); 372 } 373 374 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 375 ehci_qh_t *qh; 376 377 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 378 379 qh = buf_res.buffer; 380 381 /* initialize page cache pointer */ 382 383 qh->page_cache = sc->sc_hw.intr_start_pc + i; 384 385 /* store a pointer to queue head */ 386 387 sc->sc_intr_p_last[i] = qh; 388 389 qh->qh_self = 390 htohc32(sc, buf_res.physaddr) | 391 htohc32(sc, EHCI_LINK_QH); 392 393 qh->qh_endp = 394 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 395 qh->qh_endphub = 396 htohc32(sc, EHCI_QH_SET_MULT(1)); 397 qh->qh_curqtd = 0; 398 399 qh->qh_qtd.qtd_next = 400 htohc32(sc, EHCI_LINK_TERMINATE); 401 qh->qh_qtd.qtd_altnext = 402 htohc32(sc, EHCI_LINK_TERMINATE); 403 qh->qh_qtd.qtd_status = 404 htohc32(sc, EHCI_QTD_HALTED); 405 } 406 407 /* 408 * the QHs are arranged to give poll intervals that are 409 * powers of 2 times 1ms 410 * 411 * e.g. 64-127, 32-63, 16-31, 8-15, 4-7, 2-3, 1-1, 0 412 * 1ms 2ms 4ms 8ms 16ms 32ms 64ms 128m 413 */ 414 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 415 while (bit) { 416 x = bit; 417 while (x & bit) { 418 ehci_qh_t *qh_x; 419 ehci_qh_t *qh_y; 420 421 y = (x ^ bit) | (bit / 2); 422 423 qh_x = sc->sc_intr_p_last[x]; 424 qh_y = sc->sc_intr_p_last[y]; 425 426 /* 427 * the next QH has half the poll interval 428 */ 429 qh_x->qh_link = qh_y->qh_self; 430 431 x++; 432 } 433 bit >>= 1; 434 } 435 436 if (1) { 437 ehci_qh_t *qh; 438 439 qh = sc->sc_intr_p_last[0]; 440 441 /* the last (1ms) QH terminates */ 442 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 443 } 444 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 445 ehci_sitd_t *sitd; 446 ehci_itd_t *itd; 447 448 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 449 450 sitd = buf_res.buffer; 451 452 /* initialize page cache pointer */ 453 454 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 455 456 /* store a pointer to the transfer descriptor */ 457 458 sc->sc_isoc_fs_p_last[i] = sitd; 459 460 /* initialize full speed isochronous */ 461 462 sitd->sitd_self = 463 htohc32(sc, buf_res.physaddr) | 464 htohc32(sc, EHCI_LINK_SITD); 465 466 sitd->sitd_back = 467 htohc32(sc, EHCI_LINK_TERMINATE); 468 469 /* 470 * Point to 1ms interrupt queue heads 1:1 471 */ 472 sitd->sitd_next = 473 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 474 475 476 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 477 478 itd = buf_res.buffer; 479 480 /* initialize page cache pointer */ 481 482 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 483 484 /* store a pointer to the transfer descriptor */ 485 486 sc->sc_isoc_hs_p_last[i] = itd; 487 488 /* initialize high speed isochronous */ 489 490 itd->itd_self = 491 htohc32(sc, buf_res.physaddr) | 492 htohc32(sc, EHCI_LINK_ITD); 493 494 /* 495 * 1:1 HS -> FS 496 */ 497 itd->itd_next = 498 sitd->sitd_self; 499 } 500 501 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 502 503 if (1) { 504 uint32_t *pframes; 505 506 pframes = buf_res.buffer; 507 508 /* 509 * execution order: 510 * pframes -> high speed isochronous -> 511 * full speed isochronous -> interrupt QH's 512 * 513 * Each pframe chains through 10 queue heads. 514 * HS FS IQ1ms IQ2ms IQ4ms ... IQ128ms -> term 515 */ 516 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 517 pframes[i] = sc->sc_isoc_hs_p_last 518 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 519 } 520 } 521 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 522 523 /* 524 * Asynchronous schedule requires a QH the points to itself initially. 525 * (it is not terminated with EHCI_LINK_TERMINATE). 526 */ 527 if (1) { 528 529 ehci_qh_t *qh; 530 531 qh = buf_res.buffer; 532 533 /* initialize page cache pointer */ 534 535 qh->page_cache = &sc->sc_hw.async_start_pc; 536 537 /* store a pointer to the queue head */ 538 539 sc->sc_async_p_last = qh; 540 541 /* init dummy QH that starts the async list */ 542 543 qh->qh_self = 544 htohc32(sc, buf_res.physaddr) | 545 htohc32(sc, EHCI_LINK_QH); 546 547 /* fill the QH */ 548 qh->qh_endp = 549 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 550 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 551 qh->qh_link = qh->qh_self; 552 qh->qh_curqtd = 0; 553 554 /* fill the overlay qTD */ 555 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 556 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 557 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 558 } 559 /* flush all cache into memory */ 560 561 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 562 563 #ifdef USB_DEBUG 564 if (ehcidebug) { 565 ehci_dump_sqh(sc, sc->sc_async_p_last); 566 } 567 #endif 568 569 /* finial setup */ 570 err = ehci_init_sub(sc); 571 572 if (!err) { 573 /* catch any lost interrupts */ 574 ehci_do_poll(&sc->sc_bus); 575 } 576 return (err); 577 } 578 579 /* 580 * shut down the controller when the system is going down 581 */ 582 void 583 ehci_detach(ehci_softc_t *sc) 584 { 585 USB_BUS_LOCK(&sc->sc_bus); 586 587 usb_callout_stop(&sc->sc_tmo_pcd); 588 usb_callout_stop(&sc->sc_tmo_poll); 589 590 EOWRITE4(sc, EHCI_USBINTR, 0); 591 USB_BUS_UNLOCK(&sc->sc_bus); 592 593 if (ehci_hcreset(sc)) { 594 DPRINTF("reset failed!\n"); 595 } 596 597 /* XXX let stray task complete */ 598 usb_pause_mtx(NULL, hz / 20); 599 600 usb_callout_drain(&sc->sc_tmo_pcd); 601 usb_callout_drain(&sc->sc_tmo_poll); 602 } 603 604 static void 605 ehci_suspend(ehci_softc_t *sc) 606 { 607 DPRINTF("stopping the HC\n"); 608 609 /* reset HC */ 610 ehci_hcreset(sc); 611 } 612 613 static void 614 ehci_resume(ehci_softc_t *sc) 615 { 616 /* reset HC */ 617 ehci_hcreset(sc); 618 619 /* setup HC */ 620 ehci_init_sub(sc); 621 622 /* catch any lost interrupts */ 623 ehci_do_poll(&sc->sc_bus); 624 } 625 626 #ifdef USB_DEBUG 627 static void 628 ehci_dump_regs(ehci_softc_t *sc) 629 { 630 uint32_t i; 631 632 i = EOREAD4(sc, EHCI_USBCMD); 633 kprintf("cmd=0x%08x\n", i); 634 635 if (i & EHCI_CMD_ITC_1) 636 kprintf(" EHCI_CMD_ITC_1\n"); 637 if (i & EHCI_CMD_ITC_2) 638 kprintf(" EHCI_CMD_ITC_2\n"); 639 if (i & EHCI_CMD_ITC_4) 640 kprintf(" EHCI_CMD_ITC_4\n"); 641 if (i & EHCI_CMD_ITC_8) 642 kprintf(" EHCI_CMD_ITC_8\n"); 643 if (i & EHCI_CMD_ITC_16) 644 kprintf(" EHCI_CMD_ITC_16\n"); 645 if (i & EHCI_CMD_ITC_32) 646 kprintf(" EHCI_CMD_ITC_32\n"); 647 if (i & EHCI_CMD_ITC_64) 648 kprintf(" EHCI_CMD_ITC_64\n"); 649 if (i & EHCI_CMD_ASPME) 650 kprintf(" EHCI_CMD_ASPME\n"); 651 if (i & EHCI_CMD_ASPMC) 652 kprintf(" EHCI_CMD_ASPMC\n"); 653 if (i & EHCI_CMD_LHCR) 654 kprintf(" EHCI_CMD_LHCR\n"); 655 if (i & EHCI_CMD_IAAD) 656 kprintf(" EHCI_CMD_IAAD\n"); 657 if (i & EHCI_CMD_ASE) 658 kprintf(" EHCI_CMD_ASE\n"); 659 if (i & EHCI_CMD_PSE) 660 kprintf(" EHCI_CMD_PSE\n"); 661 if (i & EHCI_CMD_FLS_M) 662 kprintf(" EHCI_CMD_FLS_M\n"); 663 if (i & EHCI_CMD_HCRESET) 664 kprintf(" EHCI_CMD_HCRESET\n"); 665 if (i & EHCI_CMD_RS) 666 kprintf(" EHCI_CMD_RS\n"); 667 668 i = EOREAD4(sc, EHCI_USBSTS); 669 670 kprintf("sts=0x%08x\n", i); 671 672 if (i & EHCI_STS_ASS) 673 kprintf(" EHCI_STS_ASS\n"); 674 if (i & EHCI_STS_PSS) 675 kprintf(" EHCI_STS_PSS\n"); 676 if (i & EHCI_STS_REC) 677 kprintf(" EHCI_STS_REC\n"); 678 if (i & EHCI_STS_HCH) 679 kprintf(" EHCI_STS_HCH\n"); 680 if (i & EHCI_STS_IAA) 681 kprintf(" EHCI_STS_IAA\n"); 682 if (i & EHCI_STS_HSE) 683 kprintf(" EHCI_STS_HSE\n"); 684 if (i & EHCI_STS_FLR) 685 kprintf(" EHCI_STS_FLR\n"); 686 if (i & EHCI_STS_PCD) 687 kprintf(" EHCI_STS_PCD\n"); 688 if (i & EHCI_STS_ERRINT) 689 kprintf(" EHCI_STS_ERRINT\n"); 690 if (i & EHCI_STS_INT) 691 kprintf(" EHCI_STS_INT\n"); 692 693 kprintf("ien=0x%08x\n", 694 EOREAD4(sc, EHCI_USBINTR)); 695 kprintf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 696 EOREAD4(sc, EHCI_FRINDEX), 697 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 698 EOREAD4(sc, EHCI_PERIODICLISTBASE), 699 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 700 for (i = 1; i <= sc->sc_noport; i++) { 701 kprintf("port %d status=0x%08x\n", i, 702 EOREAD4(sc, EHCI_PORTSC(i))); 703 } 704 } 705 706 static void 707 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 708 { 709 link = hc32toh(sc, link); 710 kprintf("0x%08x", link); 711 if (link & EHCI_LINK_TERMINATE) 712 kprintf("<T>"); 713 else { 714 kprintf("<"); 715 if (type) { 716 switch (EHCI_LINK_TYPE(link)) { 717 case EHCI_LINK_ITD: 718 kprintf("ITD"); 719 break; 720 case EHCI_LINK_QH: 721 kprintf("QH"); 722 break; 723 case EHCI_LINK_SITD: 724 kprintf("SITD"); 725 break; 726 case EHCI_LINK_FSTN: 727 kprintf("FSTN"); 728 break; 729 } 730 } 731 kprintf(">"); 732 } 733 } 734 735 static void 736 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 737 { 738 uint32_t s; 739 740 kprintf(" next="); 741 ehci_dump_link(sc, qtd->qtd_next, 0); 742 kprintf(" altnext="); 743 ehci_dump_link(sc, qtd->qtd_altnext, 0); 744 kprintf("\n"); 745 s = hc32toh(sc, qtd->qtd_status); 746 kprintf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 747 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 748 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 749 kprintf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 750 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 751 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 752 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 753 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 754 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 755 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 756 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 757 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 758 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 759 760 for (s = 0; s < 5; s++) { 761 kprintf(" buffer[%d]=0x%08x\n", s, 762 hc32toh(sc, qtd->qtd_buffer[s])); 763 } 764 for (s = 0; s < 5; s++) { 765 kprintf(" buffer_hi[%d]=0x%08x\n", s, 766 hc32toh(sc, qtd->qtd_buffer_hi[s])); 767 } 768 } 769 770 static uint8_t 771 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 772 { 773 uint8_t temp; 774 775 usb_pc_cpu_invalidate(sqtd->page_cache); 776 kprintf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 777 ehci_dump_qtd(sc, sqtd); 778 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 779 return (temp); 780 } 781 782 static void 783 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 784 { 785 uint16_t i; 786 uint8_t stop; 787 788 stop = 0; 789 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 790 stop = ehci_dump_sqtd(sc, sqtd); 791 } 792 if (sqtd) { 793 kprintf("dump aborted, too many TDs\n"); 794 } 795 } 796 797 static void 798 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 799 { 800 uint32_t endp; 801 uint32_t endphub; 802 803 usb_pc_cpu_invalidate(qh->page_cache); 804 kprintf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 805 kprintf(" link="); 806 ehci_dump_link(sc, qh->qh_link, 1); 807 kprintf("\n"); 808 endp = hc32toh(sc, qh->qh_endp); 809 kprintf(" endp=0x%08x\n", endp); 810 kprintf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 811 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 812 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 813 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 814 kprintf(" mpl=0x%x ctl=%d nrl=%d\n", 815 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 816 EHCI_QH_GET_NRL(endp)); 817 endphub = hc32toh(sc, qh->qh_endphub); 818 kprintf(" endphub=0x%08x\n", endphub); 819 kprintf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 820 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 821 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 822 EHCI_QH_GET_MULT(endphub)); 823 kprintf(" curqtd="); 824 ehci_dump_link(sc, qh->qh_curqtd, 0); 825 kprintf("\n"); 826 kprintf("Overlay qTD:\n"); 827 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 828 } 829 830 static void 831 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 832 { 833 usb_pc_cpu_invalidate(sitd->page_cache); 834 kprintf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 835 kprintf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 836 kprintf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 837 hc32toh(sc, sitd->sitd_portaddr), 838 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 839 ? "in" : "out", 840 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 841 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 842 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 843 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 844 kprintf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 845 kprintf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 846 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 847 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 848 kprintf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 849 hc32toh(sc, sitd->sitd_back), 850 hc32toh(sc, sitd->sitd_bp[0]), 851 hc32toh(sc, sitd->sitd_bp[1]), 852 hc32toh(sc, sitd->sitd_bp_hi[0]), 853 hc32toh(sc, sitd->sitd_bp_hi[1])); 854 } 855 856 static void 857 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 858 { 859 usb_pc_cpu_invalidate(itd->page_cache); 860 kprintf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 861 kprintf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 862 kprintf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 863 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 864 kprintf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 865 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 866 kprintf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 867 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 868 kprintf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 869 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 870 kprintf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 871 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 872 kprintf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 873 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 874 kprintf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 875 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 876 kprintf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 877 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 878 kprintf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 879 kprintf(" addr=0x%02x; endpt=0x%01x\n", 880 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 881 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 882 kprintf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 883 kprintf(" dir=%s; mpl=0x%02x\n", 884 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 885 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 886 kprintf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 887 hc32toh(sc, itd->itd_bp[2]), 888 hc32toh(sc, itd->itd_bp[3]), 889 hc32toh(sc, itd->itd_bp[4]), 890 hc32toh(sc, itd->itd_bp[5]), 891 hc32toh(sc, itd->itd_bp[6])); 892 kprintf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 893 " 0x%08x,0x%08x,0x%08x\n", 894 hc32toh(sc, itd->itd_bp_hi[0]), 895 hc32toh(sc, itd->itd_bp_hi[1]), 896 hc32toh(sc, itd->itd_bp_hi[2]), 897 hc32toh(sc, itd->itd_bp_hi[3]), 898 hc32toh(sc, itd->itd_bp_hi[4]), 899 hc32toh(sc, itd->itd_bp_hi[5]), 900 hc32toh(sc, itd->itd_bp_hi[6])); 901 } 902 903 static void 904 ehci_dump_isoc(ehci_softc_t *sc) 905 { 906 ehci_itd_t *itd; 907 ehci_sitd_t *sitd; 908 uint16_t max = 1000; 909 uint16_t pos; 910 911 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 912 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 913 914 kprintf("%s: isochronous dump from frame 0x%03x:\n", 915 __func__, pos); 916 917 itd = sc->sc_isoc_hs_p_last[pos]; 918 sitd = sc->sc_isoc_fs_p_last[pos]; 919 920 while (itd && max && max--) { 921 ehci_dump_itd(sc, itd); 922 itd = itd->prev; 923 } 924 925 while (sitd && max && max--) { 926 ehci_dump_sitd(sc, sitd); 927 sitd = sitd->prev; 928 } 929 } 930 931 #endif 932 933 static void 934 ehci_ring_doorbell(ehci_softc_t *sc, struct usb_xfer *xfer) 935 { 936 uint32_t temp; 937 938 /* 939 * Request a doorbell interrupt. We can't safely disturb previously 940 * used QH's until controller has synchronized the list changes we've 941 * made. 942 * 943 * Deal with controller races if a doorbell has already been 944 * requested, we have to wait 2 doorbells in this case to be sure. 945 * 946 * (interlocked against races by the bus lock) 947 */ 948 temp = EOREAD4(sc, EHCI_USBCMD); 949 if (sc->doorbell_again == 0) { 950 if ((temp & EHCI_CMD_IAAD) == 0) 951 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 952 if (xfer) 953 xfer->doorbell_match = sc->doorbell_match + 1; 954 sc->doorbell_again = 1; 955 } else { 956 if ((temp & EHCI_CMD_IAAD) == 0) 957 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 958 if (xfer) 959 xfer->doorbell_match = sc->doorbell_match + 2; 960 sc->doorbell_again = 2; 961 } 962 } 963 964 static void 965 ehci_wait_doorbell(ehci_softc_t *sc, int match) 966 { 967 while ((int)(match - sc->doorbell_match) > 0) 968 lksleep(sc, &sc->sc_bus.bus_lock, 0, "ehcidoor", hz); 969 } 970 971 static void 972 ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 973 { 974 /* check for early completion */ 975 if (ehci_check_transfer(xfer, 1)) { 976 return; 977 } 978 /* put transfer on interrupt queue */ 979 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 980 981 /* start timeout, if any */ 982 if (xfer->timeout != 0) { 983 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 984 } 985 } 986 987 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 988 static ehci_sitd_t * 989 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 990 { 991 DPRINTFN(11, "%p to %p\n", std, last); 992 993 /* (sc->sc_bus.mtx) must be locked */ 994 995 std->next = last->next; 996 std->sitd_next = last->sitd_next; 997 998 std->prev = last; 999 1000 usb_pc_cpu_flush(std->page_cache); 1001 1002 /* 1003 * the last->next->prev is never followed: std->next->prev = std; 1004 */ 1005 last->next = std; 1006 last->sitd_next = std->sitd_self; 1007 1008 usb_pc_cpu_flush(last->page_cache); 1009 1010 return (std); 1011 } 1012 1013 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 1014 static ehci_itd_t * 1015 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1016 { 1017 DPRINTFN(11, "%p to %p\n", std, last); 1018 1019 /* (sc->sc_bus.mtx) must be locked */ 1020 1021 std->next = last->next; 1022 std->itd_next = last->itd_next; 1023 1024 std->prev = last; 1025 1026 usb_pc_cpu_flush(std->page_cache); 1027 1028 /* 1029 * the last->next->prev is never followed: std->next->prev = std; 1030 */ 1031 last->next = std; 1032 last->itd_next = std->itd_self; 1033 1034 usb_pc_cpu_flush(last->page_cache); 1035 1036 return (std); 1037 } 1038 1039 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 1040 static ehci_qh_t * 1041 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1042 { 1043 DPRINTFN(11, "%p to %p\n", sqh, last); 1044 1045 if (sqh->prev != NULL) { 1046 /* should not happen */ 1047 DPRINTFN(0, "QH already linked!\n"); 1048 return (last); 1049 } 1050 /* (sc->sc_bus.mtx) must be locked */ 1051 1052 sqh->next = last->next; 1053 sqh->qh_link = last->qh_link; 1054 1055 sqh->prev = last; 1056 1057 usb_pc_cpu_flush(sqh->page_cache); 1058 1059 /* 1060 * The last->next->prev is never followed: sqh->next->prev = sqh; 1061 * 1062 * This should activate the command. 1063 */ 1064 1065 last->next = sqh; 1066 last->qh_link = sqh->qh_self; 1067 1068 usb_pc_cpu_flush(last->page_cache); 1069 1070 return (sqh); 1071 } 1072 1073 static void 1074 ehci_stop_xfer(struct usb_xfer *xfer) 1075 { 1076 #if 0 1077 if (xfer->flags_int.onhwqueue == 0) 1078 return; 1079 return; 1080 if (ehci_check_transfer(xfer, 0)) 1081 return; 1082 kprintf("R"); 1083 retry = 10; 1084 while (retry && ehci_check_transfer(xfer, 0) == 0) { 1085 kprintf("R"); 1086 DELAY(10000); 1087 --retry; 1088 } 1089 if (retry == 0) 1090 kprintf("[can't stop xfer]\n"); 1091 #endif 1092 } 1093 1094 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1095 static ehci_sitd_t * 1096 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1097 { 1098 DPRINTFN(11, "%p from %p\n", std, last); 1099 1100 /* (sc->sc_bus.mtx) must be locked */ 1101 1102 std->prev->next = std->next; 1103 std->prev->sitd_next = std->sitd_next; 1104 1105 usb_pc_cpu_flush(std->prev->page_cache); 1106 1107 if (std->next) { 1108 std->next->prev = std->prev; 1109 usb_pc_cpu_flush(std->next->page_cache); 1110 } 1111 return ((last == std) ? std->prev : last); 1112 } 1113 1114 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1115 static ehci_itd_t * 1116 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1117 { 1118 DPRINTFN(11, "%p from %p\n", std, last); 1119 1120 /* (sc->sc_bus.mtx) must be locked */ 1121 1122 std->prev->next = std->next; 1123 std->prev->itd_next = std->itd_next; 1124 1125 usb_pc_cpu_flush(std->prev->page_cache); 1126 1127 if (std->next) { 1128 std->next->prev = std->prev; 1129 usb_pc_cpu_flush(std->next->page_cache); 1130 } 1131 return ((last == std) ? std->prev : last); 1132 } 1133 1134 #define EHCI_REMOVE_QH(sc,sqh,last) (last) = _ehci_remove_qh(sc,sqh,last) 1135 static ehci_qh_t * 1136 _ehci_remove_qh(ehci_softc_t *sc, ehci_qh_t *sqh, ehci_qh_t *last) 1137 { 1138 DPRINTFN(11, "%p from %p\n", sqh, last); 1139 1140 /* (sc->sc_bus.mtx) must be locked */ 1141 1142 /* only remove if not removed from a queue */ 1143 if (sqh->prev) { 1144 sqh->prev->next = sqh->next; 1145 if (sqh->next) 1146 sqh->next->prev = sqh->prev; 1147 last = ((last == sqh) ? sqh->prev : last); 1148 1149 /* 1150 * This is a horrible hack because basically the entire 1151 * U4B QH handling is broken. To do this correctly the 1152 * QH needs be unlinked but then not touched until the 1153 * next rollup doorbell interrupt. That is, the controller 1154 * could be racing us accessing the QH and qh_link, so 1155 * the links have to remain valid enough to not cause the 1156 * controller to blow up. 1157 * 1158 * When we mess with the links it is possible for the 1159 * controller to end up on the deleted chain(s) and miss 1160 * new requests entered after the deletion. Then it thinks 1161 * it is finished and stops scanning. Thus we must issue a 1162 * doorbell to force the controller to re-scan and pick 1163 * up anything it missed if it got off-track. 1164 * 1165 * I wanted to try to make this more reliable by setting 1166 * qh_link to htohc32(sc, EHCI_LINK_TERMINATE), but it 1167 * doesn't work. The controller barfs badly and isn't 1168 * able to probe all the usb devices. I'm not sure 1169 * why it doesn't work but... whatever. 1170 */ 1171 sqh->prev->qh_link = sqh->qh_link; 1172 usb_pc_cpu_flush(sqh->prev->page_cache); 1173 /* sqh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); */ 1174 #if 0 1175 if ((sc->sc_flags & EHCI_SCFLG_IAADBUG) == 0) { 1176 uint32_t temp = EOREAD4(sc, EHCI_USBCMD); 1177 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 1178 } 1179 #endif 1180 sqh->prev = NULL; 1181 usb_pc_cpu_flush(sqh->page_cache); 1182 } 1183 return (last); 1184 } 1185 1186 static void 1187 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1188 { 1189 uint16_t rem; 1190 uint8_t dt; 1191 1192 /* count number of full packets */ 1193 dt = (actlen / xfer->max_packet_size) & 1; 1194 1195 /* compute remainder */ 1196 rem = actlen % xfer->max_packet_size; 1197 1198 if (rem > 0) 1199 dt ^= 1; /* short packet at the end */ 1200 else if (actlen != xlen) 1201 dt ^= 1; /* zero length packet at the end */ 1202 else if (xlen == 0) 1203 dt ^= 1; /* zero length transfer */ 1204 1205 xfer->endpoint->toggle_next ^= dt; 1206 } 1207 1208 static usb_error_t 1209 ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1210 { 1211 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1212 ehci_qtd_t *td; 1213 ehci_qtd_t *td_alt_next; 1214 uint32_t status; 1215 uint16_t len; 1216 1217 td = xfer->td_transfer_cache; 1218 td_alt_next = td->alt_next; 1219 1220 if (xfer->aframes != xfer->nframes) { 1221 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1222 } 1223 while (1) { 1224 usb_pc_cpu_invalidate(td->page_cache); 1225 status = hc32toh(sc, td->qtd_status); 1226 1227 len = EHCI_QTD_GET_BYTES(status); 1228 1229 /* 1230 * Verify the status length and 1231 * add the length to "frlengths[]": 1232 */ 1233 if (len > td->len) { 1234 /* should not happen */ 1235 DPRINTF("Invalid status length, " 1236 "0x%04x/0x%04x bytes\n", len, td->len); 1237 status |= EHCI_QTD_HALTED; 1238 } else if (xfer->aframes != xfer->nframes) { 1239 xfer->frlengths[xfer->aframes] += td->len - len; 1240 /* manually update data toggle */ 1241 ehci_data_toggle_update(xfer, td->len - len, td->len); 1242 } 1243 1244 /* Check for last transfer */ 1245 if (((void *)td) == xfer->td_transfer_last) { 1246 td = NULL; 1247 break; 1248 } 1249 /* Check for transfer error */ 1250 if (status & EHCI_QTD_HALTED) { 1251 /* the transfer is finished */ 1252 td = NULL; 1253 break; 1254 } 1255 /* Check for short transfer */ 1256 if (len > 0) { 1257 if (xfer->flags_int.short_frames_ok) { 1258 /* follow alt next */ 1259 td = td->alt_next; 1260 } else { 1261 /* the transfer is finished */ 1262 td = NULL; 1263 } 1264 break; 1265 } 1266 td = td->obj_next; 1267 1268 if (td->alt_next != td_alt_next) { 1269 /* this USB frame is complete */ 1270 break; 1271 } 1272 } 1273 1274 /* update transfer cache */ 1275 1276 xfer->td_transfer_cache = td; 1277 1278 #ifdef USB_DEBUG 1279 if (status & EHCI_QTD_STATERRS) { 1280 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1281 "status=%s%s%s%s%s%s%s%s\n", 1282 xfer->address, xfer->endpointno, xfer->aframes, 1283 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1284 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1285 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1286 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1287 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1288 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1289 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1290 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1291 } 1292 #endif 1293 1294 return ((status & EHCI_QTD_HALTED) ? 1295 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1296 } 1297 1298 static void 1299 ehci_non_isoc_done(struct usb_xfer *xfer) 1300 { 1301 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1302 ehci_qh_t *qh; 1303 uint32_t status; 1304 usb_error_t err = 0; 1305 1306 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1307 xfer, xfer->endpoint); 1308 1309 #ifdef USB_DEBUG 1310 if (ehcidebug > 10) { 1311 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1312 1313 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1314 } 1315 #endif 1316 1317 /* extract data toggle directly from the QH's overlay area */ 1318 1319 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1320 1321 usb_pc_cpu_invalidate(qh->page_cache); 1322 1323 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1324 1325 /* reset scanner */ 1326 1327 xfer->td_transfer_cache = xfer->td_transfer_first; 1328 1329 if (xfer->flags_int.control_xfr) { 1330 1331 if (xfer->flags_int.control_hdr) { 1332 1333 err = ehci_non_isoc_done_sub(xfer); 1334 } 1335 xfer->aframes = 1; 1336 1337 if (xfer->td_transfer_cache == NULL) { 1338 goto done; 1339 } 1340 } 1341 while (xfer->aframes != xfer->nframes) { 1342 1343 err = ehci_non_isoc_done_sub(xfer); 1344 xfer->aframes++; 1345 1346 if (xfer->td_transfer_cache == NULL) { 1347 goto done; 1348 } 1349 } 1350 1351 if (xfer->flags_int.control_xfr && 1352 !xfer->flags_int.control_act) { 1353 1354 err = ehci_non_isoc_done_sub(xfer); 1355 } 1356 done: 1357 ehci_device_done(xfer, err); 1358 } 1359 1360 /*------------------------------------------------------------------------* 1361 * ehci_check_transfer 1362 * 1363 * Return values: 1364 * 0: USB transfer is not finished 1365 * Else: USB transfer is finished 1366 *------------------------------------------------------------------------*/ 1367 static uint8_t 1368 ehci_check_transfer(struct usb_xfer *xfer, int finish) 1369 { 1370 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1371 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1372 1373 uint32_t status; 1374 1375 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1376 1377 if (methods == &ehci_device_isoc_fs_methods) { 1378 ehci_sitd_t *td; 1379 1380 /* isochronous full speed transfer */ 1381 1382 td = xfer->td_transfer_last; 1383 usb_pc_cpu_invalidate(td->page_cache); 1384 status = hc32toh(sc, td->sitd_status); 1385 1386 /* also check if first is complete */ 1387 1388 td = xfer->td_transfer_first; 1389 usb_pc_cpu_invalidate(td->page_cache); 1390 status |= hc32toh(sc, td->sitd_status); 1391 1392 if (!(status & EHCI_SITD_ACTIVE)) { 1393 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1394 goto transferred; 1395 } 1396 } else if (methods == &ehci_device_isoc_hs_methods) { 1397 ehci_itd_t *td; 1398 1399 /* isochronous high speed transfer */ 1400 1401 /* check last transfer */ 1402 td = xfer->td_transfer_last; 1403 usb_pc_cpu_invalidate(td->page_cache); 1404 status = td->itd_status[0]; 1405 status |= td->itd_status[1]; 1406 status |= td->itd_status[2]; 1407 status |= td->itd_status[3]; 1408 status |= td->itd_status[4]; 1409 status |= td->itd_status[5]; 1410 status |= td->itd_status[6]; 1411 status |= td->itd_status[7]; 1412 1413 /* also check first transfer */ 1414 td = xfer->td_transfer_first; 1415 usb_pc_cpu_invalidate(td->page_cache); 1416 status |= td->itd_status[0]; 1417 status |= td->itd_status[1]; 1418 status |= td->itd_status[2]; 1419 status |= td->itd_status[3]; 1420 status |= td->itd_status[4]; 1421 status |= td->itd_status[5]; 1422 status |= td->itd_status[6]; 1423 status |= td->itd_status[7]; 1424 1425 /* if no transactions are active we continue */ 1426 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1427 if (finish) { 1428 ehci_device_done(xfer, 1429 USB_ERR_NORMAL_COMPLETION); 1430 } 1431 goto transferred; 1432 } 1433 } else { 1434 ehci_qtd_t *td; 1435 ehci_qh_t *qh; 1436 1437 /* non-isochronous transfer */ 1438 1439 /* 1440 * check whether there is an error somewhere in the middle, 1441 * or whether there was a short packet (SPD and not ACTIVE) 1442 */ 1443 td = xfer->td_transfer_cache; 1444 1445 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1446 1447 usb_pc_cpu_invalidate(qh->page_cache); 1448 1449 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1450 if (status & EHCI_QTD_ACTIVE) { 1451 /* transfer is pending */ 1452 goto done; 1453 } 1454 1455 while (1) { 1456 usb_pc_cpu_invalidate(td->page_cache); 1457 status = hc32toh(sc, td->qtd_status); 1458 1459 /* 1460 * Check if there is an active TD which 1461 * indicates that the transfer isn't done. 1462 */ 1463 if (status & EHCI_QTD_ACTIVE) { 1464 /* update cache */ 1465 xfer->td_transfer_cache = td; 1466 goto done; 1467 } 1468 /* 1469 * last transfer descriptor makes the transfer done 1470 */ 1471 if (((void *)td) == xfer->td_transfer_last) { 1472 break; 1473 } 1474 /* 1475 * any kind of error makes the transfer done 1476 */ 1477 if (status & EHCI_QTD_HALTED) { 1478 break; 1479 } 1480 /* 1481 * if there is no alternate next transfer, a short 1482 * packet also makes the transfer done 1483 */ 1484 if (EHCI_QTD_GET_BYTES(status)) { 1485 if (xfer->flags_int.short_frames_ok) { 1486 /* follow alt next */ 1487 if (td->alt_next) { 1488 td = td->alt_next; 1489 continue; 1490 } 1491 } 1492 /* transfer is done */ 1493 break; 1494 } 1495 td = td->obj_next; 1496 } 1497 if (finish) 1498 ehci_non_isoc_done(xfer); 1499 goto transferred; 1500 } 1501 1502 done: 1503 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1504 return (0); 1505 1506 transferred: 1507 return (1); 1508 } 1509 1510 static void 1511 ehci_pcd_enable(ehci_softc_t *sc) 1512 { 1513 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 1514 1515 sc->sc_eintrs |= EHCI_STS_PCD; 1516 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1517 1518 /* acknowledge any PCD interrupt */ 1519 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1520 1521 ehci_root_intr(sc); 1522 } 1523 1524 static void 1525 ehci_interrupt_poll(ehci_softc_t *sc) 1526 { 1527 struct usb_xfer *xfer; 1528 1529 repeat: 1530 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1531 /* 1532 * check if transfer is transferred 1533 */ 1534 if (ehci_check_transfer(xfer, 1)) { 1535 /* queue has been modified */ 1536 goto repeat; 1537 } 1538 } 1539 } 1540 1541 /* 1542 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1543 * writing back the qTD status, or miss signalling occasionally under 1544 * heavy load. If the host machine is too fast, we can miss 1545 * transaction completion - when we scan the active list the 1546 * transaction still seems to be active. This generally exhibits 1547 * itself as a umass stall that never recovers. 1548 * 1549 * We work around this behaviour by setting up this callback after any 1550 * softintr that completes with transactions still pending, giving us 1551 * another chance to check for completion after the writeback has 1552 * taken place. 1553 */ 1554 static void 1555 ehci_poll_timeout(void *arg) 1556 { 1557 ehci_softc_t *sc = arg; 1558 1559 DPRINTFN(3, "\n"); 1560 ehci_interrupt_poll(sc); 1561 } 1562 1563 /*------------------------------------------------------------------------* 1564 * ehci_interrupt - EHCI interrupt handler 1565 * 1566 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1567 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1568 * is present ! 1569 *------------------------------------------------------------------------*/ 1570 void 1571 ehci_interrupt(ehci_softc_t *sc) 1572 { 1573 uint32_t status; 1574 1575 USB_BUS_LOCK(&sc->sc_bus); 1576 1577 DPRINTFN(16, "real interrupt\n"); 1578 1579 #ifdef USB_DEBUG 1580 if (ehcidebug > 15) { 1581 ehci_dump_regs(sc); 1582 } 1583 #endif 1584 1585 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1586 #if 0 1587 /* 1588 * XXX hack workaround bug where interrupt status says 1589 * nothing is pending but xfer completions might be present. 1590 */ 1591 if (status == 0) { 1592 /* the interrupt was not for us */ 1593 goto done; 1594 } 1595 if (!(status & sc->sc_eintrs)) { 1596 goto done; 1597 } 1598 #endif 1599 /* 1600 * Acknowlege interrupts except IAA 1601 */ 1602 EOWRITE4(sc, EHCI_USBSTS, status); 1603 1604 status &= sc->sc_eintrs; 1605 1606 if (status & EHCI_STS_HSE) { 1607 kprintf("%s: unrecoverable error, " 1608 "controller halted\n", __func__); 1609 #ifdef USB_DEBUG 1610 ehci_dump_regs(sc); 1611 ehci_dump_isoc(sc); 1612 #endif 1613 } 1614 if (status & EHCI_STS_PCD) { 1615 /* 1616 * Disable PCD interrupt for now, because it will be 1617 * on until the port has been reset. 1618 */ 1619 sc->sc_eintrs &= ~EHCI_STS_PCD; 1620 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1621 1622 ehci_root_intr(sc); 1623 1624 /* do not allow RHSC interrupts > 1 per second */ 1625 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1626 (void *)&ehci_pcd_enable, sc); 1627 } 1628 1629 /* 1630 * Handle IAA doorbells, acknowledge IAA after clearing CMD_IAAD. 1631 * 1632 * The frontend may have tried to ring the doorbell after it had 1633 * already been rung, in which case it has to wait for two doorbells. 1634 * We track this with the doorbell_again counter. This counter never 1635 * goes above 2. 1636 * 1637 * NOTE: ehci_ring_doorbell() bumps doorbell_again so we need to 1638 * decrement it twice to net-out at a single decrement. 1639 */ 1640 if (status & EHCI_STS_IAA) { 1641 ++sc->doorbell_match; 1642 wakeup(sc); 1643 if (sc->doorbell_again && --sc->doorbell_again > 0) { 1644 --sc->doorbell_again; 1645 ehci_ring_doorbell(sc, NULL); 1646 } 1647 } 1648 1649 /* 1650 * Block unprocessed interrupts 1651 */ 1652 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | 1653 EHCI_STS_PCD | EHCI_STS_IAA); 1654 if (status != 0) { 1655 sc->sc_eintrs &= ~status; 1656 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1657 kprintf("%s: blocking interrupts 0x%x\n", __func__, status); 1658 } 1659 1660 /* poll all the USB transfers */ 1661 ehci_interrupt_poll(sc); 1662 1663 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1664 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1665 (void *)&ehci_poll_timeout, sc); 1666 } 1667 1668 #if 0 1669 done: 1670 #endif 1671 USB_BUS_UNLOCK(&sc->sc_bus); 1672 } 1673 1674 /* 1675 * called when a request does not complete 1676 */ 1677 static void 1678 ehci_timeout(void *arg) 1679 { 1680 struct usb_xfer *xfer = arg; 1681 1682 DPRINTF("xfer=%p\n", xfer); 1683 1684 USB_BUS_LOCK_ASSERT(xfer->xroot->bus); 1685 1686 /* transfer is transferred */ 1687 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1688 } 1689 1690 static void 1691 ehci_do_poll(struct usb_bus *bus) 1692 { 1693 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1694 1695 USB_BUS_LOCK(&sc->sc_bus); 1696 ehci_interrupt_poll(sc); 1697 USB_BUS_UNLOCK(&sc->sc_bus); 1698 } 1699 1700 static void 1701 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1702 { 1703 struct usb_page_search buf_res; 1704 ehci_qtd_t *td; 1705 ehci_qtd_t *td_next; 1706 ehci_qtd_t *td_alt_next; 1707 uint32_t buf_offset; 1708 uint32_t average; 1709 uint32_t len_old; 1710 uint32_t terminate; 1711 uint32_t qtd_altnext; 1712 uint8_t shortpkt_old; 1713 uint8_t precompute; 1714 1715 terminate = temp->sc->sc_terminate_self; 1716 qtd_altnext = temp->sc->sc_terminate_self; 1717 td_alt_next = NULL; 1718 buf_offset = 0; 1719 shortpkt_old = temp->shortpkt; 1720 len_old = temp->len; 1721 precompute = 1; 1722 1723 restart: 1724 1725 td = temp->td; /* starts out NULL */ 1726 td_next = temp->td_next; /* starts with first td */ 1727 1728 while (1) { 1729 1730 if (temp->len == 0) { 1731 1732 if (temp->shortpkt) { 1733 break; 1734 } 1735 /* send a Zero Length Packet, ZLP, last */ 1736 1737 temp->shortpkt = 1; 1738 average = 0; 1739 1740 } else { 1741 1742 average = temp->average; 1743 1744 if (average > temp->len) { 1745 if (temp->len % temp->max_frame_size) { 1746 temp->shortpkt = 1; 1747 } 1748 average = temp->len; 1749 } 1750 } 1751 1752 if (td_next == NULL) { 1753 panic("%s: out of EHCI transfer descriptors!", __func__); 1754 } 1755 /* get next TD */ 1756 1757 td = td_next; 1758 td_next = td->obj_next; 1759 1760 /* check if we are pre-computing */ 1761 1762 if (precompute) { 1763 1764 /* update remaining length */ 1765 1766 temp->len -= average; 1767 1768 continue; 1769 } 1770 /* fill out current TD */ 1771 1772 td->qtd_status = 1773 temp->qtd_status | 1774 htohc32(temp->sc, EHCI_QTD_IOC | 1775 EHCI_QTD_SET_BYTES(average)); 1776 1777 if (average == 0) { 1778 1779 if (temp->auto_data_toggle == 0) { 1780 1781 /* update data toggle, ZLP case */ 1782 1783 temp->qtd_status ^= 1784 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1785 } 1786 td->len = 0; 1787 1788 td->qtd_buffer[0] = 0; 1789 td->qtd_buffer_hi[0] = 0; 1790 1791 td->qtd_buffer[1] = 0; 1792 td->qtd_buffer_hi[1] = 0; 1793 1794 } else { 1795 1796 uint8_t x; 1797 1798 if (temp->auto_data_toggle == 0) { 1799 1800 /* update data toggle */ 1801 1802 if (((average + temp->max_frame_size - 1) / 1803 temp->max_frame_size) & 1) { 1804 temp->qtd_status ^= 1805 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1806 } 1807 } 1808 td->len = average; 1809 1810 /* update remaining length */ 1811 1812 temp->len -= average; 1813 1814 /* fill out buffer pointers */ 1815 1816 usbd_get_page(temp->pc, buf_offset, &buf_res); 1817 td->qtd_buffer[0] = 1818 htohc32(temp->sc, buf_res.physaddr); 1819 td->qtd_buffer_hi[0] = 0; 1820 1821 x = 1; 1822 1823 while (average > EHCI_PAGE_SIZE) { 1824 average -= EHCI_PAGE_SIZE; 1825 buf_offset += EHCI_PAGE_SIZE; 1826 usbd_get_page(temp->pc, buf_offset, &buf_res); 1827 td->qtd_buffer[x] = 1828 htohc32(temp->sc, 1829 buf_res.physaddr & (~0xFFF)); 1830 td->qtd_buffer_hi[x] = 0; 1831 x++; 1832 } 1833 1834 /* 1835 * NOTE: The "average" variable is never zero after 1836 * exiting the loop above ! 1837 * 1838 * NOTE: We have to subtract one from the offset to 1839 * ensure that we are computing the physical address 1840 * of a valid page ! 1841 */ 1842 buf_offset += average; 1843 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1844 td->qtd_buffer[x] = 1845 htohc32(temp->sc, 1846 buf_res.physaddr & (~0xFFF)); 1847 td->qtd_buffer_hi[x] = 0; 1848 } 1849 1850 if (td_next) { 1851 /* link the current TD with the next one */ 1852 td->qtd_next = td_next->qtd_self; 1853 } 1854 td->qtd_altnext = qtd_altnext; 1855 td->alt_next = td_alt_next; 1856 1857 usb_pc_cpu_flush(td->page_cache); 1858 } 1859 1860 if (precompute) { 1861 precompute = 0; 1862 1863 /* setup alt next pointer, if any */ 1864 if (temp->last_frame) { 1865 td_alt_next = NULL; 1866 qtd_altnext = terminate; 1867 } else { 1868 /* we use this field internally */ 1869 td_alt_next = td_next; 1870 if (temp->setup_alt_next) { 1871 qtd_altnext = td_next->qtd_self; 1872 } else { 1873 qtd_altnext = terminate; 1874 } 1875 } 1876 1877 /* restore */ 1878 temp->shortpkt = shortpkt_old; 1879 temp->len = len_old; 1880 goto restart; 1881 } 1882 temp->td = td; 1883 temp->td_next = td_next; 1884 } 1885 1886 static void 1887 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1888 { 1889 struct ehci_std_temp temp; 1890 const struct usb_pipe_methods *methods; 1891 ehci_qh_t *qh; 1892 ehci_qtd_t *td; 1893 uint32_t qh_endp; 1894 uint32_t qh_endphub; 1895 uint32_t x; 1896 1897 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1898 xfer->address, UE_GET_ADDR(xfer->endpointno), 1899 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1900 1901 temp.average = xfer->max_hc_frame_size; 1902 temp.max_frame_size = xfer->max_frame_size; 1903 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1904 1905 if (xfer->flags_int.doorbell_wait) 1906 ehci_wait_doorbell(temp.sc, xfer->doorbell_match); 1907 xfer->flags_int.doorbell_wait = 1; 1908 1909 /* toggle the DMA set we are using */ 1910 xfer->flags_int.curr_dma_set ^= 1; 1911 1912 /* get next DMA set */ 1913 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1914 1915 xfer->td_transfer_first = td; 1916 xfer->td_transfer_cache = td; 1917 1918 temp.td = NULL; 1919 temp.td_next = td; 1920 temp.qtd_status = 0; 1921 temp.last_frame = 0; 1922 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1923 1924 if (xfer->flags_int.control_xfr) { 1925 if (xfer->endpoint->toggle_next) { 1926 /* DATA1 is next */ 1927 temp.qtd_status |= 1928 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1929 } 1930 temp.auto_data_toggle = 0; 1931 } else { 1932 temp.auto_data_toggle = 1; 1933 } 1934 1935 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1936 (xfer->xroot->udev->address != 0)) { 1937 /* max 3 retries */ 1938 temp.qtd_status |= 1939 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1940 } 1941 /* check if we should prepend a setup message */ 1942 1943 if (xfer->flags_int.control_xfr) { 1944 if (xfer->flags_int.control_hdr) { 1945 1946 xfer->endpoint->toggle_next = 0; 1947 1948 temp.qtd_status &= 1949 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1950 temp.qtd_status |= htohc32(temp.sc, 1951 EHCI_QTD_ACTIVE | 1952 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1953 EHCI_QTD_SET_TOGGLE(0)); 1954 1955 temp.len = xfer->frlengths[0]; 1956 temp.pc = xfer->frbuffers + 0; 1957 temp.shortpkt = temp.len ? 1 : 0; 1958 /* check for last frame */ 1959 if (xfer->nframes == 1) { 1960 /* no STATUS stage yet, SETUP is last */ 1961 if (xfer->flags_int.control_act) { 1962 temp.last_frame = 1; 1963 temp.setup_alt_next = 0; 1964 } 1965 } 1966 ehci_setup_standard_chain_sub(&temp); 1967 } 1968 x = 1; 1969 } else { 1970 x = 0; 1971 } 1972 1973 while (x != xfer->nframes) { 1974 1975 /* DATA0 / DATA1 message */ 1976 1977 temp.len = xfer->frlengths[x]; 1978 temp.pc = xfer->frbuffers + x; 1979 1980 x++; 1981 1982 if (x == xfer->nframes) { 1983 if (xfer->flags_int.control_xfr) { 1984 /* no STATUS stage yet, DATA is last */ 1985 if (xfer->flags_int.control_act) { 1986 temp.last_frame = 1; 1987 temp.setup_alt_next = 0; 1988 } 1989 } else { 1990 temp.last_frame = 1; 1991 temp.setup_alt_next = 0; 1992 } 1993 } 1994 /* keep previous data toggle and error count */ 1995 1996 temp.qtd_status &= 1997 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1998 EHCI_QTD_SET_TOGGLE(1)); 1999 2000 if (temp.len == 0) { 2001 2002 /* make sure that we send an USB packet */ 2003 2004 temp.shortpkt = 0; 2005 2006 } else { 2007 2008 /* regular data transfer */ 2009 2010 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 2011 } 2012 2013 /* set endpoint direction */ 2014 2015 temp.qtd_status |= 2016 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 2017 htohc32(temp.sc, EHCI_QTD_ACTIVE | 2018 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 2019 htohc32(temp.sc, EHCI_QTD_ACTIVE | 2020 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 2021 2022 ehci_setup_standard_chain_sub(&temp); 2023 } 2024 2025 /* check if we should append a status stage */ 2026 2027 if (xfer->flags_int.control_xfr && 2028 !xfer->flags_int.control_act) { 2029 2030 /* 2031 * Send a DATA1 message and invert the current endpoint 2032 * direction. 2033 */ 2034 2035 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 2036 EHCI_QTD_SET_TOGGLE(1)); 2037 temp.qtd_status |= 2038 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 2039 htohc32(temp.sc, EHCI_QTD_ACTIVE | 2040 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 2041 EHCI_QTD_SET_TOGGLE(1)) : 2042 htohc32(temp.sc, EHCI_QTD_ACTIVE | 2043 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 2044 EHCI_QTD_SET_TOGGLE(1)); 2045 2046 temp.len = 0; 2047 temp.pc = NULL; 2048 temp.shortpkt = 0; 2049 temp.last_frame = 1; 2050 temp.setup_alt_next = 0; 2051 2052 ehci_setup_standard_chain_sub(&temp); 2053 } 2054 td = temp.td; 2055 2056 /* the last TD terminates the transfer: */ 2057 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 2058 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 2059 2060 usb_pc_cpu_flush(td->page_cache); 2061 2062 /* must have at least one frame! */ 2063 2064 xfer->td_transfer_last = td; 2065 2066 #ifdef USB_DEBUG 2067 if (ehcidebug > 8) { 2068 DPRINTF("nexttog=%d; data before transfer:\n", 2069 xfer->endpoint->toggle_next); 2070 ehci_dump_sqtds(temp.sc, 2071 xfer->td_transfer_first); 2072 } 2073 #endif 2074 2075 methods = xfer->endpoint->methods; 2076 2077 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2078 2079 /* the "qh_link" field is filled when the QH is added */ 2080 2081 qh_endp = 2082 (EHCI_QH_SET_ADDR(xfer->address) | 2083 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2084 EHCI_QH_SET_MPL(xfer->max_packet_size)); 2085 2086 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2087 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 2088 if (methods != &ehci_device_intr_methods) 2089 qh_endp |= EHCI_QH_SET_NRL(8); 2090 } else { 2091 2092 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 2093 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 2094 } else { 2095 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 2096 } 2097 2098 if (methods == &ehci_device_ctrl_methods) { 2099 qh_endp |= EHCI_QH_CTL; 2100 } 2101 if (methods != &ehci_device_intr_methods) { 2102 /* Only try one time per microframe! */ 2103 qh_endp |= EHCI_QH_SET_NRL(1); 2104 } 2105 } 2106 2107 if (temp.auto_data_toggle == 0) { 2108 /* software computes the data toggle */ 2109 qh_endp |= EHCI_QH_DTC; 2110 } 2111 2112 qh->qh_endp = htohc32(temp.sc, qh_endp); 2113 2114 qh_endphub = 2115 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 2116 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 2117 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 2118 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2119 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 2120 2121 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 2122 qh->qh_curqtd = 0; 2123 2124 /* fill the overlay qTD */ 2125 2126 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 2127 /* DATA1 is next */ 2128 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 2129 } else { 2130 qh->qh_qtd.qtd_status = 0; 2131 } 2132 2133 td = xfer->td_transfer_first; 2134 2135 qh->qh_qtd.qtd_next = td->qtd_self; 2136 qh->qh_qtd.qtd_altnext = 2137 htohc32(temp.sc, EHCI_LINK_TERMINATE); 2138 2139 usb_pc_cpu_flush(qh->page_cache); 2140 2141 if (xfer->xroot->udev->flags.self_suspended == 0) { 2142 KKASSERT(xfer->flags_int.onhwqueue == 0); 2143 xfer->flags_int.onhwqueue = 1; 2144 EHCI_APPEND_QH(qh, *qh_last); 2145 } 2146 ehci_ring_doorbell(temp.sc, NULL); 2147 } 2148 2149 static void 2150 ehci_root_intr(ehci_softc_t *sc) 2151 { 2152 uint16_t i; 2153 uint16_t m; 2154 2155 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2156 2157 /* clear any old interrupt data */ 2158 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2159 2160 /* set bits */ 2161 m = (sc->sc_noport + 1); 2162 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2163 m = (8 * sizeof(sc->sc_hub_idata)); 2164 } 2165 for (i = 1; i < m; i++) { 2166 /* pick out CHANGE bits from the status register */ 2167 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2168 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2169 DPRINTF("port %d changed\n", i); 2170 } 2171 } 2172 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2173 sizeof(sc->sc_hub_idata)); 2174 } 2175 2176 static void 2177 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2178 { 2179 uint32_t nframes = xfer->nframes; 2180 uint32_t status; 2181 uint32_t *plen = xfer->frlengths; 2182 uint16_t len = 0; 2183 ehci_sitd_t *td = xfer->td_transfer_first; 2184 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2185 2186 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2187 xfer, xfer->endpoint); 2188 2189 while (xfer->flags_int.onhwqueue && nframes--) { 2190 if (td == NULL) { 2191 panic("%s:%d: out of TD's\n", 2192 __func__, __LINE__); 2193 } 2194 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2195 pp_last = &sc->sc_isoc_fs_p_last[0]; 2196 } 2197 #ifdef USB_DEBUG 2198 if (ehcidebug > 15) { 2199 DPRINTF("isoc FS-TD\n"); 2200 ehci_dump_sitd(sc, td); 2201 } 2202 #endif 2203 usb_pc_cpu_invalidate(td->page_cache); 2204 status = hc32toh(sc, td->sitd_status); 2205 2206 len = EHCI_SITD_GET_LEN(status); 2207 2208 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2209 2210 if (*plen >= len) { 2211 len = *plen - len; 2212 } else { 2213 len = 0; 2214 } 2215 2216 *plen = len; 2217 2218 /* remove FS-TD from schedule */ 2219 EHCI_REMOVE_FS_TD(td, *pp_last); 2220 2221 pp_last++; 2222 plen++; 2223 td = td->obj_next; 2224 } 2225 xfer->flags_int.onhwqueue = 0; 2226 2227 xfer->aframes = xfer->nframes; 2228 } 2229 2230 static void 2231 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2232 { 2233 uint32_t nframes = xfer->nframes; 2234 uint32_t status; 2235 uint32_t *plen = xfer->frlengths; 2236 uint16_t len = 0; 2237 uint8_t td_no = 0; 2238 ehci_itd_t *td = xfer->td_transfer_first; 2239 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2240 2241 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2242 xfer, xfer->endpoint); 2243 2244 while (nframes && xfer->flags_int.onhwqueue) { 2245 if (td == NULL) { 2246 panic("%s:%d: out of TD's\n", 2247 __func__, __LINE__); 2248 } 2249 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2250 pp_last = &sc->sc_isoc_hs_p_last[0]; 2251 } 2252 #ifdef USB_DEBUG 2253 if (ehcidebug > 15) { 2254 DPRINTF("isoc HS-TD\n"); 2255 ehci_dump_itd(sc, td); 2256 } 2257 #endif 2258 2259 usb_pc_cpu_invalidate(td->page_cache); 2260 status = hc32toh(sc, td->itd_status[td_no]); 2261 2262 len = EHCI_ITD_GET_LEN(status); 2263 2264 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2265 2266 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2267 2268 if (*plen >= len) { 2269 /* 2270 * The length is valid. NOTE: The 2271 * complete length is written back 2272 * into the status field, and not the 2273 * remainder like with other transfer 2274 * descriptor types. 2275 */ 2276 } else { 2277 /* Invalid length - truncate */ 2278 len = 0; 2279 } 2280 2281 *plen = len; 2282 plen++; 2283 nframes--; 2284 } 2285 2286 td_no++; 2287 2288 if ((td_no == 8) || (nframes == 0)) { 2289 /* remove HS-TD from schedule */ 2290 EHCI_REMOVE_HS_TD(td, *pp_last); 2291 pp_last++; 2292 2293 td_no = 0; 2294 td = td->obj_next; 2295 } 2296 } 2297 xfer->aframes = xfer->nframes; 2298 xfer->flags_int.onhwqueue = 0; 2299 } 2300 2301 /* NOTE: "done" can be run two times in a row, 2302 * from close and from interrupt 2303 */ 2304 static void 2305 ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2306 { 2307 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 2308 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2309 2310 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2311 2312 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2313 xfer, xfer->endpoint, error); 2314 2315 /* 2316 * Don't throw away a timed-out transfer without safely removing 2317 * it from the controller's notice! 2318 */ 2319 if (error != USB_ERR_NORMAL_COMPLETION) 2320 ehci_stop_xfer(xfer); 2321 2322 if (xfer->flags_int.onhwqueue) { 2323 if ((methods == &ehci_device_bulk_methods) || 2324 (methods == &ehci_device_ctrl_methods)) { 2325 #ifdef USB_DEBUG 2326 if (ehcidebug > 8) { 2327 DPRINTF("nexttog=%d; data after transfer:\n", 2328 xfer->endpoint->toggle_next); 2329 ehci_dump_sqtds(sc, 2330 xfer->td_transfer_first); 2331 } 2332 #endif 2333 2334 EHCI_REMOVE_QH(sc, xfer->qh_start[xfer->flags_int.curr_dma_set], 2335 sc->sc_async_p_last); 2336 } 2337 if (methods == &ehci_device_intr_methods) { 2338 EHCI_REMOVE_QH(sc, xfer->qh_start[xfer->flags_int.curr_dma_set], 2339 sc->sc_intr_p_last[xfer->qh_pos]); 2340 } 2341 xfer->flags_int.onhwqueue = 0; 2342 ehci_ring_doorbell(sc, xfer); 2343 } 2344 2345 /* 2346 * Only finish isochronous transfers once which will update 2347 * "xfer->frlengths". 2348 */ 2349 if (xfer->td_transfer_first && 2350 xfer->td_transfer_last) { 2351 if (methods == &ehci_device_isoc_fs_methods) { 2352 ehci_isoc_fs_done(sc, xfer); 2353 } 2354 if (methods == &ehci_device_isoc_hs_methods) { 2355 ehci_isoc_hs_done(sc, xfer); 2356 } 2357 xfer->td_transfer_first = NULL; 2358 xfer->td_transfer_last = NULL; 2359 } 2360 /* dequeue transfer and start next transfer */ 2361 usbd_transfer_done(xfer, error); 2362 } 2363 2364 /*------------------------------------------------------------------------* 2365 * ehci bulk support 2366 *------------------------------------------------------------------------*/ 2367 static void 2368 ehci_device_bulk_open(struct usb_xfer *xfer) 2369 { 2370 return; 2371 } 2372 2373 static void 2374 ehci_device_bulk_close(struct usb_xfer *xfer) 2375 { 2376 ehci_device_done(xfer, USB_ERR_CANCELLED); 2377 } 2378 2379 static void 2380 ehci_device_bulk_enter(struct usb_xfer *xfer) 2381 { 2382 return; 2383 } 2384 2385 static void 2386 ehci_device_bulk_start(struct usb_xfer *xfer) 2387 { 2388 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2389 #if 0 2390 uint32_t temp; 2391 #endif 2392 2393 /* setup TD's and QH */ 2394 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2395 2396 /* put transfer on interrupt queue */ 2397 ehci_transfer_intr_enqueue(xfer); 2398 2399 #if 0 2400 /* 2401 * XXX Certain nVidia chipsets choke when using the IAAD 2402 * feature too frequently. 2403 * 2404 * XXX This code has been moved to another place which handles 2405 * more cases. EHCI appears to need the doorbell to be hit 2406 * in the other queueing cases or it can wind up not 2407 * processing the queue. 2408 */ 2409 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2410 return; 2411 2412 /* XXX Performance quirk: Some Host Controllers have a too low 2413 * interrupt rate. Issue an IAAD to stimulate the Host 2414 * Controller after queueing the BULK transfer. 2415 */ 2416 temp = EOREAD4(sc, EHCI_USBCMD); 2417 if (!(temp & EHCI_CMD_IAAD)) 2418 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2419 #endif 2420 } 2421 2422 static const struct usb_pipe_methods ehci_device_bulk_methods = 2423 { 2424 .open = ehci_device_bulk_open, 2425 .close = ehci_device_bulk_close, 2426 .enter = ehci_device_bulk_enter, 2427 .start = ehci_device_bulk_start, 2428 }; 2429 2430 /*------------------------------------------------------------------------* 2431 * ehci control support 2432 *------------------------------------------------------------------------*/ 2433 static void 2434 ehci_device_ctrl_open(struct usb_xfer *xfer) 2435 { 2436 return; 2437 } 2438 2439 static void 2440 ehci_device_ctrl_close(struct usb_xfer *xfer) 2441 { 2442 ehci_device_done(xfer, USB_ERR_CANCELLED); 2443 } 2444 2445 static void 2446 ehci_device_ctrl_enter(struct usb_xfer *xfer) 2447 { 2448 return; 2449 } 2450 2451 static void 2452 ehci_device_ctrl_start(struct usb_xfer *xfer) 2453 { 2454 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2455 2456 /* setup TD's and QH */ 2457 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2458 2459 /* put transfer on interrupt queue */ 2460 ehci_transfer_intr_enqueue(xfer); 2461 } 2462 2463 static const struct usb_pipe_methods ehci_device_ctrl_methods = 2464 { 2465 .open = ehci_device_ctrl_open, 2466 .close = ehci_device_ctrl_close, 2467 .enter = ehci_device_ctrl_enter, 2468 .start = ehci_device_ctrl_start, 2469 }; 2470 2471 /*------------------------------------------------------------------------* 2472 * ehci interrupt support 2473 *------------------------------------------------------------------------*/ 2474 static void 2475 ehci_device_intr_open(struct usb_xfer *xfer) 2476 { 2477 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2478 uint16_t best; 2479 uint16_t bit; 2480 uint16_t x; 2481 2482 usb_hs_bandwidth_alloc(xfer); 2483 2484 /* 2485 * Find the best QH position corresponding to the given interval: 2486 */ 2487 2488 best = 0; 2489 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2490 while (bit) { 2491 if (xfer->interval >= bit) { 2492 x = bit; 2493 best = bit; 2494 while (x & bit) { 2495 if (sc->sc_intr_stat[x] < 2496 sc->sc_intr_stat[best]) { 2497 best = x; 2498 } 2499 x++; 2500 } 2501 break; 2502 } 2503 bit >>= 1; 2504 } 2505 2506 sc->sc_intr_stat[best]++; 2507 xfer->qh_pos = best; 2508 2509 DPRINTFN(3, "best=%d interval=%d\n", 2510 best, xfer->interval); 2511 } 2512 2513 static void 2514 ehci_device_intr_close(struct usb_xfer *xfer) 2515 { 2516 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2517 2518 sc->sc_intr_stat[xfer->qh_pos]--; 2519 2520 ehci_device_done(xfer, USB_ERR_CANCELLED); 2521 2522 /* bandwidth must be freed after device done */ 2523 usb_hs_bandwidth_free(xfer); 2524 } 2525 2526 static void 2527 ehci_device_intr_enter(struct usb_xfer *xfer) 2528 { 2529 return; 2530 } 2531 2532 static void 2533 ehci_device_intr_start(struct usb_xfer *xfer) 2534 { 2535 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2536 2537 /* setup TD's and QH */ 2538 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2539 2540 /* put transfer on interrupt queue */ 2541 ehci_transfer_intr_enqueue(xfer); 2542 } 2543 2544 static const struct usb_pipe_methods ehci_device_intr_methods = 2545 { 2546 .open = ehci_device_intr_open, 2547 .close = ehci_device_intr_close, 2548 .enter = ehci_device_intr_enter, 2549 .start = ehci_device_intr_start, 2550 }; 2551 2552 /*------------------------------------------------------------------------* 2553 * ehci full speed isochronous support 2554 *------------------------------------------------------------------------*/ 2555 static void 2556 ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2557 { 2558 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2559 ehci_sitd_t *td; 2560 uint32_t sitd_portaddr; 2561 uint8_t ds; 2562 2563 sitd_portaddr = 2564 EHCI_SITD_SET_ADDR(xfer->address) | 2565 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2566 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2567 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2568 2569 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2570 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2571 } 2572 sitd_portaddr = htohc32(sc, sitd_portaddr); 2573 2574 /* initialize all TD's */ 2575 2576 for (ds = 0; ds != 2; ds++) { 2577 2578 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2579 2580 td->sitd_portaddr = sitd_portaddr; 2581 2582 /* 2583 * TODO: make some kind of automatic 2584 * SMASK/CMASK selection based on micro-frame 2585 * usage 2586 * 2587 * micro-frame usage (8 microframes per 1ms) 2588 */ 2589 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2590 2591 usb_pc_cpu_flush(td->page_cache); 2592 } 2593 } 2594 } 2595 2596 static void 2597 ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2598 { 2599 ehci_device_done(xfer, USB_ERR_CANCELLED); 2600 } 2601 2602 static void 2603 ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2604 { 2605 struct usb_page_search buf_res; 2606 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2607 ehci_sitd_t *td; 2608 ehci_sitd_t *td_last = NULL; 2609 ehci_sitd_t **pp_last; 2610 uint32_t *plen; 2611 uint32_t buf_offset; 2612 uint32_t nframes; 2613 uint32_t temp; 2614 uint32_t sitd_mask; 2615 uint16_t tlen; 2616 uint8_t sa; 2617 uint8_t sb; 2618 2619 #ifdef USB_DEBUG 2620 uint8_t once = 1; 2621 2622 #endif 2623 2624 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2625 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2626 2627 /* get the current frame index */ 2628 2629 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2630 2631 /* 2632 * check if the frame index is within the window where the frames 2633 * will be inserted 2634 */ 2635 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2636 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2637 2638 if ((xfer->endpoint->is_synced == 0) || 2639 (buf_offset < xfer->nframes)) { 2640 /* 2641 * If there is data underflow or the pipe queue is empty we 2642 * schedule the transfer a few frames ahead of the current 2643 * frame position. Else two isochronous transfers might 2644 * overlap. 2645 */ 2646 xfer->endpoint->isoc_next = (nframes + 3) & 2647 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2648 xfer->endpoint->is_synced = 1; 2649 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2650 } 2651 /* 2652 * compute how many milliseconds the insertion is ahead of the 2653 * current frame position: 2654 */ 2655 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2656 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2657 2658 /* 2659 * pre-compute when the isochronous transfer will be finished: 2660 */ 2661 xfer->isoc_time_complete = 2662 usb_isoc_time_expand(&sc->sc_bus, nframes) + 2663 buf_offset + xfer->nframes; 2664 2665 /* get the real number of frames */ 2666 2667 nframes = xfer->nframes; 2668 2669 buf_offset = 0; 2670 2671 plen = xfer->frlengths; 2672 2673 /* toggle the DMA set we are using */ 2674 xfer->flags_int.curr_dma_set ^= 1; 2675 2676 /* get next DMA set */ 2677 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2678 xfer->td_transfer_first = td; 2679 2680 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2681 2682 /* store starting position */ 2683 2684 xfer->qh_pos = xfer->endpoint->isoc_next; 2685 2686 while (nframes--) { 2687 if (td == NULL) { 2688 panic("%s:%d: out of TD's\n", 2689 __func__, __LINE__); 2690 } 2691 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2692 pp_last = &sc->sc_isoc_fs_p_last[0]; 2693 } 2694 /* reuse sitd_portaddr and sitd_back from last transfer */ 2695 2696 if (*plen > xfer->max_frame_size) { 2697 #ifdef USB_DEBUG 2698 if (once) { 2699 once = 0; 2700 kprintf("%s: frame length(%d) exceeds %d " 2701 "bytes (frame truncated)\n", 2702 __func__, *plen, 2703 xfer->max_frame_size); 2704 } 2705 #endif 2706 *plen = xfer->max_frame_size; 2707 } 2708 2709 /* allocate a slot */ 2710 2711 sa = usbd_fs_isoc_schedule_alloc_slot(xfer, 2712 xfer->isoc_time_complete - nframes - 1); 2713 2714 if(sa == 255) { 2715 /* 2716 * Schedule is FULL, set length to zero: 2717 */ 2718 2719 *plen = 0; 2720 sa = USB_FS_ISOC_UFRAME_MAX - 1; 2721 } 2722 if (*plen) { 2723 /* 2724 * only call "usbd_get_page()" when we have a 2725 * non-zero length 2726 */ 2727 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2728 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2729 buf_offset += *plen; 2730 /* 2731 * NOTE: We need to subtract one from the offset so 2732 * that we are on a valid page! 2733 */ 2734 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2735 &buf_res); 2736 temp = buf_res.physaddr & ~0xFFF; 2737 } else { 2738 td->sitd_bp[0] = 0; 2739 temp = 0; 2740 } 2741 2742 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2743 tlen = *plen; 2744 if (tlen <= 188) { 2745 temp |= 1; /* T-count = 1, TP = ALL */ 2746 tlen = 1; 2747 } else { 2748 tlen += 187; 2749 tlen /= 188; 2750 temp |= tlen; /* T-count = [1..6] */ 2751 temp |= 8; /* TP = Begin */ 2752 } 2753 2754 tlen += sa; 2755 2756 if (tlen >= 8) { 2757 sb = 0; 2758 } else { 2759 sb = (1 << tlen); 2760 } 2761 2762 sa = (1 << sa); 2763 sa = (sb - sa) & 0x3F; 2764 sb = 0; 2765 } else { 2766 sb = (-(4 << sa)) & 0xFE; 2767 sa = (1 << sa) & 0x3F; 2768 } 2769 2770 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2771 EHCI_SITD_SET_CMASK(sb)); 2772 2773 td->sitd_bp[1] = htohc32(sc, temp); 2774 2775 td->sitd_mask = htohc32(sc, sitd_mask); 2776 2777 if (nframes == 0) { 2778 td->sitd_status = htohc32(sc, 2779 EHCI_SITD_IOC | 2780 EHCI_SITD_ACTIVE | 2781 EHCI_SITD_SET_LEN(*plen)); 2782 } else { 2783 td->sitd_status = htohc32(sc, 2784 EHCI_SITD_ACTIVE | 2785 EHCI_SITD_SET_LEN(*plen)); 2786 } 2787 usb_pc_cpu_flush(td->page_cache); 2788 2789 #ifdef USB_DEBUG 2790 if (ehcidebug > 15) { 2791 DPRINTF("FS-TD %d\n", nframes); 2792 ehci_dump_sitd(sc, td); 2793 } 2794 #endif 2795 /* insert TD into schedule */ 2796 xfer->flags_int.onhwqueue = 1; 2797 EHCI_APPEND_FS_TD(td, *pp_last); 2798 pp_last++; 2799 2800 plen++; 2801 td_last = td; 2802 td = td->obj_next; 2803 } 2804 2805 xfer->td_transfer_last = td_last; 2806 2807 /* update isoc_next */ 2808 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2809 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2810 2811 /* 2812 * We don't allow cancelling of the SPLIT transaction USB FULL 2813 * speed transfer, because it disturbs the bandwidth 2814 * computation algorithm. 2815 */ 2816 xfer->flags_int.can_cancel_immed = 0; 2817 ehci_ring_doorbell(sc, NULL); 2818 } 2819 2820 static void 2821 ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2822 { 2823 /* 2824 * We don't allow cancelling of the SPLIT transaction USB FULL 2825 * speed transfer, because it disturbs the bandwidth 2826 * computation algorithm. 2827 */ 2828 xfer->flags_int.can_cancel_immed = 0; 2829 2830 /* set a default timeout */ 2831 if (xfer->timeout == 0) 2832 xfer->timeout = 1000; /* ms */ 2833 2834 /* put transfer on interrupt queue */ 2835 ehci_transfer_intr_enqueue(xfer); 2836 } 2837 2838 static const struct usb_pipe_methods ehci_device_isoc_fs_methods = 2839 { 2840 .open = ehci_device_isoc_fs_open, 2841 .close = ehci_device_isoc_fs_close, 2842 .enter = ehci_device_isoc_fs_enter, 2843 .start = ehci_device_isoc_fs_start, 2844 }; 2845 2846 /*------------------------------------------------------------------------* 2847 * ehci high speed isochronous support 2848 *------------------------------------------------------------------------*/ 2849 static void 2850 ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2851 { 2852 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2853 ehci_itd_t *td; 2854 uint32_t temp; 2855 uint8_t ds; 2856 2857 usb_hs_bandwidth_alloc(xfer); 2858 2859 /* initialize all TD's */ 2860 2861 for (ds = 0; ds != 2; ds++) { 2862 2863 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2864 2865 /* set TD inactive */ 2866 td->itd_status[0] = 0; 2867 td->itd_status[1] = 0; 2868 td->itd_status[2] = 0; 2869 td->itd_status[3] = 0; 2870 td->itd_status[4] = 0; 2871 td->itd_status[5] = 0; 2872 td->itd_status[6] = 0; 2873 td->itd_status[7] = 0; 2874 2875 /* set endpoint and address */ 2876 td->itd_bp[0] = htohc32(sc, 2877 EHCI_ITD_SET_ADDR(xfer->address) | 2878 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2879 2880 temp = 2881 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2882 2883 /* set direction */ 2884 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2885 temp |= EHCI_ITD_SET_DIR_IN; 2886 } 2887 /* set maximum packet size */ 2888 td->itd_bp[1] = htohc32(sc, temp); 2889 2890 /* set transfer multiplier */ 2891 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2892 2893 usb_pc_cpu_flush(td->page_cache); 2894 } 2895 } 2896 } 2897 2898 static void 2899 ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2900 { 2901 ehci_device_done(xfer, USB_ERR_CANCELLED); 2902 2903 /* bandwidth must be freed after device done */ 2904 usb_hs_bandwidth_free(xfer); 2905 } 2906 2907 static void 2908 ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2909 { 2910 struct usb_page_search buf_res; 2911 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2912 ehci_itd_t *td; 2913 ehci_itd_t *td_last = NULL; 2914 ehci_itd_t **pp_last; 2915 bus_size_t page_addr; 2916 uint32_t *plen; 2917 uint32_t status; 2918 uint32_t buf_offset; 2919 uint32_t nframes; 2920 uint32_t itd_offset[8 + 1]; 2921 uint8_t x; 2922 uint8_t td_no; 2923 uint8_t page_no; 2924 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 2925 2926 #ifdef USB_DEBUG 2927 uint8_t once = 1; 2928 2929 #endif 2930 2931 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2932 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift); 2933 2934 /* get the current frame index */ 2935 2936 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2937 2938 /* 2939 * check if the frame index is within the window where the frames 2940 * will be inserted 2941 */ 2942 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2943 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2944 2945 if ((xfer->endpoint->is_synced == 0) || 2946 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2947 /* 2948 * If there is data underflow or the pipe queue is empty we 2949 * schedule the transfer a few frames ahead of the current 2950 * frame position. Else two isochronous transfers might 2951 * overlap. 2952 */ 2953 xfer->endpoint->isoc_next = (nframes + 3) & 2954 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2955 xfer->endpoint->is_synced = 1; 2956 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2957 } 2958 /* 2959 * compute how many milliseconds the insertion is ahead of the 2960 * current frame position: 2961 */ 2962 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2963 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2964 2965 /* 2966 * pre-compute when the isochronous transfer will be finished: 2967 */ 2968 xfer->isoc_time_complete = 2969 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2970 (((xfer->nframes << shift) + 7) / 8); 2971 2972 /* get the real number of frames */ 2973 2974 nframes = xfer->nframes; 2975 2976 buf_offset = 0; 2977 td_no = 0; 2978 2979 plen = xfer->frlengths; 2980 2981 /* toggle the DMA set we are using */ 2982 xfer->flags_int.curr_dma_set ^= 1; 2983 2984 /* get next DMA set */ 2985 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2986 xfer->td_transfer_first = td; 2987 2988 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2989 2990 /* store starting position */ 2991 2992 xfer->qh_pos = xfer->endpoint->isoc_next; 2993 2994 while (nframes) { 2995 if (td == NULL) { 2996 panic("%s:%d: out of TD's\n", 2997 __func__, __LINE__); 2998 } 2999 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 3000 pp_last = &sc->sc_isoc_hs_p_last[0]; 3001 } 3002 /* range check */ 3003 if (*plen > xfer->max_frame_size) { 3004 #ifdef USB_DEBUG 3005 if (once) { 3006 once = 0; 3007 kprintf("%s: frame length(%d) exceeds %d bytes " 3008 "(frame truncated)\n", 3009 __func__, *plen, xfer->max_frame_size); 3010 } 3011 #endif 3012 *plen = xfer->max_frame_size; 3013 } 3014 3015 if (xfer->endpoint->usb_smask & (1 << td_no)) { 3016 status = (EHCI_ITD_SET_LEN(*plen) | 3017 EHCI_ITD_ACTIVE | 3018 EHCI_ITD_SET_PG(0)); 3019 td->itd_status[td_no] = htohc32(sc, status); 3020 itd_offset[td_no] = buf_offset; 3021 buf_offset += *plen; 3022 plen++; 3023 nframes --; 3024 } else { 3025 td->itd_status[td_no] = 0; /* not active */ 3026 itd_offset[td_no] = buf_offset; 3027 } 3028 3029 td_no++; 3030 3031 if ((td_no == 8) || (nframes == 0)) { 3032 3033 /* the rest of the transfers are not active, if any */ 3034 for (x = td_no; x != 8; x++) { 3035 td->itd_status[x] = 0; /* not active */ 3036 } 3037 3038 /* check if there is any data to be transferred */ 3039 if (itd_offset[0] != buf_offset) { 3040 page_no = 0; 3041 itd_offset[td_no] = buf_offset; 3042 3043 /* get first page offset */ 3044 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 3045 /* get page address */ 3046 page_addr = buf_res.physaddr & ~0xFFF; 3047 /* update page address */ 3048 td->itd_bp[0] &= htohc32(sc, 0xFFF); 3049 td->itd_bp[0] |= htohc32(sc, page_addr); 3050 3051 for (x = 0; x != td_no; x++) { 3052 /* set page number and page offset */ 3053 status = (EHCI_ITD_SET_PG(page_no) | 3054 (buf_res.physaddr & 0xFFF)); 3055 td->itd_status[x] |= htohc32(sc, status); 3056 3057 /* get next page offset */ 3058 if (itd_offset[x + 1] == buf_offset) { 3059 /* 3060 * We subtract one so that 3061 * we don't go off the last 3062 * page! 3063 */ 3064 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 3065 } else { 3066 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 3067 } 3068 3069 /* check if we need a new page */ 3070 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 3071 /* new page needed */ 3072 page_addr = buf_res.physaddr & ~0xFFF; 3073 if (page_no == 6) { 3074 panic("%s: too many pages\n", __func__); 3075 } 3076 page_no++; 3077 /* update page address */ 3078 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 3079 td->itd_bp[page_no] |= htohc32(sc, page_addr); 3080 } 3081 } 3082 } 3083 /* set IOC bit if we are complete */ 3084 if (nframes == 0) { 3085 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 3086 } 3087 usb_pc_cpu_flush(td->page_cache); 3088 #ifdef USB_DEBUG 3089 if (ehcidebug > 15) { 3090 DPRINTF("HS-TD %d\n", nframes); 3091 ehci_dump_itd(sc, td); 3092 } 3093 #endif 3094 /* insert TD into schedule */ 3095 xfer->flags_int.onhwqueue = 1; 3096 EHCI_APPEND_HS_TD(td, *pp_last); 3097 pp_last++; 3098 3099 td_no = 0; 3100 td_last = td; 3101 td = td->obj_next; 3102 } 3103 } 3104 3105 xfer->td_transfer_last = td_last; 3106 3107 /* update isoc_next */ 3108 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 3109 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 3110 ehci_ring_doorbell(sc, NULL); 3111 } 3112 3113 static void 3114 ehci_device_isoc_hs_start(struct usb_xfer *xfer) 3115 { 3116 /* put transfer on interrupt queue */ 3117 ehci_transfer_intr_enqueue(xfer); 3118 } 3119 3120 static const struct usb_pipe_methods ehci_device_isoc_hs_methods = 3121 { 3122 .open = ehci_device_isoc_hs_open, 3123 .close = ehci_device_isoc_hs_close, 3124 .enter = ehci_device_isoc_hs_enter, 3125 .start = ehci_device_isoc_hs_start, 3126 }; 3127 3128 /*------------------------------------------------------------------------* 3129 * ehci root control support 3130 *------------------------------------------------------------------------* 3131 * Simulate a hardware hub by handling all the necessary requests. 3132 *------------------------------------------------------------------------*/ 3133 3134 static const 3135 struct usb_device_descriptor ehci_devd = 3136 { 3137 sizeof(struct usb_device_descriptor), 3138 UDESC_DEVICE, /* type */ 3139 {0x00, 0x02}, /* USB version */ 3140 UDCLASS_HUB, /* class */ 3141 UDSUBCLASS_HUB, /* subclass */ 3142 UDPROTO_HSHUBSTT, /* protocol */ 3143 64, /* max packet */ 3144 {0}, {0}, {0x00, 0x01}, /* device id */ 3145 1, 2, 0, /* string indicies */ 3146 1 /* # of configurations */ 3147 }; 3148 3149 static const 3150 struct usb_device_qualifier ehci_odevd = 3151 { 3152 sizeof(struct usb_device_qualifier), 3153 UDESC_DEVICE_QUALIFIER, /* type */ 3154 {0x00, 0x02}, /* USB version */ 3155 UDCLASS_HUB, /* class */ 3156 UDSUBCLASS_HUB, /* subclass */ 3157 UDPROTO_FSHUB, /* protocol */ 3158 0, /* max packet */ 3159 0, /* # of configurations */ 3160 0 3161 }; 3162 3163 static const struct ehci_config_desc ehci_confd = { 3164 .confd = { 3165 .bLength = sizeof(struct usb_config_descriptor), 3166 .bDescriptorType = UDESC_CONFIG, 3167 .wTotalLength[0] = sizeof(ehci_confd), 3168 .bNumInterface = 1, 3169 .bConfigurationValue = 1, 3170 .iConfiguration = 0, 3171 .bmAttributes = UC_SELF_POWERED, 3172 .bMaxPower = 0 /* max power */ 3173 }, 3174 .ifcd = { 3175 .bLength = sizeof(struct usb_interface_descriptor), 3176 .bDescriptorType = UDESC_INTERFACE, 3177 .bNumEndpoints = 1, 3178 .bInterfaceClass = UICLASS_HUB, 3179 .bInterfaceSubClass = UISUBCLASS_HUB, 3180 .bInterfaceProtocol = 0, 3181 }, 3182 .endpd = { 3183 .bLength = sizeof(struct usb_endpoint_descriptor), 3184 .bDescriptorType = UDESC_ENDPOINT, 3185 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3186 .bmAttributes = UE_INTERRUPT, 3187 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3188 .bInterval = 255, 3189 }, 3190 }; 3191 3192 static const 3193 struct usb_hub_descriptor ehci_hubd = 3194 { 3195 .bDescLength = 0, /* dynamic length */ 3196 .bDescriptorType = UDESC_HUB, 3197 }; 3198 3199 static void 3200 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3201 { 3202 uint32_t port; 3203 uint32_t v; 3204 3205 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3206 3207 port = EHCI_PORTSC(index); 3208 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3209 EOWRITE4(sc, port, v | EHCI_PS_PO); 3210 } 3211 3212 static usb_error_t 3213 ehci_roothub_exec(struct usb_device *udev, 3214 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3215 { 3216 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3217 const char *str_ptr; 3218 const void *ptr; 3219 uint32_t port; 3220 uint32_t v; 3221 uint16_t len; 3222 uint16_t i; 3223 uint16_t value; 3224 uint16_t index; 3225 usb_error_t err; 3226 3227 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 3228 3229 /* buffer reset */ 3230 ptr = (const void *)&sc->sc_hub_desc; 3231 len = 0; 3232 err = 0; 3233 3234 value = UGETW(req->wValue); 3235 index = UGETW(req->wIndex); 3236 3237 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3238 "wValue=0x%04x wIndex=0x%04x\n", 3239 req->bmRequestType, req->bRequest, 3240 UGETW(req->wLength), value, index); 3241 3242 #define C(x,y) ((x) | ((y) << 8)) 3243 switch (C(req->bRequest, req->bmRequestType)) { 3244 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3245 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3246 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3247 /* 3248 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3249 * for the integrated root hub. 3250 */ 3251 break; 3252 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3253 len = 1; 3254 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3255 break; 3256 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3257 switch (value >> 8) { 3258 case UDESC_DEVICE: 3259 if ((value & 0xff) != 0) { 3260 err = USB_ERR_IOERROR; 3261 goto done; 3262 } 3263 len = sizeof(ehci_devd); 3264 ptr = (const void *)&ehci_devd; 3265 break; 3266 /* 3267 * We can't really operate at another speed, 3268 * but the specification says we need this 3269 * descriptor: 3270 */ 3271 case UDESC_DEVICE_QUALIFIER: 3272 if ((value & 0xff) != 0) { 3273 err = USB_ERR_IOERROR; 3274 goto done; 3275 } 3276 len = sizeof(ehci_odevd); 3277 ptr = (const void *)&ehci_odevd; 3278 break; 3279 3280 case UDESC_CONFIG: 3281 if ((value & 0xff) != 0) { 3282 err = USB_ERR_IOERROR; 3283 goto done; 3284 } 3285 len = sizeof(ehci_confd); 3286 ptr = (const void *)&ehci_confd; 3287 break; 3288 3289 case UDESC_STRING: 3290 switch (value & 0xff) { 3291 case 0: /* Language table */ 3292 str_ptr = "\001"; 3293 break; 3294 3295 case 1: /* Vendor */ 3296 str_ptr = sc->sc_vendor; 3297 break; 3298 3299 case 2: /* Product */ 3300 str_ptr = "EHCI root HUB"; 3301 break; 3302 3303 default: 3304 str_ptr = ""; 3305 break; 3306 } 3307 3308 len = usb_make_str_desc( 3309 sc->sc_hub_desc.temp, 3310 sizeof(sc->sc_hub_desc.temp), 3311 str_ptr); 3312 break; 3313 default: 3314 err = USB_ERR_IOERROR; 3315 goto done; 3316 } 3317 break; 3318 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3319 len = 1; 3320 sc->sc_hub_desc.temp[0] = 0; 3321 break; 3322 case C(UR_GET_STATUS, UT_READ_DEVICE): 3323 len = 2; 3324 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3325 break; 3326 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3327 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3328 len = 2; 3329 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3330 break; 3331 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3332 if (value >= EHCI_MAX_DEVICES) { 3333 err = USB_ERR_IOERROR; 3334 goto done; 3335 } 3336 sc->sc_addr = value; 3337 break; 3338 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3339 if ((value != 0) && (value != 1)) { 3340 err = USB_ERR_IOERROR; 3341 goto done; 3342 } 3343 sc->sc_conf = value; 3344 break; 3345 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3346 break; 3347 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3348 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3349 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3350 err = USB_ERR_IOERROR; 3351 goto done; 3352 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3353 break; 3354 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3355 break; 3356 /* Hub requests */ 3357 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3358 break; 3359 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3360 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3361 3362 if ((index < 1) || 3363 (index > sc->sc_noport)) { 3364 err = USB_ERR_IOERROR; 3365 goto done; 3366 } 3367 port = EHCI_PORTSC(index); 3368 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3369 switch (value) { 3370 case UHF_PORT_ENABLE: 3371 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3372 break; 3373 case UHF_PORT_SUSPEND: 3374 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3375 3376 /* 3377 * waking up a High Speed device is rather 3378 * complicated if 3379 */ 3380 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3381 } 3382 /* wait 20ms for resume sequence to complete */ 3383 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 50); 3384 3385 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3386 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3387 3388 /* 4ms settle time */ 3389 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 250); 3390 break; 3391 case UHF_PORT_POWER: 3392 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3393 break; 3394 case UHF_PORT_TEST: 3395 DPRINTFN(3, "clear port test " 3396 "%d\n", index); 3397 break; 3398 case UHF_PORT_INDICATOR: 3399 DPRINTFN(3, "clear port ind " 3400 "%d\n", index); 3401 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3402 break; 3403 case UHF_C_PORT_CONNECTION: 3404 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3405 break; 3406 case UHF_C_PORT_ENABLE: 3407 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3408 break; 3409 case UHF_C_PORT_SUSPEND: 3410 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3411 break; 3412 case UHF_C_PORT_OVER_CURRENT: 3413 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3414 break; 3415 case UHF_C_PORT_RESET: 3416 sc->sc_isreset = 0; 3417 break; 3418 default: 3419 err = USB_ERR_IOERROR; 3420 goto done; 3421 } 3422 break; 3423 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3424 if ((value & 0xff) != 0) { 3425 err = USB_ERR_IOERROR; 3426 goto done; 3427 } 3428 v = EREAD4(sc, EHCI_HCSPARAMS); 3429 3430 sc->sc_hub_desc.hubd = ehci_hubd; 3431 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3432 3433 if (EHCI_HCS_PPC(v)) 3434 i = UHD_PWR_INDIVIDUAL; 3435 else 3436 i = UHD_PWR_NO_SWITCH; 3437 3438 if (EHCI_HCS_P_INDICATOR(v)) 3439 i |= UHD_PORT_IND; 3440 3441 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3442 /* XXX can't find out? */ 3443 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3444 /* XXX don't know if ports are removable or not */ 3445 sc->sc_hub_desc.hubd.bDescLength = 3446 8 + ((sc->sc_noport + 7) / 8); 3447 len = sc->sc_hub_desc.hubd.bDescLength; 3448 break; 3449 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3450 len = 16; 3451 memset(sc->sc_hub_desc.temp, 0, 16); 3452 break; 3453 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3454 DPRINTFN(9, "get port status i=%d\n", 3455 index); 3456 if ((index < 1) || 3457 (index > sc->sc_noport)) { 3458 err = USB_ERR_IOERROR; 3459 goto done; 3460 } 3461 v = EOREAD4(sc, EHCI_PORTSC(index)); 3462 DPRINTFN(9, "port status=0x%04x\n", v); 3463 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) { 3464 if ((v & 0xc000000) == 0x8000000) 3465 i = UPS_HIGH_SPEED; 3466 else if ((v & 0xc000000) == 0x4000000) 3467 i = UPS_LOW_SPEED; 3468 else 3469 i = 0; 3470 } else { 3471 i = UPS_HIGH_SPEED; 3472 } 3473 if (v & EHCI_PS_CS) 3474 i |= UPS_CURRENT_CONNECT_STATUS; 3475 if (v & EHCI_PS_PE) 3476 i |= UPS_PORT_ENABLED; 3477 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3478 i |= UPS_SUSPEND; 3479 if (v & EHCI_PS_OCA) 3480 i |= UPS_OVERCURRENT_INDICATOR; 3481 if (v & EHCI_PS_PR) 3482 i |= UPS_RESET; 3483 if (v & EHCI_PS_PP) 3484 i |= UPS_PORT_POWER; 3485 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3486 i = 0; 3487 if (v & EHCI_PS_CSC) 3488 i |= UPS_C_CONNECT_STATUS; 3489 if (v & EHCI_PS_PEC) 3490 i |= UPS_C_PORT_ENABLED; 3491 if (v & EHCI_PS_OCC) 3492 i |= UPS_C_OVERCURRENT_INDICATOR; 3493 if (v & EHCI_PS_FPR) 3494 i |= UPS_C_SUSPEND; 3495 if (sc->sc_isreset) 3496 i |= UPS_C_PORT_RESET; 3497 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3498 len = sizeof(sc->sc_hub_desc.ps); 3499 break; 3500 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3501 err = USB_ERR_IOERROR; 3502 goto done; 3503 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3504 break; 3505 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3506 if ((index < 1) || 3507 (index > sc->sc_noport)) { 3508 err = USB_ERR_IOERROR; 3509 goto done; 3510 } 3511 port = EHCI_PORTSC(index); 3512 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3513 switch (value) { 3514 case UHF_PORT_ENABLE: 3515 EOWRITE4(sc, port, v | EHCI_PS_PE); 3516 break; 3517 case UHF_PORT_SUSPEND: 3518 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3519 break; 3520 case UHF_PORT_RESET: 3521 DPRINTFN(6, "reset port %d\n", index); 3522 #ifdef USB_DEBUG 3523 if (ehcinohighspeed) { 3524 /* 3525 * Connect USB device to companion 3526 * controller. 3527 */ 3528 ehci_disown(sc, index, 1); 3529 break; 3530 } 3531 #endif 3532 if (EHCI_PS_IS_LOWSPEED(v) && 3533 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3534 /* Low speed device, give up ownership. */ 3535 ehci_disown(sc, index, 1); 3536 break; 3537 } 3538 /* Start reset sequence. */ 3539 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3540 EOWRITE4(sc, port, v | EHCI_PS_PR); 3541 3542 /* Wait for reset to complete. */ 3543 usb_pause_mtx(&sc->sc_bus.bus_lock, 3544 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 3545 3546 /* Terminate reset sequence. */ 3547 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3548 EOWRITE4(sc, port, v); 3549 3550 /* Wait for HC to complete reset. */ 3551 usb_pause_mtx(&sc->sc_bus.bus_lock, 3552 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3553 3554 v = EOREAD4(sc, port); 3555 DPRINTF("ehci after reset, status=0x%08x\n", v); 3556 if (v & EHCI_PS_PR) { 3557 device_printf(sc->sc_bus.bdev, 3558 "port reset timeout\n"); 3559 err = USB_ERR_TIMEOUT; 3560 goto done; 3561 } 3562 if (!(v & EHCI_PS_PE) && 3563 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3564 /* Not a high speed device, give up ownership.*/ 3565 ehci_disown(sc, index, 0); 3566 break; 3567 } 3568 sc->sc_isreset = 1; 3569 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3570 index, v); 3571 break; 3572 3573 case UHF_PORT_POWER: 3574 DPRINTFN(3, "set port power %d\n", index); 3575 EOWRITE4(sc, port, v | EHCI_PS_PP); 3576 break; 3577 3578 case UHF_PORT_TEST: 3579 DPRINTFN(3, "set port test %d\n", index); 3580 break; 3581 3582 case UHF_PORT_INDICATOR: 3583 DPRINTFN(3, "set port ind %d\n", index); 3584 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3585 break; 3586 3587 default: 3588 err = USB_ERR_IOERROR; 3589 goto done; 3590 } 3591 break; 3592 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3593 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3594 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3595 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3596 break; 3597 default: 3598 err = USB_ERR_IOERROR; 3599 goto done; 3600 } 3601 done: 3602 *plength = len; 3603 *pptr = ptr; 3604 return (err); 3605 } 3606 3607 static void 3608 ehci_xfer_setup(struct usb_setup_params *parm) 3609 { 3610 struct usb_page_search page_info; 3611 struct usb_page_cache *pc; 3612 ehci_softc_t *sc; 3613 struct usb_xfer *xfer; 3614 void *last_obj; 3615 uint32_t nqtd; 3616 uint32_t nqh; 3617 uint32_t nsitd; 3618 uint32_t nitd; 3619 uint32_t n; 3620 3621 sc = EHCI_BUS2SC(parm->udev->bus); 3622 xfer = parm->curr_xfer; 3623 3624 nqtd = 0; 3625 nqh = 0; 3626 nsitd = 0; 3627 nitd = 0; 3628 3629 /* 3630 * compute maximum number of some structures 3631 */ 3632 if (parm->methods == &ehci_device_ctrl_methods) { 3633 3634 /* 3635 * The proof for the "nqtd" formula is illustrated like 3636 * this: 3637 * 3638 * +------------------------------------+ 3639 * | | 3640 * | |remainder -> | 3641 * | +-----+---+ | 3642 * | | xxx | x | frm 0 | 3643 * | +-----+---++ | 3644 * | | xxx | xx | frm 1 | 3645 * | +-----+----+ | 3646 * | ... | 3647 * +------------------------------------+ 3648 * 3649 * "xxx" means a completely full USB transfer descriptor 3650 * 3651 * "x" and "xx" means a short USB packet 3652 * 3653 * For the remainder of an USB transfer modulo 3654 * "max_data_length" we need two USB transfer descriptors. 3655 * One to transfer the remaining data and one to finalise 3656 * with a zero length packet in case the "force_short_xfer" 3657 * flag is set. We only need two USB transfer descriptors in 3658 * the case where the transfer length of the first one is a 3659 * factor of "max_frame_size". The rest of the needed USB 3660 * transfer descriptors is given by the buffer size divided 3661 * by the maximum data payload. 3662 */ 3663 parm->hc_max_packet_size = 0x400; 3664 parm->hc_max_packet_count = 1; 3665 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3666 xfer->flags_int.bdma_enable = 1; 3667 3668 usbd_transfer_setup_sub(parm); 3669 3670 nqh = 1; 3671 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3672 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3673 } else if (parm->methods == &ehci_device_bulk_methods) { 3674 3675 parm->hc_max_packet_size = 0x400; 3676 parm->hc_max_packet_count = 1; 3677 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3678 xfer->flags_int.bdma_enable = 1; 3679 3680 usbd_transfer_setup_sub(parm); 3681 3682 nqh = 1; 3683 nqtd = ((2 * xfer->nframes) 3684 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3685 3686 } else if (parm->methods == &ehci_device_intr_methods) { 3687 3688 if (parm->speed == USB_SPEED_HIGH) { 3689 parm->hc_max_packet_size = 0x400; 3690 parm->hc_max_packet_count = 3; 3691 } else if (parm->speed == USB_SPEED_FULL) { 3692 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3693 parm->hc_max_packet_count = 1; 3694 } else { 3695 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3696 parm->hc_max_packet_count = 1; 3697 } 3698 3699 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3700 xfer->flags_int.bdma_enable = 1; 3701 3702 usbd_transfer_setup_sub(parm); 3703 3704 nqh = 1; 3705 nqtd = ((2 * xfer->nframes) 3706 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3707 3708 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3709 3710 parm->hc_max_packet_size = 0x3FF; 3711 parm->hc_max_packet_count = 1; 3712 parm->hc_max_frame_size = 0x3FF; 3713 xfer->flags_int.bdma_enable = 1; 3714 3715 usbd_transfer_setup_sub(parm); 3716 3717 nsitd = xfer->nframes; 3718 3719 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3720 3721 parm->hc_max_packet_size = 0x400; 3722 parm->hc_max_packet_count = 3; 3723 parm->hc_max_frame_size = 0xC00; 3724 xfer->flags_int.bdma_enable = 1; 3725 3726 usbd_transfer_setup_sub(parm); 3727 3728 nitd = ((xfer->nframes + 7) / 8) << 3729 usbd_xfer_get_fps_shift(xfer); 3730 3731 } else { 3732 3733 parm->hc_max_packet_size = 0x400; 3734 parm->hc_max_packet_count = 1; 3735 parm->hc_max_frame_size = 0x400; 3736 3737 usbd_transfer_setup_sub(parm); 3738 } 3739 3740 alloc_dma_set: 3741 3742 if (parm->err) { 3743 return; 3744 } 3745 /* 3746 * Allocate queue heads and transfer descriptors 3747 */ 3748 last_obj = NULL; 3749 3750 if (usbd_transfer_setup_sub_malloc( 3751 parm, &pc, sizeof(ehci_itd_t), 3752 EHCI_ITD_ALIGN, nitd)) { 3753 parm->err = USB_ERR_NOMEM; 3754 return; 3755 } 3756 if (parm->buf) { 3757 for (n = 0; n != nitd; n++) { 3758 ehci_itd_t *td; 3759 3760 usbd_get_page(pc + n, 0, &page_info); 3761 3762 td = page_info.buffer; 3763 3764 /* init TD */ 3765 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3766 td->obj_next = last_obj; 3767 td->page_cache = pc + n; 3768 3769 last_obj = td; 3770 3771 usb_pc_cpu_flush(pc + n); 3772 } 3773 } 3774 if (usbd_transfer_setup_sub_malloc( 3775 parm, &pc, sizeof(ehci_sitd_t), 3776 EHCI_SITD_ALIGN, nsitd)) { 3777 parm->err = USB_ERR_NOMEM; 3778 return; 3779 } 3780 if (parm->buf) { 3781 for (n = 0; n != nsitd; n++) { 3782 ehci_sitd_t *td; 3783 3784 usbd_get_page(pc + n, 0, &page_info); 3785 3786 td = page_info.buffer; 3787 3788 /* init TD */ 3789 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3790 td->obj_next = last_obj; 3791 td->page_cache = pc + n; 3792 3793 last_obj = td; 3794 3795 usb_pc_cpu_flush(pc + n); 3796 } 3797 } 3798 if (usbd_transfer_setup_sub_malloc( 3799 parm, &pc, sizeof(ehci_qtd_t), 3800 EHCI_QTD_ALIGN, nqtd)) { 3801 parm->err = USB_ERR_NOMEM; 3802 return; 3803 } 3804 if (parm->buf) { 3805 for (n = 0; n != nqtd; n++) { 3806 ehci_qtd_t *qtd; 3807 3808 usbd_get_page(pc + n, 0, &page_info); 3809 3810 qtd = page_info.buffer; 3811 3812 /* init TD */ 3813 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3814 qtd->obj_next = last_obj; 3815 qtd->page_cache = pc + n; 3816 3817 last_obj = qtd; 3818 3819 usb_pc_cpu_flush(pc + n); 3820 } 3821 } 3822 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3823 3824 last_obj = NULL; 3825 3826 if (usbd_transfer_setup_sub_malloc( 3827 parm, &pc, sizeof(ehci_qh_t), 3828 EHCI_QH_ALIGN, nqh)) { 3829 parm->err = USB_ERR_NOMEM; 3830 return; 3831 } 3832 if (parm->buf) { 3833 for (n = 0; n != nqh; n++) { 3834 ehci_qh_t *qh; 3835 3836 usbd_get_page(pc + n, 0, &page_info); 3837 3838 qh = page_info.buffer; 3839 3840 /* init QH */ 3841 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3842 qh->obj_next = last_obj; 3843 qh->page_cache = pc + n; 3844 3845 last_obj = qh; 3846 3847 usb_pc_cpu_flush(pc + n); 3848 } 3849 } 3850 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3851 3852 if (!xfer->flags_int.curr_dma_set) { 3853 xfer->flags_int.curr_dma_set = 1; 3854 goto alloc_dma_set; 3855 } 3856 } 3857 3858 static void 3859 ehci_xfer_unsetup(struct usb_xfer *xfer) 3860 { 3861 return; 3862 } 3863 3864 static void 3865 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3866 struct usb_endpoint *ep) 3867 { 3868 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3869 3870 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3871 ep, udev->address, 3872 edesc->bEndpointAddress, udev->flags.usb_mode, 3873 sc->sc_addr); 3874 3875 if (udev->device_index != sc->sc_addr) { 3876 3877 if ((udev->speed != USB_SPEED_HIGH) && 3878 ((udev->hs_hub_addr == 0) || 3879 (udev->hs_port_no == 0) || 3880 (udev->parent_hs_hub == NULL) || 3881 (udev->parent_hs_hub->hub == NULL))) { 3882 /* We need a transaction translator */ 3883 goto done; 3884 } 3885 switch (edesc->bmAttributes & UE_XFERTYPE) { 3886 case UE_CONTROL: 3887 ep->methods = &ehci_device_ctrl_methods; 3888 break; 3889 case UE_INTERRUPT: 3890 ep->methods = &ehci_device_intr_methods; 3891 break; 3892 case UE_ISOCHRONOUS: 3893 if (udev->speed == USB_SPEED_HIGH) { 3894 ep->methods = &ehci_device_isoc_hs_methods; 3895 } else if (udev->speed == USB_SPEED_FULL) { 3896 ep->methods = &ehci_device_isoc_fs_methods; 3897 } 3898 break; 3899 case UE_BULK: 3900 ep->methods = &ehci_device_bulk_methods; 3901 break; 3902 default: 3903 /* do nothing */ 3904 break; 3905 } 3906 } 3907 done: 3908 return; 3909 } 3910 3911 static void 3912 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3913 { 3914 /* 3915 * Wait until the hardware has finished any possible use of 3916 * the transfer descriptor(s) and QH 3917 */ 3918 *pus = (188); /* microseconds */ 3919 } 3920 3921 static void 3922 ehci_device_resume(struct usb_device *udev) 3923 { 3924 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3925 struct usb_xfer *xfer; 3926 const struct usb_pipe_methods *methods; 3927 3928 DPRINTF("\n"); 3929 3930 USB_BUS_LOCK(udev->bus); 3931 3932 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3933 3934 if (xfer->xroot->udev == udev) { 3935 3936 methods = xfer->endpoint->methods; 3937 KKASSERT(xfer->flags_int.onhwqueue == 0); 3938 if ((methods == &ehci_device_bulk_methods) || 3939 (methods == &ehci_device_ctrl_methods)) { 3940 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3941 sc->sc_async_p_last); 3942 } 3943 if (methods == &ehci_device_intr_methods) { 3944 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3945 sc->sc_intr_p_last[xfer->qh_pos]); 3946 } 3947 xfer->flags_int.onhwqueue = 1; 3948 } 3949 } 3950 ehci_ring_doorbell(sc, NULL); 3951 3952 USB_BUS_UNLOCK(udev->bus); 3953 3954 return; 3955 } 3956 3957 static void 3958 ehci_device_suspend(struct usb_device *udev) 3959 { 3960 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3961 struct usb_xfer *xfer; 3962 const struct usb_pipe_methods *methods; 3963 3964 DPRINTF("\n"); 3965 3966 USB_BUS_LOCK(udev->bus); 3967 3968 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3969 3970 if (xfer->xroot->udev == udev) { 3971 methods = xfer->endpoint->methods; 3972 3973 if ((methods == &ehci_device_bulk_methods) || 3974 (methods == &ehci_device_ctrl_methods)) { 3975 EHCI_REMOVE_QH(sc, xfer->qh_start[xfer->flags_int.curr_dma_set], 3976 sc->sc_async_p_last); 3977 } 3978 if (methods == &ehci_device_intr_methods) { 3979 EHCI_REMOVE_QH(sc, xfer->qh_start[xfer->flags_int.curr_dma_set], 3980 sc->sc_intr_p_last[xfer->qh_pos]); 3981 } 3982 xfer->flags_int.onhwqueue = 0; 3983 } 3984 } 3985 ehci_ring_doorbell(sc, NULL); 3986 3987 USB_BUS_UNLOCK(udev->bus); 3988 } 3989 3990 static void 3991 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3992 { 3993 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3994 3995 switch (state) { 3996 case USB_HW_POWER_SUSPEND: 3997 case USB_HW_POWER_SHUTDOWN: 3998 ehci_suspend(sc); 3999 break; 4000 case USB_HW_POWER_RESUME: 4001 ehci_resume(sc); 4002 break; 4003 default: 4004 break; 4005 } 4006 } 4007 4008 static void 4009 ehci_set_hw_power(struct usb_bus *bus) 4010 { 4011 ehci_softc_t *sc = EHCI_BUS2SC(bus); 4012 uint32_t temp; 4013 uint32_t flags; 4014 4015 DPRINTF("\n"); 4016 4017 USB_BUS_LOCK(bus); 4018 4019 flags = bus->hw_power_state; 4020 4021 temp = EOREAD4(sc, EHCI_USBCMD); 4022 4023 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 4024 4025 if (flags & (USB_HW_POWER_CONTROL | 4026 USB_HW_POWER_BULK)) { 4027 DPRINTF("Async is active\n"); 4028 temp |= EHCI_CMD_ASE; 4029 } 4030 if (flags & (USB_HW_POWER_INTERRUPT | 4031 USB_HW_POWER_ISOC)) { 4032 DPRINTF("Periodic is active\n"); 4033 temp |= EHCI_CMD_PSE; 4034 } 4035 EOWRITE4(sc, EHCI_USBCMD, temp); 4036 4037 USB_BUS_UNLOCK(bus); 4038 4039 return; 4040 } 4041 4042 static const struct usb_bus_methods ehci_bus_methods = 4043 { 4044 .endpoint_init = ehci_ep_init, 4045 .xfer_setup = ehci_xfer_setup, 4046 .xfer_unsetup = ehci_xfer_unsetup, 4047 .get_dma_delay = ehci_get_dma_delay, 4048 .device_resume = ehci_device_resume, 4049 .device_suspend = ehci_device_suspend, 4050 .set_hw_power = ehci_set_hw_power, 4051 .set_hw_power_sleep = ehci_set_hw_power_sleep, 4052 .roothub_exec = ehci_roothub_exec, 4053 .xfer_poll = ehci_do_poll, 4054 }; 4055