1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 31 * 32 * The EHCI 0.96 spec can be found at 33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 34 * The EHCI 1.0 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 36 * and the USB 2.0 spec at 37 * http://www.usb.org/developers/docs/usb_20.zip 38 * 39 */ 40 41 /* 42 * TODO: 43 * 1) command failures are not recovered correctly 44 */ 45 46 #include <sys/stdint.h> 47 #include <sys/param.h> 48 #include <sys/queue.h> 49 #include <sys/types.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/bus.h> 53 #include <sys/module.h> 54 #include <sys/lock.h> 55 #include <sys/condvar.h> 56 #include <sys/sysctl.h> 57 #include <sys/unistd.h> 58 #include <sys/callout.h> 59 #include <sys/malloc.h> 60 #include <sys/priv.h> 61 62 #include <bus/u4b/usb.h> 63 #include <bus/u4b/usbdi.h> 64 65 #define USB_DEBUG_VAR ehcidebug 66 67 #include <bus/u4b/usb_core.h> 68 #include <bus/u4b/usb_debug.h> 69 #include <bus/u4b/usb_busdma.h> 70 #include <bus/u4b/usb_process.h> 71 #include <bus/u4b/usb_transfer.h> 72 #include <bus/u4b/usb_device.h> 73 #include <bus/u4b/usb_hub.h> 74 #include <bus/u4b/usb_util.h> 75 76 #include <bus/u4b/usb_controller.h> 77 #include <bus/u4b/usb_bus.h> 78 #include <bus/u4b/controller/ehci.h> 79 #include <bus/u4b/controller/ehcireg.h> 80 81 #define EHCI_BUS2SC(bus) \ 82 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 83 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 84 85 #ifdef USB_DEBUG 86 static int ehcidebug = 0; 87 static int ehcinohighspeed = 0; 88 static int ehciiaadbug = 0; 89 static int ehcilostintrbug = 0; 90 91 static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 92 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW, 93 &ehcidebug, 0, "Debug level"); 94 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 95 &ehcinohighspeed, 0, "Disable High Speed USB"); 96 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW, 97 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 98 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW, 99 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 100 101 TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug); 102 TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed); 103 TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug); 104 TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug); 105 106 static void ehci_dump_regs(ehci_softc_t *sc); 107 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 108 109 #endif 110 111 #define EHCI_INTR_ENDPT 1 112 113 extern struct usb_bus_methods ehci_bus_methods; 114 extern struct usb_pipe_methods ehci_device_bulk_methods; 115 extern struct usb_pipe_methods ehci_device_ctrl_methods; 116 extern struct usb_pipe_methods ehci_device_intr_methods; 117 extern struct usb_pipe_methods ehci_device_isoc_fs_methods; 118 extern struct usb_pipe_methods ehci_device_isoc_hs_methods; 119 120 static void ehci_do_poll(struct usb_bus *); 121 static void ehci_device_done(struct usb_xfer *, usb_error_t); 122 static uint8_t ehci_check_transfer(struct usb_xfer *); 123 static void ehci_timeout(void *); 124 static void ehci_poll_timeout(void *); 125 126 static void ehci_root_intr(ehci_softc_t *sc); 127 128 struct ehci_std_temp { 129 ehci_softc_t *sc; 130 struct usb_page_cache *pc; 131 ehci_qtd_t *td; 132 ehci_qtd_t *td_next; 133 uint32_t average; 134 uint32_t qtd_status; 135 uint32_t len; 136 uint16_t max_frame_size; 137 uint8_t shortpkt; 138 uint8_t auto_data_toggle; 139 uint8_t setup_alt_next; 140 uint8_t last_frame; 141 }; 142 143 void 144 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 145 { 146 ehci_softc_t *sc = EHCI_BUS2SC(bus); 147 uint32_t i; 148 149 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 150 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 151 152 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 153 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 154 155 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 156 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 157 158 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 159 cb(bus, sc->sc_hw.intr_start_pc + i, 160 sc->sc_hw.intr_start_pg + i, 161 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 162 } 163 164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 165 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 166 sc->sc_hw.isoc_hs_start_pg + i, 167 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 168 } 169 170 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 171 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 172 sc->sc_hw.isoc_fs_start_pg + i, 173 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 174 } 175 } 176 177 usb_error_t 178 ehci_reset(ehci_softc_t *sc) 179 { 180 uint32_t hcr; 181 int i; 182 183 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 184 for (i = 0; i < 100; i++) { 185 usb_pause_mtx(NULL, hz / 128); 186 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 187 if (!hcr) { 188 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) { 189 /* 190 * Force USBMODE as requested. Controllers 191 * may have multiple operating modes. 192 */ 193 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE); 194 if (sc->sc_flags & EHCI_SCFLG_SETMODE) { 195 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST; 196 device_printf(sc->sc_bus.bdev, 197 "set host controller mode\n"); 198 } 199 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) { 200 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE; 201 device_printf(sc->sc_bus.bdev, 202 "set big-endian mode\n"); 203 } 204 EOWRITE4(sc, EHCI_USBMODE, usbmode); 205 } 206 return (0); 207 } 208 } 209 device_printf(sc->sc_bus.bdev, "Reset timeout\n"); 210 return (USB_ERR_IOERROR); 211 } 212 213 static usb_error_t 214 ehci_hcreset(ehci_softc_t *sc) 215 { 216 uint32_t hcr; 217 int i; 218 219 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 220 for (i = 0; i < 100; i++) { 221 usb_pause_mtx(NULL, hz / 128); 222 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 223 if (hcr) 224 break; 225 } 226 if (!hcr) 227 /* 228 * Fall through and try reset anyway even though 229 * Table 2-9 in the EHCI spec says this will result 230 * in undefined behavior. 231 */ 232 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 233 234 return (ehci_reset(sc)); 235 } 236 237 static int 238 ehci_init_sub(struct ehci_softc *sc) 239 { 240 struct usb_page_search buf_res; 241 uint32_t cparams; 242 uint32_t hcr; 243 uint8_t i; 244 245 cparams = EREAD4(sc, EHCI_HCCPARAMS); 246 247 DPRINTF("cparams=0x%x\n", cparams); 248 249 if (EHCI_HCC_64BIT(cparams)) { 250 DPRINTF("HCC uses 64-bit structures\n"); 251 252 /* MUST clear segment register if 64 bit capable */ 253 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 254 } 255 256 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 257 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 258 259 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 260 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 261 262 /* enable interrupts */ 263 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 264 265 /* turn on controller */ 266 EOWRITE4(sc, EHCI_USBCMD, 267 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 268 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 269 EHCI_CMD_ASE | 270 EHCI_CMD_PSE | 271 EHCI_CMD_RS); 272 273 /* Take over port ownership */ 274 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 275 276 for (i = 0; i < 100; i++) { 277 usb_pause_mtx(NULL, hz / 128); 278 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 279 if (!hcr) { 280 break; 281 } 282 } 283 if (hcr) { 284 device_printf(sc->sc_bus.bdev, "Run timeout\n"); 285 return (USB_ERR_IOERROR); 286 } 287 return (USB_ERR_NORMAL_COMPLETION); 288 } 289 290 usb_error_t 291 ehci_init(ehci_softc_t *sc) 292 { 293 struct usb_page_search buf_res; 294 uint32_t version; 295 uint32_t sparams; 296 uint16_t i; 297 uint16_t x; 298 uint16_t y; 299 uint16_t bit; 300 usb_error_t err = 0; 301 302 DPRINTF("start\n"); 303 304 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_lock, 0); 305 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_lock, 0); 306 307 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 308 309 #ifdef USB_DEBUG 310 if (ehciiaadbug) 311 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 312 if (ehcilostintrbug) 313 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 314 if (ehcidebug > 2) { 315 ehci_dump_regs(sc); 316 } 317 #endif 318 319 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 320 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 321 version >> 8, version & 0xff); 322 323 sparams = EREAD4(sc, EHCI_HCSPARAMS); 324 DPRINTF("sparams=0x%x\n", sparams); 325 326 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 327 sc->sc_bus.usbrev = USB_REV_2_0; 328 329 /* Reset the controller */ 330 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 331 332 err = ehci_hcreset(sc); 333 if (err) { 334 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 335 return (err); 336 } 337 /* 338 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 339 * bytes 2: 256*4 bytes 3: unknown 340 */ 341 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 342 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 343 return (USB_ERR_IOERROR); 344 } 345 /* set up the bus struct */ 346 sc->sc_bus.methods = &ehci_bus_methods; 347 348 sc->sc_eintrs = EHCI_NORMAL_INTRS; 349 350 if (1) { 351 struct ehci_qh_sub *qh; 352 353 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 354 355 qh = buf_res.buffer; 356 357 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 358 359 /* init terminate TD */ 360 qh->qtd_next = 361 htohc32(sc, EHCI_LINK_TERMINATE); 362 qh->qtd_altnext = 363 htohc32(sc, EHCI_LINK_TERMINATE); 364 qh->qtd_status = 365 htohc32(sc, EHCI_QTD_HALTED); 366 } 367 368 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 369 ehci_qh_t *qh; 370 371 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 372 373 qh = buf_res.buffer; 374 375 /* initialize page cache pointer */ 376 377 qh->page_cache = sc->sc_hw.intr_start_pc + i; 378 379 /* store a pointer to queue head */ 380 381 sc->sc_intr_p_last[i] = qh; 382 383 qh->qh_self = 384 htohc32(sc, buf_res.physaddr) | 385 htohc32(sc, EHCI_LINK_QH); 386 387 qh->qh_endp = 388 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 389 qh->qh_endphub = 390 htohc32(sc, EHCI_QH_SET_MULT(1)); 391 qh->qh_curqtd = 0; 392 393 qh->qh_qtd.qtd_next = 394 htohc32(sc, EHCI_LINK_TERMINATE); 395 qh->qh_qtd.qtd_altnext = 396 htohc32(sc, EHCI_LINK_TERMINATE); 397 qh->qh_qtd.qtd_status = 398 htohc32(sc, EHCI_QTD_HALTED); 399 } 400 401 /* 402 * the QHs are arranged to give poll intervals that are 403 * powers of 2 times 1ms 404 */ 405 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 406 while (bit) { 407 x = bit; 408 while (x & bit) { 409 ehci_qh_t *qh_x; 410 ehci_qh_t *qh_y; 411 412 y = (x ^ bit) | (bit / 2); 413 414 qh_x = sc->sc_intr_p_last[x]; 415 qh_y = sc->sc_intr_p_last[y]; 416 417 /* 418 * the next QH has half the poll interval 419 */ 420 qh_x->qh_link = qh_y->qh_self; 421 422 x++; 423 } 424 bit >>= 1; 425 } 426 427 if (1) { 428 ehci_qh_t *qh; 429 430 qh = sc->sc_intr_p_last[0]; 431 432 /* the last (1ms) QH terminates */ 433 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 434 } 435 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 436 ehci_sitd_t *sitd; 437 ehci_itd_t *itd; 438 439 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 440 441 sitd = buf_res.buffer; 442 443 /* initialize page cache pointer */ 444 445 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 446 447 /* store a pointer to the transfer descriptor */ 448 449 sc->sc_isoc_fs_p_last[i] = sitd; 450 451 /* initialize full speed isochronous */ 452 453 sitd->sitd_self = 454 htohc32(sc, buf_res.physaddr) | 455 htohc32(sc, EHCI_LINK_SITD); 456 457 sitd->sitd_back = 458 htohc32(sc, EHCI_LINK_TERMINATE); 459 460 sitd->sitd_next = 461 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 462 463 464 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 465 466 itd = buf_res.buffer; 467 468 /* initialize page cache pointer */ 469 470 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 471 472 /* store a pointer to the transfer descriptor */ 473 474 sc->sc_isoc_hs_p_last[i] = itd; 475 476 /* initialize high speed isochronous */ 477 478 itd->itd_self = 479 htohc32(sc, buf_res.physaddr) | 480 htohc32(sc, EHCI_LINK_ITD); 481 482 itd->itd_next = 483 sitd->sitd_self; 484 } 485 486 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 487 488 if (1) { 489 uint32_t *pframes; 490 491 pframes = buf_res.buffer; 492 493 /* 494 * execution order: 495 * pframes -> high speed isochronous -> 496 * full speed isochronous -> interrupt QH's 497 */ 498 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 499 pframes[i] = sc->sc_isoc_hs_p_last 500 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 501 } 502 } 503 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 504 505 if (1) { 506 507 ehci_qh_t *qh; 508 509 qh = buf_res.buffer; 510 511 /* initialize page cache pointer */ 512 513 qh->page_cache = &sc->sc_hw.async_start_pc; 514 515 /* store a pointer to the queue head */ 516 517 sc->sc_async_p_last = qh; 518 519 /* init dummy QH that starts the async list */ 520 521 qh->qh_self = 522 htohc32(sc, buf_res.physaddr) | 523 htohc32(sc, EHCI_LINK_QH); 524 525 /* fill the QH */ 526 qh->qh_endp = 527 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 528 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 529 qh->qh_link = qh->qh_self; 530 qh->qh_curqtd = 0; 531 532 /* fill the overlay qTD */ 533 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 534 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 535 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 536 } 537 /* flush all cache into memory */ 538 539 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 540 541 #ifdef USB_DEBUG 542 if (ehcidebug) { 543 ehci_dump_sqh(sc, sc->sc_async_p_last); 544 } 545 #endif 546 547 /* finial setup */ 548 err = ehci_init_sub(sc); 549 550 if (!err) { 551 /* catch any lost interrupts */ 552 ehci_do_poll(&sc->sc_bus); 553 } 554 return (err); 555 } 556 557 /* 558 * shut down the controller when the system is going down 559 */ 560 void 561 ehci_detach(ehci_softc_t *sc) 562 { 563 USB_BUS_LOCK(&sc->sc_bus); 564 565 usb_callout_stop(&sc->sc_tmo_pcd); 566 usb_callout_stop(&sc->sc_tmo_poll); 567 568 EOWRITE4(sc, EHCI_USBINTR, 0); 569 USB_BUS_UNLOCK(&sc->sc_bus); 570 571 if (ehci_hcreset(sc)) { 572 DPRINTF("reset failed!\n"); 573 } 574 575 /* XXX let stray task complete */ 576 usb_pause_mtx(NULL, hz / 20); 577 578 usb_callout_drain(&sc->sc_tmo_pcd); 579 usb_callout_drain(&sc->sc_tmo_poll); 580 } 581 582 static void 583 ehci_suspend(ehci_softc_t *sc) 584 { 585 DPRINTF("stopping the HC\n"); 586 587 /* reset HC */ 588 ehci_hcreset(sc); 589 } 590 591 static void 592 ehci_resume(ehci_softc_t *sc) 593 { 594 /* reset HC */ 595 ehci_hcreset(sc); 596 597 /* setup HC */ 598 ehci_init_sub(sc); 599 600 /* catch any lost interrupts */ 601 ehci_do_poll(&sc->sc_bus); 602 } 603 604 #ifdef USB_DEBUG 605 static void 606 ehci_dump_regs(ehci_softc_t *sc) 607 { 608 uint32_t i; 609 610 i = EOREAD4(sc, EHCI_USBCMD); 611 kprintf("cmd=0x%08x\n", i); 612 613 if (i & EHCI_CMD_ITC_1) 614 kprintf(" EHCI_CMD_ITC_1\n"); 615 if (i & EHCI_CMD_ITC_2) 616 kprintf(" EHCI_CMD_ITC_2\n"); 617 if (i & EHCI_CMD_ITC_4) 618 kprintf(" EHCI_CMD_ITC_4\n"); 619 if (i & EHCI_CMD_ITC_8) 620 kprintf(" EHCI_CMD_ITC_8\n"); 621 if (i & EHCI_CMD_ITC_16) 622 kprintf(" EHCI_CMD_ITC_16\n"); 623 if (i & EHCI_CMD_ITC_32) 624 kprintf(" EHCI_CMD_ITC_32\n"); 625 if (i & EHCI_CMD_ITC_64) 626 kprintf(" EHCI_CMD_ITC_64\n"); 627 if (i & EHCI_CMD_ASPME) 628 kprintf(" EHCI_CMD_ASPME\n"); 629 if (i & EHCI_CMD_ASPMC) 630 kprintf(" EHCI_CMD_ASPMC\n"); 631 if (i & EHCI_CMD_LHCR) 632 kprintf(" EHCI_CMD_LHCR\n"); 633 if (i & EHCI_CMD_IAAD) 634 kprintf(" EHCI_CMD_IAAD\n"); 635 if (i & EHCI_CMD_ASE) 636 kprintf(" EHCI_CMD_ASE\n"); 637 if (i & EHCI_CMD_PSE) 638 kprintf(" EHCI_CMD_PSE\n"); 639 if (i & EHCI_CMD_FLS_M) 640 kprintf(" EHCI_CMD_FLS_M\n"); 641 if (i & EHCI_CMD_HCRESET) 642 kprintf(" EHCI_CMD_HCRESET\n"); 643 if (i & EHCI_CMD_RS) 644 kprintf(" EHCI_CMD_RS\n"); 645 646 i = EOREAD4(sc, EHCI_USBSTS); 647 648 kprintf("sts=0x%08x\n", i); 649 650 if (i & EHCI_STS_ASS) 651 kprintf(" EHCI_STS_ASS\n"); 652 if (i & EHCI_STS_PSS) 653 kprintf(" EHCI_STS_PSS\n"); 654 if (i & EHCI_STS_REC) 655 kprintf(" EHCI_STS_REC\n"); 656 if (i & EHCI_STS_HCH) 657 kprintf(" EHCI_STS_HCH\n"); 658 if (i & EHCI_STS_IAA) 659 kprintf(" EHCI_STS_IAA\n"); 660 if (i & EHCI_STS_HSE) 661 kprintf(" EHCI_STS_HSE\n"); 662 if (i & EHCI_STS_FLR) 663 kprintf(" EHCI_STS_FLR\n"); 664 if (i & EHCI_STS_PCD) 665 kprintf(" EHCI_STS_PCD\n"); 666 if (i & EHCI_STS_ERRINT) 667 kprintf(" EHCI_STS_ERRINT\n"); 668 if (i & EHCI_STS_INT) 669 kprintf(" EHCI_STS_INT\n"); 670 671 kprintf("ien=0x%08x\n", 672 EOREAD4(sc, EHCI_USBINTR)); 673 kprintf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 674 EOREAD4(sc, EHCI_FRINDEX), 675 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 676 EOREAD4(sc, EHCI_PERIODICLISTBASE), 677 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 678 for (i = 1; i <= sc->sc_noport; i++) { 679 kprintf("port %d status=0x%08x\n", i, 680 EOREAD4(sc, EHCI_PORTSC(i))); 681 } 682 } 683 684 static void 685 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 686 { 687 link = hc32toh(sc, link); 688 kprintf("0x%08x", link); 689 if (link & EHCI_LINK_TERMINATE) 690 kprintf("<T>"); 691 else { 692 kprintf("<"); 693 if (type) { 694 switch (EHCI_LINK_TYPE(link)) { 695 case EHCI_LINK_ITD: 696 kprintf("ITD"); 697 break; 698 case EHCI_LINK_QH: 699 kprintf("QH"); 700 break; 701 case EHCI_LINK_SITD: 702 kprintf("SITD"); 703 break; 704 case EHCI_LINK_FSTN: 705 kprintf("FSTN"); 706 break; 707 } 708 } 709 kprintf(">"); 710 } 711 } 712 713 static void 714 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 715 { 716 uint32_t s; 717 718 kprintf(" next="); 719 ehci_dump_link(sc, qtd->qtd_next, 0); 720 kprintf(" altnext="); 721 ehci_dump_link(sc, qtd->qtd_altnext, 0); 722 kprintf("\n"); 723 s = hc32toh(sc, qtd->qtd_status); 724 kprintf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 725 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 726 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 727 kprintf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 728 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 729 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 730 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 731 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 732 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 733 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 734 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 735 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 736 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 737 738 for (s = 0; s < 5; s++) { 739 kprintf(" buffer[%d]=0x%08x\n", s, 740 hc32toh(sc, qtd->qtd_buffer[s])); 741 } 742 for (s = 0; s < 5; s++) { 743 kprintf(" buffer_hi[%d]=0x%08x\n", s, 744 hc32toh(sc, qtd->qtd_buffer_hi[s])); 745 } 746 } 747 748 static uint8_t 749 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 750 { 751 uint8_t temp; 752 753 usb_pc_cpu_invalidate(sqtd->page_cache); 754 kprintf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 755 ehci_dump_qtd(sc, sqtd); 756 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 757 return (temp); 758 } 759 760 static void 761 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 762 { 763 uint16_t i; 764 uint8_t stop; 765 766 stop = 0; 767 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 768 stop = ehci_dump_sqtd(sc, sqtd); 769 } 770 if (sqtd) { 771 kprintf("dump aborted, too many TDs\n"); 772 } 773 } 774 775 static void 776 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 777 { 778 uint32_t endp; 779 uint32_t endphub; 780 781 usb_pc_cpu_invalidate(qh->page_cache); 782 kprintf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 783 kprintf(" link="); 784 ehci_dump_link(sc, qh->qh_link, 1); 785 kprintf("\n"); 786 endp = hc32toh(sc, qh->qh_endp); 787 kprintf(" endp=0x%08x\n", endp); 788 kprintf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 789 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 790 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 791 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 792 kprintf(" mpl=0x%x ctl=%d nrl=%d\n", 793 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 794 EHCI_QH_GET_NRL(endp)); 795 endphub = hc32toh(sc, qh->qh_endphub); 796 kprintf(" endphub=0x%08x\n", endphub); 797 kprintf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 798 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 799 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 800 EHCI_QH_GET_MULT(endphub)); 801 kprintf(" curqtd="); 802 ehci_dump_link(sc, qh->qh_curqtd, 0); 803 kprintf("\n"); 804 kprintf("Overlay qTD:\n"); 805 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 806 } 807 808 static void 809 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 810 { 811 usb_pc_cpu_invalidate(sitd->page_cache); 812 kprintf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 813 kprintf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 814 kprintf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 815 hc32toh(sc, sitd->sitd_portaddr), 816 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 817 ? "in" : "out", 818 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 819 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 820 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 821 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 822 kprintf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 823 kprintf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 824 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 825 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 826 kprintf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 827 hc32toh(sc, sitd->sitd_back), 828 hc32toh(sc, sitd->sitd_bp[0]), 829 hc32toh(sc, sitd->sitd_bp[1]), 830 hc32toh(sc, sitd->sitd_bp_hi[0]), 831 hc32toh(sc, sitd->sitd_bp_hi[1])); 832 } 833 834 static void 835 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 836 { 837 usb_pc_cpu_invalidate(itd->page_cache); 838 kprintf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 839 kprintf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 840 kprintf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 841 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 842 kprintf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 843 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 844 kprintf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 845 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 846 kprintf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 847 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 848 kprintf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 849 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 850 kprintf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 851 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 852 kprintf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 853 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 854 kprintf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 855 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 856 kprintf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 857 kprintf(" addr=0x%02x; endpt=0x%01x\n", 858 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 859 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 860 kprintf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 861 kprintf(" dir=%s; mpl=0x%02x\n", 862 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 863 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 864 kprintf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 865 hc32toh(sc, itd->itd_bp[2]), 866 hc32toh(sc, itd->itd_bp[3]), 867 hc32toh(sc, itd->itd_bp[4]), 868 hc32toh(sc, itd->itd_bp[5]), 869 hc32toh(sc, itd->itd_bp[6])); 870 kprintf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 871 " 0x%08x,0x%08x,0x%08x\n", 872 hc32toh(sc, itd->itd_bp_hi[0]), 873 hc32toh(sc, itd->itd_bp_hi[1]), 874 hc32toh(sc, itd->itd_bp_hi[2]), 875 hc32toh(sc, itd->itd_bp_hi[3]), 876 hc32toh(sc, itd->itd_bp_hi[4]), 877 hc32toh(sc, itd->itd_bp_hi[5]), 878 hc32toh(sc, itd->itd_bp_hi[6])); 879 } 880 881 static void 882 ehci_dump_isoc(ehci_softc_t *sc) 883 { 884 ehci_itd_t *itd; 885 ehci_sitd_t *sitd; 886 uint16_t max = 1000; 887 uint16_t pos; 888 889 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 890 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 891 892 kprintf("%s: isochronous dump from frame 0x%03x:\n", 893 __func__, pos); 894 895 itd = sc->sc_isoc_hs_p_last[pos]; 896 sitd = sc->sc_isoc_fs_p_last[pos]; 897 898 while (itd && max && max--) { 899 ehci_dump_itd(sc, itd); 900 itd = itd->prev; 901 } 902 903 while (sitd && max && max--) { 904 ehci_dump_sitd(sc, sitd); 905 sitd = sitd->prev; 906 } 907 } 908 909 #endif 910 911 static void 912 ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 913 { 914 /* check for early completion */ 915 if (ehci_check_transfer(xfer)) { 916 return; 917 } 918 /* put transfer on interrupt queue */ 919 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 920 921 /* start timeout, if any */ 922 if (xfer->timeout != 0) { 923 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 924 } 925 } 926 927 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 928 static ehci_sitd_t * 929 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 930 { 931 DPRINTFN(11, "%p to %p\n", std, last); 932 933 /* (sc->sc_bus.mtx) must be locked */ 934 935 std->next = last->next; 936 std->sitd_next = last->sitd_next; 937 938 std->prev = last; 939 940 usb_pc_cpu_flush(std->page_cache); 941 942 /* 943 * the last->next->prev is never followed: std->next->prev = std; 944 */ 945 last->next = std; 946 last->sitd_next = std->sitd_self; 947 948 usb_pc_cpu_flush(last->page_cache); 949 950 return (std); 951 } 952 953 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 954 static ehci_itd_t * 955 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 956 { 957 DPRINTFN(11, "%p to %p\n", std, last); 958 959 /* (sc->sc_bus.mtx) must be locked */ 960 961 std->next = last->next; 962 std->itd_next = last->itd_next; 963 964 std->prev = last; 965 966 usb_pc_cpu_flush(std->page_cache); 967 968 /* 969 * the last->next->prev is never followed: std->next->prev = std; 970 */ 971 last->next = std; 972 last->itd_next = std->itd_self; 973 974 usb_pc_cpu_flush(last->page_cache); 975 976 return (std); 977 } 978 979 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 980 static ehci_qh_t * 981 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 982 { 983 DPRINTFN(11, "%p to %p\n", sqh, last); 984 985 if (sqh->prev != NULL) { 986 /* should not happen */ 987 DPRINTFN(0, "QH already linked!\n"); 988 return (last); 989 } 990 /* (sc->sc_bus.mtx) must be locked */ 991 992 sqh->next = last->next; 993 sqh->qh_link = last->qh_link; 994 995 sqh->prev = last; 996 997 usb_pc_cpu_flush(sqh->page_cache); 998 999 /* 1000 * the last->next->prev is never followed: sqh->next->prev = sqh; 1001 */ 1002 1003 last->next = sqh; 1004 last->qh_link = sqh->qh_self; 1005 1006 usb_pc_cpu_flush(last->page_cache); 1007 1008 return (sqh); 1009 } 1010 1011 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1012 static ehci_sitd_t * 1013 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1014 { 1015 DPRINTFN(11, "%p from %p\n", std, last); 1016 1017 /* (sc->sc_bus.mtx) must be locked */ 1018 1019 std->prev->next = std->next; 1020 std->prev->sitd_next = std->sitd_next; 1021 1022 usb_pc_cpu_flush(std->prev->page_cache); 1023 1024 if (std->next) { 1025 std->next->prev = std->prev; 1026 usb_pc_cpu_flush(std->next->page_cache); 1027 } 1028 return ((last == std) ? std->prev : last); 1029 } 1030 1031 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1032 static ehci_itd_t * 1033 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1034 { 1035 DPRINTFN(11, "%p from %p\n", std, last); 1036 1037 /* (sc->sc_bus.mtx) must be locked */ 1038 1039 std->prev->next = std->next; 1040 std->prev->itd_next = std->itd_next; 1041 1042 usb_pc_cpu_flush(std->prev->page_cache); 1043 1044 if (std->next) { 1045 std->next->prev = std->prev; 1046 usb_pc_cpu_flush(std->next->page_cache); 1047 } 1048 return ((last == std) ? std->prev : last); 1049 } 1050 1051 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1052 static ehci_qh_t * 1053 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1054 { 1055 DPRINTFN(11, "%p from %p\n", sqh, last); 1056 1057 /* (sc->sc_bus.mtx) must be locked */ 1058 1059 /* only remove if not removed from a queue */ 1060 if (sqh->prev) { 1061 1062 sqh->prev->next = sqh->next; 1063 sqh->prev->qh_link = sqh->qh_link; 1064 1065 usb_pc_cpu_flush(sqh->prev->page_cache); 1066 1067 if (sqh->next) { 1068 sqh->next->prev = sqh->prev; 1069 usb_pc_cpu_flush(sqh->next->page_cache); 1070 } 1071 last = ((last == sqh) ? sqh->prev : last); 1072 1073 sqh->prev = 0; 1074 1075 usb_pc_cpu_flush(sqh->page_cache); 1076 } 1077 return (last); 1078 } 1079 1080 static void 1081 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1082 { 1083 uint16_t rem; 1084 uint8_t dt; 1085 1086 /* count number of full packets */ 1087 dt = (actlen / xfer->max_packet_size) & 1; 1088 1089 /* compute remainder */ 1090 rem = actlen % xfer->max_packet_size; 1091 1092 if (rem > 0) 1093 dt ^= 1; /* short packet at the end */ 1094 else if (actlen != xlen) 1095 dt ^= 1; /* zero length packet at the end */ 1096 else if (xlen == 0) 1097 dt ^= 1; /* zero length transfer */ 1098 1099 xfer->endpoint->toggle_next ^= dt; 1100 } 1101 1102 static usb_error_t 1103 ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1104 { 1105 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1106 ehci_qtd_t *td; 1107 ehci_qtd_t *td_alt_next; 1108 uint32_t status; 1109 uint16_t len; 1110 1111 td = xfer->td_transfer_cache; 1112 td_alt_next = td->alt_next; 1113 1114 if (xfer->aframes != xfer->nframes) { 1115 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1116 } 1117 while (1) { 1118 1119 usb_pc_cpu_invalidate(td->page_cache); 1120 status = hc32toh(sc, td->qtd_status); 1121 1122 len = EHCI_QTD_GET_BYTES(status); 1123 1124 /* 1125 * Verify the status length and 1126 * add the length to "frlengths[]": 1127 */ 1128 if (len > td->len) { 1129 /* should not happen */ 1130 DPRINTF("Invalid status length, " 1131 "0x%04x/0x%04x bytes\n", len, td->len); 1132 status |= EHCI_QTD_HALTED; 1133 } else if (xfer->aframes != xfer->nframes) { 1134 xfer->frlengths[xfer->aframes] += td->len - len; 1135 /* manually update data toggle */ 1136 ehci_data_toggle_update(xfer, td->len - len, td->len); 1137 } 1138 1139 /* Check for last transfer */ 1140 if (((void *)td) == xfer->td_transfer_last) { 1141 td = NULL; 1142 break; 1143 } 1144 /* Check for transfer error */ 1145 if (status & EHCI_QTD_HALTED) { 1146 /* the transfer is finished */ 1147 td = NULL; 1148 break; 1149 } 1150 /* Check for short transfer */ 1151 if (len > 0) { 1152 if (xfer->flags_int.short_frames_ok) { 1153 /* follow alt next */ 1154 td = td->alt_next; 1155 } else { 1156 /* the transfer is finished */ 1157 td = NULL; 1158 } 1159 break; 1160 } 1161 td = td->obj_next; 1162 1163 if (td->alt_next != td_alt_next) { 1164 /* this USB frame is complete */ 1165 break; 1166 } 1167 } 1168 1169 /* update transfer cache */ 1170 1171 xfer->td_transfer_cache = td; 1172 1173 #ifdef USB_DEBUG 1174 if (status & EHCI_QTD_STATERRS) { 1175 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1176 "status=%s%s%s%s%s%s%s%s\n", 1177 xfer->address, xfer->endpointno, xfer->aframes, 1178 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1179 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1180 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1181 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1182 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1183 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1184 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1185 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1186 } 1187 #endif 1188 1189 return ((status & EHCI_QTD_HALTED) ? 1190 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1191 } 1192 1193 static void 1194 ehci_non_isoc_done(struct usb_xfer *xfer) 1195 { 1196 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1197 ehci_qh_t *qh; 1198 uint32_t status; 1199 usb_error_t err = 0; 1200 1201 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1202 xfer, xfer->endpoint); 1203 1204 #ifdef USB_DEBUG 1205 if (ehcidebug > 10) { 1206 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1207 1208 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1209 } 1210 #endif 1211 1212 /* extract data toggle directly from the QH's overlay area */ 1213 1214 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1215 1216 usb_pc_cpu_invalidate(qh->page_cache); 1217 1218 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1219 1220 /* reset scanner */ 1221 1222 xfer->td_transfer_cache = xfer->td_transfer_first; 1223 1224 if (xfer->flags_int.control_xfr) { 1225 1226 if (xfer->flags_int.control_hdr) { 1227 1228 err = ehci_non_isoc_done_sub(xfer); 1229 } 1230 xfer->aframes = 1; 1231 1232 if (xfer->td_transfer_cache == NULL) { 1233 goto done; 1234 } 1235 } 1236 while (xfer->aframes != xfer->nframes) { 1237 1238 err = ehci_non_isoc_done_sub(xfer); 1239 xfer->aframes++; 1240 1241 if (xfer->td_transfer_cache == NULL) { 1242 goto done; 1243 } 1244 } 1245 1246 if (xfer->flags_int.control_xfr && 1247 !xfer->flags_int.control_act) { 1248 1249 err = ehci_non_isoc_done_sub(xfer); 1250 } 1251 done: 1252 ehci_device_done(xfer, err); 1253 } 1254 1255 /*------------------------------------------------------------------------* 1256 * ehci_check_transfer 1257 * 1258 * Return values: 1259 * 0: USB transfer is not finished 1260 * Else: USB transfer is finished 1261 *------------------------------------------------------------------------*/ 1262 static uint8_t 1263 ehci_check_transfer(struct usb_xfer *xfer) 1264 { 1265 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1266 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1267 1268 uint32_t status; 1269 1270 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1271 1272 if (methods == &ehci_device_isoc_fs_methods) { 1273 ehci_sitd_t *td; 1274 1275 /* isochronous full speed transfer */ 1276 1277 td = xfer->td_transfer_last; 1278 usb_pc_cpu_invalidate(td->page_cache); 1279 status = hc32toh(sc, td->sitd_status); 1280 1281 /* also check if first is complete */ 1282 1283 td = xfer->td_transfer_first; 1284 usb_pc_cpu_invalidate(td->page_cache); 1285 status |= hc32toh(sc, td->sitd_status); 1286 1287 if (!(status & EHCI_SITD_ACTIVE)) { 1288 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1289 goto transferred; 1290 } 1291 } else if (methods == &ehci_device_isoc_hs_methods) { 1292 ehci_itd_t *td; 1293 1294 /* isochronous high speed transfer */ 1295 1296 /* check last transfer */ 1297 td = xfer->td_transfer_last; 1298 usb_pc_cpu_invalidate(td->page_cache); 1299 status = td->itd_status[0]; 1300 status |= td->itd_status[1]; 1301 status |= td->itd_status[2]; 1302 status |= td->itd_status[3]; 1303 status |= td->itd_status[4]; 1304 status |= td->itd_status[5]; 1305 status |= td->itd_status[6]; 1306 status |= td->itd_status[7]; 1307 1308 /* also check first transfer */ 1309 td = xfer->td_transfer_first; 1310 usb_pc_cpu_invalidate(td->page_cache); 1311 status |= td->itd_status[0]; 1312 status |= td->itd_status[1]; 1313 status |= td->itd_status[2]; 1314 status |= td->itd_status[3]; 1315 status |= td->itd_status[4]; 1316 status |= td->itd_status[5]; 1317 status |= td->itd_status[6]; 1318 status |= td->itd_status[7]; 1319 1320 /* if no transactions are active we continue */ 1321 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1322 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1323 goto transferred; 1324 } 1325 } else { 1326 ehci_qtd_t *td; 1327 ehci_qh_t *qh; 1328 1329 /* non-isochronous transfer */ 1330 1331 /* 1332 * check whether there is an error somewhere in the middle, 1333 * or whether there was a short packet (SPD and not ACTIVE) 1334 */ 1335 td = xfer->td_transfer_cache; 1336 1337 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1338 1339 usb_pc_cpu_invalidate(qh->page_cache); 1340 1341 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1342 if (status & EHCI_QTD_ACTIVE) { 1343 /* transfer is pending */ 1344 goto done; 1345 } 1346 1347 while (1) { 1348 usb_pc_cpu_invalidate(td->page_cache); 1349 status = hc32toh(sc, td->qtd_status); 1350 1351 /* 1352 * Check if there is an active TD which 1353 * indicates that the transfer isn't done. 1354 */ 1355 if (status & EHCI_QTD_ACTIVE) { 1356 /* update cache */ 1357 xfer->td_transfer_cache = td; 1358 goto done; 1359 } 1360 /* 1361 * last transfer descriptor makes the transfer done 1362 */ 1363 if (((void *)td) == xfer->td_transfer_last) { 1364 break; 1365 } 1366 /* 1367 * any kind of error makes the transfer done 1368 */ 1369 if (status & EHCI_QTD_HALTED) { 1370 break; 1371 } 1372 /* 1373 * if there is no alternate next transfer, a short 1374 * packet also makes the transfer done 1375 */ 1376 if (EHCI_QTD_GET_BYTES(status)) { 1377 if (xfer->flags_int.short_frames_ok) { 1378 /* follow alt next */ 1379 if (td->alt_next) { 1380 td = td->alt_next; 1381 continue; 1382 } 1383 } 1384 /* transfer is done */ 1385 break; 1386 } 1387 td = td->obj_next; 1388 } 1389 ehci_non_isoc_done(xfer); 1390 goto transferred; 1391 } 1392 1393 done: 1394 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1395 return (0); 1396 1397 transferred: 1398 return (1); 1399 } 1400 1401 static void 1402 ehci_pcd_enable(ehci_softc_t *sc) 1403 { 1404 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 1405 1406 sc->sc_eintrs |= EHCI_STS_PCD; 1407 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1408 1409 /* acknowledge any PCD interrupt */ 1410 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1411 1412 ehci_root_intr(sc); 1413 } 1414 1415 static void 1416 ehci_interrupt_poll(ehci_softc_t *sc) 1417 { 1418 struct usb_xfer *xfer; 1419 1420 repeat: 1421 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1422 /* 1423 * check if transfer is transferred 1424 */ 1425 if (ehci_check_transfer(xfer)) { 1426 /* queue has been modified */ 1427 goto repeat; 1428 } 1429 } 1430 } 1431 1432 /* 1433 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1434 * writing back the qTD status, or miss signalling occasionally under 1435 * heavy load. If the host machine is too fast, we can miss 1436 * transaction completion - when we scan the active list the 1437 * transaction still seems to be active. This generally exhibits 1438 * itself as a umass stall that never recovers. 1439 * 1440 * We work around this behaviour by setting up this callback after any 1441 * softintr that completes with transactions still pending, giving us 1442 * another chance to check for completion after the writeback has 1443 * taken place. 1444 */ 1445 static void 1446 ehci_poll_timeout(void *arg) 1447 { 1448 ehci_softc_t *sc = arg; 1449 1450 DPRINTFN(3, "\n"); 1451 ehci_interrupt_poll(sc); 1452 } 1453 1454 /*------------------------------------------------------------------------* 1455 * ehci_interrupt - EHCI interrupt handler 1456 * 1457 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1458 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1459 * is present ! 1460 *------------------------------------------------------------------------*/ 1461 void 1462 ehci_interrupt(ehci_softc_t *sc) 1463 { 1464 uint32_t status; 1465 1466 USB_BUS_LOCK(&sc->sc_bus); 1467 1468 DPRINTFN(16, "real interrupt\n"); 1469 1470 #ifdef USB_DEBUG 1471 if (ehcidebug > 15) { 1472 ehci_dump_regs(sc); 1473 } 1474 #endif 1475 1476 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1477 if (status == 0) { 1478 /* the interrupt was not for us */ 1479 goto done; 1480 } 1481 if (!(status & sc->sc_eintrs)) { 1482 goto done; 1483 } 1484 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1485 1486 status &= sc->sc_eintrs; 1487 1488 if (status & EHCI_STS_HSE) { 1489 kprintf("%s: unrecoverable error, " 1490 "controller halted\n", __func__); 1491 #ifdef USB_DEBUG 1492 ehci_dump_regs(sc); 1493 ehci_dump_isoc(sc); 1494 #endif 1495 } 1496 if (status & EHCI_STS_PCD) { 1497 /* 1498 * Disable PCD interrupt for now, because it will be 1499 * on until the port has been reset. 1500 */ 1501 sc->sc_eintrs &= ~EHCI_STS_PCD; 1502 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1503 1504 ehci_root_intr(sc); 1505 1506 /* do not allow RHSC interrupts > 1 per second */ 1507 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1508 (void *)&ehci_pcd_enable, sc); 1509 } 1510 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1511 1512 if (status != 0) { 1513 /* block unprocessed interrupts */ 1514 sc->sc_eintrs &= ~status; 1515 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1516 kprintf("%s: blocking interrupts 0x%x\n", __func__, status); 1517 } 1518 /* poll all the USB transfers */ 1519 ehci_interrupt_poll(sc); 1520 1521 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1522 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1523 (void *)&ehci_poll_timeout, sc); 1524 } 1525 1526 done: 1527 USB_BUS_UNLOCK(&sc->sc_bus); 1528 } 1529 1530 /* 1531 * called when a request does not complete 1532 */ 1533 static void 1534 ehci_timeout(void *arg) 1535 { 1536 struct usb_xfer *xfer = arg; 1537 1538 DPRINTF("xfer=%p\n", xfer); 1539 1540 USB_BUS_LOCK_ASSERT(xfer->xroot->bus); 1541 1542 /* transfer is transferred */ 1543 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1544 } 1545 1546 static void 1547 ehci_do_poll(struct usb_bus *bus) 1548 { 1549 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1550 1551 USB_BUS_LOCK(&sc->sc_bus); 1552 ehci_interrupt_poll(sc); 1553 USB_BUS_UNLOCK(&sc->sc_bus); 1554 } 1555 1556 static void 1557 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1558 { 1559 struct usb_page_search buf_res; 1560 ehci_qtd_t *td; 1561 ehci_qtd_t *td_next; 1562 ehci_qtd_t *td_alt_next; 1563 uint32_t buf_offset; 1564 uint32_t average; 1565 uint32_t len_old; 1566 uint32_t terminate; 1567 uint32_t qtd_altnext; 1568 uint8_t shortpkt_old; 1569 uint8_t precompute; 1570 1571 terminate = temp->sc->sc_terminate_self; 1572 qtd_altnext = temp->sc->sc_terminate_self; 1573 td_alt_next = NULL; 1574 buf_offset = 0; 1575 shortpkt_old = temp->shortpkt; 1576 len_old = temp->len; 1577 precompute = 1; 1578 1579 restart: 1580 1581 td = temp->td; 1582 td_next = temp->td_next; 1583 1584 while (1) { 1585 1586 if (temp->len == 0) { 1587 1588 if (temp->shortpkt) { 1589 break; 1590 } 1591 /* send a Zero Length Packet, ZLP, last */ 1592 1593 temp->shortpkt = 1; 1594 average = 0; 1595 1596 } else { 1597 1598 average = temp->average; 1599 1600 if (temp->len < average) { 1601 if (temp->len % temp->max_frame_size) { 1602 temp->shortpkt = 1; 1603 } 1604 average = temp->len; 1605 } 1606 } 1607 1608 if (td_next == NULL) { 1609 panic("%s: out of EHCI transfer descriptors!", __func__); 1610 } 1611 /* get next TD */ 1612 1613 td = td_next; 1614 td_next = td->obj_next; 1615 1616 /* check if we are pre-computing */ 1617 1618 if (precompute) { 1619 1620 /* update remaining length */ 1621 1622 temp->len -= average; 1623 1624 continue; 1625 } 1626 /* fill out current TD */ 1627 1628 td->qtd_status = 1629 temp->qtd_status | 1630 htohc32(temp->sc, EHCI_QTD_IOC | 1631 EHCI_QTD_SET_BYTES(average)); 1632 1633 if (average == 0) { 1634 1635 if (temp->auto_data_toggle == 0) { 1636 1637 /* update data toggle, ZLP case */ 1638 1639 temp->qtd_status ^= 1640 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1641 } 1642 td->len = 0; 1643 1644 td->qtd_buffer[0] = 0; 1645 td->qtd_buffer_hi[0] = 0; 1646 1647 td->qtd_buffer[1] = 0; 1648 td->qtd_buffer_hi[1] = 0; 1649 1650 } else { 1651 1652 uint8_t x; 1653 1654 if (temp->auto_data_toggle == 0) { 1655 1656 /* update data toggle */ 1657 1658 if (((average + temp->max_frame_size - 1) / 1659 temp->max_frame_size) & 1) { 1660 temp->qtd_status ^= 1661 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1662 } 1663 } 1664 td->len = average; 1665 1666 /* update remaining length */ 1667 1668 temp->len -= average; 1669 1670 /* fill out buffer pointers */ 1671 1672 usbd_get_page(temp->pc, buf_offset, &buf_res); 1673 td->qtd_buffer[0] = 1674 htohc32(temp->sc, buf_res.physaddr); 1675 td->qtd_buffer_hi[0] = 0; 1676 1677 x = 1; 1678 1679 while (average > EHCI_PAGE_SIZE) { 1680 average -= EHCI_PAGE_SIZE; 1681 buf_offset += EHCI_PAGE_SIZE; 1682 usbd_get_page(temp->pc, buf_offset, &buf_res); 1683 td->qtd_buffer[x] = 1684 htohc32(temp->sc, 1685 buf_res.physaddr & (~0xFFF)); 1686 td->qtd_buffer_hi[x] = 0; 1687 x++; 1688 } 1689 1690 /* 1691 * NOTE: The "average" variable is never zero after 1692 * exiting the loop above ! 1693 * 1694 * NOTE: We have to subtract one from the offset to 1695 * ensure that we are computing the physical address 1696 * of a valid page ! 1697 */ 1698 buf_offset += average; 1699 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1700 td->qtd_buffer[x] = 1701 htohc32(temp->sc, 1702 buf_res.physaddr & (~0xFFF)); 1703 td->qtd_buffer_hi[x] = 0; 1704 } 1705 1706 if (td_next) { 1707 /* link the current TD with the next one */ 1708 td->qtd_next = td_next->qtd_self; 1709 } 1710 td->qtd_altnext = qtd_altnext; 1711 td->alt_next = td_alt_next; 1712 1713 usb_pc_cpu_flush(td->page_cache); 1714 } 1715 1716 if (precompute) { 1717 precompute = 0; 1718 1719 /* setup alt next pointer, if any */ 1720 if (temp->last_frame) { 1721 td_alt_next = NULL; 1722 qtd_altnext = terminate; 1723 } else { 1724 /* we use this field internally */ 1725 td_alt_next = td_next; 1726 if (temp->setup_alt_next) { 1727 qtd_altnext = td_next->qtd_self; 1728 } else { 1729 qtd_altnext = terminate; 1730 } 1731 } 1732 1733 /* restore */ 1734 temp->shortpkt = shortpkt_old; 1735 temp->len = len_old; 1736 goto restart; 1737 } 1738 temp->td = td; 1739 temp->td_next = td_next; 1740 } 1741 1742 static void 1743 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1744 { 1745 struct ehci_std_temp temp; 1746 struct usb_pipe_methods *methods; 1747 ehci_qh_t *qh; 1748 ehci_qtd_t *td; 1749 uint32_t qh_endp; 1750 uint32_t qh_endphub; 1751 uint32_t x; 1752 1753 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1754 xfer->address, UE_GET_ADDR(xfer->endpointno), 1755 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1756 1757 temp.average = xfer->max_hc_frame_size; 1758 temp.max_frame_size = xfer->max_frame_size; 1759 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1760 1761 /* toggle the DMA set we are using */ 1762 xfer->flags_int.curr_dma_set ^= 1; 1763 1764 /* get next DMA set */ 1765 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1766 1767 xfer->td_transfer_first = td; 1768 xfer->td_transfer_cache = td; 1769 1770 temp.td = NULL; 1771 temp.td_next = td; 1772 temp.qtd_status = 0; 1773 temp.last_frame = 0; 1774 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1775 1776 if (xfer->flags_int.control_xfr) { 1777 if (xfer->endpoint->toggle_next) { 1778 /* DATA1 is next */ 1779 temp.qtd_status |= 1780 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1781 } 1782 temp.auto_data_toggle = 0; 1783 } else { 1784 temp.auto_data_toggle = 1; 1785 } 1786 1787 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1788 (xfer->xroot->udev->address != 0)) { 1789 /* max 3 retries */ 1790 temp.qtd_status |= 1791 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1792 } 1793 /* check if we should prepend a setup message */ 1794 1795 if (xfer->flags_int.control_xfr) { 1796 if (xfer->flags_int.control_hdr) { 1797 1798 xfer->endpoint->toggle_next = 0; 1799 1800 temp.qtd_status &= 1801 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1802 temp.qtd_status |= htohc32(temp.sc, 1803 EHCI_QTD_ACTIVE | 1804 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1805 EHCI_QTD_SET_TOGGLE(0)); 1806 1807 temp.len = xfer->frlengths[0]; 1808 temp.pc = xfer->frbuffers + 0; 1809 temp.shortpkt = temp.len ? 1 : 0; 1810 /* check for last frame */ 1811 if (xfer->nframes == 1) { 1812 /* no STATUS stage yet, SETUP is last */ 1813 if (xfer->flags_int.control_act) { 1814 temp.last_frame = 1; 1815 temp.setup_alt_next = 0; 1816 } 1817 } 1818 ehci_setup_standard_chain_sub(&temp); 1819 } 1820 x = 1; 1821 } else { 1822 x = 0; 1823 } 1824 1825 while (x != xfer->nframes) { 1826 1827 /* DATA0 / DATA1 message */ 1828 1829 temp.len = xfer->frlengths[x]; 1830 temp.pc = xfer->frbuffers + x; 1831 1832 x++; 1833 1834 if (x == xfer->nframes) { 1835 if (xfer->flags_int.control_xfr) { 1836 /* no STATUS stage yet, DATA is last */ 1837 if (xfer->flags_int.control_act) { 1838 temp.last_frame = 1; 1839 temp.setup_alt_next = 0; 1840 } 1841 } else { 1842 temp.last_frame = 1; 1843 temp.setup_alt_next = 0; 1844 } 1845 } 1846 /* keep previous data toggle and error count */ 1847 1848 temp.qtd_status &= 1849 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1850 EHCI_QTD_SET_TOGGLE(1)); 1851 1852 if (temp.len == 0) { 1853 1854 /* make sure that we send an USB packet */ 1855 1856 temp.shortpkt = 0; 1857 1858 } else { 1859 1860 /* regular data transfer */ 1861 1862 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1863 } 1864 1865 /* set endpoint direction */ 1866 1867 temp.qtd_status |= 1868 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1869 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1870 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1871 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1872 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1873 1874 ehci_setup_standard_chain_sub(&temp); 1875 } 1876 1877 /* check if we should append a status stage */ 1878 1879 if (xfer->flags_int.control_xfr && 1880 !xfer->flags_int.control_act) { 1881 1882 /* 1883 * Send a DATA1 message and invert the current endpoint 1884 * direction. 1885 */ 1886 1887 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1888 EHCI_QTD_SET_TOGGLE(1)); 1889 temp.qtd_status |= 1890 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1891 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1892 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1893 EHCI_QTD_SET_TOGGLE(1)) : 1894 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1895 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1896 EHCI_QTD_SET_TOGGLE(1)); 1897 1898 temp.len = 0; 1899 temp.pc = NULL; 1900 temp.shortpkt = 0; 1901 temp.last_frame = 1; 1902 temp.setup_alt_next = 0; 1903 1904 ehci_setup_standard_chain_sub(&temp); 1905 } 1906 td = temp.td; 1907 1908 /* the last TD terminates the transfer: */ 1909 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1910 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1911 1912 usb_pc_cpu_flush(td->page_cache); 1913 1914 /* must have at least one frame! */ 1915 1916 xfer->td_transfer_last = td; 1917 1918 #ifdef USB_DEBUG 1919 if (ehcidebug > 8) { 1920 DPRINTF("nexttog=%d; data before transfer:\n", 1921 xfer->endpoint->toggle_next); 1922 ehci_dump_sqtds(temp.sc, 1923 xfer->td_transfer_first); 1924 } 1925 #endif 1926 1927 methods = xfer->endpoint->methods; 1928 1929 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1930 1931 /* the "qh_link" field is filled when the QH is added */ 1932 1933 qh_endp = 1934 (EHCI_QH_SET_ADDR(xfer->address) | 1935 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1936 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1937 1938 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1939 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1940 if (methods != &ehci_device_intr_methods) 1941 qh_endp |= EHCI_QH_SET_NRL(8); 1942 } else { 1943 1944 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1945 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 1946 } else { 1947 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 1948 } 1949 1950 if (methods == &ehci_device_ctrl_methods) { 1951 qh_endp |= EHCI_QH_CTL; 1952 } 1953 if (methods != &ehci_device_intr_methods) { 1954 /* Only try one time per microframe! */ 1955 qh_endp |= EHCI_QH_SET_NRL(1); 1956 } 1957 } 1958 1959 if (temp.auto_data_toggle == 0) { 1960 /* software computes the data toggle */ 1961 qh_endp |= EHCI_QH_DTC; 1962 } 1963 1964 qh->qh_endp = htohc32(temp.sc, qh_endp); 1965 1966 qh_endphub = 1967 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1968 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 1969 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 1970 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1971 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1972 1973 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1974 qh->qh_curqtd = 0; 1975 1976 /* fill the overlay qTD */ 1977 1978 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 1979 /* DATA1 is next */ 1980 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1981 } else { 1982 qh->qh_qtd.qtd_status = 0; 1983 } 1984 1985 td = xfer->td_transfer_first; 1986 1987 qh->qh_qtd.qtd_next = td->qtd_self; 1988 qh->qh_qtd.qtd_altnext = 1989 htohc32(temp.sc, EHCI_LINK_TERMINATE); 1990 1991 usb_pc_cpu_flush(qh->page_cache); 1992 1993 if (xfer->xroot->udev->flags.self_suspended == 0) { 1994 EHCI_APPEND_QH(qh, *qh_last); 1995 } 1996 } 1997 1998 static void 1999 ehci_root_intr(ehci_softc_t *sc) 2000 { 2001 uint16_t i; 2002 uint16_t m; 2003 2004 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2005 2006 /* clear any old interrupt data */ 2007 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2008 2009 /* set bits */ 2010 m = (sc->sc_noport + 1); 2011 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2012 m = (8 * sizeof(sc->sc_hub_idata)); 2013 } 2014 for (i = 1; i < m; i++) { 2015 /* pick out CHANGE bits from the status register */ 2016 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2017 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2018 DPRINTF("port %d changed\n", i); 2019 } 2020 } 2021 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2022 sizeof(sc->sc_hub_idata)); 2023 } 2024 2025 static void 2026 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2027 { 2028 uint32_t nframes = xfer->nframes; 2029 uint32_t status; 2030 uint32_t *plen = xfer->frlengths; 2031 uint16_t len = 0; 2032 ehci_sitd_t *td = xfer->td_transfer_first; 2033 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2034 2035 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2036 xfer, xfer->endpoint); 2037 2038 while (nframes--) { 2039 if (td == NULL) { 2040 panic("%s:%d: out of TD's\n", 2041 __func__, __LINE__); 2042 } 2043 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2044 pp_last = &sc->sc_isoc_fs_p_last[0]; 2045 } 2046 #ifdef USB_DEBUG 2047 if (ehcidebug > 15) { 2048 DPRINTF("isoc FS-TD\n"); 2049 ehci_dump_sitd(sc, td); 2050 } 2051 #endif 2052 usb_pc_cpu_invalidate(td->page_cache); 2053 status = hc32toh(sc, td->sitd_status); 2054 2055 len = EHCI_SITD_GET_LEN(status); 2056 2057 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2058 2059 if (*plen >= len) { 2060 len = *plen - len; 2061 } else { 2062 len = 0; 2063 } 2064 2065 *plen = len; 2066 2067 /* remove FS-TD from schedule */ 2068 EHCI_REMOVE_FS_TD(td, *pp_last); 2069 2070 pp_last++; 2071 plen++; 2072 td = td->obj_next; 2073 } 2074 2075 xfer->aframes = xfer->nframes; 2076 } 2077 2078 static void 2079 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2080 { 2081 uint32_t nframes = xfer->nframes; 2082 uint32_t status; 2083 uint32_t *plen = xfer->frlengths; 2084 uint16_t len = 0; 2085 uint8_t td_no = 0; 2086 ehci_itd_t *td = xfer->td_transfer_first; 2087 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2088 2089 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2090 xfer, xfer->endpoint); 2091 2092 while (nframes) { 2093 if (td == NULL) { 2094 panic("%s:%d: out of TD's\n", 2095 __func__, __LINE__); 2096 } 2097 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2098 pp_last = &sc->sc_isoc_hs_p_last[0]; 2099 } 2100 #ifdef USB_DEBUG 2101 if (ehcidebug > 15) { 2102 DPRINTF("isoc HS-TD\n"); 2103 ehci_dump_itd(sc, td); 2104 } 2105 #endif 2106 2107 usb_pc_cpu_invalidate(td->page_cache); 2108 status = hc32toh(sc, td->itd_status[td_no]); 2109 2110 len = EHCI_ITD_GET_LEN(status); 2111 2112 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2113 2114 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2115 2116 if (*plen >= len) { 2117 /* 2118 * The length is valid. NOTE: The 2119 * complete length is written back 2120 * into the status field, and not the 2121 * remainder like with other transfer 2122 * descriptor types. 2123 */ 2124 } else { 2125 /* Invalid length - truncate */ 2126 len = 0; 2127 } 2128 2129 *plen = len; 2130 plen++; 2131 nframes--; 2132 } 2133 2134 td_no++; 2135 2136 if ((td_no == 8) || (nframes == 0)) { 2137 /* remove HS-TD from schedule */ 2138 EHCI_REMOVE_HS_TD(td, *pp_last); 2139 pp_last++; 2140 2141 td_no = 0; 2142 td = td->obj_next; 2143 } 2144 } 2145 xfer->aframes = xfer->nframes; 2146 } 2147 2148 /* NOTE: "done" can be run two times in a row, 2149 * from close and from interrupt 2150 */ 2151 static void 2152 ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2153 { 2154 struct usb_pipe_methods *methods = xfer->endpoint->methods; 2155 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2156 2157 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2158 2159 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2160 xfer, xfer->endpoint, error); 2161 2162 if ((methods == &ehci_device_bulk_methods) || 2163 (methods == &ehci_device_ctrl_methods)) { 2164 #ifdef USB_DEBUG 2165 if (ehcidebug > 8) { 2166 DPRINTF("nexttog=%d; data after transfer:\n", 2167 xfer->endpoint->toggle_next); 2168 ehci_dump_sqtds(sc, 2169 xfer->td_transfer_first); 2170 } 2171 #endif 2172 2173 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2174 sc->sc_async_p_last); 2175 } 2176 if (methods == &ehci_device_intr_methods) { 2177 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2178 sc->sc_intr_p_last[xfer->qh_pos]); 2179 } 2180 /* 2181 * Only finish isochronous transfers once which will update 2182 * "xfer->frlengths". 2183 */ 2184 if (xfer->td_transfer_first && 2185 xfer->td_transfer_last) { 2186 if (methods == &ehci_device_isoc_fs_methods) { 2187 ehci_isoc_fs_done(sc, xfer); 2188 } 2189 if (methods == &ehci_device_isoc_hs_methods) { 2190 ehci_isoc_hs_done(sc, xfer); 2191 } 2192 xfer->td_transfer_first = NULL; 2193 xfer->td_transfer_last = NULL; 2194 } 2195 /* dequeue transfer and start next transfer */ 2196 usbd_transfer_done(xfer, error); 2197 } 2198 2199 /*------------------------------------------------------------------------* 2200 * ehci bulk support 2201 *------------------------------------------------------------------------*/ 2202 static void 2203 ehci_device_bulk_open(struct usb_xfer *xfer) 2204 { 2205 return; 2206 } 2207 2208 static void 2209 ehci_device_bulk_close(struct usb_xfer *xfer) 2210 { 2211 ehci_device_done(xfer, USB_ERR_CANCELLED); 2212 } 2213 2214 static void 2215 ehci_device_bulk_enter(struct usb_xfer *xfer) 2216 { 2217 return; 2218 } 2219 2220 static void 2221 ehci_device_bulk_start(struct usb_xfer *xfer) 2222 { 2223 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2224 uint32_t temp; 2225 2226 /* setup TD's and QH */ 2227 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2228 2229 /* put transfer on interrupt queue */ 2230 ehci_transfer_intr_enqueue(xfer); 2231 2232 /* 2233 * XXX Certain nVidia chipsets choke when using the IAAD 2234 * feature too frequently. 2235 */ 2236 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2237 return; 2238 2239 /* XXX Performance quirk: Some Host Controllers have a too low 2240 * interrupt rate. Issue an IAAD to stimulate the Host 2241 * Controller after queueing the BULK transfer. 2242 */ 2243 temp = EOREAD4(sc, EHCI_USBCMD); 2244 if (!(temp & EHCI_CMD_IAAD)) 2245 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2246 } 2247 2248 struct usb_pipe_methods ehci_device_bulk_methods = 2249 { 2250 .open = ehci_device_bulk_open, 2251 .close = ehci_device_bulk_close, 2252 .enter = ehci_device_bulk_enter, 2253 .start = ehci_device_bulk_start, 2254 }; 2255 2256 /*------------------------------------------------------------------------* 2257 * ehci control support 2258 *------------------------------------------------------------------------*/ 2259 static void 2260 ehci_device_ctrl_open(struct usb_xfer *xfer) 2261 { 2262 return; 2263 } 2264 2265 static void 2266 ehci_device_ctrl_close(struct usb_xfer *xfer) 2267 { 2268 ehci_device_done(xfer, USB_ERR_CANCELLED); 2269 } 2270 2271 static void 2272 ehci_device_ctrl_enter(struct usb_xfer *xfer) 2273 { 2274 return; 2275 } 2276 2277 static void 2278 ehci_device_ctrl_start(struct usb_xfer *xfer) 2279 { 2280 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2281 2282 /* setup TD's and QH */ 2283 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2284 2285 /* put transfer on interrupt queue */ 2286 ehci_transfer_intr_enqueue(xfer); 2287 } 2288 2289 struct usb_pipe_methods ehci_device_ctrl_methods = 2290 { 2291 .open = ehci_device_ctrl_open, 2292 .close = ehci_device_ctrl_close, 2293 .enter = ehci_device_ctrl_enter, 2294 .start = ehci_device_ctrl_start, 2295 }; 2296 2297 /*------------------------------------------------------------------------* 2298 * ehci interrupt support 2299 *------------------------------------------------------------------------*/ 2300 static void 2301 ehci_device_intr_open(struct usb_xfer *xfer) 2302 { 2303 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2304 uint16_t best; 2305 uint16_t bit; 2306 uint16_t x; 2307 2308 usb_hs_bandwidth_alloc(xfer); 2309 2310 /* 2311 * Find the best QH position corresponding to the given interval: 2312 */ 2313 2314 best = 0; 2315 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2316 while (bit) { 2317 if (xfer->interval >= bit) { 2318 x = bit; 2319 best = bit; 2320 while (x & bit) { 2321 if (sc->sc_intr_stat[x] < 2322 sc->sc_intr_stat[best]) { 2323 best = x; 2324 } 2325 x++; 2326 } 2327 break; 2328 } 2329 bit >>= 1; 2330 } 2331 2332 sc->sc_intr_stat[best]++; 2333 xfer->qh_pos = best; 2334 2335 DPRINTFN(3, "best=%d interval=%d\n", 2336 best, xfer->interval); 2337 } 2338 2339 static void 2340 ehci_device_intr_close(struct usb_xfer *xfer) 2341 { 2342 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2343 2344 sc->sc_intr_stat[xfer->qh_pos]--; 2345 2346 ehci_device_done(xfer, USB_ERR_CANCELLED); 2347 2348 /* bandwidth must be freed after device done */ 2349 usb_hs_bandwidth_free(xfer); 2350 } 2351 2352 static void 2353 ehci_device_intr_enter(struct usb_xfer *xfer) 2354 { 2355 return; 2356 } 2357 2358 static void 2359 ehci_device_intr_start(struct usb_xfer *xfer) 2360 { 2361 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2362 2363 /* setup TD's and QH */ 2364 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2365 2366 /* put transfer on interrupt queue */ 2367 ehci_transfer_intr_enqueue(xfer); 2368 } 2369 2370 struct usb_pipe_methods ehci_device_intr_methods = 2371 { 2372 .open = ehci_device_intr_open, 2373 .close = ehci_device_intr_close, 2374 .enter = ehci_device_intr_enter, 2375 .start = ehci_device_intr_start, 2376 }; 2377 2378 /*------------------------------------------------------------------------* 2379 * ehci full speed isochronous support 2380 *------------------------------------------------------------------------*/ 2381 static void 2382 ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2383 { 2384 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2385 ehci_sitd_t *td; 2386 uint32_t sitd_portaddr; 2387 uint8_t ds; 2388 2389 sitd_portaddr = 2390 EHCI_SITD_SET_ADDR(xfer->address) | 2391 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2392 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2393 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2394 2395 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2396 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2397 } 2398 sitd_portaddr = htohc32(sc, sitd_portaddr); 2399 2400 /* initialize all TD's */ 2401 2402 for (ds = 0; ds != 2; ds++) { 2403 2404 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2405 2406 td->sitd_portaddr = sitd_portaddr; 2407 2408 /* 2409 * TODO: make some kind of automatic 2410 * SMASK/CMASK selection based on micro-frame 2411 * usage 2412 * 2413 * micro-frame usage (8 microframes per 1ms) 2414 */ 2415 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2416 2417 usb_pc_cpu_flush(td->page_cache); 2418 } 2419 } 2420 } 2421 2422 static void 2423 ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2424 { 2425 ehci_device_done(xfer, USB_ERR_CANCELLED); 2426 } 2427 2428 static void 2429 ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2430 { 2431 struct usb_page_search buf_res; 2432 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2433 struct usb_fs_isoc_schedule *fss_start; 2434 struct usb_fs_isoc_schedule *fss_end; 2435 struct usb_fs_isoc_schedule *fss; 2436 ehci_sitd_t *td; 2437 ehci_sitd_t *td_last = NULL; 2438 ehci_sitd_t **pp_last; 2439 uint32_t *plen; 2440 uint32_t buf_offset; 2441 uint32_t nframes; 2442 uint32_t temp; 2443 uint32_t sitd_mask; 2444 uint16_t tlen; 2445 uint8_t sa; 2446 uint8_t sb; 2447 uint8_t error; 2448 2449 #ifdef USB_DEBUG 2450 uint8_t once = 1; 2451 2452 #endif 2453 2454 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2455 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2456 2457 /* get the current frame index */ 2458 2459 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2460 2461 /* 2462 * check if the frame index is within the window where the frames 2463 * will be inserted 2464 */ 2465 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2466 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2467 2468 if ((xfer->endpoint->is_synced == 0) || 2469 (buf_offset < xfer->nframes)) { 2470 /* 2471 * If there is data underflow or the pipe queue is empty we 2472 * schedule the transfer a few frames ahead of the current 2473 * frame position. Else two isochronous transfers might 2474 * overlap. 2475 */ 2476 xfer->endpoint->isoc_next = (nframes + 3) & 2477 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2478 xfer->endpoint->is_synced = 1; 2479 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2480 } 2481 /* 2482 * compute how many milliseconds the insertion is ahead of the 2483 * current frame position: 2484 */ 2485 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2486 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2487 2488 /* 2489 * pre-compute when the isochronous transfer will be finished: 2490 */ 2491 xfer->isoc_time_complete = 2492 usbd_fs_isoc_schedule_isoc_time_expand 2493 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset + 2494 xfer->nframes; 2495 2496 /* get the real number of frames */ 2497 2498 nframes = xfer->nframes; 2499 2500 buf_offset = 0; 2501 2502 plen = xfer->frlengths; 2503 2504 /* toggle the DMA set we are using */ 2505 xfer->flags_int.curr_dma_set ^= 1; 2506 2507 /* get next DMA set */ 2508 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2509 xfer->td_transfer_first = td; 2510 2511 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2512 2513 /* store starting position */ 2514 2515 xfer->qh_pos = xfer->endpoint->isoc_next; 2516 2517 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX); 2518 2519 while (nframes--) { 2520 if (td == NULL) { 2521 panic("%s:%d: out of TD's\n", 2522 __func__, __LINE__); 2523 } 2524 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2525 pp_last = &sc->sc_isoc_fs_p_last[0]; 2526 } 2527 if (fss >= fss_end) { 2528 fss = fss_start; 2529 } 2530 /* reuse sitd_portaddr and sitd_back from last transfer */ 2531 2532 if (*plen > xfer->max_frame_size) { 2533 #ifdef USB_DEBUG 2534 if (once) { 2535 once = 0; 2536 kprintf("%s: frame length(%d) exceeds %d " 2537 "bytes (frame truncated)\n", 2538 __func__, *plen, 2539 xfer->max_frame_size); 2540 } 2541 #endif 2542 *plen = xfer->max_frame_size; 2543 } 2544 /* 2545 * We currently don't care if the ISOCHRONOUS schedule is 2546 * full! 2547 */ 2548 error = usbd_fs_isoc_schedule_alloc(fss, &sa, *plen); 2549 if (error) { 2550 /* 2551 * The FULL speed schedule is FULL! Set length 2552 * to zero. 2553 */ 2554 *plen = 0; 2555 } 2556 if (*plen) { 2557 /* 2558 * only call "usbd_get_page()" when we have a 2559 * non-zero length 2560 */ 2561 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2562 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2563 buf_offset += *plen; 2564 /* 2565 * NOTE: We need to subtract one from the offset so 2566 * that we are on a valid page! 2567 */ 2568 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2569 &buf_res); 2570 temp = buf_res.physaddr & ~0xFFF; 2571 } else { 2572 td->sitd_bp[0] = 0; 2573 temp = 0; 2574 } 2575 2576 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2577 tlen = *plen; 2578 if (tlen <= 188) { 2579 temp |= 1; /* T-count = 1, TP = ALL */ 2580 tlen = 1; 2581 } else { 2582 tlen += 187; 2583 tlen /= 188; 2584 temp |= tlen; /* T-count = [1..6] */ 2585 temp |= 8; /* TP = Begin */ 2586 } 2587 2588 tlen += sa; 2589 2590 if (tlen >= 8) { 2591 sb = 0; 2592 } else { 2593 sb = (1 << tlen); 2594 } 2595 2596 sa = (1 << sa); 2597 sa = (sb - sa) & 0x3F; 2598 sb = 0; 2599 } else { 2600 sb = (-(4 << sa)) & 0xFE; 2601 sa = (1 << sa) & 0x3F; 2602 } 2603 2604 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2605 EHCI_SITD_SET_CMASK(sb)); 2606 2607 td->sitd_bp[1] = htohc32(sc, temp); 2608 2609 td->sitd_mask = htohc32(sc, sitd_mask); 2610 2611 if (nframes == 0) { 2612 td->sitd_status = htohc32(sc, 2613 EHCI_SITD_IOC | 2614 EHCI_SITD_ACTIVE | 2615 EHCI_SITD_SET_LEN(*plen)); 2616 } else { 2617 td->sitd_status = htohc32(sc, 2618 EHCI_SITD_ACTIVE | 2619 EHCI_SITD_SET_LEN(*plen)); 2620 } 2621 usb_pc_cpu_flush(td->page_cache); 2622 2623 #ifdef USB_DEBUG 2624 if (ehcidebug > 15) { 2625 DPRINTF("FS-TD %d\n", nframes); 2626 ehci_dump_sitd(sc, td); 2627 } 2628 #endif 2629 /* insert TD into schedule */ 2630 EHCI_APPEND_FS_TD(td, *pp_last); 2631 pp_last++; 2632 2633 plen++; 2634 fss++; 2635 td_last = td; 2636 td = td->obj_next; 2637 } 2638 2639 xfer->td_transfer_last = td_last; 2640 2641 /* update isoc_next */ 2642 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2643 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2644 } 2645 2646 static void 2647 ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2648 { 2649 /* put transfer on interrupt queue */ 2650 ehci_transfer_intr_enqueue(xfer); 2651 } 2652 2653 struct usb_pipe_methods ehci_device_isoc_fs_methods = 2654 { 2655 .open = ehci_device_isoc_fs_open, 2656 .close = ehci_device_isoc_fs_close, 2657 .enter = ehci_device_isoc_fs_enter, 2658 .start = ehci_device_isoc_fs_start, 2659 }; 2660 2661 /*------------------------------------------------------------------------* 2662 * ehci high speed isochronous support 2663 *------------------------------------------------------------------------*/ 2664 static void 2665 ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2666 { 2667 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2668 ehci_itd_t *td; 2669 uint32_t temp; 2670 uint8_t ds; 2671 2672 usb_hs_bandwidth_alloc(xfer); 2673 2674 /* initialize all TD's */ 2675 2676 for (ds = 0; ds != 2; ds++) { 2677 2678 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2679 2680 /* set TD inactive */ 2681 td->itd_status[0] = 0; 2682 td->itd_status[1] = 0; 2683 td->itd_status[2] = 0; 2684 td->itd_status[3] = 0; 2685 td->itd_status[4] = 0; 2686 td->itd_status[5] = 0; 2687 td->itd_status[6] = 0; 2688 td->itd_status[7] = 0; 2689 2690 /* set endpoint and address */ 2691 td->itd_bp[0] = htohc32(sc, 2692 EHCI_ITD_SET_ADDR(xfer->address) | 2693 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2694 2695 temp = 2696 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2697 2698 /* set direction */ 2699 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2700 temp |= EHCI_ITD_SET_DIR_IN; 2701 } 2702 /* set maximum packet size */ 2703 td->itd_bp[1] = htohc32(sc, temp); 2704 2705 /* set transfer multiplier */ 2706 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2707 2708 usb_pc_cpu_flush(td->page_cache); 2709 } 2710 } 2711 } 2712 2713 static void 2714 ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2715 { 2716 ehci_device_done(xfer, USB_ERR_CANCELLED); 2717 2718 /* bandwidth must be freed after device done */ 2719 usb_hs_bandwidth_free(xfer); 2720 } 2721 2722 static void 2723 ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2724 { 2725 struct usb_page_search buf_res; 2726 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2727 ehci_itd_t *td; 2728 ehci_itd_t *td_last = NULL; 2729 ehci_itd_t **pp_last; 2730 bus_size_t page_addr; 2731 uint32_t *plen; 2732 uint32_t status; 2733 uint32_t buf_offset; 2734 uint32_t nframes; 2735 uint32_t itd_offset[8 + 1]; 2736 uint8_t x; 2737 uint8_t td_no; 2738 uint8_t page_no; 2739 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 2740 2741 #ifdef USB_DEBUG 2742 uint8_t once = 1; 2743 2744 #endif 2745 2746 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2747 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift); 2748 2749 /* get the current frame index */ 2750 2751 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2752 2753 /* 2754 * check if the frame index is within the window where the frames 2755 * will be inserted 2756 */ 2757 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2758 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2759 2760 if ((xfer->endpoint->is_synced == 0) || 2761 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2762 /* 2763 * If there is data underflow or the pipe queue is empty we 2764 * schedule the transfer a few frames ahead of the current 2765 * frame position. Else two isochronous transfers might 2766 * overlap. 2767 */ 2768 xfer->endpoint->isoc_next = (nframes + 3) & 2769 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2770 xfer->endpoint->is_synced = 1; 2771 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2772 } 2773 /* 2774 * compute how many milliseconds the insertion is ahead of the 2775 * current frame position: 2776 */ 2777 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2778 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2779 2780 /* 2781 * pre-compute when the isochronous transfer will be finished: 2782 */ 2783 xfer->isoc_time_complete = 2784 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2785 (((xfer->nframes << shift) + 7) / 8); 2786 2787 /* get the real number of frames */ 2788 2789 nframes = xfer->nframes; 2790 2791 buf_offset = 0; 2792 td_no = 0; 2793 2794 plen = xfer->frlengths; 2795 2796 /* toggle the DMA set we are using */ 2797 xfer->flags_int.curr_dma_set ^= 1; 2798 2799 /* get next DMA set */ 2800 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2801 xfer->td_transfer_first = td; 2802 2803 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2804 2805 /* store starting position */ 2806 2807 xfer->qh_pos = xfer->endpoint->isoc_next; 2808 2809 while (nframes) { 2810 if (td == NULL) { 2811 panic("%s:%d: out of TD's\n", 2812 __func__, __LINE__); 2813 } 2814 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2815 pp_last = &sc->sc_isoc_hs_p_last[0]; 2816 } 2817 /* range check */ 2818 if (*plen > xfer->max_frame_size) { 2819 #ifdef USB_DEBUG 2820 if (once) { 2821 once = 0; 2822 kprintf("%s: frame length(%d) exceeds %d bytes " 2823 "(frame truncated)\n", 2824 __func__, *plen, xfer->max_frame_size); 2825 } 2826 #endif 2827 *plen = xfer->max_frame_size; 2828 } 2829 2830 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2831 status = (EHCI_ITD_SET_LEN(*plen) | 2832 EHCI_ITD_ACTIVE | 2833 EHCI_ITD_SET_PG(0)); 2834 td->itd_status[td_no] = htohc32(sc, status); 2835 itd_offset[td_no] = buf_offset; 2836 buf_offset += *plen; 2837 plen++; 2838 nframes --; 2839 } else { 2840 td->itd_status[td_no] = 0; /* not active */ 2841 itd_offset[td_no] = buf_offset; 2842 } 2843 2844 td_no++; 2845 2846 if ((td_no == 8) || (nframes == 0)) { 2847 2848 /* the rest of the transfers are not active, if any */ 2849 for (x = td_no; x != 8; x++) { 2850 td->itd_status[x] = 0; /* not active */ 2851 } 2852 2853 /* check if there is any data to be transferred */ 2854 if (itd_offset[0] != buf_offset) { 2855 page_no = 0; 2856 itd_offset[td_no] = buf_offset; 2857 2858 /* get first page offset */ 2859 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2860 /* get page address */ 2861 page_addr = buf_res.physaddr & ~0xFFF; 2862 /* update page address */ 2863 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2864 td->itd_bp[0] |= htohc32(sc, page_addr); 2865 2866 for (x = 0; x != td_no; x++) { 2867 /* set page number and page offset */ 2868 status = (EHCI_ITD_SET_PG(page_no) | 2869 (buf_res.physaddr & 0xFFF)); 2870 td->itd_status[x] |= htohc32(sc, status); 2871 2872 /* get next page offset */ 2873 if (itd_offset[x + 1] == buf_offset) { 2874 /* 2875 * We subtract one so that 2876 * we don't go off the last 2877 * page! 2878 */ 2879 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2880 } else { 2881 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2882 } 2883 2884 /* check if we need a new page */ 2885 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2886 /* new page needed */ 2887 page_addr = buf_res.physaddr & ~0xFFF; 2888 if (page_no == 6) { 2889 panic("%s: too many pages\n", __func__); 2890 } 2891 page_no++; 2892 /* update page address */ 2893 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2894 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2895 } 2896 } 2897 } 2898 /* set IOC bit if we are complete */ 2899 if (nframes == 0) { 2900 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2901 } 2902 usb_pc_cpu_flush(td->page_cache); 2903 #ifdef USB_DEBUG 2904 if (ehcidebug > 15) { 2905 DPRINTF("HS-TD %d\n", nframes); 2906 ehci_dump_itd(sc, td); 2907 } 2908 #endif 2909 /* insert TD into schedule */ 2910 EHCI_APPEND_HS_TD(td, *pp_last); 2911 pp_last++; 2912 2913 td_no = 0; 2914 td_last = td; 2915 td = td->obj_next; 2916 } 2917 } 2918 2919 xfer->td_transfer_last = td_last; 2920 2921 /* update isoc_next */ 2922 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2923 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2924 } 2925 2926 static void 2927 ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2928 { 2929 /* put transfer on interrupt queue */ 2930 ehci_transfer_intr_enqueue(xfer); 2931 } 2932 2933 struct usb_pipe_methods ehci_device_isoc_hs_methods = 2934 { 2935 .open = ehci_device_isoc_hs_open, 2936 .close = ehci_device_isoc_hs_close, 2937 .enter = ehci_device_isoc_hs_enter, 2938 .start = ehci_device_isoc_hs_start, 2939 }; 2940 2941 /*------------------------------------------------------------------------* 2942 * ehci root control support 2943 *------------------------------------------------------------------------* 2944 * Simulate a hardware hub by handling all the necessary requests. 2945 *------------------------------------------------------------------------*/ 2946 2947 static const 2948 struct usb_device_descriptor ehci_devd = 2949 { 2950 sizeof(struct usb_device_descriptor), 2951 UDESC_DEVICE, /* type */ 2952 {0x00, 0x02}, /* USB version */ 2953 UDCLASS_HUB, /* class */ 2954 UDSUBCLASS_HUB, /* subclass */ 2955 UDPROTO_HSHUBSTT, /* protocol */ 2956 64, /* max packet */ 2957 {0}, {0}, {0x00, 0x01}, /* device id */ 2958 1, 2, 0, /* string indicies */ 2959 1 /* # of configurations */ 2960 }; 2961 2962 static const 2963 struct usb_device_qualifier ehci_odevd = 2964 { 2965 sizeof(struct usb_device_qualifier), 2966 UDESC_DEVICE_QUALIFIER, /* type */ 2967 {0x00, 0x02}, /* USB version */ 2968 UDCLASS_HUB, /* class */ 2969 UDSUBCLASS_HUB, /* subclass */ 2970 UDPROTO_FSHUB, /* protocol */ 2971 0, /* max packet */ 2972 0, /* # of configurations */ 2973 0 2974 }; 2975 2976 static const struct ehci_config_desc ehci_confd = { 2977 .confd = { 2978 .bLength = sizeof(struct usb_config_descriptor), 2979 .bDescriptorType = UDESC_CONFIG, 2980 .wTotalLength[0] = sizeof(ehci_confd), 2981 .bNumInterface = 1, 2982 .bConfigurationValue = 1, 2983 .iConfiguration = 0, 2984 .bmAttributes = UC_SELF_POWERED, 2985 .bMaxPower = 0 /* max power */ 2986 }, 2987 .ifcd = { 2988 .bLength = sizeof(struct usb_interface_descriptor), 2989 .bDescriptorType = UDESC_INTERFACE, 2990 .bNumEndpoints = 1, 2991 .bInterfaceClass = UICLASS_HUB, 2992 .bInterfaceSubClass = UISUBCLASS_HUB, 2993 .bInterfaceProtocol = 0, 2994 }, 2995 .endpd = { 2996 .bLength = sizeof(struct usb_endpoint_descriptor), 2997 .bDescriptorType = UDESC_ENDPOINT, 2998 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 2999 .bmAttributes = UE_INTERRUPT, 3000 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3001 .bInterval = 255, 3002 }, 3003 }; 3004 3005 static const 3006 struct usb_hub_descriptor ehci_hubd = 3007 { 3008 0, /* dynamic length */ 3009 UDESC_HUB, 3010 0, 3011 {0, 0}, 3012 0, 3013 0, 3014 {0}, 3015 }; 3016 3017 static void 3018 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3019 { 3020 uint32_t port; 3021 uint32_t v; 3022 3023 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3024 3025 port = EHCI_PORTSC(index); 3026 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3027 EOWRITE4(sc, port, v | EHCI_PS_PO); 3028 } 3029 3030 static usb_error_t 3031 ehci_roothub_exec(struct usb_device *udev, 3032 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3033 { 3034 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3035 const char *str_ptr; 3036 const void *ptr; 3037 uint32_t port; 3038 uint32_t v; 3039 uint16_t len; 3040 uint16_t i; 3041 uint16_t value; 3042 uint16_t index; 3043 usb_error_t err; 3044 3045 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 3046 3047 /* buffer reset */ 3048 ptr = (const void *)&sc->sc_hub_desc; 3049 len = 0; 3050 err = 0; 3051 3052 value = UGETW(req->wValue); 3053 index = UGETW(req->wIndex); 3054 3055 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3056 "wValue=0x%04x wIndex=0x%04x\n", 3057 req->bmRequestType, req->bRequest, 3058 UGETW(req->wLength), value, index); 3059 3060 #define C(x,y) ((x) | ((y) << 8)) 3061 switch (C(req->bRequest, req->bmRequestType)) { 3062 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3063 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3064 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3065 /* 3066 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3067 * for the integrated root hub. 3068 */ 3069 break; 3070 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3071 len = 1; 3072 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3073 break; 3074 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3075 switch (value >> 8) { 3076 case UDESC_DEVICE: 3077 if ((value & 0xff) != 0) { 3078 err = USB_ERR_IOERROR; 3079 goto done; 3080 } 3081 len = sizeof(ehci_devd); 3082 ptr = (const void *)&ehci_devd; 3083 break; 3084 /* 3085 * We can't really operate at another speed, 3086 * but the specification says we need this 3087 * descriptor: 3088 */ 3089 case UDESC_DEVICE_QUALIFIER: 3090 if ((value & 0xff) != 0) { 3091 err = USB_ERR_IOERROR; 3092 goto done; 3093 } 3094 len = sizeof(ehci_odevd); 3095 ptr = (const void *)&ehci_odevd; 3096 break; 3097 3098 case UDESC_CONFIG: 3099 if ((value & 0xff) != 0) { 3100 err = USB_ERR_IOERROR; 3101 goto done; 3102 } 3103 len = sizeof(ehci_confd); 3104 ptr = (const void *)&ehci_confd; 3105 break; 3106 3107 case UDESC_STRING: 3108 switch (value & 0xff) { 3109 case 0: /* Language table */ 3110 str_ptr = "\001"; 3111 break; 3112 3113 case 1: /* Vendor */ 3114 str_ptr = sc->sc_vendor; 3115 break; 3116 3117 case 2: /* Product */ 3118 str_ptr = "EHCI root HUB"; 3119 break; 3120 3121 default: 3122 str_ptr = ""; 3123 break; 3124 } 3125 3126 len = usb_make_str_desc( 3127 sc->sc_hub_desc.temp, 3128 sizeof(sc->sc_hub_desc.temp), 3129 str_ptr); 3130 break; 3131 default: 3132 err = USB_ERR_IOERROR; 3133 goto done; 3134 } 3135 break; 3136 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3137 len = 1; 3138 sc->sc_hub_desc.temp[0] = 0; 3139 break; 3140 case C(UR_GET_STATUS, UT_READ_DEVICE): 3141 len = 2; 3142 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3143 break; 3144 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3145 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3146 len = 2; 3147 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3148 break; 3149 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3150 if (value >= EHCI_MAX_DEVICES) { 3151 err = USB_ERR_IOERROR; 3152 goto done; 3153 } 3154 sc->sc_addr = value; 3155 break; 3156 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3157 if ((value != 0) && (value != 1)) { 3158 err = USB_ERR_IOERROR; 3159 goto done; 3160 } 3161 sc->sc_conf = value; 3162 break; 3163 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3164 break; 3165 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3166 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3167 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3168 err = USB_ERR_IOERROR; 3169 goto done; 3170 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3171 break; 3172 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3173 break; 3174 /* Hub requests */ 3175 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3176 break; 3177 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3178 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3179 3180 if ((index < 1) || 3181 (index > sc->sc_noport)) { 3182 err = USB_ERR_IOERROR; 3183 goto done; 3184 } 3185 port = EHCI_PORTSC(index); 3186 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3187 switch (value) { 3188 case UHF_PORT_ENABLE: 3189 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3190 break; 3191 case UHF_PORT_SUSPEND: 3192 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3193 3194 /* 3195 * waking up a High Speed device is rather 3196 * complicated if 3197 */ 3198 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3199 } 3200 /* wait 20ms for resume sequence to complete */ 3201 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 50); 3202 3203 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3204 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3205 3206 /* 4ms settle time */ 3207 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 250); 3208 break; 3209 case UHF_PORT_POWER: 3210 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3211 break; 3212 case UHF_PORT_TEST: 3213 DPRINTFN(3, "clear port test " 3214 "%d\n", index); 3215 break; 3216 case UHF_PORT_INDICATOR: 3217 DPRINTFN(3, "clear port ind " 3218 "%d\n", index); 3219 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3220 break; 3221 case UHF_C_PORT_CONNECTION: 3222 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3223 break; 3224 case UHF_C_PORT_ENABLE: 3225 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3226 break; 3227 case UHF_C_PORT_SUSPEND: 3228 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3229 break; 3230 case UHF_C_PORT_OVER_CURRENT: 3231 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3232 break; 3233 case UHF_C_PORT_RESET: 3234 sc->sc_isreset = 0; 3235 break; 3236 default: 3237 err = USB_ERR_IOERROR; 3238 goto done; 3239 } 3240 break; 3241 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3242 if ((value & 0xff) != 0) { 3243 err = USB_ERR_IOERROR; 3244 goto done; 3245 } 3246 v = EREAD4(sc, EHCI_HCSPARAMS); 3247 3248 sc->sc_hub_desc.hubd = ehci_hubd; 3249 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3250 3251 if (EHCI_HCS_PPC(v)) 3252 i = UHD_PWR_INDIVIDUAL; 3253 else 3254 i = UHD_PWR_NO_SWITCH; 3255 3256 if (EHCI_HCS_P_INDICATOR(v)) 3257 i |= UHD_PORT_IND; 3258 3259 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3260 /* XXX can't find out? */ 3261 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3262 /* XXX don't know if ports are removable or not */ 3263 sc->sc_hub_desc.hubd.bDescLength = 3264 8 + ((sc->sc_noport + 7) / 8); 3265 len = sc->sc_hub_desc.hubd.bDescLength; 3266 break; 3267 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3268 len = 16; 3269 memset(sc->sc_hub_desc.temp, 0, 16); 3270 break; 3271 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3272 DPRINTFN(9, "get port status i=%d\n", 3273 index); 3274 if ((index < 1) || 3275 (index > sc->sc_noport)) { 3276 err = USB_ERR_IOERROR; 3277 goto done; 3278 } 3279 v = EOREAD4(sc, EHCI_PORTSC(index)); 3280 DPRINTFN(9, "port status=0x%04x\n", v); 3281 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) { 3282 if ((v & 0xc000000) == 0x8000000) 3283 i = UPS_HIGH_SPEED; 3284 else if ((v & 0xc000000) == 0x4000000) 3285 i = UPS_LOW_SPEED; 3286 else 3287 i = 0; 3288 } else { 3289 i = UPS_HIGH_SPEED; 3290 } 3291 if (v & EHCI_PS_CS) 3292 i |= UPS_CURRENT_CONNECT_STATUS; 3293 if (v & EHCI_PS_PE) 3294 i |= UPS_PORT_ENABLED; 3295 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3296 i |= UPS_SUSPEND; 3297 if (v & EHCI_PS_OCA) 3298 i |= UPS_OVERCURRENT_INDICATOR; 3299 if (v & EHCI_PS_PR) 3300 i |= UPS_RESET; 3301 if (v & EHCI_PS_PP) 3302 i |= UPS_PORT_POWER; 3303 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3304 i = 0; 3305 if (v & EHCI_PS_CSC) 3306 i |= UPS_C_CONNECT_STATUS; 3307 if (v & EHCI_PS_PEC) 3308 i |= UPS_C_PORT_ENABLED; 3309 if (v & EHCI_PS_OCC) 3310 i |= UPS_C_OVERCURRENT_INDICATOR; 3311 if (v & EHCI_PS_FPR) 3312 i |= UPS_C_SUSPEND; 3313 if (sc->sc_isreset) 3314 i |= UPS_C_PORT_RESET; 3315 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3316 len = sizeof(sc->sc_hub_desc.ps); 3317 break; 3318 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3319 err = USB_ERR_IOERROR; 3320 goto done; 3321 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3322 break; 3323 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3324 if ((index < 1) || 3325 (index > sc->sc_noport)) { 3326 err = USB_ERR_IOERROR; 3327 goto done; 3328 } 3329 port = EHCI_PORTSC(index); 3330 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3331 switch (value) { 3332 case UHF_PORT_ENABLE: 3333 EOWRITE4(sc, port, v | EHCI_PS_PE); 3334 break; 3335 case UHF_PORT_SUSPEND: 3336 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3337 break; 3338 case UHF_PORT_RESET: 3339 DPRINTFN(6, "reset port %d\n", index); 3340 #ifdef USB_DEBUG 3341 if (ehcinohighspeed) { 3342 /* 3343 * Connect USB device to companion 3344 * controller. 3345 */ 3346 ehci_disown(sc, index, 1); 3347 break; 3348 } 3349 #endif 3350 if (EHCI_PS_IS_LOWSPEED(v) && 3351 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3352 /* Low speed device, give up ownership. */ 3353 ehci_disown(sc, index, 1); 3354 break; 3355 } 3356 /* Start reset sequence. */ 3357 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3358 EOWRITE4(sc, port, v | EHCI_PS_PR); 3359 3360 /* Wait for reset to complete. */ 3361 usb_pause_mtx(&sc->sc_bus.bus_lock, 3362 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 3363 3364 /* Terminate reset sequence. */ 3365 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3366 EOWRITE4(sc, port, v); 3367 3368 /* Wait for HC to complete reset. */ 3369 usb_pause_mtx(&sc->sc_bus.bus_lock, 3370 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3371 3372 v = EOREAD4(sc, port); 3373 DPRINTF("ehci after reset, status=0x%08x\n", v); 3374 if (v & EHCI_PS_PR) { 3375 device_printf(sc->sc_bus.bdev, 3376 "port reset timeout\n"); 3377 err = USB_ERR_TIMEOUT; 3378 goto done; 3379 } 3380 if (!(v & EHCI_PS_PE) && 3381 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3382 /* Not a high speed device, give up ownership.*/ 3383 ehci_disown(sc, index, 0); 3384 break; 3385 } 3386 sc->sc_isreset = 1; 3387 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3388 index, v); 3389 break; 3390 3391 case UHF_PORT_POWER: 3392 DPRINTFN(3, "set port power %d\n", index); 3393 EOWRITE4(sc, port, v | EHCI_PS_PP); 3394 break; 3395 3396 case UHF_PORT_TEST: 3397 DPRINTFN(3, "set port test %d\n", index); 3398 break; 3399 3400 case UHF_PORT_INDICATOR: 3401 DPRINTFN(3, "set port ind %d\n", index); 3402 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3403 break; 3404 3405 default: 3406 err = USB_ERR_IOERROR; 3407 goto done; 3408 } 3409 break; 3410 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3411 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3412 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3413 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3414 break; 3415 default: 3416 err = USB_ERR_IOERROR; 3417 goto done; 3418 } 3419 done: 3420 *plength = len; 3421 *pptr = ptr; 3422 return (err); 3423 } 3424 3425 static void 3426 ehci_xfer_setup(struct usb_setup_params *parm) 3427 { 3428 struct usb_page_search page_info; 3429 struct usb_page_cache *pc; 3430 ehci_softc_t *sc; 3431 struct usb_xfer *xfer; 3432 void *last_obj; 3433 uint32_t nqtd; 3434 uint32_t nqh; 3435 uint32_t nsitd; 3436 uint32_t nitd; 3437 uint32_t n; 3438 3439 sc = EHCI_BUS2SC(parm->udev->bus); 3440 xfer = parm->curr_xfer; 3441 3442 nqtd = 0; 3443 nqh = 0; 3444 nsitd = 0; 3445 nitd = 0; 3446 3447 /* 3448 * compute maximum number of some structures 3449 */ 3450 if (parm->methods == &ehci_device_ctrl_methods) { 3451 3452 /* 3453 * The proof for the "nqtd" formula is illustrated like 3454 * this: 3455 * 3456 * +------------------------------------+ 3457 * | | 3458 * | |remainder -> | 3459 * | +-----+---+ | 3460 * | | xxx | x | frm 0 | 3461 * | +-----+---++ | 3462 * | | xxx | xx | frm 1 | 3463 * | +-----+----+ | 3464 * | ... | 3465 * +------------------------------------+ 3466 * 3467 * "xxx" means a completely full USB transfer descriptor 3468 * 3469 * "x" and "xx" means a short USB packet 3470 * 3471 * For the remainder of an USB transfer modulo 3472 * "max_data_length" we need two USB transfer descriptors. 3473 * One to transfer the remaining data and one to finalise 3474 * with a zero length packet in case the "force_short_xfer" 3475 * flag is set. We only need two USB transfer descriptors in 3476 * the case where the transfer length of the first one is a 3477 * factor of "max_frame_size". The rest of the needed USB 3478 * transfer descriptors is given by the buffer size divided 3479 * by the maximum data payload. 3480 */ 3481 parm->hc_max_packet_size = 0x400; 3482 parm->hc_max_packet_count = 1; 3483 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3484 xfer->flags_int.bdma_enable = 1; 3485 3486 usbd_transfer_setup_sub(parm); 3487 3488 nqh = 1; 3489 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3490 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3491 3492 } else if (parm->methods == &ehci_device_bulk_methods) { 3493 3494 parm->hc_max_packet_size = 0x400; 3495 parm->hc_max_packet_count = 1; 3496 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3497 xfer->flags_int.bdma_enable = 1; 3498 3499 usbd_transfer_setup_sub(parm); 3500 3501 nqh = 1; 3502 nqtd = ((2 * xfer->nframes) 3503 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3504 3505 } else if (parm->methods == &ehci_device_intr_methods) { 3506 3507 if (parm->speed == USB_SPEED_HIGH) { 3508 parm->hc_max_packet_size = 0x400; 3509 parm->hc_max_packet_count = 3; 3510 } else if (parm->speed == USB_SPEED_FULL) { 3511 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3512 parm->hc_max_packet_count = 1; 3513 } else { 3514 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3515 parm->hc_max_packet_count = 1; 3516 } 3517 3518 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3519 xfer->flags_int.bdma_enable = 1; 3520 3521 usbd_transfer_setup_sub(parm); 3522 3523 nqh = 1; 3524 nqtd = ((2 * xfer->nframes) 3525 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3526 3527 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3528 3529 parm->hc_max_packet_size = 0x3FF; 3530 parm->hc_max_packet_count = 1; 3531 parm->hc_max_frame_size = 0x3FF; 3532 xfer->flags_int.bdma_enable = 1; 3533 3534 usbd_transfer_setup_sub(parm); 3535 3536 nsitd = xfer->nframes; 3537 3538 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3539 3540 parm->hc_max_packet_size = 0x400; 3541 parm->hc_max_packet_count = 3; 3542 parm->hc_max_frame_size = 0xC00; 3543 xfer->flags_int.bdma_enable = 1; 3544 3545 usbd_transfer_setup_sub(parm); 3546 3547 nitd = ((xfer->nframes + 7) / 8) << 3548 usbd_xfer_get_fps_shift(xfer); 3549 3550 } else { 3551 3552 parm->hc_max_packet_size = 0x400; 3553 parm->hc_max_packet_count = 1; 3554 parm->hc_max_frame_size = 0x400; 3555 3556 usbd_transfer_setup_sub(parm); 3557 } 3558 3559 alloc_dma_set: 3560 3561 if (parm->err) { 3562 return; 3563 } 3564 /* 3565 * Allocate queue heads and transfer descriptors 3566 */ 3567 last_obj = NULL; 3568 3569 if (usbd_transfer_setup_sub_malloc( 3570 parm, &pc, sizeof(ehci_itd_t), 3571 EHCI_ITD_ALIGN, nitd)) { 3572 parm->err = USB_ERR_NOMEM; 3573 return; 3574 } 3575 if (parm->buf) { 3576 for (n = 0; n != nitd; n++) { 3577 ehci_itd_t *td; 3578 3579 usbd_get_page(pc + n, 0, &page_info); 3580 3581 td = page_info.buffer; 3582 3583 /* init TD */ 3584 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3585 td->obj_next = last_obj; 3586 td->page_cache = pc + n; 3587 3588 last_obj = td; 3589 3590 usb_pc_cpu_flush(pc + n); 3591 } 3592 } 3593 if (usbd_transfer_setup_sub_malloc( 3594 parm, &pc, sizeof(ehci_sitd_t), 3595 EHCI_SITD_ALIGN, nsitd)) { 3596 parm->err = USB_ERR_NOMEM; 3597 return; 3598 } 3599 if (parm->buf) { 3600 for (n = 0; n != nsitd; n++) { 3601 ehci_sitd_t *td; 3602 3603 usbd_get_page(pc + n, 0, &page_info); 3604 3605 td = page_info.buffer; 3606 3607 /* init TD */ 3608 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3609 td->obj_next = last_obj; 3610 td->page_cache = pc + n; 3611 3612 last_obj = td; 3613 3614 usb_pc_cpu_flush(pc + n); 3615 } 3616 } 3617 if (usbd_transfer_setup_sub_malloc( 3618 parm, &pc, sizeof(ehci_qtd_t), 3619 EHCI_QTD_ALIGN, nqtd)) { 3620 parm->err = USB_ERR_NOMEM; 3621 return; 3622 } 3623 if (parm->buf) { 3624 for (n = 0; n != nqtd; n++) { 3625 ehci_qtd_t *qtd; 3626 3627 usbd_get_page(pc + n, 0, &page_info); 3628 3629 qtd = page_info.buffer; 3630 3631 /* init TD */ 3632 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3633 qtd->obj_next = last_obj; 3634 qtd->page_cache = pc + n; 3635 3636 last_obj = qtd; 3637 3638 usb_pc_cpu_flush(pc + n); 3639 } 3640 } 3641 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3642 3643 last_obj = NULL; 3644 3645 if (usbd_transfer_setup_sub_malloc( 3646 parm, &pc, sizeof(ehci_qh_t), 3647 EHCI_QH_ALIGN, nqh)) { 3648 parm->err = USB_ERR_NOMEM; 3649 return; 3650 } 3651 if (parm->buf) { 3652 for (n = 0; n != nqh; n++) { 3653 ehci_qh_t *qh; 3654 3655 usbd_get_page(pc + n, 0, &page_info); 3656 3657 qh = page_info.buffer; 3658 3659 /* init QH */ 3660 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3661 qh->obj_next = last_obj; 3662 qh->page_cache = pc + n; 3663 3664 last_obj = qh; 3665 3666 usb_pc_cpu_flush(pc + n); 3667 } 3668 } 3669 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3670 3671 if (!xfer->flags_int.curr_dma_set) { 3672 xfer->flags_int.curr_dma_set = 1; 3673 goto alloc_dma_set; 3674 } 3675 } 3676 3677 static void 3678 ehci_xfer_unsetup(struct usb_xfer *xfer) 3679 { 3680 return; 3681 } 3682 3683 static void 3684 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3685 struct usb_endpoint *ep) 3686 { 3687 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3688 3689 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3690 ep, udev->address, 3691 edesc->bEndpointAddress, udev->flags.usb_mode, 3692 sc->sc_addr); 3693 3694 if (udev->flags.usb_mode != USB_MODE_HOST) { 3695 /* not supported */ 3696 return; 3697 } 3698 if (udev->device_index != sc->sc_addr) { 3699 3700 if ((udev->speed != USB_SPEED_HIGH) && 3701 ((udev->hs_hub_addr == 0) || 3702 (udev->hs_port_no == 0) || 3703 (udev->parent_hs_hub == NULL) || 3704 (udev->parent_hs_hub->hub == NULL))) { 3705 /* We need a transaction translator */ 3706 goto done; 3707 } 3708 switch (edesc->bmAttributes & UE_XFERTYPE) { 3709 case UE_CONTROL: 3710 ep->methods = &ehci_device_ctrl_methods; 3711 break; 3712 case UE_INTERRUPT: 3713 ep->methods = &ehci_device_intr_methods; 3714 break; 3715 case UE_ISOCHRONOUS: 3716 if (udev->speed == USB_SPEED_HIGH) { 3717 ep->methods = &ehci_device_isoc_hs_methods; 3718 } else if (udev->speed == USB_SPEED_FULL) { 3719 ep->methods = &ehci_device_isoc_fs_methods; 3720 } 3721 break; 3722 case UE_BULK: 3723 ep->methods = &ehci_device_bulk_methods; 3724 break; 3725 default: 3726 /* do nothing */ 3727 break; 3728 } 3729 } 3730 done: 3731 return; 3732 } 3733 3734 static void 3735 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3736 { 3737 /* 3738 * Wait until the hardware has finished any possible use of 3739 * the transfer descriptor(s) and QH 3740 */ 3741 *pus = (188); /* microseconds */ 3742 } 3743 3744 static void 3745 ehci_device_resume(struct usb_device *udev) 3746 { 3747 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3748 struct usb_xfer *xfer; 3749 struct usb_pipe_methods *methods; 3750 3751 DPRINTF("\n"); 3752 3753 USB_BUS_LOCK(udev->bus); 3754 3755 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3756 3757 if (xfer->xroot->udev == udev) { 3758 3759 methods = xfer->endpoint->methods; 3760 3761 if ((methods == &ehci_device_bulk_methods) || 3762 (methods == &ehci_device_ctrl_methods)) { 3763 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3764 sc->sc_async_p_last); 3765 } 3766 if (methods == &ehci_device_intr_methods) { 3767 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3768 sc->sc_intr_p_last[xfer->qh_pos]); 3769 } 3770 } 3771 } 3772 3773 USB_BUS_UNLOCK(udev->bus); 3774 3775 return; 3776 } 3777 3778 static void 3779 ehci_device_suspend(struct usb_device *udev) 3780 { 3781 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3782 struct usb_xfer *xfer; 3783 struct usb_pipe_methods *methods; 3784 3785 DPRINTF("\n"); 3786 3787 USB_BUS_LOCK(udev->bus); 3788 3789 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3790 3791 if (xfer->xroot->udev == udev) { 3792 3793 methods = xfer->endpoint->methods; 3794 3795 if ((methods == &ehci_device_bulk_methods) || 3796 (methods == &ehci_device_ctrl_methods)) { 3797 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3798 sc->sc_async_p_last); 3799 } 3800 if (methods == &ehci_device_intr_methods) { 3801 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3802 sc->sc_intr_p_last[xfer->qh_pos]); 3803 } 3804 } 3805 } 3806 3807 USB_BUS_UNLOCK(udev->bus); 3808 } 3809 3810 static void 3811 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3812 { 3813 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3814 3815 switch (state) { 3816 case USB_HW_POWER_SUSPEND: 3817 case USB_HW_POWER_SHUTDOWN: 3818 ehci_suspend(sc); 3819 break; 3820 case USB_HW_POWER_RESUME: 3821 ehci_resume(sc); 3822 break; 3823 default: 3824 break; 3825 } 3826 } 3827 3828 static void 3829 ehci_set_hw_power(struct usb_bus *bus) 3830 { 3831 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3832 uint32_t temp; 3833 uint32_t flags; 3834 3835 DPRINTF("\n"); 3836 3837 USB_BUS_LOCK(bus); 3838 3839 flags = bus->hw_power_state; 3840 3841 temp = EOREAD4(sc, EHCI_USBCMD); 3842 3843 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3844 3845 if (flags & (USB_HW_POWER_CONTROL | 3846 USB_HW_POWER_BULK)) { 3847 DPRINTF("Async is active\n"); 3848 temp |= EHCI_CMD_ASE; 3849 } 3850 if (flags & (USB_HW_POWER_INTERRUPT | 3851 USB_HW_POWER_ISOC)) { 3852 DPRINTF("Periodic is active\n"); 3853 temp |= EHCI_CMD_PSE; 3854 } 3855 EOWRITE4(sc, EHCI_USBCMD, temp); 3856 3857 USB_BUS_UNLOCK(bus); 3858 3859 return; 3860 } 3861 3862 struct usb_bus_methods ehci_bus_methods = 3863 { 3864 .endpoint_init = ehci_ep_init, 3865 .xfer_setup = ehci_xfer_setup, 3866 .xfer_unsetup = ehci_xfer_unsetup, 3867 .get_dma_delay = ehci_get_dma_delay, 3868 .device_resume = ehci_device_resume, 3869 .device_suspend = ehci_device_suspend, 3870 .set_hw_power = ehci_set_hw_power, 3871 .set_hw_power_sleep = ehci_set_hw_power_sleep, 3872 .roothub_exec = ehci_roothub_exec, 3873 .xfer_poll = ehci_do_poll, 3874 }; 3875