1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * USB Open Host Controller driver. 30 * 31 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 32 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 33 */ 34 35 #include <sys/stdint.h> 36 #include <sys/param.h> 37 #include <sys/queue.h> 38 #include <sys/types.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/bus.h> 42 #include <sys/module.h> 43 #include <sys/lock.h> 44 #include <sys/mutex.h> 45 #include <sys/condvar.h> 46 #include <sys/sysctl.h> 47 #include <sys/unistd.h> 48 #include <sys/callout.h> 49 #include <sys/malloc.h> 50 #include <sys/priv.h> 51 52 #include <bus/u4b/usb.h> 53 #include <bus/u4b/usbdi.h> 54 55 #define USB_DEBUG_VAR ohcidebug 56 57 #include <bus/u4b/usb_core.h> 58 #include <bus/u4b/usb_debug.h> 59 #include <bus/u4b/usb_busdma.h> 60 #include <bus/u4b/usb_process.h> 61 #include <bus/u4b/usb_transfer.h> 62 #include <bus/u4b/usb_device.h> 63 #include <bus/u4b/usb_hub.h> 64 #include <bus/u4b/usb_util.h> 65 66 #include <bus/u4b/usb_controller.h> 67 #include <bus/u4b/usb_bus.h> 68 #include <bus/u4b/controller/ohci.h> 69 #include <bus/u4b/controller/ohcireg.h> 70 71 #define OHCI_BUS2SC(bus) \ 72 ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 73 ((uint8_t *)&(((ohci_softc_t *)0)->sc_bus)))) 74 75 #ifdef USB_DEBUG 76 static int ohcidebug = 0; 77 78 static SYSCTL_NODE(_hw_usb, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 79 SYSCTL_INT(_hw_usb_ohci, OID_AUTO, debug, CTLFLAG_RW, 80 &ohcidebug, 0, "ohci debug level"); 81 82 TUNABLE_INT("hw.usb.ohci.debug", &ohcidebug); 83 84 static void ohci_dumpregs(ohci_softc_t *); 85 static void ohci_dump_tds(ohci_td_t *); 86 static uint8_t ohci_dump_td(ohci_td_t *); 87 static void ohci_dump_ed(ohci_ed_t *); 88 static uint8_t ohci_dump_itd(ohci_itd_t *); 89 static void ohci_dump_itds(ohci_itd_t *); 90 91 #endif 92 93 #define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 94 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 95 #define OWRITE1(sc, r, x) \ 96 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 97 #define OWRITE2(sc, r, x) \ 98 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 99 #define OWRITE4(sc, r, x) \ 100 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 101 #define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 102 #define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 103 #define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 104 105 #define OHCI_INTR_ENDPT 1 106 107 extern struct usb_bus_methods ohci_bus_methods; 108 extern struct usb_pipe_methods ohci_device_bulk_methods; 109 extern struct usb_pipe_methods ohci_device_ctrl_methods; 110 extern struct usb_pipe_methods ohci_device_intr_methods; 111 extern struct usb_pipe_methods ohci_device_isoc_methods; 112 113 static void ohci_do_poll(struct usb_bus *bus); 114 static void ohci_device_done(struct usb_xfer *xfer, usb_error_t error); 115 static void ohci_timeout(void *arg); 116 static uint8_t ohci_check_transfer(struct usb_xfer *xfer); 117 static void ohci_root_intr(ohci_softc_t *sc); 118 119 struct ohci_std_temp { 120 struct usb_page_cache *pc; 121 ohci_td_t *td; 122 ohci_td_t *td_next; 123 uint32_t average; 124 uint32_t td_flags; 125 uint32_t len; 126 uint16_t max_frame_size; 127 uint8_t shortpkt; 128 uint8_t setup_alt_next; 129 uint8_t last_frame; 130 }; 131 132 static struct ohci_hcca * 133 ohci_get_hcca(ohci_softc_t *sc) 134 { 135 usb_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 136 return (sc->sc_hcca_p); 137 } 138 139 void 140 ohci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 141 { 142 struct ohci_softc *sc = OHCI_BUS2SC(bus); 143 uint32_t i; 144 145 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 146 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 147 148 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 149 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 150 151 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 152 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 153 154 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 155 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 156 157 for (i = 0; i != OHCI_NO_EDS; i++) { 158 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 159 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 160 } 161 } 162 163 static usb_error_t 164 ohci_controller_init(ohci_softc_t *sc, int do_suspend) 165 { 166 struct usb_page_search buf_res; 167 uint32_t i; 168 uint32_t ctl; 169 uint32_t ival; 170 uint32_t hcr; 171 uint32_t fm; 172 uint32_t per; 173 uint32_t desca; 174 175 /* Determine in what context we are running. */ 176 ctl = OREAD4(sc, OHCI_CONTROL); 177 if (ctl & OHCI_IR) { 178 /* SMM active, request change */ 179 DPRINTF("SMM active, request owner change\n"); 180 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 181 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 182 usb_pause_mtx(NULL, hz / 1000); 183 ctl = OREAD4(sc, OHCI_CONTROL); 184 } 185 if (ctl & OHCI_IR) { 186 device_printf(sc->sc_bus.bdev, 187 "SMM does not respond, resetting\n"); 188 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 189 goto reset; 190 } 191 } else { 192 DPRINTF("cold started\n"); 193 reset: 194 /* controller was cold started */ 195 usb_pause_mtx(NULL, 196 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 197 } 198 199 /* 200 * This reset should not be necessary according to the OHCI spec, but 201 * without it some controllers do not start. 202 */ 203 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 204 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 205 206 usb_pause_mtx(NULL, 207 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 208 209 /* we now own the host controller and the bus has been reset */ 210 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 211 212 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 213 /* nominal time for a reset is 10 us */ 214 for (i = 0; i < 10; i++) { 215 DELAY(10); 216 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 217 if (!hcr) { 218 break; 219 } 220 } 221 if (hcr) { 222 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 223 return (USB_ERR_IOERROR); 224 } 225 #ifdef USB_DEBUG 226 if (ohcidebug > 15) { 227 ohci_dumpregs(sc); 228 } 229 #endif 230 231 if (do_suspend) { 232 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_SUSPEND); 233 return (USB_ERR_NORMAL_COMPLETION); 234 } 235 236 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 237 238 /* set up HC registers */ 239 usbd_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 240 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 241 242 usbd_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 243 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 244 245 usbd_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 246 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 247 248 /* disable all interrupts and then switch on all desired interrupts */ 249 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 250 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 251 /* switch on desired functional features */ 252 ctl = OREAD4(sc, OHCI_CONTROL); 253 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 254 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 255 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 256 /* And finally start it! */ 257 OWRITE4(sc, OHCI_CONTROL, ctl); 258 259 /* 260 * The controller is now OPERATIONAL. Set a some final 261 * registers that should be set earlier, but that the 262 * controller ignores when in the SUSPEND state. 263 */ 264 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 265 fm |= OHCI_FSMPS(ival) | ival; 266 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 267 per = OHCI_PERIODIC(ival); /* 90% periodic */ 268 OWRITE4(sc, OHCI_PERIODIC_START, per); 269 270 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 271 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 272 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 273 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 274 usb_pause_mtx(NULL, 275 USB_MS_TO_TICKS(OHCI_ENABLE_POWER_DELAY)); 276 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 277 278 /* 279 * The AMD756 requires a delay before re-reading the register, 280 * otherwise it will occasionally report 0 ports. 281 */ 282 sc->sc_noport = 0; 283 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 284 usb_pause_mtx(NULL, 285 USB_MS_TO_TICKS(OHCI_READ_DESC_DELAY)); 286 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 287 } 288 289 #ifdef USB_DEBUG 290 if (ohcidebug > 5) { 291 ohci_dumpregs(sc); 292 } 293 #endif 294 return (USB_ERR_NORMAL_COMPLETION); 295 } 296 297 static struct ohci_ed * 298 ohci_init_ed(struct usb_page_cache *pc) 299 { 300 struct usb_page_search buf_res; 301 struct ohci_ed *ed; 302 303 usbd_get_page(pc, 0, &buf_res); 304 305 ed = buf_res.buffer; 306 307 ed->ed_self = htole32(buf_res.physaddr); 308 ed->ed_flags = htole32(OHCI_ED_SKIP); 309 ed->page_cache = pc; 310 311 return (ed); 312 } 313 314 usb_error_t 315 ohci_init(ohci_softc_t *sc) 316 { 317 struct usb_page_search buf_res; 318 uint16_t i; 319 uint16_t bit; 320 uint16_t x; 321 uint16_t y; 322 323 DPRINTF("start\n"); 324 325 sc->sc_eintrs = OHCI_NORMAL_INTRS; 326 327 /* 328 * Setup all ED's 329 */ 330 331 sc->sc_ctrl_p_last = 332 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 333 334 sc->sc_bulk_p_last = 335 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 336 337 sc->sc_isoc_p_last = 338 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 339 340 for (i = 0; i != OHCI_NO_EDS; i++) { 341 sc->sc_intr_p_last[i] = 342 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 343 } 344 345 /* 346 * the QHs are arranged to give poll intervals that are 347 * powers of 2 times 1ms 348 */ 349 bit = OHCI_NO_EDS / 2; 350 while (bit) { 351 x = bit; 352 while (x & bit) { 353 ohci_ed_t *ed_x; 354 ohci_ed_t *ed_y; 355 356 y = (x ^ bit) | (bit / 2); 357 358 /* 359 * the next QH has half the poll interval 360 */ 361 ed_x = sc->sc_intr_p_last[x]; 362 ed_y = sc->sc_intr_p_last[y]; 363 364 ed_x->next = NULL; 365 ed_x->ed_next = ed_y->ed_self; 366 367 x++; 368 } 369 bit >>= 1; 370 } 371 372 if (1) { 373 374 ohci_ed_t *ed_int; 375 ohci_ed_t *ed_isc; 376 377 ed_int = sc->sc_intr_p_last[0]; 378 ed_isc = sc->sc_isoc_p_last; 379 380 /* the last (1ms) QH */ 381 ed_int->next = ed_isc; 382 ed_int->ed_next = ed_isc->ed_self; 383 } 384 usbd_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 385 386 sc->sc_hcca_p = buf_res.buffer; 387 388 /* 389 * Fill HCCA interrupt table. The bit reversal is to get 390 * the tree set up properly to spread the interrupts. 391 */ 392 for (i = 0; i != OHCI_NO_INTRS; i++) { 393 sc->sc_hcca_p->hcca_interrupt_table[i] = 394 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 395 } 396 /* flush all cache into memory */ 397 398 usb_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 399 400 /* set up the bus struct */ 401 sc->sc_bus.methods = &ohci_bus_methods; 402 403 usb_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_lock, 0); 404 405 #ifdef USB_DEBUG 406 if (ohcidebug > 15) { 407 for (i = 0; i != OHCI_NO_EDS; i++) { 408 kprintf("ed#%d ", i); 409 ohci_dump_ed(sc->sc_intr_p_last[i]); 410 } 411 kprintf("iso "); 412 ohci_dump_ed(sc->sc_isoc_p_last); 413 } 414 #endif 415 416 sc->sc_bus.usbrev = USB_REV_1_0; 417 418 if (ohci_controller_init(sc, 0) != 0) 419 return (USB_ERR_INVAL); 420 421 /* catch any lost interrupts */ 422 ohci_do_poll(&sc->sc_bus); 423 return (USB_ERR_NORMAL_COMPLETION); 424 } 425 426 /* 427 * shut down the controller when the system is going down 428 */ 429 void 430 ohci_detach(struct ohci_softc *sc) 431 { 432 USB_BUS_LOCK(&sc->sc_bus); 433 434 usb_callout_stop(&sc->sc_tmo_rhsc); 435 436 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 437 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 438 439 USB_BUS_UNLOCK(&sc->sc_bus); 440 441 /* XXX let stray task complete */ 442 usb_pause_mtx(NULL, hz / 20); 443 444 usb_callout_drain(&sc->sc_tmo_rhsc); 445 } 446 447 static void 448 ohci_suspend(ohci_softc_t *sc) 449 { 450 DPRINTF("\n"); 451 452 #ifdef USB_DEBUG 453 if (ohcidebug > 2) 454 ohci_dumpregs(sc); 455 #endif 456 457 /* reset HC and leave it suspended */ 458 ohci_controller_init(sc, 1); 459 } 460 461 static void 462 ohci_resume(ohci_softc_t *sc) 463 { 464 DPRINTF("\n"); 465 466 #ifdef USB_DEBUG 467 if (ohcidebug > 2) 468 ohci_dumpregs(sc); 469 #endif 470 471 /* some broken BIOSes never initialize the Controller chip */ 472 ohci_controller_init(sc, 0); 473 474 /* catch any lost interrupts */ 475 ohci_do_poll(&sc->sc_bus); 476 } 477 478 #ifdef USB_DEBUG 479 static void 480 ohci_dumpregs(ohci_softc_t *sc) 481 { 482 struct ohci_hcca *hcca; 483 484 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 485 OREAD4(sc, OHCI_REVISION), 486 OREAD4(sc, OHCI_CONTROL), 487 OREAD4(sc, OHCI_COMMAND_STATUS)); 488 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 489 OREAD4(sc, OHCI_INTERRUPT_STATUS), 490 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 491 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 492 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 493 OREAD4(sc, OHCI_HCCA), 494 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 495 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 496 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 497 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 498 OREAD4(sc, OHCI_BULK_HEAD_ED), 499 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 500 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 501 OREAD4(sc, OHCI_DONE_HEAD), 502 OREAD4(sc, OHCI_FM_INTERVAL), 503 OREAD4(sc, OHCI_FM_REMAINING)); 504 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 505 OREAD4(sc, OHCI_FM_NUMBER), 506 OREAD4(sc, OHCI_PERIODIC_START), 507 OREAD4(sc, OHCI_LS_THRESHOLD)); 508 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 509 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 510 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 511 OREAD4(sc, OHCI_RH_STATUS)); 512 DPRINTF(" port1=0x%08x port2=0x%08x\n", 513 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 514 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 515 516 hcca = ohci_get_hcca(sc); 517 518 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 519 le32toh(hcca->hcca_frame_number), 520 le32toh(hcca->hcca_done_head)); 521 } 522 static void 523 ohci_dump_tds(ohci_td_t *std) 524 { 525 for (; std; std = std->obj_next) { 526 if (ohci_dump_td(std)) { 527 break; 528 } 529 } 530 } 531 532 static uint8_t 533 ohci_dump_td(ohci_td_t *std) 534 { 535 uint32_t td_flags; 536 uint8_t temp; 537 538 usb_pc_cpu_invalidate(std->page_cache); 539 540 td_flags = le32toh(std->td_flags); 541 temp = (std->td_next == 0); 542 543 kprintf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 544 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 545 std, le32toh(std->td_self), 546 (td_flags & OHCI_TD_R) ? "-R" : "", 547 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 548 (td_flags & OHCI_TD_IN) ? "-IN" : "", 549 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 550 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 551 OHCI_TD_GET_DI(td_flags), 552 OHCI_TD_GET_EC(td_flags), 553 OHCI_TD_GET_CC(td_flags), 554 le32toh(std->td_cbp), 555 le32toh(std->td_next), 556 le32toh(std->td_be)); 557 558 return (temp); 559 } 560 561 static uint8_t 562 ohci_dump_itd(ohci_itd_t *sitd) 563 { 564 uint32_t itd_flags; 565 uint16_t i; 566 uint8_t temp; 567 568 usb_pc_cpu_invalidate(sitd->page_cache); 569 570 itd_flags = le32toh(sitd->itd_flags); 571 temp = (sitd->itd_next == 0); 572 573 kprintf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 574 "bp0=0x%08x next=0x%08x be=0x%08x\n", 575 sitd, le32toh(sitd->itd_self), 576 OHCI_ITD_GET_SF(itd_flags), 577 OHCI_ITD_GET_DI(itd_flags), 578 OHCI_ITD_GET_FC(itd_flags), 579 OHCI_ITD_GET_CC(itd_flags), 580 le32toh(sitd->itd_bp0), 581 le32toh(sitd->itd_next), 582 le32toh(sitd->itd_be)); 583 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 584 kprintf("offs[%d]=0x%04x ", i, 585 (uint32_t)le16toh(sitd->itd_offset[i])); 586 } 587 kprintf("\n"); 588 589 return (temp); 590 } 591 592 static void 593 ohci_dump_itds(ohci_itd_t *sitd) 594 { 595 for (; sitd; sitd = sitd->obj_next) { 596 if (ohci_dump_itd(sitd)) { 597 break; 598 } 599 } 600 } 601 602 static void 603 ohci_dump_ed(ohci_ed_t *sed) 604 { 605 uint32_t ed_flags; 606 uint32_t ed_headp; 607 608 usb_pc_cpu_invalidate(sed->page_cache); 609 610 ed_flags = le32toh(sed->ed_flags); 611 ed_headp = le32toh(sed->ed_headp); 612 613 kprintf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 614 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 615 sed, le32toh(sed->ed_self), 616 OHCI_ED_GET_FA(ed_flags), 617 OHCI_ED_GET_EN(ed_flags), 618 OHCI_ED_GET_MAXP(ed_flags), 619 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 620 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 621 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 622 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 623 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 624 le32toh(sed->ed_tailp), 625 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 626 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 627 le32toh(sed->ed_headp), 628 le32toh(sed->ed_next)); 629 } 630 631 #endif 632 633 static void 634 ohci_transfer_intr_enqueue(struct usb_xfer *xfer) 635 { 636 /* check for early completion */ 637 if (ohci_check_transfer(xfer)) { 638 return; 639 } 640 /* put transfer on interrupt queue */ 641 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 642 643 /* start timeout, if any */ 644 if (xfer->timeout != 0) { 645 usbd_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 646 } 647 } 648 649 #define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 650 static ohci_ed_t * 651 _ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 652 { 653 DPRINTFN(11, "%p to %p\n", sed, last); 654 655 if (sed->prev != NULL) { 656 /* should not happen */ 657 DPRINTFN(0, "ED already linked!\n"); 658 return (last); 659 } 660 /* (sc->sc_bus.bus_lock) must be locked */ 661 662 sed->next = last->next; 663 sed->ed_next = last->ed_next; 664 sed->ed_tailp = 0; 665 666 sed->prev = last; 667 668 usb_pc_cpu_flush(sed->page_cache); 669 670 /* 671 * the last->next->prev is never followed: sed->next->prev = sed; 672 */ 673 674 last->next = sed; 675 last->ed_next = sed->ed_self; 676 677 usb_pc_cpu_flush(last->page_cache); 678 679 return (sed); 680 } 681 682 #define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 683 static ohci_ed_t * 684 _ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 685 { 686 DPRINTFN(11, "%p from %p\n", sed, last); 687 688 /* (sc->sc_bus.bus_lock) must be locked */ 689 690 /* only remove if not removed from a queue */ 691 if (sed->prev) { 692 693 sed->prev->next = sed->next; 694 sed->prev->ed_next = sed->ed_next; 695 696 usb_pc_cpu_flush(sed->prev->page_cache); 697 698 if (sed->next) { 699 sed->next->prev = sed->prev; 700 usb_pc_cpu_flush(sed->next->page_cache); 701 } 702 last = ((last == sed) ? sed->prev : last); 703 704 sed->prev = 0; 705 706 usb_pc_cpu_flush(sed->page_cache); 707 } 708 return (last); 709 } 710 711 static void 712 ohci_isoc_done(struct usb_xfer *xfer) 713 { 714 uint8_t nframes; 715 uint32_t *plen = xfer->frlengths; 716 volatile uint16_t *olen; 717 uint16_t len = 0; 718 ohci_itd_t *td = xfer->td_transfer_first; 719 720 while (1) { 721 if (td == NULL) { 722 panic("%s:%d: out of TD's\n", 723 __FUNCTION__, __LINE__); 724 } 725 #ifdef USB_DEBUG 726 if (ohcidebug > 5) { 727 DPRINTF("isoc TD\n"); 728 ohci_dump_itd(td); 729 } 730 #endif 731 usb_pc_cpu_invalidate(td->page_cache); 732 733 nframes = td->frames; 734 olen = &td->itd_offset[0]; 735 736 if (nframes > 8) { 737 nframes = 8; 738 } 739 while (nframes--) { 740 len = le16toh(*olen); 741 742 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 743 len = 0; 744 } else { 745 len &= ((1 << 12) - 1); 746 } 747 748 if (len > *plen) { 749 len = 0;/* invalid length */ 750 } 751 *plen = len; 752 plen++; 753 olen++; 754 } 755 756 if (((void *)td) == xfer->td_transfer_last) { 757 break; 758 } 759 td = td->obj_next; 760 } 761 762 xfer->aframes = xfer->nframes; 763 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 764 } 765 766 #ifdef USB_DEBUG 767 static const char *const 768 ohci_cc_strs[] = 769 { 770 "NO_ERROR", 771 "CRC", 772 "BIT_STUFFING", 773 "DATA_TOGGLE_MISMATCH", 774 775 "STALL", 776 "DEVICE_NOT_RESPONDING", 777 "PID_CHECK_FAILURE", 778 "UNEXPECTED_PID", 779 780 "DATA_OVERRUN", 781 "DATA_UNDERRUN", 782 "BUFFER_OVERRUN", 783 "BUFFER_UNDERRUN", 784 785 "reserved", 786 "reserved", 787 "NOT_ACCESSED", 788 "NOT_ACCESSED" 789 }; 790 791 #endif 792 793 static usb_error_t 794 ohci_non_isoc_done_sub(struct usb_xfer *xfer) 795 { 796 ohci_td_t *td; 797 ohci_td_t *td_alt_next; 798 uint32_t temp; 799 uint32_t phy_start; 800 uint32_t phy_end; 801 uint32_t td_flags; 802 uint16_t cc; 803 804 td = xfer->td_transfer_cache; 805 td_alt_next = td->alt_next; 806 td_flags = 0; 807 808 if (xfer->aframes != xfer->nframes) { 809 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 810 } 811 while (1) { 812 813 usb_pc_cpu_invalidate(td->page_cache); 814 phy_start = le32toh(td->td_cbp); 815 td_flags = le32toh(td->td_flags); 816 cc = OHCI_TD_GET_CC(td_flags); 817 818 if (phy_start) { 819 /* 820 * short transfer - compute the number of remaining 821 * bytes in the hardware buffer: 822 */ 823 phy_end = le32toh(td->td_be); 824 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 825 (OHCI_PAGE_SIZE + 1) : 0x0001); 826 temp += OHCI_PAGE_OFFSET(phy_end); 827 temp -= OHCI_PAGE_OFFSET(phy_start); 828 829 if (temp > td->len) { 830 /* guard against corruption */ 831 cc = OHCI_CC_STALL; 832 } else if (xfer->aframes != xfer->nframes) { 833 /* 834 * Sum up total transfer length 835 * in "frlengths[]": 836 */ 837 xfer->frlengths[xfer->aframes] += td->len - temp; 838 } 839 } else { 840 if (xfer->aframes != xfer->nframes) { 841 /* transfer was complete */ 842 xfer->frlengths[xfer->aframes] += td->len; 843 } 844 } 845 /* Check for last transfer */ 846 if (((void *)td) == xfer->td_transfer_last) { 847 td = NULL; 848 break; 849 } 850 /* Check transfer status */ 851 if (cc) { 852 /* the transfer is finished */ 853 td = NULL; 854 break; 855 } 856 /* Check for short transfer */ 857 if (phy_start) { 858 if (xfer->flags_int.short_frames_ok) { 859 /* follow alt next */ 860 td = td->alt_next; 861 } else { 862 /* the transfer is finished */ 863 td = NULL; 864 } 865 break; 866 } 867 td = td->obj_next; 868 869 if (td->alt_next != td_alt_next) { 870 /* this USB frame is complete */ 871 break; 872 } 873 } 874 875 /* update transfer cache */ 876 877 xfer->td_transfer_cache = td; 878 879 DPRINTFN(16, "error cc=%d (%s)\n", 880 cc, ohci_cc_strs[cc]); 881 882 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 883 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 884 } 885 886 static void 887 ohci_non_isoc_done(struct usb_xfer *xfer) 888 { 889 usb_error_t err = 0; 890 891 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 892 xfer, xfer->endpoint); 893 894 #ifdef USB_DEBUG 895 if (ohcidebug > 10) { 896 ohci_dump_tds(xfer->td_transfer_first); 897 } 898 #endif 899 900 /* reset scanner */ 901 902 xfer->td_transfer_cache = xfer->td_transfer_first; 903 904 if (xfer->flags_int.control_xfr) { 905 906 if (xfer->flags_int.control_hdr) { 907 908 err = ohci_non_isoc_done_sub(xfer); 909 } 910 xfer->aframes = 1; 911 912 if (xfer->td_transfer_cache == NULL) { 913 goto done; 914 } 915 } 916 while (xfer->aframes != xfer->nframes) { 917 918 err = ohci_non_isoc_done_sub(xfer); 919 xfer->aframes++; 920 921 if (xfer->td_transfer_cache == NULL) { 922 goto done; 923 } 924 } 925 926 if (xfer->flags_int.control_xfr && 927 !xfer->flags_int.control_act) { 928 929 err = ohci_non_isoc_done_sub(xfer); 930 } 931 done: 932 ohci_device_done(xfer, err); 933 } 934 935 /*------------------------------------------------------------------------* 936 * ohci_check_transfer_sub 937 *------------------------------------------------------------------------*/ 938 static void 939 ohci_check_transfer_sub(struct usb_xfer *xfer) 940 { 941 ohci_td_t *td; 942 ohci_ed_t *ed; 943 uint32_t phy_start; 944 uint32_t td_flags; 945 uint32_t td_next; 946 uint16_t cc; 947 948 td = xfer->td_transfer_cache; 949 950 while (1) { 951 952 usb_pc_cpu_invalidate(td->page_cache); 953 phy_start = le32toh(td->td_cbp); 954 td_flags = le32toh(td->td_flags); 955 td_next = le32toh(td->td_next); 956 957 /* Check for last transfer */ 958 if (((void *)td) == xfer->td_transfer_last) { 959 /* the transfer is finished */ 960 td = NULL; 961 break; 962 } 963 /* Check transfer status */ 964 cc = OHCI_TD_GET_CC(td_flags); 965 if (cc) { 966 /* the transfer is finished */ 967 td = NULL; 968 break; 969 } 970 /* 971 * Check if we reached the last packet 972 * or if there is a short packet: 973 */ 974 975 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 976 /* follow alt next */ 977 td = td->alt_next; 978 break; 979 } 980 td = td->obj_next; 981 } 982 983 /* update transfer cache */ 984 985 xfer->td_transfer_cache = td; 986 987 if (td) { 988 989 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 990 991 ed->ed_headp = td->td_self; 992 usb_pc_cpu_flush(ed->page_cache); 993 994 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 995 996 /* 997 * Make sure that the OHCI re-scans the schedule by 998 * writing the BLF and CLF bits: 999 */ 1000 1001 if (xfer->xroot->udev->flags.self_suspended) { 1002 /* nothing to do */ 1003 } else if (xfer->endpoint->methods == &ohci_device_bulk_methods) { 1004 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1005 1006 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1007 } else if (xfer->endpoint->methods == &ohci_device_ctrl_methods) { 1008 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1009 1010 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1011 } 1012 } 1013 } 1014 1015 /*------------------------------------------------------------------------* 1016 * ohci_check_transfer 1017 * 1018 * Return values: 1019 * 0: USB transfer is not finished 1020 * Else: USB transfer is finished 1021 *------------------------------------------------------------------------*/ 1022 static uint8_t 1023 ohci_check_transfer(struct usb_xfer *xfer) 1024 { 1025 ohci_ed_t *ed; 1026 uint32_t ed_headp; 1027 uint32_t ed_tailp; 1028 1029 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1030 1031 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1032 1033 usb_pc_cpu_invalidate(ed->page_cache); 1034 ed_headp = le32toh(ed->ed_headp); 1035 ed_tailp = le32toh(ed->ed_tailp); 1036 1037 if ((ed_headp & OHCI_HALTED) || 1038 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1039 if (xfer->endpoint->methods == &ohci_device_isoc_methods) { 1040 /* isochronous transfer */ 1041 ohci_isoc_done(xfer); 1042 } else { 1043 if (xfer->flags_int.short_frames_ok) { 1044 ohci_check_transfer_sub(xfer); 1045 if (xfer->td_transfer_cache) { 1046 /* not finished yet */ 1047 return (0); 1048 } 1049 } 1050 /* store data-toggle */ 1051 if (ed_headp & OHCI_TOGGLECARRY) { 1052 xfer->endpoint->toggle_next = 1; 1053 } else { 1054 xfer->endpoint->toggle_next = 0; 1055 } 1056 1057 /* non-isochronous transfer */ 1058 ohci_non_isoc_done(xfer); 1059 } 1060 return (1); 1061 } 1062 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1063 return (0); 1064 } 1065 1066 static void 1067 ohci_rhsc_enable(ohci_softc_t *sc) 1068 { 1069 DPRINTFN(5, "\n"); 1070 1071 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 1072 1073 sc->sc_eintrs |= OHCI_RHSC; 1074 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1075 1076 /* acknowledge any RHSC interrupt */ 1077 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1078 1079 ohci_root_intr(sc); 1080 } 1081 1082 static void 1083 ohci_interrupt_poll(ohci_softc_t *sc) 1084 { 1085 struct usb_xfer *xfer; 1086 1087 repeat: 1088 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1089 /* 1090 * check if transfer is transferred 1091 */ 1092 if (ohci_check_transfer(xfer)) { 1093 /* queue has been modified */ 1094 goto repeat; 1095 } 1096 } 1097 } 1098 1099 /*------------------------------------------------------------------------* 1100 * ohci_interrupt - OHCI interrupt handler 1101 * 1102 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1103 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1104 * is present ! 1105 *------------------------------------------------------------------------*/ 1106 void 1107 ohci_interrupt(ohci_softc_t *sc) 1108 { 1109 struct ohci_hcca *hcca; 1110 uint32_t status; 1111 uint32_t done; 1112 1113 USB_BUS_LOCK(&sc->sc_bus); 1114 1115 hcca = ohci_get_hcca(sc); 1116 1117 DPRINTFN(16, "real interrupt\n"); 1118 1119 #ifdef USB_DEBUG 1120 if (ohcidebug > 15) { 1121 ohci_dumpregs(sc); 1122 } 1123 #endif 1124 1125 done = le32toh(hcca->hcca_done_head); 1126 1127 /* 1128 * The LSb of done is used to inform the HC Driver that an interrupt 1129 * condition exists for both the Done list and for another event 1130 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1131 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1132 * the interrupt was caused by other than the HccaDoneHead update 1133 * and the HcInterruptStatus register needs to be accessed to 1134 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1135 * then a Done list update interrupt is indicated and if the LSb of 1136 * done is nonzero, then an additional interrupt event is indicated 1137 * and HcInterruptStatus should be checked to determine its cause. 1138 */ 1139 if (done != 0) { 1140 status = 0; 1141 1142 if (done & ~OHCI_DONE_INTRS) { 1143 status |= OHCI_WDH; 1144 } 1145 if (done & OHCI_DONE_INTRS) { 1146 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1147 } 1148 hcca->hcca_done_head = 0; 1149 1150 usb_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1151 } else { 1152 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1153 } 1154 1155 status &= ~OHCI_MIE; 1156 if (status == 0) { 1157 /* 1158 * nothing to be done (PCI shared 1159 * interrupt) 1160 */ 1161 goto done; 1162 } 1163 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1164 1165 status &= sc->sc_eintrs; 1166 if (status == 0) { 1167 goto done; 1168 } 1169 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1170 #if 0 1171 if (status & OHCI_SO) { 1172 /* XXX do what */ 1173 } 1174 #endif 1175 if (status & OHCI_RD) { 1176 kprintf("%s: resume detect\n", __FUNCTION__); 1177 /* XXX process resume detect */ 1178 } 1179 if (status & OHCI_UE) { 1180 kprintf("%s: unrecoverable error, " 1181 "controller halted\n", __FUNCTION__); 1182 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1183 /* XXX what else */ 1184 } 1185 if (status & OHCI_RHSC) { 1186 /* 1187 * Disable RHSC interrupt for now, because it will be 1188 * on until the port has been reset. 1189 */ 1190 sc->sc_eintrs &= ~OHCI_RHSC; 1191 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1192 1193 ohci_root_intr(sc); 1194 1195 /* do not allow RHSC interrupts > 1 per second */ 1196 usb_callout_reset(&sc->sc_tmo_rhsc, hz, 1197 (void *)&ohci_rhsc_enable, sc); 1198 } 1199 } 1200 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1201 if (status != 0) { 1202 /* Block unprocessed interrupts. XXX */ 1203 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1204 sc->sc_eintrs &= ~status; 1205 kprintf("%s: blocking intrs 0x%x\n", 1206 __FUNCTION__, status); 1207 } 1208 /* poll all the USB transfers */ 1209 ohci_interrupt_poll(sc); 1210 1211 done: 1212 USB_BUS_UNLOCK(&sc->sc_bus); 1213 } 1214 1215 /* 1216 * called when a request does not complete 1217 */ 1218 static void 1219 ohci_timeout(void *arg) 1220 { 1221 struct usb_xfer *xfer = arg; 1222 1223 DPRINTF("xfer=%p\n", xfer); 1224 1225 USB_BUS_LOCK_ASSERT(xfer->xroot->bus); 1226 1227 /* transfer is transferred */ 1228 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1229 } 1230 1231 static void 1232 ohci_do_poll(struct usb_bus *bus) 1233 { 1234 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1235 1236 USB_BUS_LOCK(&sc->sc_bus); 1237 ohci_interrupt_poll(sc); 1238 USB_BUS_UNLOCK(&sc->sc_bus); 1239 } 1240 1241 static void 1242 ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1243 { 1244 struct usb_page_search buf_res; 1245 ohci_td_t *td; 1246 ohci_td_t *td_next; 1247 ohci_td_t *td_alt_next; 1248 uint32_t buf_offset; 1249 uint32_t average; 1250 uint32_t len_old; 1251 uint8_t shortpkt_old; 1252 uint8_t precompute; 1253 1254 td_alt_next = NULL; 1255 buf_offset = 0; 1256 shortpkt_old = temp->shortpkt; 1257 len_old = temp->len; 1258 precompute = 1; 1259 1260 /* software is used to detect short incoming transfers */ 1261 1262 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1263 temp->td_flags |= htole32(OHCI_TD_R); 1264 } else { 1265 temp->td_flags &= ~htole32(OHCI_TD_R); 1266 } 1267 1268 restart: 1269 1270 td = temp->td; 1271 td_next = temp->td_next; 1272 1273 while (1) { 1274 1275 if (temp->len == 0) { 1276 1277 if (temp->shortpkt) { 1278 break; 1279 } 1280 /* send a Zero Length Packet, ZLP, last */ 1281 1282 temp->shortpkt = 1; 1283 average = 0; 1284 1285 } else { 1286 1287 average = temp->average; 1288 1289 if (temp->len < average) { 1290 if (temp->len % temp->max_frame_size) { 1291 temp->shortpkt = 1; 1292 } 1293 average = temp->len; 1294 } 1295 } 1296 1297 if (td_next == NULL) { 1298 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1299 } 1300 /* get next TD */ 1301 1302 td = td_next; 1303 td_next = td->obj_next; 1304 1305 /* check if we are pre-computing */ 1306 1307 if (precompute) { 1308 1309 /* update remaining length */ 1310 1311 temp->len -= average; 1312 1313 continue; 1314 } 1315 /* fill out current TD */ 1316 td->td_flags = temp->td_flags; 1317 1318 /* the next TD uses TOGGLE_CARRY */ 1319 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1320 1321 if (average == 0) { 1322 /* 1323 * The buffer start and end phys addresses should be 1324 * 0x0 for a zero length packet. 1325 */ 1326 td->td_cbp = 0; 1327 td->td_be = 0; 1328 td->len = 0; 1329 1330 } else { 1331 1332 usbd_get_page(temp->pc, buf_offset, &buf_res); 1333 td->td_cbp = htole32(buf_res.physaddr); 1334 buf_offset += (average - 1); 1335 1336 usbd_get_page(temp->pc, buf_offset, &buf_res); 1337 td->td_be = htole32(buf_res.physaddr); 1338 buf_offset++; 1339 1340 td->len = average; 1341 1342 /* update remaining length */ 1343 1344 temp->len -= average; 1345 } 1346 1347 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1348 /* we need to receive these frames one by one ! */ 1349 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1350 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1351 td->td_next = htole32(OHCI_TD_NEXT_END); 1352 } else { 1353 if (td_next) { 1354 /* link the current TD with the next one */ 1355 td->td_next = td_next->td_self; 1356 } 1357 } 1358 1359 td->alt_next = td_alt_next; 1360 1361 usb_pc_cpu_flush(td->page_cache); 1362 } 1363 1364 if (precompute) { 1365 precompute = 0; 1366 1367 /* setup alt next pointer, if any */ 1368 if (temp->last_frame) { 1369 /* no alternate next */ 1370 td_alt_next = NULL; 1371 } else { 1372 /* we use this field internally */ 1373 td_alt_next = td_next; 1374 } 1375 1376 /* restore */ 1377 temp->shortpkt = shortpkt_old; 1378 temp->len = len_old; 1379 goto restart; 1380 } 1381 temp->td = td; 1382 temp->td_next = td_next; 1383 } 1384 1385 static void 1386 ohci_setup_standard_chain(struct usb_xfer *xfer, ohci_ed_t **ed_last) 1387 { 1388 struct ohci_std_temp temp; 1389 struct usb_pipe_methods *methods; 1390 ohci_ed_t *ed; 1391 ohci_td_t *td; 1392 uint32_t ed_flags; 1393 uint32_t x; 1394 1395 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1396 xfer->address, UE_GET_ADDR(xfer->endpointno), 1397 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1398 1399 temp.average = xfer->max_hc_frame_size; 1400 temp.max_frame_size = xfer->max_frame_size; 1401 1402 /* toggle the DMA set we are using */ 1403 xfer->flags_int.curr_dma_set ^= 1; 1404 1405 /* get next DMA set */ 1406 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1407 1408 xfer->td_transfer_first = td; 1409 xfer->td_transfer_cache = td; 1410 1411 temp.td = NULL; 1412 temp.td_next = td; 1413 temp.last_frame = 0; 1414 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1415 1416 methods = xfer->endpoint->methods; 1417 1418 /* check if we should prepend a setup message */ 1419 1420 if (xfer->flags_int.control_xfr) { 1421 if (xfer->flags_int.control_hdr) { 1422 1423 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1424 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1425 1426 temp.len = xfer->frlengths[0]; 1427 temp.pc = xfer->frbuffers + 0; 1428 temp.shortpkt = temp.len ? 1 : 0; 1429 /* check for last frame */ 1430 if (xfer->nframes == 1) { 1431 /* no STATUS stage yet, SETUP is last */ 1432 if (xfer->flags_int.control_act) { 1433 temp.last_frame = 1; 1434 temp.setup_alt_next = 0; 1435 } 1436 } 1437 ohci_setup_standard_chain_sub(&temp); 1438 1439 /* 1440 * XXX assume that the setup message is 1441 * contained within one USB packet: 1442 */ 1443 xfer->endpoint->toggle_next = 1; 1444 } 1445 x = 1; 1446 } else { 1447 x = 0; 1448 } 1449 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1450 1451 /* set data toggle */ 1452 1453 if (xfer->endpoint->toggle_next) { 1454 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1455 } else { 1456 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1457 } 1458 1459 /* set endpoint direction */ 1460 1461 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1462 temp.td_flags |= htole32(OHCI_TD_IN); 1463 } else { 1464 temp.td_flags |= htole32(OHCI_TD_OUT); 1465 } 1466 1467 while (x != xfer->nframes) { 1468 1469 /* DATA0 / DATA1 message */ 1470 1471 temp.len = xfer->frlengths[x]; 1472 temp.pc = xfer->frbuffers + x; 1473 1474 x++; 1475 1476 if (x == xfer->nframes) { 1477 if (xfer->flags_int.control_xfr) { 1478 /* no STATUS stage yet, DATA is last */ 1479 if (xfer->flags_int.control_act) { 1480 temp.last_frame = 1; 1481 temp.setup_alt_next = 0; 1482 } 1483 } else { 1484 temp.last_frame = 1; 1485 temp.setup_alt_next = 0; 1486 } 1487 } 1488 if (temp.len == 0) { 1489 1490 /* make sure that we send an USB packet */ 1491 1492 temp.shortpkt = 0; 1493 1494 } else { 1495 1496 /* regular data transfer */ 1497 1498 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1499 } 1500 1501 ohci_setup_standard_chain_sub(&temp); 1502 } 1503 1504 /* check if we should append a status stage */ 1505 1506 if (xfer->flags_int.control_xfr && 1507 !xfer->flags_int.control_act) { 1508 1509 /* 1510 * Send a DATA1 message and invert the current endpoint 1511 * direction. 1512 */ 1513 1514 /* set endpoint direction and data toggle */ 1515 1516 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1517 temp.td_flags = htole32(OHCI_TD_OUT | 1518 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1519 } else { 1520 temp.td_flags = htole32(OHCI_TD_IN | 1521 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1522 } 1523 1524 temp.len = 0; 1525 temp.pc = NULL; 1526 temp.shortpkt = 0; 1527 temp.last_frame = 1; 1528 temp.setup_alt_next = 0; 1529 1530 ohci_setup_standard_chain_sub(&temp); 1531 } 1532 td = temp.td; 1533 1534 /* Ensure that last TD is terminating: */ 1535 td->td_next = htole32(OHCI_TD_NEXT_END); 1536 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1537 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1538 1539 usb_pc_cpu_flush(td->page_cache); 1540 1541 /* must have at least one frame! */ 1542 1543 xfer->td_transfer_last = td; 1544 1545 #ifdef USB_DEBUG 1546 if (ohcidebug > 8) { 1547 DPRINTF("nexttog=%d; data before transfer:\n", 1548 xfer->endpoint->toggle_next); 1549 ohci_dump_tds(xfer->td_transfer_first); 1550 } 1551 #endif 1552 1553 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1554 1555 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1556 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 1557 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1558 1559 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1560 1561 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1562 ed_flags |= OHCI_ED_SPEED; 1563 } 1564 ed->ed_flags = htole32(ed_flags); 1565 1566 td = xfer->td_transfer_first; 1567 1568 ed->ed_headp = td->td_self; 1569 1570 if (xfer->xroot->udev->flags.self_suspended == 0) { 1571 /* the append function will flush the endpoint descriptor */ 1572 OHCI_APPEND_QH(ed, *ed_last); 1573 1574 if (methods == &ohci_device_bulk_methods) { 1575 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1576 1577 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1578 } 1579 if (methods == &ohci_device_ctrl_methods) { 1580 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1581 1582 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1583 } 1584 } else { 1585 usb_pc_cpu_flush(ed->page_cache); 1586 } 1587 } 1588 1589 static void 1590 ohci_root_intr(ohci_softc_t *sc) 1591 { 1592 uint32_t hstatus; 1593 uint16_t i; 1594 uint16_t m; 1595 1596 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 1597 1598 /* clear any old interrupt data */ 1599 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 1600 1601 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1602 DPRINTF("sc=%p hstatus=0x%08x\n", 1603 sc, hstatus); 1604 1605 /* set bits */ 1606 m = (sc->sc_noport + 1); 1607 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1608 m = (8 * sizeof(sc->sc_hub_idata)); 1609 } 1610 for (i = 1; i < m; i++) { 1611 /* pick out CHANGE bits from the status register */ 1612 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1613 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1614 DPRINTF("port %d changed\n", i); 1615 } 1616 } 1617 1618 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1619 sizeof(sc->sc_hub_idata)); 1620 } 1621 1622 /* NOTE: "done" can be run two times in a row, 1623 * from close and from interrupt 1624 */ 1625 static void 1626 ohci_device_done(struct usb_xfer *xfer, usb_error_t error) 1627 { 1628 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1629 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1630 ohci_ed_t *ed; 1631 1632 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 1633 1634 1635 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1636 xfer, xfer->endpoint, error); 1637 1638 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1639 if (ed) { 1640 usb_pc_cpu_invalidate(ed->page_cache); 1641 } 1642 if (methods == &ohci_device_bulk_methods) { 1643 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1644 } 1645 if (methods == &ohci_device_ctrl_methods) { 1646 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1647 } 1648 if (methods == &ohci_device_intr_methods) { 1649 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1650 } 1651 if (methods == &ohci_device_isoc_methods) { 1652 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1653 } 1654 xfer->td_transfer_first = NULL; 1655 xfer->td_transfer_last = NULL; 1656 1657 /* dequeue transfer and start next transfer */ 1658 usbd_transfer_done(xfer, error); 1659 } 1660 1661 /*------------------------------------------------------------------------* 1662 * ohci bulk support 1663 *------------------------------------------------------------------------*/ 1664 static void 1665 ohci_device_bulk_open(struct usb_xfer *xfer) 1666 { 1667 return; 1668 } 1669 1670 static void 1671 ohci_device_bulk_close(struct usb_xfer *xfer) 1672 { 1673 ohci_device_done(xfer, USB_ERR_CANCELLED); 1674 } 1675 1676 static void 1677 ohci_device_bulk_enter(struct usb_xfer *xfer) 1678 { 1679 return; 1680 } 1681 1682 static void 1683 ohci_device_bulk_start(struct usb_xfer *xfer) 1684 { 1685 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1686 1687 /* setup TD's and QH */ 1688 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1689 1690 /* put transfer on interrupt queue */ 1691 ohci_transfer_intr_enqueue(xfer); 1692 } 1693 1694 struct usb_pipe_methods ohci_device_bulk_methods = 1695 { 1696 .open = ohci_device_bulk_open, 1697 .close = ohci_device_bulk_close, 1698 .enter = ohci_device_bulk_enter, 1699 .start = ohci_device_bulk_start, 1700 }; 1701 1702 /*------------------------------------------------------------------------* 1703 * ohci control support 1704 *------------------------------------------------------------------------*/ 1705 static void 1706 ohci_device_ctrl_open(struct usb_xfer *xfer) 1707 { 1708 return; 1709 } 1710 1711 static void 1712 ohci_device_ctrl_close(struct usb_xfer *xfer) 1713 { 1714 ohci_device_done(xfer, USB_ERR_CANCELLED); 1715 } 1716 1717 static void 1718 ohci_device_ctrl_enter(struct usb_xfer *xfer) 1719 { 1720 return; 1721 } 1722 1723 static void 1724 ohci_device_ctrl_start(struct usb_xfer *xfer) 1725 { 1726 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1727 1728 /* setup TD's and QH */ 1729 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1730 1731 /* put transfer on interrupt queue */ 1732 ohci_transfer_intr_enqueue(xfer); 1733 } 1734 1735 struct usb_pipe_methods ohci_device_ctrl_methods = 1736 { 1737 .open = ohci_device_ctrl_open, 1738 .close = ohci_device_ctrl_close, 1739 .enter = ohci_device_ctrl_enter, 1740 .start = ohci_device_ctrl_start, 1741 }; 1742 1743 /*------------------------------------------------------------------------* 1744 * ohci interrupt support 1745 *------------------------------------------------------------------------*/ 1746 static void 1747 ohci_device_intr_open(struct usb_xfer *xfer) 1748 { 1749 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1750 uint16_t best; 1751 uint16_t bit; 1752 uint16_t x; 1753 1754 best = 0; 1755 bit = OHCI_NO_EDS / 2; 1756 while (bit) { 1757 if (xfer->interval >= bit) { 1758 x = bit; 1759 best = bit; 1760 while (x & bit) { 1761 if (sc->sc_intr_stat[x] < 1762 sc->sc_intr_stat[best]) { 1763 best = x; 1764 } 1765 x++; 1766 } 1767 break; 1768 } 1769 bit >>= 1; 1770 } 1771 1772 sc->sc_intr_stat[best]++; 1773 xfer->qh_pos = best; 1774 1775 DPRINTFN(3, "best=%d interval=%d\n", 1776 best, xfer->interval); 1777 } 1778 1779 static void 1780 ohci_device_intr_close(struct usb_xfer *xfer) 1781 { 1782 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1783 1784 sc->sc_intr_stat[xfer->qh_pos]--; 1785 1786 ohci_device_done(xfer, USB_ERR_CANCELLED); 1787 } 1788 1789 static void 1790 ohci_device_intr_enter(struct usb_xfer *xfer) 1791 { 1792 return; 1793 } 1794 1795 static void 1796 ohci_device_intr_start(struct usb_xfer *xfer) 1797 { 1798 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1799 1800 /* setup TD's and QH */ 1801 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1802 1803 /* put transfer on interrupt queue */ 1804 ohci_transfer_intr_enqueue(xfer); 1805 } 1806 1807 struct usb_pipe_methods ohci_device_intr_methods = 1808 { 1809 .open = ohci_device_intr_open, 1810 .close = ohci_device_intr_close, 1811 .enter = ohci_device_intr_enter, 1812 .start = ohci_device_intr_start, 1813 }; 1814 1815 /*------------------------------------------------------------------------* 1816 * ohci isochronous support 1817 *------------------------------------------------------------------------*/ 1818 static void 1819 ohci_device_isoc_open(struct usb_xfer *xfer) 1820 { 1821 return; 1822 } 1823 1824 static void 1825 ohci_device_isoc_close(struct usb_xfer *xfer) 1826 { 1827 /**/ 1828 ohci_device_done(xfer, USB_ERR_CANCELLED); 1829 } 1830 1831 static void 1832 ohci_device_isoc_enter(struct usb_xfer *xfer) 1833 { 1834 struct usb_page_search buf_res; 1835 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1836 struct ohci_hcca *hcca; 1837 uint32_t buf_offset; 1838 uint32_t nframes; 1839 uint32_t ed_flags; 1840 uint32_t *plen; 1841 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1842 uint16_t length; 1843 uint8_t ncur; 1844 ohci_itd_t *td; 1845 ohci_itd_t *td_last = NULL; 1846 ohci_ed_t *ed; 1847 1848 hcca = ohci_get_hcca(sc); 1849 1850 nframes = le32toh(hcca->hcca_frame_number); 1851 1852 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1853 xfer, xfer->endpoint->isoc_next, xfer->nframes, nframes); 1854 1855 if ((xfer->endpoint->is_synced == 0) || 1856 (((nframes - xfer->endpoint->isoc_next) & 0xFFFF) < xfer->nframes) || 1857 (((xfer->endpoint->isoc_next - nframes) & 0xFFFF) >= 128)) { 1858 /* 1859 * If there is data underflow or the pipe queue is empty we 1860 * schedule the transfer a few frames ahead of the current 1861 * frame position. Else two isochronous transfers might 1862 * overlap. 1863 */ 1864 xfer->endpoint->isoc_next = (nframes + 3) & 0xFFFF; 1865 xfer->endpoint->is_synced = 1; 1866 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1867 } 1868 /* 1869 * compute how many milliseconds the insertion is ahead of the 1870 * current frame position: 1871 */ 1872 buf_offset = ((xfer->endpoint->isoc_next - nframes) & 0xFFFF); 1873 1874 /* 1875 * pre-compute when the isochronous transfer will be finished: 1876 */ 1877 xfer->isoc_time_complete = 1878 (usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1879 xfer->nframes); 1880 1881 /* get the real number of frames */ 1882 1883 nframes = xfer->nframes; 1884 1885 buf_offset = 0; 1886 1887 plen = xfer->frlengths; 1888 1889 /* toggle the DMA set we are using */ 1890 xfer->flags_int.curr_dma_set ^= 1; 1891 1892 /* get next DMA set */ 1893 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1894 1895 xfer->td_transfer_first = td; 1896 1897 ncur = 0; 1898 length = 0; 1899 1900 while (nframes--) { 1901 if (td == NULL) { 1902 panic("%s:%d: out of TD's\n", 1903 __FUNCTION__, __LINE__); 1904 } 1905 itd_offset[ncur] = length; 1906 buf_offset += *plen; 1907 length += *plen; 1908 plen++; 1909 ncur++; 1910 1911 if ( /* check if the ITD is full */ 1912 (ncur == OHCI_ITD_NOFFSET) || 1913 /* check if we have put more than 4K into the ITD */ 1914 (length & 0xF000) || 1915 /* check if it is the last frame */ 1916 (nframes == 0)) { 1917 1918 /* fill current ITD */ 1919 td->itd_flags = htole32( 1920 OHCI_ITD_NOCC | 1921 OHCI_ITD_SET_SF(xfer->endpoint->isoc_next) | 1922 OHCI_ITD_NOINTR | 1923 OHCI_ITD_SET_FC(ncur)); 1924 1925 td->frames = ncur; 1926 xfer->endpoint->isoc_next += ncur; 1927 1928 if (length == 0) { 1929 /* all zero */ 1930 td->itd_bp0 = 0; 1931 td->itd_be = ~0; 1932 1933 while (ncur--) { 1934 td->itd_offset[ncur] = 1935 htole16(OHCI_ITD_MK_OFFS(0)); 1936 } 1937 } else { 1938 usbd_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1939 length = OHCI_PAGE_MASK(buf_res.physaddr); 1940 buf_res.physaddr = 1941 OHCI_PAGE(buf_res.physaddr); 1942 td->itd_bp0 = htole32(buf_res.physaddr); 1943 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1944 td->itd_be = htole32(buf_res.physaddr); 1945 1946 while (ncur--) { 1947 itd_offset[ncur] += length; 1948 itd_offset[ncur] = 1949 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1950 td->itd_offset[ncur] = 1951 htole16(itd_offset[ncur]); 1952 } 1953 } 1954 ncur = 0; 1955 length = 0; 1956 td_last = td; 1957 td = td->obj_next; 1958 1959 if (td) { 1960 /* link the last TD with the next one */ 1961 td_last->itd_next = td->itd_self; 1962 } 1963 usb_pc_cpu_flush(td_last->page_cache); 1964 } 1965 } 1966 1967 /* update the last TD */ 1968 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 1969 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 1970 td_last->itd_next = 0; 1971 1972 usb_pc_cpu_flush(td_last->page_cache); 1973 1974 xfer->td_transfer_last = td_last; 1975 1976 #ifdef USB_DEBUG 1977 if (ohcidebug > 8) { 1978 DPRINTF("data before transfer:\n"); 1979 ohci_dump_itds(xfer->td_transfer_first); 1980 } 1981 #endif 1982 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1983 1984 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 1985 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 1986 else 1987 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 1988 1989 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 1990 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 1991 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1992 1993 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1994 ed_flags |= OHCI_ED_SPEED; 1995 } 1996 ed->ed_flags = htole32(ed_flags); 1997 1998 td = xfer->td_transfer_first; 1999 2000 ed->ed_headp = td->itd_self; 2001 2002 /* isochronous transfers are not affected by suspend / resume */ 2003 /* the append function will flush the endpoint descriptor */ 2004 2005 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2006 } 2007 2008 static void 2009 ohci_device_isoc_start(struct usb_xfer *xfer) 2010 { 2011 /* put transfer on interrupt queue */ 2012 ohci_transfer_intr_enqueue(xfer); 2013 } 2014 2015 struct usb_pipe_methods ohci_device_isoc_methods = 2016 { 2017 .open = ohci_device_isoc_open, 2018 .close = ohci_device_isoc_close, 2019 .enter = ohci_device_isoc_enter, 2020 .start = ohci_device_isoc_start, 2021 }; 2022 2023 /*------------------------------------------------------------------------* 2024 * ohci root control support 2025 *------------------------------------------------------------------------* 2026 * Simulate a hardware hub by handling all the necessary requests. 2027 *------------------------------------------------------------------------*/ 2028 2029 static const 2030 struct usb_device_descriptor ohci_devd = 2031 { 2032 sizeof(struct usb_device_descriptor), 2033 UDESC_DEVICE, /* type */ 2034 {0x00, 0x01}, /* USB version */ 2035 UDCLASS_HUB, /* class */ 2036 UDSUBCLASS_HUB, /* subclass */ 2037 UDPROTO_FSHUB, /* protocol */ 2038 64, /* max packet */ 2039 {0}, {0}, {0x00, 0x01}, /* device id */ 2040 1, 2, 0, /* string indicies */ 2041 1 /* # of configurations */ 2042 }; 2043 2044 static const 2045 struct ohci_config_desc ohci_confd = 2046 { 2047 .confd = { 2048 .bLength = sizeof(struct usb_config_descriptor), 2049 .bDescriptorType = UDESC_CONFIG, 2050 .wTotalLength[0] = sizeof(ohci_confd), 2051 .bNumInterface = 1, 2052 .bConfigurationValue = 1, 2053 .iConfiguration = 0, 2054 .bmAttributes = UC_SELF_POWERED, 2055 .bMaxPower = 0, /* max power */ 2056 }, 2057 .ifcd = { 2058 .bLength = sizeof(struct usb_interface_descriptor), 2059 .bDescriptorType = UDESC_INTERFACE, 2060 .bNumEndpoints = 1, 2061 .bInterfaceClass = UICLASS_HUB, 2062 .bInterfaceSubClass = UISUBCLASS_HUB, 2063 .bInterfaceProtocol = 0, 2064 }, 2065 .endpd = { 2066 .bLength = sizeof(struct usb_endpoint_descriptor), 2067 .bDescriptorType = UDESC_ENDPOINT, 2068 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2069 .bmAttributes = UE_INTERRUPT, 2070 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2071 .bInterval = 255, 2072 }, 2073 }; 2074 2075 static const 2076 struct usb_hub_descriptor ohci_hubd = 2077 { 2078 0, /* dynamic length */ 2079 UDESC_HUB, 2080 0, 2081 {0, 0}, 2082 0, 2083 0, 2084 {0}, 2085 }; 2086 2087 static usb_error_t 2088 ohci_roothub_exec(struct usb_device *udev, 2089 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2090 { 2091 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2092 const void *ptr; 2093 const char *str_ptr; 2094 uint32_t port; 2095 uint32_t v; 2096 uint16_t len; 2097 uint16_t value; 2098 uint16_t index; 2099 uint8_t l; 2100 usb_error_t err; 2101 2102 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2103 2104 /* buffer reset */ 2105 ptr = (const void *)&sc->sc_hub_desc.temp; 2106 len = 0; 2107 err = 0; 2108 2109 value = UGETW(req->wValue); 2110 index = UGETW(req->wIndex); 2111 2112 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2113 "wValue=0x%04x wIndex=0x%04x\n", 2114 req->bmRequestType, req->bRequest, 2115 UGETW(req->wLength), value, index); 2116 2117 #define C(x,y) ((x) | ((y) << 8)) 2118 switch (C(req->bRequest, req->bmRequestType)) { 2119 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2120 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2121 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2122 /* 2123 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2124 * for the integrated root hub. 2125 */ 2126 break; 2127 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2128 len = 1; 2129 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2130 break; 2131 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2132 switch (value >> 8) { 2133 case UDESC_DEVICE: 2134 if ((value & 0xff) != 0) { 2135 err = USB_ERR_IOERROR; 2136 goto done; 2137 } 2138 len = sizeof(ohci_devd); 2139 ptr = (const void *)&ohci_devd; 2140 break; 2141 2142 case UDESC_CONFIG: 2143 if ((value & 0xff) != 0) { 2144 err = USB_ERR_IOERROR; 2145 goto done; 2146 } 2147 len = sizeof(ohci_confd); 2148 ptr = (const void *)&ohci_confd; 2149 break; 2150 2151 case UDESC_STRING: 2152 switch (value & 0xff) { 2153 case 0: /* Language table */ 2154 str_ptr = "\001"; 2155 break; 2156 2157 case 1: /* Vendor */ 2158 str_ptr = sc->sc_vendor; 2159 break; 2160 2161 case 2: /* Product */ 2162 str_ptr = "OHCI root HUB"; 2163 break; 2164 2165 default: 2166 str_ptr = ""; 2167 break; 2168 } 2169 2170 len = usb_make_str_desc( 2171 sc->sc_hub_desc.temp, 2172 sizeof(sc->sc_hub_desc.temp), 2173 str_ptr); 2174 break; 2175 2176 default: 2177 err = USB_ERR_IOERROR; 2178 goto done; 2179 } 2180 break; 2181 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2182 len = 1; 2183 sc->sc_hub_desc.temp[0] = 0; 2184 break; 2185 case C(UR_GET_STATUS, UT_READ_DEVICE): 2186 len = 2; 2187 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2188 break; 2189 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2190 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2191 len = 2; 2192 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2193 break; 2194 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2195 if (value >= OHCI_MAX_DEVICES) { 2196 err = USB_ERR_IOERROR; 2197 goto done; 2198 } 2199 sc->sc_addr = value; 2200 break; 2201 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2202 if ((value != 0) && (value != 1)) { 2203 err = USB_ERR_IOERROR; 2204 goto done; 2205 } 2206 sc->sc_conf = value; 2207 break; 2208 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2209 break; 2210 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2211 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2212 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2213 err = USB_ERR_IOERROR; 2214 goto done; 2215 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2216 break; 2217 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2218 break; 2219 /* Hub requests */ 2220 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2221 break; 2222 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2223 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2224 "port=%d feature=%d\n", 2225 index, value); 2226 if ((index < 1) || 2227 (index > sc->sc_noport)) { 2228 err = USB_ERR_IOERROR; 2229 goto done; 2230 } 2231 port = OHCI_RH_PORT_STATUS(index); 2232 switch (value) { 2233 case UHF_PORT_ENABLE: 2234 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2235 break; 2236 case UHF_PORT_SUSPEND: 2237 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2238 break; 2239 case UHF_PORT_POWER: 2240 /* Yes, writing to the LOW_SPEED bit clears power. */ 2241 OWRITE4(sc, port, UPS_LOW_SPEED); 2242 break; 2243 case UHF_C_PORT_CONNECTION: 2244 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2245 break; 2246 case UHF_C_PORT_ENABLE: 2247 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2248 break; 2249 case UHF_C_PORT_SUSPEND: 2250 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2251 break; 2252 case UHF_C_PORT_OVER_CURRENT: 2253 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2254 break; 2255 case UHF_C_PORT_RESET: 2256 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2257 break; 2258 default: 2259 err = USB_ERR_IOERROR; 2260 goto done; 2261 } 2262 switch (value) { 2263 case UHF_C_PORT_CONNECTION: 2264 case UHF_C_PORT_ENABLE: 2265 case UHF_C_PORT_SUSPEND: 2266 case UHF_C_PORT_OVER_CURRENT: 2267 case UHF_C_PORT_RESET: 2268 /* enable RHSC interrupt if condition is cleared. */ 2269 if ((OREAD4(sc, port) >> 16) == 0) 2270 ohci_rhsc_enable(sc); 2271 break; 2272 default: 2273 break; 2274 } 2275 break; 2276 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2277 if ((value & 0xff) != 0) { 2278 err = USB_ERR_IOERROR; 2279 goto done; 2280 } 2281 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2282 2283 sc->sc_hub_desc.hubd = ohci_hubd; 2284 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2285 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2286 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2287 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2288 /* XXX overcurrent */ 2289 ); 2290 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2291 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2292 2293 for (l = 0; l < sc->sc_noport; l++) { 2294 if (v & 1) { 2295 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2296 } 2297 v >>= 1; 2298 } 2299 sc->sc_hub_desc.hubd.bDescLength = 2300 8 + ((sc->sc_noport + 7) / 8); 2301 len = sc->sc_hub_desc.hubd.bDescLength; 2302 break; 2303 2304 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2305 len = 16; 2306 memset(sc->sc_hub_desc.temp, 0, 16); 2307 break; 2308 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2309 DPRINTFN(9, "get port status i=%d\n", 2310 index); 2311 if ((index < 1) || 2312 (index > sc->sc_noport)) { 2313 err = USB_ERR_IOERROR; 2314 goto done; 2315 } 2316 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2317 DPRINTFN(9, "port status=0x%04x\n", v); 2318 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2319 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2320 len = sizeof(sc->sc_hub_desc.ps); 2321 break; 2322 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2323 err = USB_ERR_IOERROR; 2324 goto done; 2325 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2326 break; 2327 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2328 if ((index < 1) || 2329 (index > sc->sc_noport)) { 2330 err = USB_ERR_IOERROR; 2331 goto done; 2332 } 2333 port = OHCI_RH_PORT_STATUS(index); 2334 switch (value) { 2335 case UHF_PORT_ENABLE: 2336 OWRITE4(sc, port, UPS_PORT_ENABLED); 2337 break; 2338 case UHF_PORT_SUSPEND: 2339 OWRITE4(sc, port, UPS_SUSPEND); 2340 break; 2341 case UHF_PORT_RESET: 2342 DPRINTFN(6, "reset port %d\n", index); 2343 OWRITE4(sc, port, UPS_RESET); 2344 for (v = 0;; v++) { 2345 if (v < 12) { 2346 usb_pause_mtx(&sc->sc_bus.bus_lock, 2347 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2348 2349 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2350 break; 2351 } 2352 } else { 2353 err = USB_ERR_TIMEOUT; 2354 goto done; 2355 } 2356 } 2357 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2358 index, OREAD4(sc, port)); 2359 break; 2360 case UHF_PORT_POWER: 2361 DPRINTFN(3, "set port power %d\n", index); 2362 OWRITE4(sc, port, UPS_PORT_POWER); 2363 break; 2364 default: 2365 err = USB_ERR_IOERROR; 2366 goto done; 2367 } 2368 break; 2369 default: 2370 err = USB_ERR_IOERROR; 2371 goto done; 2372 } 2373 done: 2374 *plength = len; 2375 *pptr = ptr; 2376 return (err); 2377 } 2378 2379 static void 2380 ohci_xfer_setup(struct usb_setup_params *parm) 2381 { 2382 struct usb_page_search page_info; 2383 struct usb_page_cache *pc; 2384 ohci_softc_t *sc; 2385 struct usb_xfer *xfer; 2386 void *last_obj; 2387 uint32_t ntd; 2388 uint32_t nitd; 2389 uint32_t nqh; 2390 uint32_t n; 2391 2392 sc = OHCI_BUS2SC(parm->udev->bus); 2393 xfer = parm->curr_xfer; 2394 2395 parm->hc_max_packet_size = 0x500; 2396 parm->hc_max_packet_count = 1; 2397 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2398 2399 /* 2400 * calculate ntd and nqh 2401 */ 2402 if (parm->methods == &ohci_device_ctrl_methods) { 2403 xfer->flags_int.bdma_enable = 1; 2404 2405 usbd_transfer_setup_sub(parm); 2406 2407 nitd = 0; 2408 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2409 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2410 nqh = 1; 2411 2412 } else if (parm->methods == &ohci_device_bulk_methods) { 2413 xfer->flags_int.bdma_enable = 1; 2414 2415 usbd_transfer_setup_sub(parm); 2416 2417 nitd = 0; 2418 ntd = ((2 * xfer->nframes) 2419 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2420 nqh = 1; 2421 2422 } else if (parm->methods == &ohci_device_intr_methods) { 2423 xfer->flags_int.bdma_enable = 1; 2424 2425 usbd_transfer_setup_sub(parm); 2426 2427 nitd = 0; 2428 ntd = ((2 * xfer->nframes) 2429 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2430 nqh = 1; 2431 2432 } else if (parm->methods == &ohci_device_isoc_methods) { 2433 xfer->flags_int.bdma_enable = 1; 2434 2435 usbd_transfer_setup_sub(parm); 2436 2437 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2438 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2439 1 /* EXTRA */ ); 2440 ntd = 0; 2441 nqh = 1; 2442 2443 } else { 2444 2445 usbd_transfer_setup_sub(parm); 2446 2447 nitd = 0; 2448 ntd = 0; 2449 nqh = 0; 2450 } 2451 2452 alloc_dma_set: 2453 2454 if (parm->err) { 2455 return; 2456 } 2457 last_obj = NULL; 2458 2459 if (usbd_transfer_setup_sub_malloc( 2460 parm, &pc, sizeof(ohci_td_t), 2461 OHCI_TD_ALIGN, ntd)) { 2462 parm->err = USB_ERR_NOMEM; 2463 return; 2464 } 2465 if (parm->buf) { 2466 for (n = 0; n != ntd; n++) { 2467 ohci_td_t *td; 2468 2469 usbd_get_page(pc + n, 0, &page_info); 2470 2471 td = page_info.buffer; 2472 2473 /* init TD */ 2474 td->td_self = htole32(page_info.physaddr); 2475 td->obj_next = last_obj; 2476 td->page_cache = pc + n; 2477 2478 last_obj = td; 2479 2480 usb_pc_cpu_flush(pc + n); 2481 } 2482 } 2483 if (usbd_transfer_setup_sub_malloc( 2484 parm, &pc, sizeof(ohci_itd_t), 2485 OHCI_ITD_ALIGN, nitd)) { 2486 parm->err = USB_ERR_NOMEM; 2487 return; 2488 } 2489 if (parm->buf) { 2490 for (n = 0; n != nitd; n++) { 2491 ohci_itd_t *itd; 2492 2493 usbd_get_page(pc + n, 0, &page_info); 2494 2495 itd = page_info.buffer; 2496 2497 /* init TD */ 2498 itd->itd_self = htole32(page_info.physaddr); 2499 itd->obj_next = last_obj; 2500 itd->page_cache = pc + n; 2501 2502 last_obj = itd; 2503 2504 usb_pc_cpu_flush(pc + n); 2505 } 2506 } 2507 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2508 2509 last_obj = NULL; 2510 2511 if (usbd_transfer_setup_sub_malloc( 2512 parm, &pc, sizeof(ohci_ed_t), 2513 OHCI_ED_ALIGN, nqh)) { 2514 parm->err = USB_ERR_NOMEM; 2515 return; 2516 } 2517 if (parm->buf) { 2518 for (n = 0; n != nqh; n++) { 2519 ohci_ed_t *ed; 2520 2521 usbd_get_page(pc + n, 0, &page_info); 2522 2523 ed = page_info.buffer; 2524 2525 /* init QH */ 2526 ed->ed_self = htole32(page_info.physaddr); 2527 ed->obj_next = last_obj; 2528 ed->page_cache = pc + n; 2529 2530 last_obj = ed; 2531 2532 usb_pc_cpu_flush(pc + n); 2533 } 2534 } 2535 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2536 2537 if (!xfer->flags_int.curr_dma_set) { 2538 xfer->flags_int.curr_dma_set = 1; 2539 goto alloc_dma_set; 2540 } 2541 } 2542 2543 static void 2544 ohci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2545 struct usb_endpoint *ep) 2546 { 2547 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2548 2549 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2550 ep, udev->address, 2551 edesc->bEndpointAddress, udev->flags.usb_mode, 2552 sc->sc_addr); 2553 2554 if (udev->flags.usb_mode != USB_MODE_HOST) { 2555 /* not supported */ 2556 return; 2557 } 2558 if (udev->device_index != sc->sc_addr) { 2559 switch (edesc->bmAttributes & UE_XFERTYPE) { 2560 case UE_CONTROL: 2561 ep->methods = &ohci_device_ctrl_methods; 2562 break; 2563 case UE_INTERRUPT: 2564 ep->methods = &ohci_device_intr_methods; 2565 break; 2566 case UE_ISOCHRONOUS: 2567 if (udev->speed == USB_SPEED_FULL) { 2568 ep->methods = &ohci_device_isoc_methods; 2569 } 2570 break; 2571 case UE_BULK: 2572 ep->methods = &ohci_device_bulk_methods; 2573 break; 2574 default: 2575 /* do nothing */ 2576 break; 2577 } 2578 } 2579 } 2580 2581 static void 2582 ohci_xfer_unsetup(struct usb_xfer *xfer) 2583 { 2584 return; 2585 } 2586 2587 static void 2588 ohci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 2589 { 2590 /* 2591 * Wait until hardware has finished any possible use of the 2592 * transfer descriptor(s) and QH 2593 */ 2594 *pus = (1125); /* microseconds */ 2595 } 2596 2597 static void 2598 ohci_device_resume(struct usb_device *udev) 2599 { 2600 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2601 struct usb_xfer *xfer; 2602 struct usb_pipe_methods *methods; 2603 ohci_ed_t *ed; 2604 2605 DPRINTF("\n"); 2606 2607 USB_BUS_LOCK(udev->bus); 2608 2609 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2610 2611 if (xfer->xroot->udev == udev) { 2612 2613 methods = xfer->endpoint->methods; 2614 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2615 2616 if (methods == &ohci_device_bulk_methods) { 2617 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2618 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2619 } 2620 if (methods == &ohci_device_ctrl_methods) { 2621 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2622 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2623 } 2624 if (methods == &ohci_device_intr_methods) { 2625 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2626 } 2627 } 2628 } 2629 2630 USB_BUS_UNLOCK(udev->bus); 2631 2632 return; 2633 } 2634 2635 static void 2636 ohci_device_suspend(struct usb_device *udev) 2637 { 2638 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2639 struct usb_xfer *xfer; 2640 struct usb_pipe_methods *methods; 2641 ohci_ed_t *ed; 2642 2643 DPRINTF("\n"); 2644 2645 USB_BUS_LOCK(udev->bus); 2646 2647 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2648 2649 if (xfer->xroot->udev == udev) { 2650 2651 methods = xfer->endpoint->methods; 2652 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2653 2654 if (methods == &ohci_device_bulk_methods) { 2655 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2656 } 2657 if (methods == &ohci_device_ctrl_methods) { 2658 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2659 } 2660 if (methods == &ohci_device_intr_methods) { 2661 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2662 } 2663 } 2664 } 2665 2666 USB_BUS_UNLOCK(udev->bus); 2667 2668 return; 2669 } 2670 2671 static void 2672 ohci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2673 { 2674 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2675 2676 switch (state) { 2677 case USB_HW_POWER_SUSPEND: 2678 case USB_HW_POWER_SHUTDOWN: 2679 ohci_suspend(sc); 2680 break; 2681 case USB_HW_POWER_RESUME: 2682 ohci_resume(sc); 2683 break; 2684 default: 2685 break; 2686 } 2687 } 2688 2689 static void 2690 ohci_set_hw_power(struct usb_bus *bus) 2691 { 2692 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2693 uint32_t temp; 2694 uint32_t flags; 2695 2696 DPRINTF("\n"); 2697 2698 USB_BUS_LOCK(bus); 2699 2700 flags = bus->hw_power_state; 2701 2702 temp = OREAD4(sc, OHCI_CONTROL); 2703 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2704 2705 if (flags & USB_HW_POWER_CONTROL) 2706 temp |= OHCI_CLE; 2707 2708 if (flags & USB_HW_POWER_BULK) 2709 temp |= OHCI_BLE; 2710 2711 if (flags & USB_HW_POWER_INTERRUPT) 2712 temp |= OHCI_PLE; 2713 2714 if (flags & USB_HW_POWER_ISOC) 2715 temp |= OHCI_IE | OHCI_PLE; 2716 2717 OWRITE4(sc, OHCI_CONTROL, temp); 2718 2719 USB_BUS_UNLOCK(bus); 2720 2721 return; 2722 } 2723 2724 struct usb_bus_methods ohci_bus_methods = 2725 { 2726 .endpoint_init = ohci_ep_init, 2727 .xfer_setup = ohci_xfer_setup, 2728 .xfer_unsetup = ohci_xfer_unsetup, 2729 .get_dma_delay = ohci_get_dma_delay, 2730 .device_resume = ohci_device_resume, 2731 .device_suspend = ohci_device_suspend, 2732 .set_hw_power = ohci_set_hw_power, 2733 .set_hw_power_sleep = ohci_set_hw_power_sleep, 2734 .roothub_exec = ohci_roothub_exec, 2735 .xfer_poll = ohci_do_poll, 2736 }; 2737