1 /* $FreeBSD: head/sys/dev/usb/controller/ohci.c 267992 2014-06-28 03:56:17Z hselasky $ */ 2 /*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 5 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Open Host Controller driver. 31 * 32 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 33 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 34 */ 35 36 #include <sys/stdint.h> 37 #include <sys/param.h> 38 #include <sys/queue.h> 39 #include <sys/types.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 #include <sys/condvar.h> 47 #include <sys/sysctl.h> 48 #include <sys/unistd.h> 49 #include <sys/callout.h> 50 #include <sys/malloc.h> 51 #include <sys/priv.h> 52 53 #include <bus/u4b/usb.h> 54 #include <bus/u4b/usbdi.h> 55 56 #define USB_DEBUG_VAR ohcidebug 57 58 #include <bus/u4b/usb_core.h> 59 #include <bus/u4b/usb_debug.h> 60 #include <bus/u4b/usb_busdma.h> 61 #include <bus/u4b/usb_process.h> 62 #include <bus/u4b/usb_transfer.h> 63 #include <bus/u4b/usb_device.h> 64 #include <bus/u4b/usb_hub.h> 65 #include <bus/u4b/usb_util.h> 66 67 #include <bus/u4b/usb_controller.h> 68 #include <bus/u4b/usb_bus.h> 69 #include <bus/u4b/controller/ohci.h> 70 #include <bus/u4b/controller/ohcireg.h> 71 72 #define OHCI_BUS2SC(bus) \ 73 ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 74 ((uint8_t *)&(((ohci_softc_t *)0)->sc_bus)))) 75 76 #ifdef USB_DEBUG 77 static int ohcidebug = 0; 78 79 static SYSCTL_NODE(_hw_usb, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 80 SYSCTL_INT(_hw_usb_ohci, OID_AUTO, debug, CTLFLAG_RW, 81 &ohcidebug, 0, "ohci debug level"); 82 83 TUNABLE_INT("hw.usb.ohci.debug", &ohcidebug); 84 85 static void ohci_dumpregs(ohci_softc_t *); 86 static void ohci_dump_tds(ohci_td_t *); 87 static uint8_t ohci_dump_td(ohci_td_t *); 88 static void ohci_dump_ed(ohci_ed_t *); 89 static uint8_t ohci_dump_itd(ohci_itd_t *); 90 static void ohci_dump_itds(ohci_itd_t *); 91 92 #endif 93 94 #define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 95 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 96 #define OWRITE1(sc, r, x) \ 97 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 98 #define OWRITE2(sc, r, x) \ 99 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 100 #define OWRITE4(sc, r, x) \ 101 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 102 #define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 103 #define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 104 #define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 105 106 #define OHCI_INTR_ENDPT 1 107 108 static const struct usb_bus_methods ohci_bus_methods; 109 static const struct usb_pipe_methods ohci_device_bulk_methods; 110 static const struct usb_pipe_methods ohci_device_ctrl_methods; 111 static const struct usb_pipe_methods ohci_device_intr_methods; 112 static const struct usb_pipe_methods ohci_device_isoc_methods; 113 114 static void ohci_do_poll(struct usb_bus *bus); 115 static void ohci_device_done(struct usb_xfer *xfer, usb_error_t error); 116 static void ohci_timeout(void *arg); 117 static uint8_t ohci_check_transfer(struct usb_xfer *xfer); 118 static void ohci_root_intr(ohci_softc_t *sc); 119 120 struct ohci_std_temp { 121 struct usb_page_cache *pc; 122 ohci_td_t *td; 123 ohci_td_t *td_next; 124 uint32_t average; 125 uint32_t td_flags; 126 uint32_t len; 127 uint16_t max_frame_size; 128 uint8_t shortpkt; 129 uint8_t setup_alt_next; 130 uint8_t last_frame; 131 }; 132 133 static struct ohci_hcca * 134 ohci_get_hcca(ohci_softc_t *sc) 135 { 136 usb_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 137 return (sc->sc_hcca_p); 138 } 139 140 void 141 ohci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 142 { 143 struct ohci_softc *sc = OHCI_BUS2SC(bus); 144 uint32_t i; 145 146 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 147 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 148 149 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 150 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 151 152 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 153 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 154 155 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 156 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 157 158 for (i = 0; i != OHCI_NO_EDS; i++) { 159 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 160 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 161 } 162 } 163 164 static usb_error_t 165 ohci_controller_init(ohci_softc_t *sc, int do_suspend) 166 { 167 struct usb_page_search buf_res; 168 uint32_t i; 169 uint32_t ctl; 170 uint32_t ival; 171 uint32_t hcr; 172 uint32_t fm; 173 uint32_t per; 174 uint32_t desca; 175 176 /* Determine in what context we are running. */ 177 ctl = OREAD4(sc, OHCI_CONTROL); 178 if (ctl & OHCI_IR) { 179 /* SMM active, request change */ 180 DPRINTF("SMM active, request owner change\n"); 181 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 182 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 183 usb_pause_mtx(NULL, hz / 1000); 184 ctl = OREAD4(sc, OHCI_CONTROL); 185 } 186 if (ctl & OHCI_IR) { 187 device_printf(sc->sc_bus.bdev, 188 "SMM does not respond, resetting\n"); 189 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 190 goto reset; 191 } 192 } else { 193 DPRINTF("cold started\n"); 194 reset: 195 /* controller was cold started */ 196 usb_pause_mtx(NULL, 197 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 198 } 199 200 /* 201 * This reset should not be necessary according to the OHCI spec, but 202 * without it some controllers do not start. 203 */ 204 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 205 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 206 207 usb_pause_mtx(NULL, 208 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 209 210 /* we now own the host controller and the bus has been reset */ 211 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 212 213 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 214 /* nominal time for a reset is 10 us */ 215 for (i = 0; i < 10; i++) { 216 DELAY(10); 217 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 218 if (!hcr) { 219 break; 220 } 221 } 222 if (hcr) { 223 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 224 return (USB_ERR_IOERROR); 225 } 226 #ifdef USB_DEBUG 227 if (ohcidebug > 15) { 228 ohci_dumpregs(sc); 229 } 230 #endif 231 232 if (do_suspend) { 233 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_SUSPEND); 234 return (USB_ERR_NORMAL_COMPLETION); 235 } 236 237 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 238 239 /* set up HC registers */ 240 usbd_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 241 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 242 243 usbd_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 244 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 245 246 usbd_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 247 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 248 249 /* disable all interrupts and then switch on all desired interrupts */ 250 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 251 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 252 /* switch on desired functional features */ 253 ctl = OREAD4(sc, OHCI_CONTROL); 254 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 255 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 256 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 257 /* And finally start it! */ 258 OWRITE4(sc, OHCI_CONTROL, ctl); 259 260 /* 261 * The controller is now OPERATIONAL. Set a some final 262 * registers that should be set earlier, but that the 263 * controller ignores when in the SUSPEND state. 264 */ 265 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 266 fm |= OHCI_FSMPS(ival) | ival; 267 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 268 per = OHCI_PERIODIC(ival); /* 90% periodic */ 269 OWRITE4(sc, OHCI_PERIODIC_START, per); 270 271 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 272 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 273 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 274 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 275 usb_pause_mtx(NULL, 276 USB_MS_TO_TICKS(OHCI_ENABLE_POWER_DELAY)); 277 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 278 279 /* 280 * The AMD756 requires a delay before re-reading the register, 281 * otherwise it will occasionally report 0 ports. 282 */ 283 sc->sc_noport = 0; 284 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 285 usb_pause_mtx(NULL, 286 USB_MS_TO_TICKS(OHCI_READ_DESC_DELAY)); 287 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 288 } 289 290 #ifdef USB_DEBUG 291 if (ohcidebug > 5) { 292 ohci_dumpregs(sc); 293 } 294 #endif 295 return (USB_ERR_NORMAL_COMPLETION); 296 } 297 298 static struct ohci_ed * 299 ohci_init_ed(struct usb_page_cache *pc) 300 { 301 struct usb_page_search buf_res; 302 struct ohci_ed *ed; 303 304 usbd_get_page(pc, 0, &buf_res); 305 306 ed = buf_res.buffer; 307 308 ed->ed_self = htole32(buf_res.physaddr); 309 ed->ed_flags = htole32(OHCI_ED_SKIP); 310 ed->page_cache = pc; 311 312 return (ed); 313 } 314 315 usb_error_t 316 ohci_init(ohci_softc_t *sc) 317 { 318 struct usb_page_search buf_res; 319 uint16_t i; 320 uint16_t bit; 321 uint16_t x; 322 uint16_t y; 323 324 DPRINTF("start\n"); 325 326 sc->sc_eintrs = OHCI_NORMAL_INTRS; 327 328 /* 329 * Setup all ED's 330 */ 331 332 sc->sc_ctrl_p_last = 333 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 334 335 sc->sc_bulk_p_last = 336 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 337 338 sc->sc_isoc_p_last = 339 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 340 341 for (i = 0; i != OHCI_NO_EDS; i++) { 342 sc->sc_intr_p_last[i] = 343 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 344 } 345 346 /* 347 * the QHs are arranged to give poll intervals that are 348 * powers of 2 times 1ms 349 */ 350 bit = OHCI_NO_EDS / 2; 351 while (bit) { 352 x = bit; 353 while (x & bit) { 354 ohci_ed_t *ed_x; 355 ohci_ed_t *ed_y; 356 357 y = (x ^ bit) | (bit / 2); 358 359 /* 360 * the next QH has half the poll interval 361 */ 362 ed_x = sc->sc_intr_p_last[x]; 363 ed_y = sc->sc_intr_p_last[y]; 364 365 ed_x->next = NULL; 366 ed_x->ed_next = ed_y->ed_self; 367 368 x++; 369 } 370 bit >>= 1; 371 } 372 373 if (1) { 374 375 ohci_ed_t *ed_int; 376 ohci_ed_t *ed_isc; 377 378 ed_int = sc->sc_intr_p_last[0]; 379 ed_isc = sc->sc_isoc_p_last; 380 381 /* the last (1ms) QH */ 382 ed_int->next = ed_isc; 383 ed_int->ed_next = ed_isc->ed_self; 384 } 385 usbd_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 386 387 sc->sc_hcca_p = buf_res.buffer; 388 389 /* 390 * Fill HCCA interrupt table. The bit reversal is to get 391 * the tree set up properly to spread the interrupts. 392 */ 393 for (i = 0; i != OHCI_NO_INTRS; i++) { 394 sc->sc_hcca_p->hcca_interrupt_table[i] = 395 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 396 } 397 /* flush all cache into memory */ 398 399 usb_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 400 401 /* set up the bus struct */ 402 sc->sc_bus.methods = &ohci_bus_methods; 403 404 usb_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_lock, 0); 405 406 #ifdef USB_DEBUG 407 if (ohcidebug > 15) { 408 for (i = 0; i != OHCI_NO_EDS; i++) { 409 kprintf("ed#%d ", i); 410 ohci_dump_ed(sc->sc_intr_p_last[i]); 411 } 412 kprintf("iso "); 413 ohci_dump_ed(sc->sc_isoc_p_last); 414 } 415 #endif 416 417 sc->sc_bus.usbrev = USB_REV_1_0; 418 419 if (ohci_controller_init(sc, 0) != 0) 420 return (USB_ERR_INVAL); 421 422 /* catch any lost interrupts */ 423 ohci_do_poll(&sc->sc_bus); 424 return (USB_ERR_NORMAL_COMPLETION); 425 } 426 427 /* 428 * shut down the controller when the system is going down 429 */ 430 void 431 ohci_detach(struct ohci_softc *sc) 432 { 433 USB_BUS_LOCK(&sc->sc_bus); 434 435 usb_callout_stop(&sc->sc_tmo_rhsc); 436 437 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 438 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 439 440 USB_BUS_UNLOCK(&sc->sc_bus); 441 442 /* XXX let stray task complete */ 443 usb_pause_mtx(NULL, hz / 20); 444 445 usb_callout_drain(&sc->sc_tmo_rhsc); 446 } 447 448 static void 449 ohci_suspend(ohci_softc_t *sc) 450 { 451 DPRINTF("\n"); 452 453 #ifdef USB_DEBUG 454 if (ohcidebug > 2) 455 ohci_dumpregs(sc); 456 #endif 457 458 /* reset HC and leave it suspended */ 459 ohci_controller_init(sc, 1); 460 } 461 462 static void 463 ohci_resume(ohci_softc_t *sc) 464 { 465 DPRINTF("\n"); 466 467 #ifdef USB_DEBUG 468 if (ohcidebug > 2) 469 ohci_dumpregs(sc); 470 #endif 471 472 /* some broken BIOSes never initialize the Controller chip */ 473 ohci_controller_init(sc, 0); 474 475 /* catch any lost interrupts */ 476 ohci_do_poll(&sc->sc_bus); 477 } 478 479 #ifdef USB_DEBUG 480 static void 481 ohci_dumpregs(ohci_softc_t *sc) 482 { 483 struct ohci_hcca *hcca; 484 485 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 486 OREAD4(sc, OHCI_REVISION), 487 OREAD4(sc, OHCI_CONTROL), 488 OREAD4(sc, OHCI_COMMAND_STATUS)); 489 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 490 OREAD4(sc, OHCI_INTERRUPT_STATUS), 491 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 492 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 493 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 494 OREAD4(sc, OHCI_HCCA), 495 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 496 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 497 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 498 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 499 OREAD4(sc, OHCI_BULK_HEAD_ED), 500 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 501 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 502 OREAD4(sc, OHCI_DONE_HEAD), 503 OREAD4(sc, OHCI_FM_INTERVAL), 504 OREAD4(sc, OHCI_FM_REMAINING)); 505 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 506 OREAD4(sc, OHCI_FM_NUMBER), 507 OREAD4(sc, OHCI_PERIODIC_START), 508 OREAD4(sc, OHCI_LS_THRESHOLD)); 509 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 510 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 511 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 512 OREAD4(sc, OHCI_RH_STATUS)); 513 DPRINTF(" port1=0x%08x port2=0x%08x\n", 514 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 515 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 516 517 hcca = ohci_get_hcca(sc); 518 519 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 520 le32toh(hcca->hcca_frame_number), 521 le32toh(hcca->hcca_done_head)); 522 } 523 static void 524 ohci_dump_tds(ohci_td_t *std) 525 { 526 for (; std; std = std->obj_next) { 527 if (ohci_dump_td(std)) { 528 break; 529 } 530 } 531 } 532 533 static uint8_t 534 ohci_dump_td(ohci_td_t *std) 535 { 536 uint32_t td_flags; 537 uint8_t temp; 538 539 usb_pc_cpu_invalidate(std->page_cache); 540 541 td_flags = le32toh(std->td_flags); 542 temp = (std->td_next == 0); 543 544 kprintf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 545 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 546 std, le32toh(std->td_self), 547 (td_flags & OHCI_TD_R) ? "-R" : "", 548 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 549 (td_flags & OHCI_TD_IN) ? "-IN" : "", 550 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 551 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 552 OHCI_TD_GET_DI(td_flags), 553 OHCI_TD_GET_EC(td_flags), 554 OHCI_TD_GET_CC(td_flags), 555 le32toh(std->td_cbp), 556 le32toh(std->td_next), 557 le32toh(std->td_be)); 558 559 return (temp); 560 } 561 562 static uint8_t 563 ohci_dump_itd(ohci_itd_t *sitd) 564 { 565 uint32_t itd_flags; 566 uint16_t i; 567 uint8_t temp; 568 569 usb_pc_cpu_invalidate(sitd->page_cache); 570 571 itd_flags = le32toh(sitd->itd_flags); 572 temp = (sitd->itd_next == 0); 573 574 kprintf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 575 "bp0=0x%08x next=0x%08x be=0x%08x\n", 576 sitd, le32toh(sitd->itd_self), 577 OHCI_ITD_GET_SF(itd_flags), 578 OHCI_ITD_GET_DI(itd_flags), 579 OHCI_ITD_GET_FC(itd_flags), 580 OHCI_ITD_GET_CC(itd_flags), 581 le32toh(sitd->itd_bp0), 582 le32toh(sitd->itd_next), 583 le32toh(sitd->itd_be)); 584 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 585 kprintf("offs[%d]=0x%04x ", i, 586 (uint32_t)le16toh(sitd->itd_offset[i])); 587 } 588 kprintf("\n"); 589 590 return (temp); 591 } 592 593 static void 594 ohci_dump_itds(ohci_itd_t *sitd) 595 { 596 for (; sitd; sitd = sitd->obj_next) { 597 if (ohci_dump_itd(sitd)) { 598 break; 599 } 600 } 601 } 602 603 static void 604 ohci_dump_ed(ohci_ed_t *sed) 605 { 606 uint32_t ed_flags; 607 uint32_t ed_headp; 608 609 usb_pc_cpu_invalidate(sed->page_cache); 610 611 ed_flags = le32toh(sed->ed_flags); 612 ed_headp = le32toh(sed->ed_headp); 613 614 kprintf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 615 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 616 sed, le32toh(sed->ed_self), 617 OHCI_ED_GET_FA(ed_flags), 618 OHCI_ED_GET_EN(ed_flags), 619 OHCI_ED_GET_MAXP(ed_flags), 620 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 621 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 622 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 623 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 624 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 625 le32toh(sed->ed_tailp), 626 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 627 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 628 le32toh(sed->ed_headp), 629 le32toh(sed->ed_next)); 630 } 631 632 #endif 633 634 static void 635 ohci_transfer_intr_enqueue(struct usb_xfer *xfer) 636 { 637 /* check for early completion */ 638 if (ohci_check_transfer(xfer)) { 639 return; 640 } 641 /* put transfer on interrupt queue */ 642 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 643 644 /* start timeout, if any */ 645 if (xfer->timeout != 0) { 646 usbd_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 647 } 648 } 649 650 #define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 651 static ohci_ed_t * 652 _ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 653 { 654 DPRINTFN(11, "%p to %p\n", sed, last); 655 656 if (sed->prev != NULL) { 657 /* should not happen */ 658 DPRINTFN(0, "ED already linked!\n"); 659 return (last); 660 } 661 /* (sc->sc_bus.bus_lock) must be locked */ 662 663 sed->next = last->next; 664 sed->ed_next = last->ed_next; 665 sed->ed_tailp = 0; 666 667 sed->prev = last; 668 669 usb_pc_cpu_flush(sed->page_cache); 670 671 /* 672 * the last->next->prev is never followed: sed->next->prev = sed; 673 */ 674 675 last->next = sed; 676 last->ed_next = sed->ed_self; 677 678 usb_pc_cpu_flush(last->page_cache); 679 680 return (sed); 681 } 682 683 #define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 684 static ohci_ed_t * 685 _ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 686 { 687 DPRINTFN(11, "%p from %p\n", sed, last); 688 689 /* (sc->sc_bus.bus_lock) must be locked */ 690 691 /* only remove if not removed from a queue */ 692 if (sed->prev) { 693 694 sed->prev->next = sed->next; 695 sed->prev->ed_next = sed->ed_next; 696 697 usb_pc_cpu_flush(sed->prev->page_cache); 698 699 if (sed->next) { 700 sed->next->prev = sed->prev; 701 usb_pc_cpu_flush(sed->next->page_cache); 702 } 703 last = ((last == sed) ? sed->prev : last); 704 705 sed->prev = 0; 706 707 usb_pc_cpu_flush(sed->page_cache); 708 } 709 return (last); 710 } 711 712 static void 713 ohci_isoc_done(struct usb_xfer *xfer) 714 { 715 uint8_t nframes; 716 uint32_t *plen = xfer->frlengths; 717 volatile uint16_t *olen; 718 uint16_t len = 0; 719 ohci_itd_t *td = xfer->td_transfer_first; 720 721 while (1) { 722 if (td == NULL) { 723 panic("%s:%d: out of TD's\n", 724 __func__, __LINE__); 725 } 726 #ifdef USB_DEBUG 727 if (ohcidebug > 5) { 728 DPRINTF("isoc TD\n"); 729 ohci_dump_itd(td); 730 } 731 #endif 732 usb_pc_cpu_invalidate(td->page_cache); 733 734 nframes = td->frames; 735 olen = &td->itd_offset[0]; 736 737 if (nframes > 8) { 738 nframes = 8; 739 } 740 while (nframes--) { 741 len = le16toh(*olen); 742 743 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 744 len = 0; 745 } else { 746 len &= ((1 << 12) - 1); 747 } 748 749 if (len > *plen) { 750 len = 0;/* invalid length */ 751 } 752 *plen = len; 753 plen++; 754 olen++; 755 } 756 757 if (((void *)td) == xfer->td_transfer_last) { 758 break; 759 } 760 td = td->obj_next; 761 } 762 763 xfer->aframes = xfer->nframes; 764 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 765 } 766 767 #ifdef USB_DEBUG 768 static const char *const 769 ohci_cc_strs[] = 770 { 771 "NO_ERROR", 772 "CRC", 773 "BIT_STUFFING", 774 "DATA_TOGGLE_MISMATCH", 775 776 "STALL", 777 "DEVICE_NOT_RESPONDING", 778 "PID_CHECK_FAILURE", 779 "UNEXPECTED_PID", 780 781 "DATA_OVERRUN", 782 "DATA_UNDERRUN", 783 "BUFFER_OVERRUN", 784 "BUFFER_UNDERRUN", 785 786 "reserved", 787 "reserved", 788 "NOT_ACCESSED", 789 "NOT_ACCESSED" 790 }; 791 792 #endif 793 794 static usb_error_t 795 ohci_non_isoc_done_sub(struct usb_xfer *xfer) 796 { 797 ohci_td_t *td; 798 ohci_td_t *td_alt_next; 799 uint32_t temp; 800 uint32_t phy_start; 801 uint32_t phy_end; 802 uint32_t td_flags; 803 uint16_t cc; 804 805 td = xfer->td_transfer_cache; 806 td_alt_next = td->alt_next; 807 td_flags = 0; 808 809 if (xfer->aframes != xfer->nframes) { 810 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 811 } 812 while (1) { 813 814 usb_pc_cpu_invalidate(td->page_cache); 815 phy_start = le32toh(td->td_cbp); 816 td_flags = le32toh(td->td_flags); 817 cc = OHCI_TD_GET_CC(td_flags); 818 819 if (phy_start) { 820 /* 821 * short transfer - compute the number of remaining 822 * bytes in the hardware buffer: 823 */ 824 phy_end = le32toh(td->td_be); 825 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 826 (OHCI_PAGE_SIZE + 1) : 0x0001); 827 temp += OHCI_PAGE_OFFSET(phy_end); 828 temp -= OHCI_PAGE_OFFSET(phy_start); 829 830 if (temp > td->len) { 831 /* guard against corruption */ 832 cc = OHCI_CC_STALL; 833 } else if (xfer->aframes != xfer->nframes) { 834 /* 835 * Sum up total transfer length 836 * in "frlengths[]": 837 */ 838 xfer->frlengths[xfer->aframes] += td->len - temp; 839 } 840 } else { 841 if (xfer->aframes != xfer->nframes) { 842 /* transfer was complete */ 843 xfer->frlengths[xfer->aframes] += td->len; 844 } 845 } 846 /* Check for last transfer */ 847 if (((void *)td) == xfer->td_transfer_last) { 848 td = NULL; 849 break; 850 } 851 /* Check transfer status */ 852 if (cc) { 853 /* the transfer is finished */ 854 td = NULL; 855 break; 856 } 857 /* Check for short transfer */ 858 if (phy_start) { 859 if (xfer->flags_int.short_frames_ok) { 860 /* follow alt next */ 861 td = td->alt_next; 862 } else { 863 /* the transfer is finished */ 864 td = NULL; 865 } 866 break; 867 } 868 td = td->obj_next; 869 870 if (td->alt_next != td_alt_next) { 871 /* this USB frame is complete */ 872 break; 873 } 874 } 875 876 /* update transfer cache */ 877 878 xfer->td_transfer_cache = td; 879 880 DPRINTFN(16, "error cc=%d (%s)\n", 881 cc, ohci_cc_strs[cc]); 882 883 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 884 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 885 } 886 887 static void 888 ohci_non_isoc_done(struct usb_xfer *xfer) 889 { 890 usb_error_t err = 0; 891 892 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 893 xfer, xfer->endpoint); 894 895 #ifdef USB_DEBUG 896 if (ohcidebug > 10) { 897 ohci_dump_tds(xfer->td_transfer_first); 898 } 899 #endif 900 901 /* reset scanner */ 902 903 xfer->td_transfer_cache = xfer->td_transfer_first; 904 905 if (xfer->flags_int.control_xfr) { 906 907 if (xfer->flags_int.control_hdr) { 908 909 err = ohci_non_isoc_done_sub(xfer); 910 } 911 xfer->aframes = 1; 912 913 if (xfer->td_transfer_cache == NULL) { 914 goto done; 915 } 916 } 917 while (xfer->aframes != xfer->nframes) { 918 919 err = ohci_non_isoc_done_sub(xfer); 920 xfer->aframes++; 921 922 if (xfer->td_transfer_cache == NULL) { 923 goto done; 924 } 925 } 926 927 if (xfer->flags_int.control_xfr && 928 !xfer->flags_int.control_act) { 929 930 err = ohci_non_isoc_done_sub(xfer); 931 } 932 done: 933 ohci_device_done(xfer, err); 934 } 935 936 /*------------------------------------------------------------------------* 937 * ohci_check_transfer_sub 938 *------------------------------------------------------------------------*/ 939 static void 940 ohci_check_transfer_sub(struct usb_xfer *xfer) 941 { 942 ohci_td_t *td; 943 ohci_ed_t *ed; 944 uint32_t phy_start; 945 uint32_t td_flags; 946 uint32_t td_next; 947 uint16_t cc; 948 949 td = xfer->td_transfer_cache; 950 951 while (1) { 952 953 usb_pc_cpu_invalidate(td->page_cache); 954 phy_start = le32toh(td->td_cbp); 955 td_flags = le32toh(td->td_flags); 956 td_next = le32toh(td->td_next); 957 958 /* Check for last transfer */ 959 if (((void *)td) == xfer->td_transfer_last) { 960 /* the transfer is finished */ 961 td = NULL; 962 break; 963 } 964 /* Check transfer status */ 965 cc = OHCI_TD_GET_CC(td_flags); 966 if (cc) { 967 /* the transfer is finished */ 968 td = NULL; 969 break; 970 } 971 /* 972 * Check if we reached the last packet 973 * or if there is a short packet: 974 */ 975 976 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 977 /* follow alt next */ 978 td = td->alt_next; 979 break; 980 } 981 td = td->obj_next; 982 } 983 984 /* update transfer cache */ 985 986 xfer->td_transfer_cache = td; 987 988 if (td) { 989 990 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 991 992 ed->ed_headp = td->td_self; 993 usb_pc_cpu_flush(ed->page_cache); 994 995 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 996 997 /* 998 * Make sure that the OHCI re-scans the schedule by 999 * writing the BLF and CLF bits: 1000 */ 1001 1002 if (xfer->xroot->udev->flags.self_suspended) { 1003 /* nothing to do */ 1004 } else if (xfer->endpoint->methods == &ohci_device_bulk_methods) { 1005 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1006 1007 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1008 } else if (xfer->endpoint->methods == &ohci_device_ctrl_methods) { 1009 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1010 1011 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1012 } 1013 } 1014 } 1015 1016 /*------------------------------------------------------------------------* 1017 * ohci_check_transfer 1018 * 1019 * Return values: 1020 * 0: USB transfer is not finished 1021 * Else: USB transfer is finished 1022 *------------------------------------------------------------------------*/ 1023 static uint8_t 1024 ohci_check_transfer(struct usb_xfer *xfer) 1025 { 1026 ohci_ed_t *ed; 1027 uint32_t ed_headp; 1028 uint32_t ed_tailp; 1029 1030 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1031 1032 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1033 1034 usb_pc_cpu_invalidate(ed->page_cache); 1035 ed_headp = le32toh(ed->ed_headp); 1036 ed_tailp = le32toh(ed->ed_tailp); 1037 1038 if ((ed_headp & OHCI_HALTED) || 1039 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1040 if (xfer->endpoint->methods == &ohci_device_isoc_methods) { 1041 /* isochronous transfer */ 1042 ohci_isoc_done(xfer); 1043 } else { 1044 if (xfer->flags_int.short_frames_ok) { 1045 ohci_check_transfer_sub(xfer); 1046 if (xfer->td_transfer_cache) { 1047 /* not finished yet */ 1048 return (0); 1049 } 1050 } 1051 /* store data-toggle */ 1052 if (ed_headp & OHCI_TOGGLECARRY) { 1053 xfer->endpoint->toggle_next = 1; 1054 } else { 1055 xfer->endpoint->toggle_next = 0; 1056 } 1057 1058 /* non-isochronous transfer */ 1059 ohci_non_isoc_done(xfer); 1060 } 1061 return (1); 1062 } 1063 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1064 return (0); 1065 } 1066 1067 static void 1068 ohci_rhsc_enable(ohci_softc_t *sc) 1069 { 1070 DPRINTFN(5, "\n"); 1071 1072 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 1073 1074 sc->sc_eintrs |= OHCI_RHSC; 1075 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1076 1077 /* acknowledge any RHSC interrupt */ 1078 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1079 1080 ohci_root_intr(sc); 1081 } 1082 1083 static void 1084 ohci_interrupt_poll(ohci_softc_t *sc) 1085 { 1086 struct usb_xfer *xfer; 1087 1088 repeat: 1089 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1090 /* 1091 * check if transfer is transferred 1092 */ 1093 if (ohci_check_transfer(xfer)) { 1094 /* queue has been modified */ 1095 goto repeat; 1096 } 1097 } 1098 } 1099 1100 /*------------------------------------------------------------------------* 1101 * ohci_interrupt - OHCI interrupt handler 1102 * 1103 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1104 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1105 * is present ! 1106 *------------------------------------------------------------------------*/ 1107 void 1108 ohci_interrupt(ohci_softc_t *sc) 1109 { 1110 struct ohci_hcca *hcca; 1111 uint32_t status; 1112 uint32_t done; 1113 1114 USB_BUS_LOCK(&sc->sc_bus); 1115 1116 hcca = ohci_get_hcca(sc); 1117 1118 DPRINTFN(16, "real interrupt\n"); 1119 1120 #ifdef USB_DEBUG 1121 if (ohcidebug > 15) { 1122 ohci_dumpregs(sc); 1123 } 1124 #endif 1125 1126 done = le32toh(hcca->hcca_done_head); 1127 1128 /* 1129 * The LSb of done is used to inform the HC Driver that an interrupt 1130 * condition exists for both the Done list and for another event 1131 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1132 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1133 * the interrupt was caused by other than the HccaDoneHead update 1134 * and the HcInterruptStatus register needs to be accessed to 1135 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1136 * then a Done list update interrupt is indicated and if the LSb of 1137 * done is nonzero, then an additional interrupt event is indicated 1138 * and HcInterruptStatus should be checked to determine its cause. 1139 */ 1140 if (done != 0) { 1141 status = 0; 1142 1143 if (done & ~OHCI_DONE_INTRS) { 1144 status |= OHCI_WDH; 1145 } 1146 if (done & OHCI_DONE_INTRS) { 1147 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1148 } 1149 hcca->hcca_done_head = 0; 1150 1151 usb_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1152 } else { 1153 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1154 } 1155 1156 status &= ~OHCI_MIE; 1157 if (status == 0) { 1158 /* 1159 * nothing to be done (PCI shared 1160 * interrupt) 1161 */ 1162 goto done; 1163 } 1164 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1165 1166 status &= sc->sc_eintrs; 1167 if (status == 0) { 1168 goto done; 1169 } 1170 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1171 #if 0 1172 if (status & OHCI_SO) { 1173 /* XXX do what */ 1174 } 1175 #endif 1176 if (status & OHCI_RD) { 1177 kprintf("%s: resume detect\n", __func__); 1178 /* XXX process resume detect */ 1179 } 1180 if (status & OHCI_UE) { 1181 kprintf("%s: unrecoverable error, " 1182 "controller halted\n", __func__); 1183 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1184 /* XXX what else */ 1185 } 1186 if (status & OHCI_RHSC) { 1187 /* 1188 * Disable RHSC interrupt for now, because it will be 1189 * on until the port has been reset. 1190 */ 1191 sc->sc_eintrs &= ~OHCI_RHSC; 1192 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1193 1194 ohci_root_intr(sc); 1195 1196 /* do not allow RHSC interrupts > 1 per second */ 1197 usb_callout_reset(&sc->sc_tmo_rhsc, hz, 1198 (void *)&ohci_rhsc_enable, sc); 1199 } 1200 } 1201 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1202 if (status != 0) { 1203 /* Block unprocessed interrupts. XXX */ 1204 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1205 sc->sc_eintrs &= ~status; 1206 kprintf("%s: blocking intrs 0x%x\n", 1207 __func__, status); 1208 } 1209 /* poll all the USB transfers */ 1210 ohci_interrupt_poll(sc); 1211 1212 done: 1213 USB_BUS_UNLOCK(&sc->sc_bus); 1214 } 1215 1216 /* 1217 * called when a request does not complete 1218 */ 1219 static void 1220 ohci_timeout(void *arg) 1221 { 1222 struct usb_xfer *xfer = arg; 1223 1224 DPRINTF("xfer=%p\n", xfer); 1225 1226 USB_BUS_LOCK_ASSERT(xfer->xroot->bus); 1227 1228 /* transfer is transferred */ 1229 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1230 } 1231 1232 static void 1233 ohci_do_poll(struct usb_bus *bus) 1234 { 1235 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1236 1237 USB_BUS_LOCK(&sc->sc_bus); 1238 ohci_interrupt_poll(sc); 1239 USB_BUS_UNLOCK(&sc->sc_bus); 1240 } 1241 1242 static void 1243 ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1244 { 1245 struct usb_page_search buf_res; 1246 ohci_td_t *td; 1247 ohci_td_t *td_next; 1248 ohci_td_t *td_alt_next; 1249 uint32_t buf_offset; 1250 uint32_t average; 1251 uint32_t len_old; 1252 uint8_t shortpkt_old; 1253 uint8_t precompute; 1254 1255 td_alt_next = NULL; 1256 buf_offset = 0; 1257 shortpkt_old = temp->shortpkt; 1258 len_old = temp->len; 1259 precompute = 1; 1260 1261 /* software is used to detect short incoming transfers */ 1262 1263 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1264 temp->td_flags |= htole32(OHCI_TD_R); 1265 } else { 1266 temp->td_flags &= ~htole32(OHCI_TD_R); 1267 } 1268 1269 restart: 1270 1271 td = temp->td; 1272 td_next = temp->td_next; 1273 1274 while (1) { 1275 1276 if (temp->len == 0) { 1277 1278 if (temp->shortpkt) { 1279 break; 1280 } 1281 /* send a Zero Length Packet, ZLP, last */ 1282 1283 temp->shortpkt = 1; 1284 average = 0; 1285 1286 } else { 1287 1288 average = temp->average; 1289 1290 if (temp->len < average) { 1291 if (temp->len % temp->max_frame_size) { 1292 temp->shortpkt = 1; 1293 } 1294 average = temp->len; 1295 } 1296 } 1297 1298 if (td_next == NULL) { 1299 panic("%s: out of OHCI transfer descriptors!", __func__); 1300 } 1301 /* get next TD */ 1302 1303 td = td_next; 1304 td_next = td->obj_next; 1305 1306 /* check if we are pre-computing */ 1307 1308 if (precompute) { 1309 1310 /* update remaining length */ 1311 1312 temp->len -= average; 1313 1314 continue; 1315 } 1316 /* fill out current TD */ 1317 td->td_flags = temp->td_flags; 1318 1319 /* the next TD uses TOGGLE_CARRY */ 1320 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1321 1322 if (average == 0) { 1323 /* 1324 * The buffer start and end phys addresses should be 1325 * 0x0 for a zero length packet. 1326 */ 1327 td->td_cbp = 0; 1328 td->td_be = 0; 1329 td->len = 0; 1330 1331 } else { 1332 1333 usbd_get_page(temp->pc, buf_offset, &buf_res); 1334 td->td_cbp = htole32(buf_res.physaddr); 1335 buf_offset += (average - 1); 1336 1337 usbd_get_page(temp->pc, buf_offset, &buf_res); 1338 td->td_be = htole32(buf_res.physaddr); 1339 buf_offset++; 1340 1341 td->len = average; 1342 1343 /* update remaining length */ 1344 1345 temp->len -= average; 1346 } 1347 1348 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1349 /* we need to receive these frames one by one ! */ 1350 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1351 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1352 td->td_next = htole32(OHCI_TD_NEXT_END); 1353 } else { 1354 if (td_next) { 1355 /* link the current TD with the next one */ 1356 td->td_next = td_next->td_self; 1357 } 1358 } 1359 1360 td->alt_next = td_alt_next; 1361 1362 usb_pc_cpu_flush(td->page_cache); 1363 } 1364 1365 if (precompute) { 1366 precompute = 0; 1367 1368 /* setup alt next pointer, if any */ 1369 if (temp->last_frame) { 1370 /* no alternate next */ 1371 td_alt_next = NULL; 1372 } else { 1373 /* we use this field internally */ 1374 td_alt_next = td_next; 1375 } 1376 1377 /* restore */ 1378 temp->shortpkt = shortpkt_old; 1379 temp->len = len_old; 1380 goto restart; 1381 } 1382 temp->td = td; 1383 temp->td_next = td_next; 1384 } 1385 1386 static void 1387 ohci_setup_standard_chain(struct usb_xfer *xfer, ohci_ed_t **ed_last) 1388 { 1389 struct ohci_std_temp temp; 1390 const struct usb_pipe_methods *methods; 1391 ohci_ed_t *ed; 1392 ohci_td_t *td; 1393 uint32_t ed_flags; 1394 uint32_t x; 1395 1396 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1397 xfer->address, UE_GET_ADDR(xfer->endpointno), 1398 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1399 1400 temp.average = xfer->max_hc_frame_size; 1401 temp.max_frame_size = xfer->max_frame_size; 1402 1403 /* toggle the DMA set we are using */ 1404 xfer->flags_int.curr_dma_set ^= 1; 1405 1406 /* get next DMA set */ 1407 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1408 1409 xfer->td_transfer_first = td; 1410 xfer->td_transfer_cache = td; 1411 1412 temp.td = NULL; 1413 temp.td_next = td; 1414 temp.last_frame = 0; 1415 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1416 1417 methods = xfer->endpoint->methods; 1418 1419 /* check if we should prepend a setup message */ 1420 1421 if (xfer->flags_int.control_xfr) { 1422 if (xfer->flags_int.control_hdr) { 1423 1424 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1425 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1426 1427 temp.len = xfer->frlengths[0]; 1428 temp.pc = xfer->frbuffers + 0; 1429 temp.shortpkt = temp.len ? 1 : 0; 1430 /* check for last frame */ 1431 if (xfer->nframes == 1) { 1432 /* no STATUS stage yet, SETUP is last */ 1433 if (xfer->flags_int.control_act) { 1434 temp.last_frame = 1; 1435 temp.setup_alt_next = 0; 1436 } 1437 } 1438 ohci_setup_standard_chain_sub(&temp); 1439 1440 /* 1441 * XXX assume that the setup message is 1442 * contained within one USB packet: 1443 */ 1444 xfer->endpoint->toggle_next = 1; 1445 } 1446 x = 1; 1447 } else { 1448 x = 0; 1449 } 1450 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1451 1452 /* set data toggle */ 1453 1454 if (xfer->endpoint->toggle_next) { 1455 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1456 } else { 1457 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1458 } 1459 1460 /* set endpoint direction */ 1461 1462 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1463 temp.td_flags |= htole32(OHCI_TD_IN); 1464 } else { 1465 temp.td_flags |= htole32(OHCI_TD_OUT); 1466 } 1467 1468 while (x != xfer->nframes) { 1469 1470 /* DATA0 / DATA1 message */ 1471 1472 temp.len = xfer->frlengths[x]; 1473 temp.pc = xfer->frbuffers + x; 1474 1475 x++; 1476 1477 if (x == xfer->nframes) { 1478 if (xfer->flags_int.control_xfr) { 1479 /* no STATUS stage yet, DATA is last */ 1480 if (xfer->flags_int.control_act) { 1481 temp.last_frame = 1; 1482 temp.setup_alt_next = 0; 1483 } 1484 } else { 1485 temp.last_frame = 1; 1486 temp.setup_alt_next = 0; 1487 } 1488 } 1489 if (temp.len == 0) { 1490 1491 /* make sure that we send an USB packet */ 1492 1493 temp.shortpkt = 0; 1494 1495 } else { 1496 1497 /* regular data transfer */ 1498 1499 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1500 } 1501 1502 ohci_setup_standard_chain_sub(&temp); 1503 } 1504 1505 /* check if we should append a status stage */ 1506 1507 if (xfer->flags_int.control_xfr && 1508 !xfer->flags_int.control_act) { 1509 1510 /* 1511 * Send a DATA1 message and invert the current endpoint 1512 * direction. 1513 */ 1514 1515 /* set endpoint direction and data toggle */ 1516 1517 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1518 temp.td_flags = htole32(OHCI_TD_OUT | 1519 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1520 } else { 1521 temp.td_flags = htole32(OHCI_TD_IN | 1522 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1523 } 1524 1525 temp.len = 0; 1526 temp.pc = NULL; 1527 temp.shortpkt = 0; 1528 temp.last_frame = 1; 1529 temp.setup_alt_next = 0; 1530 1531 ohci_setup_standard_chain_sub(&temp); 1532 } 1533 td = temp.td; 1534 1535 /* Ensure that last TD is terminating: */ 1536 td->td_next = htole32(OHCI_TD_NEXT_END); 1537 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1538 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1539 1540 usb_pc_cpu_flush(td->page_cache); 1541 1542 /* must have at least one frame! */ 1543 1544 xfer->td_transfer_last = td; 1545 1546 #ifdef USB_DEBUG 1547 if (ohcidebug > 8) { 1548 DPRINTF("nexttog=%d; data before transfer:\n", 1549 xfer->endpoint->toggle_next); 1550 ohci_dump_tds(xfer->td_transfer_first); 1551 } 1552 #endif 1553 1554 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1555 1556 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1557 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 1558 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1559 1560 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1561 1562 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1563 ed_flags |= OHCI_ED_SPEED; 1564 } 1565 ed->ed_flags = htole32(ed_flags); 1566 1567 td = xfer->td_transfer_first; 1568 1569 ed->ed_headp = td->td_self; 1570 1571 if (xfer->xroot->udev->flags.self_suspended == 0) { 1572 /* the append function will flush the endpoint descriptor */ 1573 OHCI_APPEND_QH(ed, *ed_last); 1574 1575 if (methods == &ohci_device_bulk_methods) { 1576 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1577 1578 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1579 } 1580 if (methods == &ohci_device_ctrl_methods) { 1581 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1582 1583 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1584 } 1585 } else { 1586 usb_pc_cpu_flush(ed->page_cache); 1587 } 1588 } 1589 1590 static void 1591 ohci_root_intr(ohci_softc_t *sc) 1592 { 1593 uint32_t hstatus; 1594 uint16_t i; 1595 uint16_t m; 1596 1597 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 1598 1599 /* clear any old interrupt data */ 1600 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 1601 1602 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1603 DPRINTF("sc=%p hstatus=0x%08x\n", 1604 sc, hstatus); 1605 1606 /* set bits */ 1607 m = (sc->sc_noport + 1); 1608 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1609 m = (8 * sizeof(sc->sc_hub_idata)); 1610 } 1611 for (i = 1; i < m; i++) { 1612 /* pick out CHANGE bits from the status register */ 1613 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1614 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1615 DPRINTF("port %d changed\n", i); 1616 } 1617 } 1618 1619 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1620 sizeof(sc->sc_hub_idata)); 1621 } 1622 1623 /* NOTE: "done" can be run two times in a row, 1624 * from close and from interrupt 1625 */ 1626 static void 1627 ohci_device_done(struct usb_xfer *xfer, usb_error_t error) 1628 { 1629 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1630 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1631 ohci_ed_t *ed; 1632 1633 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 1634 1635 1636 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1637 xfer, xfer->endpoint, error); 1638 1639 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1640 if (ed) { 1641 usb_pc_cpu_invalidate(ed->page_cache); 1642 } 1643 if (methods == &ohci_device_bulk_methods) { 1644 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1645 } 1646 if (methods == &ohci_device_ctrl_methods) { 1647 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1648 } 1649 if (methods == &ohci_device_intr_methods) { 1650 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1651 } 1652 if (methods == &ohci_device_isoc_methods) { 1653 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1654 } 1655 xfer->td_transfer_first = NULL; 1656 xfer->td_transfer_last = NULL; 1657 1658 /* dequeue transfer and start next transfer */ 1659 usbd_transfer_done(xfer, error); 1660 } 1661 1662 /*------------------------------------------------------------------------* 1663 * ohci bulk support 1664 *------------------------------------------------------------------------*/ 1665 static void 1666 ohci_device_bulk_open(struct usb_xfer *xfer) 1667 { 1668 return; 1669 } 1670 1671 static void 1672 ohci_device_bulk_close(struct usb_xfer *xfer) 1673 { 1674 ohci_device_done(xfer, USB_ERR_CANCELLED); 1675 } 1676 1677 static void 1678 ohci_device_bulk_enter(struct usb_xfer *xfer) 1679 { 1680 return; 1681 } 1682 1683 static void 1684 ohci_device_bulk_start(struct usb_xfer *xfer) 1685 { 1686 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1687 1688 /* setup TD's and QH */ 1689 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1690 1691 /* put transfer on interrupt queue */ 1692 ohci_transfer_intr_enqueue(xfer); 1693 } 1694 1695 static const struct usb_pipe_methods ohci_device_bulk_methods = 1696 { 1697 .open = ohci_device_bulk_open, 1698 .close = ohci_device_bulk_close, 1699 .enter = ohci_device_bulk_enter, 1700 .start = ohci_device_bulk_start, 1701 }; 1702 1703 /*------------------------------------------------------------------------* 1704 * ohci control support 1705 *------------------------------------------------------------------------*/ 1706 static void 1707 ohci_device_ctrl_open(struct usb_xfer *xfer) 1708 { 1709 return; 1710 } 1711 1712 static void 1713 ohci_device_ctrl_close(struct usb_xfer *xfer) 1714 { 1715 ohci_device_done(xfer, USB_ERR_CANCELLED); 1716 } 1717 1718 static void 1719 ohci_device_ctrl_enter(struct usb_xfer *xfer) 1720 { 1721 return; 1722 } 1723 1724 static void 1725 ohci_device_ctrl_start(struct usb_xfer *xfer) 1726 { 1727 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1728 1729 /* setup TD's and QH */ 1730 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1731 1732 /* put transfer on interrupt queue */ 1733 ohci_transfer_intr_enqueue(xfer); 1734 } 1735 1736 static const struct usb_pipe_methods ohci_device_ctrl_methods = 1737 { 1738 .open = ohci_device_ctrl_open, 1739 .close = ohci_device_ctrl_close, 1740 .enter = ohci_device_ctrl_enter, 1741 .start = ohci_device_ctrl_start, 1742 }; 1743 1744 /*------------------------------------------------------------------------* 1745 * ohci interrupt support 1746 *------------------------------------------------------------------------*/ 1747 static void 1748 ohci_device_intr_open(struct usb_xfer *xfer) 1749 { 1750 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1751 uint16_t best; 1752 uint16_t bit; 1753 uint16_t x; 1754 1755 best = 0; 1756 bit = OHCI_NO_EDS / 2; 1757 while (bit) { 1758 if (xfer->interval >= bit) { 1759 x = bit; 1760 best = bit; 1761 while (x & bit) { 1762 if (sc->sc_intr_stat[x] < 1763 sc->sc_intr_stat[best]) { 1764 best = x; 1765 } 1766 x++; 1767 } 1768 break; 1769 } 1770 bit >>= 1; 1771 } 1772 1773 sc->sc_intr_stat[best]++; 1774 xfer->qh_pos = best; 1775 1776 DPRINTFN(3, "best=%d interval=%d\n", 1777 best, xfer->interval); 1778 } 1779 1780 static void 1781 ohci_device_intr_close(struct usb_xfer *xfer) 1782 { 1783 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1784 1785 sc->sc_intr_stat[xfer->qh_pos]--; 1786 1787 ohci_device_done(xfer, USB_ERR_CANCELLED); 1788 } 1789 1790 static void 1791 ohci_device_intr_enter(struct usb_xfer *xfer) 1792 { 1793 return; 1794 } 1795 1796 static void 1797 ohci_device_intr_start(struct usb_xfer *xfer) 1798 { 1799 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1800 1801 /* setup TD's and QH */ 1802 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1803 1804 /* put transfer on interrupt queue */ 1805 ohci_transfer_intr_enqueue(xfer); 1806 } 1807 1808 static const struct usb_pipe_methods ohci_device_intr_methods = 1809 { 1810 .open = ohci_device_intr_open, 1811 .close = ohci_device_intr_close, 1812 .enter = ohci_device_intr_enter, 1813 .start = ohci_device_intr_start, 1814 }; 1815 1816 /*------------------------------------------------------------------------* 1817 * ohci isochronous support 1818 *------------------------------------------------------------------------*/ 1819 static void 1820 ohci_device_isoc_open(struct usb_xfer *xfer) 1821 { 1822 return; 1823 } 1824 1825 static void 1826 ohci_device_isoc_close(struct usb_xfer *xfer) 1827 { 1828 /**/ 1829 ohci_device_done(xfer, USB_ERR_CANCELLED); 1830 } 1831 1832 static void 1833 ohci_device_isoc_enter(struct usb_xfer *xfer) 1834 { 1835 struct usb_page_search buf_res; 1836 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1837 struct ohci_hcca *hcca; 1838 uint32_t buf_offset; 1839 uint32_t nframes; 1840 uint32_t ed_flags; 1841 uint32_t *plen; 1842 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1843 uint16_t length; 1844 uint8_t ncur; 1845 ohci_itd_t *td; 1846 ohci_itd_t *td_last = NULL; 1847 ohci_ed_t *ed; 1848 1849 hcca = ohci_get_hcca(sc); 1850 1851 nframes = le32toh(hcca->hcca_frame_number); 1852 1853 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1854 xfer, xfer->endpoint->isoc_next, xfer->nframes, nframes); 1855 1856 if ((xfer->endpoint->is_synced == 0) || 1857 (((nframes - xfer->endpoint->isoc_next) & 0xFFFF) < xfer->nframes) || 1858 (((xfer->endpoint->isoc_next - nframes) & 0xFFFF) >= 128)) { 1859 /* 1860 * If there is data underflow or the pipe queue is empty we 1861 * schedule the transfer a few frames ahead of the current 1862 * frame position. Else two isochronous transfers might 1863 * overlap. 1864 */ 1865 xfer->endpoint->isoc_next = (nframes + 3) & 0xFFFF; 1866 xfer->endpoint->is_synced = 1; 1867 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1868 } 1869 /* 1870 * compute how many milliseconds the insertion is ahead of the 1871 * current frame position: 1872 */ 1873 buf_offset = ((xfer->endpoint->isoc_next - nframes) & 0xFFFF); 1874 1875 /* 1876 * pre-compute when the isochronous transfer will be finished: 1877 */ 1878 xfer->isoc_time_complete = 1879 (usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1880 xfer->nframes); 1881 1882 /* get the real number of frames */ 1883 1884 nframes = xfer->nframes; 1885 1886 buf_offset = 0; 1887 1888 plen = xfer->frlengths; 1889 1890 /* toggle the DMA set we are using */ 1891 xfer->flags_int.curr_dma_set ^= 1; 1892 1893 /* get next DMA set */ 1894 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1895 1896 xfer->td_transfer_first = td; 1897 1898 ncur = 0; 1899 length = 0; 1900 1901 while (nframes--) { 1902 if (td == NULL) { 1903 panic("%s:%d: out of TD's\n", 1904 __func__, __LINE__); 1905 } 1906 itd_offset[ncur] = length; 1907 buf_offset += *plen; 1908 length += *plen; 1909 plen++; 1910 ncur++; 1911 1912 if ( /* check if the ITD is full */ 1913 (ncur == OHCI_ITD_NOFFSET) || 1914 /* check if we have put more than 4K into the ITD */ 1915 (length & 0xF000) || 1916 /* check if it is the last frame */ 1917 (nframes == 0)) { 1918 1919 /* fill current ITD */ 1920 td->itd_flags = htole32( 1921 OHCI_ITD_NOCC | 1922 OHCI_ITD_SET_SF(xfer->endpoint->isoc_next) | 1923 OHCI_ITD_NOINTR | 1924 OHCI_ITD_SET_FC(ncur)); 1925 1926 td->frames = ncur; 1927 xfer->endpoint->isoc_next += ncur; 1928 1929 if (length == 0) { 1930 /* all zero */ 1931 td->itd_bp0 = 0; 1932 td->itd_be = ~0; 1933 1934 while (ncur--) { 1935 td->itd_offset[ncur] = 1936 htole16(OHCI_ITD_MK_OFFS(0)); 1937 } 1938 } else { 1939 usbd_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1940 length = OHCI_PAGE_MASK(buf_res.physaddr); 1941 buf_res.physaddr = 1942 OHCI_PAGE(buf_res.physaddr); 1943 td->itd_bp0 = htole32(buf_res.physaddr); 1944 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1945 td->itd_be = htole32(buf_res.physaddr); 1946 1947 while (ncur--) { 1948 itd_offset[ncur] += length; 1949 itd_offset[ncur] = 1950 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1951 td->itd_offset[ncur] = 1952 htole16(itd_offset[ncur]); 1953 } 1954 } 1955 ncur = 0; 1956 length = 0; 1957 td_last = td; 1958 td = td->obj_next; 1959 1960 if (td) { 1961 /* link the last TD with the next one */ 1962 td_last->itd_next = td->itd_self; 1963 } 1964 usb_pc_cpu_flush(td_last->page_cache); 1965 } 1966 } 1967 1968 /* update the last TD */ 1969 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 1970 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 1971 td_last->itd_next = 0; 1972 1973 usb_pc_cpu_flush(td_last->page_cache); 1974 1975 xfer->td_transfer_last = td_last; 1976 1977 #ifdef USB_DEBUG 1978 if (ohcidebug > 8) { 1979 DPRINTF("data before transfer:\n"); 1980 ohci_dump_itds(xfer->td_transfer_first); 1981 } 1982 #endif 1983 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1984 1985 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 1986 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 1987 else 1988 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 1989 1990 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 1991 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 1992 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1993 1994 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1995 ed_flags |= OHCI_ED_SPEED; 1996 } 1997 ed->ed_flags = htole32(ed_flags); 1998 1999 td = xfer->td_transfer_first; 2000 2001 ed->ed_headp = td->itd_self; 2002 2003 /* isochronous transfers are not affected by suspend / resume */ 2004 /* the append function will flush the endpoint descriptor */ 2005 2006 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2007 } 2008 2009 static void 2010 ohci_device_isoc_start(struct usb_xfer *xfer) 2011 { 2012 /* put transfer on interrupt queue */ 2013 ohci_transfer_intr_enqueue(xfer); 2014 } 2015 2016 static const struct usb_pipe_methods ohci_device_isoc_methods = 2017 { 2018 .open = ohci_device_isoc_open, 2019 .close = ohci_device_isoc_close, 2020 .enter = ohci_device_isoc_enter, 2021 .start = ohci_device_isoc_start, 2022 }; 2023 2024 /*------------------------------------------------------------------------* 2025 * ohci root control support 2026 *------------------------------------------------------------------------* 2027 * Simulate a hardware hub by handling all the necessary requests. 2028 *------------------------------------------------------------------------*/ 2029 2030 static const 2031 struct usb_device_descriptor ohci_devd = 2032 { 2033 sizeof(struct usb_device_descriptor), 2034 UDESC_DEVICE, /* type */ 2035 {0x00, 0x01}, /* USB version */ 2036 UDCLASS_HUB, /* class */ 2037 UDSUBCLASS_HUB, /* subclass */ 2038 UDPROTO_FSHUB, /* protocol */ 2039 64, /* max packet */ 2040 {0}, {0}, {0x00, 0x01}, /* device id */ 2041 1, 2, 0, /* string indicies */ 2042 1 /* # of configurations */ 2043 }; 2044 2045 static const 2046 struct ohci_config_desc ohci_confd = 2047 { 2048 .confd = { 2049 .bLength = sizeof(struct usb_config_descriptor), 2050 .bDescriptorType = UDESC_CONFIG, 2051 .wTotalLength[0] = sizeof(ohci_confd), 2052 .bNumInterface = 1, 2053 .bConfigurationValue = 1, 2054 .iConfiguration = 0, 2055 .bmAttributes = UC_SELF_POWERED, 2056 .bMaxPower = 0, /* max power */ 2057 }, 2058 .ifcd = { 2059 .bLength = sizeof(struct usb_interface_descriptor), 2060 .bDescriptorType = UDESC_INTERFACE, 2061 .bNumEndpoints = 1, 2062 .bInterfaceClass = UICLASS_HUB, 2063 .bInterfaceSubClass = UISUBCLASS_HUB, 2064 .bInterfaceProtocol = 0, 2065 }, 2066 .endpd = { 2067 .bLength = sizeof(struct usb_endpoint_descriptor), 2068 .bDescriptorType = UDESC_ENDPOINT, 2069 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2070 .bmAttributes = UE_INTERRUPT, 2071 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2072 .bInterval = 255, 2073 }, 2074 }; 2075 2076 static const 2077 struct usb_hub_descriptor ohci_hubd = 2078 { 2079 .bDescLength = 0, /* dynamic length */ 2080 .bDescriptorType = UDESC_HUB, 2081 }; 2082 2083 static usb_error_t 2084 ohci_roothub_exec(struct usb_device *udev, 2085 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2086 { 2087 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2088 const void *ptr; 2089 const char *str_ptr; 2090 uint32_t port; 2091 uint32_t v; 2092 uint16_t len; 2093 uint16_t value; 2094 uint16_t index; 2095 uint8_t l; 2096 usb_error_t err; 2097 2098 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2099 2100 /* buffer reset */ 2101 ptr = (const void *)&sc->sc_hub_desc.temp; 2102 len = 0; 2103 err = 0; 2104 2105 value = UGETW(req->wValue); 2106 index = UGETW(req->wIndex); 2107 2108 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2109 "wValue=0x%04x wIndex=0x%04x\n", 2110 req->bmRequestType, req->bRequest, 2111 UGETW(req->wLength), value, index); 2112 2113 #define C(x,y) ((x) | ((y) << 8)) 2114 switch (C(req->bRequest, req->bmRequestType)) { 2115 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2116 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2117 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2118 /* 2119 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2120 * for the integrated root hub. 2121 */ 2122 break; 2123 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2124 len = 1; 2125 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2126 break; 2127 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2128 switch (value >> 8) { 2129 case UDESC_DEVICE: 2130 if ((value & 0xff) != 0) { 2131 err = USB_ERR_IOERROR; 2132 goto done; 2133 } 2134 len = sizeof(ohci_devd); 2135 ptr = (const void *)&ohci_devd; 2136 break; 2137 2138 case UDESC_CONFIG: 2139 if ((value & 0xff) != 0) { 2140 err = USB_ERR_IOERROR; 2141 goto done; 2142 } 2143 len = sizeof(ohci_confd); 2144 ptr = (const void *)&ohci_confd; 2145 break; 2146 2147 case UDESC_STRING: 2148 switch (value & 0xff) { 2149 case 0: /* Language table */ 2150 str_ptr = "\001"; 2151 break; 2152 2153 case 1: /* Vendor */ 2154 str_ptr = sc->sc_vendor; 2155 break; 2156 2157 case 2: /* Product */ 2158 str_ptr = "OHCI root HUB"; 2159 break; 2160 2161 default: 2162 str_ptr = ""; 2163 break; 2164 } 2165 2166 len = usb_make_str_desc( 2167 sc->sc_hub_desc.temp, 2168 sizeof(sc->sc_hub_desc.temp), 2169 str_ptr); 2170 break; 2171 2172 default: 2173 err = USB_ERR_IOERROR; 2174 goto done; 2175 } 2176 break; 2177 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2178 len = 1; 2179 sc->sc_hub_desc.temp[0] = 0; 2180 break; 2181 case C(UR_GET_STATUS, UT_READ_DEVICE): 2182 len = 2; 2183 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2184 break; 2185 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2186 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2187 len = 2; 2188 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2189 break; 2190 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2191 if (value >= OHCI_MAX_DEVICES) { 2192 err = USB_ERR_IOERROR; 2193 goto done; 2194 } 2195 sc->sc_addr = value; 2196 break; 2197 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2198 if ((value != 0) && (value != 1)) { 2199 err = USB_ERR_IOERROR; 2200 goto done; 2201 } 2202 sc->sc_conf = value; 2203 break; 2204 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2205 break; 2206 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2207 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2208 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2209 err = USB_ERR_IOERROR; 2210 goto done; 2211 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2212 break; 2213 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2214 break; 2215 /* Hub requests */ 2216 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2217 break; 2218 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2219 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2220 "port=%d feature=%d\n", 2221 index, value); 2222 if ((index < 1) || 2223 (index > sc->sc_noport)) { 2224 err = USB_ERR_IOERROR; 2225 goto done; 2226 } 2227 port = OHCI_RH_PORT_STATUS(index); 2228 switch (value) { 2229 case UHF_PORT_ENABLE: 2230 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2231 break; 2232 case UHF_PORT_SUSPEND: 2233 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2234 break; 2235 case UHF_PORT_POWER: 2236 /* Yes, writing to the LOW_SPEED bit clears power. */ 2237 OWRITE4(sc, port, UPS_LOW_SPEED); 2238 break; 2239 case UHF_C_PORT_CONNECTION: 2240 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2241 break; 2242 case UHF_C_PORT_ENABLE: 2243 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2244 break; 2245 case UHF_C_PORT_SUSPEND: 2246 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2247 break; 2248 case UHF_C_PORT_OVER_CURRENT: 2249 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2250 break; 2251 case UHF_C_PORT_RESET: 2252 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2253 break; 2254 default: 2255 err = USB_ERR_IOERROR; 2256 goto done; 2257 } 2258 switch (value) { 2259 case UHF_C_PORT_CONNECTION: 2260 case UHF_C_PORT_ENABLE: 2261 case UHF_C_PORT_SUSPEND: 2262 case UHF_C_PORT_OVER_CURRENT: 2263 case UHF_C_PORT_RESET: 2264 /* enable RHSC interrupt if condition is cleared. */ 2265 if ((OREAD4(sc, port) >> 16) == 0) 2266 ohci_rhsc_enable(sc); 2267 break; 2268 default: 2269 break; 2270 } 2271 break; 2272 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2273 if ((value & 0xff) != 0) { 2274 err = USB_ERR_IOERROR; 2275 goto done; 2276 } 2277 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2278 2279 sc->sc_hub_desc.hubd = ohci_hubd; 2280 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2281 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2282 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2283 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2284 /* XXX overcurrent */ 2285 ); 2286 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2287 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2288 2289 for (l = 0; l < sc->sc_noport; l++) { 2290 if (v & 1) { 2291 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2292 } 2293 v >>= 1; 2294 } 2295 sc->sc_hub_desc.hubd.bDescLength = 2296 8 + ((sc->sc_noport + 7) / 8); 2297 len = sc->sc_hub_desc.hubd.bDescLength; 2298 break; 2299 2300 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2301 len = 16; 2302 memset(sc->sc_hub_desc.temp, 0, 16); 2303 break; 2304 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2305 DPRINTFN(9, "get port status i=%d\n", 2306 index); 2307 if ((index < 1) || 2308 (index > sc->sc_noport)) { 2309 err = USB_ERR_IOERROR; 2310 goto done; 2311 } 2312 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2313 DPRINTFN(9, "port status=0x%04x\n", v); 2314 v &= ~UPS_PORT_MODE_DEVICE; /* force host mode */ 2315 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2316 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2317 len = sizeof(sc->sc_hub_desc.ps); 2318 break; 2319 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2320 err = USB_ERR_IOERROR; 2321 goto done; 2322 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2323 break; 2324 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2325 if ((index < 1) || 2326 (index > sc->sc_noport)) { 2327 err = USB_ERR_IOERROR; 2328 goto done; 2329 } 2330 port = OHCI_RH_PORT_STATUS(index); 2331 switch (value) { 2332 case UHF_PORT_ENABLE: 2333 OWRITE4(sc, port, UPS_PORT_ENABLED); 2334 break; 2335 case UHF_PORT_SUSPEND: 2336 OWRITE4(sc, port, UPS_SUSPEND); 2337 break; 2338 case UHF_PORT_RESET: 2339 DPRINTFN(6, "reset port %d\n", index); 2340 OWRITE4(sc, port, UPS_RESET); 2341 for (v = 0;; v++) { 2342 if (v < 12) { 2343 usb_pause_mtx(&sc->sc_bus.bus_lock, 2344 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 2345 2346 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2347 break; 2348 } 2349 } else { 2350 err = USB_ERR_TIMEOUT; 2351 goto done; 2352 } 2353 } 2354 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2355 index, OREAD4(sc, port)); 2356 break; 2357 case UHF_PORT_POWER: 2358 DPRINTFN(3, "set port power %d\n", index); 2359 OWRITE4(sc, port, UPS_PORT_POWER); 2360 break; 2361 default: 2362 err = USB_ERR_IOERROR; 2363 goto done; 2364 } 2365 break; 2366 default: 2367 err = USB_ERR_IOERROR; 2368 goto done; 2369 } 2370 done: 2371 *plength = len; 2372 *pptr = ptr; 2373 return (err); 2374 } 2375 2376 static void 2377 ohci_xfer_setup(struct usb_setup_params *parm) 2378 { 2379 struct usb_page_search page_info; 2380 struct usb_page_cache *pc; 2381 ohci_softc_t *sc; 2382 struct usb_xfer *xfer; 2383 void *last_obj; 2384 uint32_t ntd; 2385 uint32_t nitd; 2386 uint32_t nqh; 2387 uint32_t n; 2388 2389 sc = OHCI_BUS2SC(parm->udev->bus); 2390 xfer = parm->curr_xfer; 2391 2392 parm->hc_max_packet_size = 0x500; 2393 parm->hc_max_packet_count = 1; 2394 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2395 2396 /* 2397 * calculate ntd and nqh 2398 */ 2399 if (parm->methods == &ohci_device_ctrl_methods) { 2400 xfer->flags_int.bdma_enable = 1; 2401 2402 usbd_transfer_setup_sub(parm); 2403 2404 nitd = 0; 2405 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2406 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2407 nqh = 1; 2408 2409 } else if (parm->methods == &ohci_device_bulk_methods) { 2410 xfer->flags_int.bdma_enable = 1; 2411 2412 usbd_transfer_setup_sub(parm); 2413 2414 nitd = 0; 2415 ntd = ((2 * xfer->nframes) 2416 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2417 nqh = 1; 2418 2419 } else if (parm->methods == &ohci_device_intr_methods) { 2420 xfer->flags_int.bdma_enable = 1; 2421 2422 usbd_transfer_setup_sub(parm); 2423 2424 nitd = 0; 2425 ntd = ((2 * xfer->nframes) 2426 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2427 nqh = 1; 2428 2429 } else if (parm->methods == &ohci_device_isoc_methods) { 2430 xfer->flags_int.bdma_enable = 1; 2431 2432 usbd_transfer_setup_sub(parm); 2433 2434 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2435 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2436 1 /* EXTRA */ ); 2437 ntd = 0; 2438 nqh = 1; 2439 2440 } else { 2441 2442 usbd_transfer_setup_sub(parm); 2443 2444 nitd = 0; 2445 ntd = 0; 2446 nqh = 0; 2447 } 2448 2449 alloc_dma_set: 2450 2451 if (parm->err) { 2452 return; 2453 } 2454 last_obj = NULL; 2455 2456 if (usbd_transfer_setup_sub_malloc( 2457 parm, &pc, sizeof(ohci_td_t), 2458 OHCI_TD_ALIGN, ntd)) { 2459 parm->err = USB_ERR_NOMEM; 2460 return; 2461 } 2462 if (parm->buf) { 2463 for (n = 0; n != ntd; n++) { 2464 ohci_td_t *td; 2465 2466 usbd_get_page(pc + n, 0, &page_info); 2467 2468 td = page_info.buffer; 2469 2470 /* init TD */ 2471 td->td_self = htole32(page_info.physaddr); 2472 td->obj_next = last_obj; 2473 td->page_cache = pc + n; 2474 2475 last_obj = td; 2476 2477 usb_pc_cpu_flush(pc + n); 2478 } 2479 } 2480 if (usbd_transfer_setup_sub_malloc( 2481 parm, &pc, sizeof(ohci_itd_t), 2482 OHCI_ITD_ALIGN, nitd)) { 2483 parm->err = USB_ERR_NOMEM; 2484 return; 2485 } 2486 if (parm->buf) { 2487 for (n = 0; n != nitd; n++) { 2488 ohci_itd_t *itd; 2489 2490 usbd_get_page(pc + n, 0, &page_info); 2491 2492 itd = page_info.buffer; 2493 2494 /* init TD */ 2495 itd->itd_self = htole32(page_info.physaddr); 2496 itd->obj_next = last_obj; 2497 itd->page_cache = pc + n; 2498 2499 last_obj = itd; 2500 2501 usb_pc_cpu_flush(pc + n); 2502 } 2503 } 2504 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2505 2506 last_obj = NULL; 2507 2508 if (usbd_transfer_setup_sub_malloc( 2509 parm, &pc, sizeof(ohci_ed_t), 2510 OHCI_ED_ALIGN, nqh)) { 2511 parm->err = USB_ERR_NOMEM; 2512 return; 2513 } 2514 if (parm->buf) { 2515 for (n = 0; n != nqh; n++) { 2516 ohci_ed_t *ed; 2517 2518 usbd_get_page(pc + n, 0, &page_info); 2519 2520 ed = page_info.buffer; 2521 2522 /* init QH */ 2523 ed->ed_self = htole32(page_info.physaddr); 2524 ed->obj_next = last_obj; 2525 ed->page_cache = pc + n; 2526 2527 last_obj = ed; 2528 2529 usb_pc_cpu_flush(pc + n); 2530 } 2531 } 2532 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2533 2534 if (!xfer->flags_int.curr_dma_set) { 2535 xfer->flags_int.curr_dma_set = 1; 2536 goto alloc_dma_set; 2537 } 2538 } 2539 2540 static void 2541 ohci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2542 struct usb_endpoint *ep) 2543 { 2544 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2545 2546 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2547 ep, udev->address, 2548 edesc->bEndpointAddress, udev->flags.usb_mode, 2549 sc->sc_addr); 2550 2551 if (udev->device_index != sc->sc_addr) { 2552 switch (edesc->bmAttributes & UE_XFERTYPE) { 2553 case UE_CONTROL: 2554 ep->methods = &ohci_device_ctrl_methods; 2555 break; 2556 case UE_INTERRUPT: 2557 ep->methods = &ohci_device_intr_methods; 2558 break; 2559 case UE_ISOCHRONOUS: 2560 if (udev->speed == USB_SPEED_FULL) { 2561 ep->methods = &ohci_device_isoc_methods; 2562 } 2563 break; 2564 case UE_BULK: 2565 ep->methods = &ohci_device_bulk_methods; 2566 break; 2567 default: 2568 /* do nothing */ 2569 break; 2570 } 2571 } 2572 } 2573 2574 static void 2575 ohci_xfer_unsetup(struct usb_xfer *xfer) 2576 { 2577 return; 2578 } 2579 2580 static void 2581 ohci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 2582 { 2583 /* 2584 * Wait until hardware has finished any possible use of the 2585 * transfer descriptor(s) and QH 2586 */ 2587 *pus = (1125); /* microseconds */ 2588 } 2589 2590 static void 2591 ohci_device_resume(struct usb_device *udev) 2592 { 2593 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2594 struct usb_xfer *xfer; 2595 const struct usb_pipe_methods *methods; 2596 ohci_ed_t *ed; 2597 2598 DPRINTF("\n"); 2599 2600 USB_BUS_LOCK(udev->bus); 2601 2602 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2603 2604 if (xfer->xroot->udev == udev) { 2605 2606 methods = xfer->endpoint->methods; 2607 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2608 2609 if (methods == &ohci_device_bulk_methods) { 2610 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2611 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2612 } 2613 if (methods == &ohci_device_ctrl_methods) { 2614 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2615 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2616 } 2617 if (methods == &ohci_device_intr_methods) { 2618 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2619 } 2620 } 2621 } 2622 2623 USB_BUS_UNLOCK(udev->bus); 2624 2625 return; 2626 } 2627 2628 static void 2629 ohci_device_suspend(struct usb_device *udev) 2630 { 2631 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2632 struct usb_xfer *xfer; 2633 const struct usb_pipe_methods *methods; 2634 ohci_ed_t *ed; 2635 2636 DPRINTF("\n"); 2637 2638 USB_BUS_LOCK(udev->bus); 2639 2640 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2641 2642 if (xfer->xroot->udev == udev) { 2643 2644 methods = xfer->endpoint->methods; 2645 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2646 2647 if (methods == &ohci_device_bulk_methods) { 2648 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2649 } 2650 if (methods == &ohci_device_ctrl_methods) { 2651 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2652 } 2653 if (methods == &ohci_device_intr_methods) { 2654 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2655 } 2656 } 2657 } 2658 2659 USB_BUS_UNLOCK(udev->bus); 2660 2661 return; 2662 } 2663 2664 static void 2665 ohci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2666 { 2667 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2668 2669 switch (state) { 2670 case USB_HW_POWER_SUSPEND: 2671 case USB_HW_POWER_SHUTDOWN: 2672 ohci_suspend(sc); 2673 break; 2674 case USB_HW_POWER_RESUME: 2675 ohci_resume(sc); 2676 break; 2677 default: 2678 break; 2679 } 2680 } 2681 2682 static void 2683 ohci_set_hw_power(struct usb_bus *bus) 2684 { 2685 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2686 uint32_t temp; 2687 uint32_t flags; 2688 2689 DPRINTF("\n"); 2690 2691 USB_BUS_LOCK(bus); 2692 2693 flags = bus->hw_power_state; 2694 2695 temp = OREAD4(sc, OHCI_CONTROL); 2696 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2697 2698 if (flags & USB_HW_POWER_CONTROL) 2699 temp |= OHCI_CLE; 2700 2701 if (flags & USB_HW_POWER_BULK) 2702 temp |= OHCI_BLE; 2703 2704 if (flags & USB_HW_POWER_INTERRUPT) 2705 temp |= OHCI_PLE; 2706 2707 if (flags & USB_HW_POWER_ISOC) 2708 temp |= OHCI_IE | OHCI_PLE; 2709 2710 OWRITE4(sc, OHCI_CONTROL, temp); 2711 2712 USB_BUS_UNLOCK(bus); 2713 2714 return; 2715 } 2716 2717 static const struct usb_bus_methods ohci_bus_methods = 2718 { 2719 .endpoint_init = ohci_ep_init, 2720 .xfer_setup = ohci_xfer_setup, 2721 .xfer_unsetup = ohci_xfer_unsetup, 2722 .get_dma_delay = ohci_get_dma_delay, 2723 .device_resume = ohci_device_resume, 2724 .device_suspend = ohci_device_suspend, 2725 .set_hw_power = ohci_set_hw_power, 2726 .set_hw_power_sleep = ohci_set_hw_power_sleep, 2727 .roothub_exec = ohci_roothub_exec, 2728 .xfer_poll = ohci_do_poll, 2729 }; 2730