xref: /dragonfly/sys/bus/u4b/controller/ohci_pci.c (revision 57bed822)
1 /*-
2  * Copyright (c) 1998 The NetBSD Foundation, Inc.
3  * All rights reserved.
4  *
5  * This code is derived from software contributed to The NetBSD Foundation
6  * by Lennart Augustsson (augustss@carlstedt.se) at
7  * Carlstedt Research & Technology.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  * POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 /*
32  * USB Open Host Controller driver.
33  *
34  * OHCI spec: http://www.intel.com/design/usb/ohci11d.pdf
35  */
36 
37 /* The low level controller code for OHCI has been split into
38  * PCI probes and OHCI specific code. This was done to facilitate the
39  * sharing of code between *BSD's
40  */
41 
42 #include <sys/stdint.h>
43 #include <sys/param.h>
44 #include <sys/queue.h>
45 #include <sys/types.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/bus.h>
49 #include <sys/module.h>
50 #include <sys/lock.h>
51 #include <sys/condvar.h>
52 #include <sys/sysctl.h>
53 #include <sys/unistd.h>
54 #include <sys/callout.h>
55 #include <sys/malloc.h>
56 #include <sys/priv.h>
57 
58 #include <bus/u4b/usb.h>
59 #include <bus/u4b/usbdi.h>
60 
61 #include <bus/u4b/usb_core.h>
62 #include <bus/u4b/usb_busdma.h>
63 #include <bus/u4b/usb_process.h>
64 #include <bus/u4b/usb_util.h>
65 
66 #include <bus/u4b/usb_controller.h>
67 #include <bus/u4b/usb_bus.h>
68 #include <bus/u4b/usb_pci.h>
69 #include <bus/u4b/controller/ohci.h>
70 #include <bus/u4b/controller/ohcireg.h>
71 #include "usb_if.h"
72 
73 #define	PCI_OHCI_VENDORID_ACERLABS	0x10b9
74 #define	PCI_OHCI_VENDORID_AMD		0x1022
75 #define	PCI_OHCI_VENDORID_APPLE		0x106b
76 #define	PCI_OHCI_VENDORID_ATI		0x1002
77 #define	PCI_OHCI_VENDORID_CMDTECH	0x1095
78 #define	PCI_OHCI_VENDORID_NEC		0x1033
79 #define	PCI_OHCI_VENDORID_NVIDIA	0x12D2
80 #define	PCI_OHCI_VENDORID_NVIDIA2	0x10DE
81 #define	PCI_OHCI_VENDORID_OPTI		0x1045
82 #define	PCI_OHCI_VENDORID_SIS		0x1039
83 #define	PCI_OHCI_VENDORID_SUN		0x108e
84 
85 #define	PCI_OHCI_BASE_REG	0x10
86 
87 static device_probe_t ohci_pci_probe;
88 static device_attach_t ohci_pci_attach;
89 static device_detach_t ohci_pci_detach;
90 static usb_take_controller_t ohci_pci_take_controller;
91 
92 static int
93 ohci_pci_take_controller(device_t self)
94 {
95 	uint32_t reg;
96 	uint32_t int_line;
97 
98 	if (pci_get_powerstate(self) != PCI_POWERSTATE_D0) {
99 		device_printf(self, "chip is in D%d mode "
100 		    "-- setting to D0\n", pci_get_powerstate(self));
101 		reg = pci_read_config(self, PCI_CBMEM, 4);
102 		int_line = pci_read_config(self, PCIR_INTLINE, 4);
103 		pci_set_powerstate(self, PCI_POWERSTATE_D0);
104 		pci_write_config(self, PCI_CBMEM, reg, 4);
105 		pci_write_config(self, PCIR_INTLINE, int_line, 4);
106 	}
107 	return (0);
108 }
109 
110 static const char *
111 ohci_pci_match(device_t self)
112 {
113 	uint32_t device_id = pci_get_devid(self);
114 
115 	switch (device_id) {
116 	case 0x523710b9:
117 		return ("AcerLabs M5237 (Aladdin-V) USB controller");
118 
119 	case 0x740c1022:
120 		return ("AMD-756 USB Controller");
121 
122 	case 0x74141022:
123 		return ("AMD-766 USB Controller");
124 
125 	case 0x43741002:
126 		return "ATI SB400 USB Controller";
127 	case 0x43751002:
128 		return "ATI SB400 USB Controller";
129 	case 0x43971002:
130 		return ("AMD SB7x0/SB8x0/SB9x0 USB controller");
131 	case 0x43981002:
132 		return ("AMD SB7x0/SB8x0/SB9x0 USB controller");
133 	case 0x43991002:
134 		return ("AMD SB7x0/SB8x0/SB9x0 USB controller");
135 
136 	case 0x06701095:
137 		return ("CMD Tech 670 (USB0670) USB controller");
138 
139 	case 0x06731095:
140 		return ("CMD Tech 673 (USB0673) USB controller");
141 
142 	case 0xc8611045:
143 		return ("OPTi 82C861 (FireLink) USB controller");
144 
145 	case 0x00351033:
146 		return ("NEC uPD 9210 USB controller");
147 
148 	case 0x00d710de:
149 		return ("nVidia nForce3 USB Controller");
150 
151 	case 0x036c10de:
152 		return ("nVidia nForce MCP55 USB Controller");
153 	case 0x03f110de:
154 		return ("nVidia nForce MCP61 USB Controller");
155 	case 0x0aa510de:
156 		return ("nVidia nForce MCP79 USB Controller");
157 	case 0x0aa710de:
158 		return ("nVidia nForce MCP79 USB Controller");
159 	case 0x0aa810de:
160 		return ("nVidia nForce MCP79 USB Controller");
161 
162 	case 0x70011039:
163 		return ("SiS 5571 USB controller");
164 
165 	case 0x1103108e:
166 		return "Sun PCIO-2 USB controller";
167 
168 	case 0x0019106b:
169 		return ("Apple KeyLargo USB controller");
170 
171 	default:
172 		break;
173 	}
174 	if ((pci_get_class(self) == PCIC_SERIALBUS) &&
175 	    (pci_get_subclass(self) == PCIS_SERIALBUS_USB) &&
176 	    (pci_get_progif(self) == PCI_INTERFACE_OHCI)) {
177 		return ("OHCI (generic) USB controller");
178 	}
179 	return (NULL);
180 }
181 
182 static int
183 ohci_pci_probe(device_t self)
184 {
185 	const char *desc = ohci_pci_match(self);
186 
187 	if (desc) {
188 		device_set_desc(self, desc);
189 		return (0);
190 	} else {
191 		return (ENXIO);
192 	}
193 }
194 
195 static int
196 ohci_pci_attach(device_t self)
197 {
198 	ohci_softc_t *sc = device_get_softc(self);
199 	int rid;
200 	int err;
201 
202 	/* initialise some bus fields */
203 	sc->sc_bus.parent = self;
204 	sc->sc_bus.devices = sc->sc_devices;
205 	sc->sc_bus.devices_max = OHCI_MAX_DEVICES;
206 
207 	/* get all DMA memory */
208 	if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(self),
209 	    &ohci_iterate_hw_softc)) {
210 		return (ENOMEM);
211 	}
212 	sc->sc_dev = self;
213 
214 	pci_enable_busmaster(self);
215 
216 	/*
217 	 * Some Sun PCIO-2 USB controllers have their intpin register
218 	 * bogusly set to 0, although it should be 4.  Correct that.
219 	 */
220 	if (pci_get_devid(self) == 0x1103108e && pci_get_intpin(self) == 0)
221 		pci_set_intpin(self, 4);
222 
223 	rid = PCI_CBMEM;
224 	sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
225 	    RF_ACTIVE);
226 	if (!sc->sc_io_res) {
227 		device_printf(self, "Could not map memory\n");
228 		goto error;
229 	}
230 	sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
231 	sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
232 	sc->sc_io_size = rman_get_size(sc->sc_io_res);
233 
234 	rid = 0;
235 	sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
236 	    RF_SHAREABLE | RF_ACTIVE);
237 	if (sc->sc_irq_res == NULL) {
238 		device_printf(self, "Could not allocate irq\n");
239 		goto error;
240 	}
241 	sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
242 	if (!sc->sc_bus.bdev) {
243 		device_printf(self, "Could not add USB device\n");
244 		goto error;
245 	}
246 	device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
247 
248 	/*
249 	 * ohci_pci_match will never return NULL if ohci_pci_probe
250 	 * succeeded
251 	 */
252 	device_set_desc(sc->sc_bus.bdev, ohci_pci_match(self));
253 	switch (pci_get_vendor(self)) {
254 	case PCI_OHCI_VENDORID_ACERLABS:
255 		ksprintf(sc->sc_vendor, "AcerLabs");
256 		break;
257 	case PCI_OHCI_VENDORID_AMD:
258 		ksprintf(sc->sc_vendor, "AMD");
259 		break;
260 	case PCI_OHCI_VENDORID_APPLE:
261 		ksprintf(sc->sc_vendor, "Apple");
262 		break;
263 	case PCI_OHCI_VENDORID_ATI:
264 		ksprintf(sc->sc_vendor, "ATI");
265 		break;
266 	case PCI_OHCI_VENDORID_CMDTECH:
267 		ksprintf(sc->sc_vendor, "CMDTECH");
268 		break;
269 	case PCI_OHCI_VENDORID_NEC:
270 		ksprintf(sc->sc_vendor, "NEC");
271 		break;
272 	case PCI_OHCI_VENDORID_NVIDIA:
273 	case PCI_OHCI_VENDORID_NVIDIA2:
274 		ksprintf(sc->sc_vendor, "nVidia");
275 		break;
276 	case PCI_OHCI_VENDORID_OPTI:
277 		ksprintf(sc->sc_vendor, "OPTi");
278 		break;
279 	case PCI_OHCI_VENDORID_SIS:
280 		ksprintf(sc->sc_vendor, "SiS");
281 		break;
282 	case PCI_OHCI_VENDORID_SUN:
283 		ksprintf(sc->sc_vendor, "SUN");
284 		break;
285 	default:
286 		if (bootverbose) {
287 			device_printf(self, "(New OHCI DeviceId=0x%08x)\n",
288 			    pci_get_devid(self));
289 		}
290 		ksprintf(sc->sc_vendor, "(0x%04x)", pci_get_vendor(self));
291 	}
292 
293 	/* sc->sc_bus.usbrev; set by ohci_init() */
294 
295 	err = bus_setup_intr(self, sc->sc_irq_res, INTR_MPSAFE,
296 	    (driver_intr_t *)ohci_interrupt, sc, &sc->sc_intr_hdl, NULL);
297 	if (err) {
298 		device_printf(self, "Could not setup irq, %d\n", err);
299 		sc->sc_intr_hdl = NULL;
300 		goto error;
301 	}
302 	err = ohci_init(sc);
303 	if (!err) {
304 		err = device_probe_and_attach(sc->sc_bus.bdev);
305 	}
306 	if (err) {
307 		device_printf(self, "USB init failed\n");
308 		goto error;
309 	}
310 	return (0);
311 
312 error:
313 	ohci_pci_detach(self);
314 	return (ENXIO);
315 }
316 
317 static int
318 ohci_pci_detach(device_t self)
319 {
320 	ohci_softc_t *sc = device_get_softc(self);
321 	device_t bdev;
322 
323 	if (sc->sc_bus.bdev) {
324 		bdev = sc->sc_bus.bdev;
325 		device_detach(bdev);
326 		device_delete_child(self, bdev);
327 	}
328  	/* during module unload there are lots of children leftover */
329 	device_delete_children(self);
330 
331 	pci_disable_busmaster(self);
332 
333 	if (sc->sc_irq_res && sc->sc_intr_hdl) {
334 		/*
335 		 * only call ohci_detach() after ohci_init()
336 		 */
337 		ohci_detach(sc);
338 
339 		int err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
340 
341 		if (err) {
342 			/* XXX or should we panic? */
343 			device_printf(self, "Could not tear down irq, %d\n",
344 			    err);
345 		}
346 		sc->sc_intr_hdl = NULL;
347 	}
348 	if (sc->sc_irq_res) {
349 		bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
350 		sc->sc_irq_res = NULL;
351 	}
352 	if (sc->sc_io_res) {
353 		bus_release_resource(self, SYS_RES_MEMORY, PCI_CBMEM,
354 		    sc->sc_io_res);
355 		sc->sc_io_res = NULL;
356 	}
357 	usb_bus_mem_free_all(&sc->sc_bus, &ohci_iterate_hw_softc);
358 
359 	return (0);
360 }
361 
362 static device_method_t ohci_pci_methods[] = {
363 	/* Device interface */
364 	DEVMETHOD(device_probe, ohci_pci_probe),
365 	DEVMETHOD(device_attach, ohci_pci_attach),
366 	DEVMETHOD(device_detach, ohci_pci_detach),
367 	DEVMETHOD(device_suspend, bus_generic_suspend),
368 	DEVMETHOD(device_resume, bus_generic_resume),
369 	DEVMETHOD(device_shutdown, bus_generic_shutdown),
370 	DEVMETHOD(usb_take_controller, ohci_pci_take_controller),
371 
372 	DEVMETHOD_END
373 };
374 
375 static driver_t ohci_driver = {
376 	.name = "ohci",
377 	.methods = ohci_pci_methods,
378 	.size = sizeof(struct ohci_softc),
379 };
380 
381 static devclass_t ohci_devclass;
382 
383 DRIVER_MODULE(ohci, pci, ohci_driver, ohci_devclass, NULL, NULL);
384 MODULE_DEPEND(ohci, usb, 1, 1, 1);
385