1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * USB Universal Host Controller driver. 30 * Handles e.g. PIIX3 and PIIX4. 31 * 32 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 33 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 34 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 35 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 36 */ 37 38 #include <sys/stdint.h> 39 #include <sys/param.h> 40 #include <sys/queue.h> 41 #include <sys/types.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/bus.h> 45 #include <sys/module.h> 46 #include <sys/lock.h> 47 #include <sys/condvar.h> 48 #include <sys/sysctl.h> 49 #include <sys/unistd.h> 50 #include <sys/callout.h> 51 #include <sys/malloc.h> 52 #include <sys/priv.h> 53 54 #include <bus/u4b/usb.h> 55 #include <bus/u4b/usbdi.h> 56 57 #define USB_DEBUG_VAR uhcidebug 58 59 #include <bus/u4b/usb_core.h> 60 #include <bus/u4b/usb_debug.h> 61 #include <bus/u4b/usb_busdma.h> 62 #include <bus/u4b/usb_process.h> 63 #include <bus/u4b/usb_transfer.h> 64 #include <bus/u4b/usb_device.h> 65 #include <bus/u4b/usb_hub.h> 66 #include <bus/u4b/usb_util.h> 67 68 #include <bus/u4b/usb_controller.h> 69 #include <bus/u4b/usb_bus.h> 70 #include <bus/u4b/controller/uhci.h> 71 #include <bus/u4b/controller/uhcireg.h> 72 73 #define alt_next next 74 #define UHCI_BUS2SC(bus) \ 75 ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 76 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus)))) 77 78 #ifdef USB_DEBUG 79 static int uhcidebug = 0; 80 static int uhcinoloop = 0; 81 82 static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 83 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RW, 84 &uhcidebug, 0, "uhci debug level"); 85 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RW, 86 &uhcinoloop, 0, "uhci noloop"); 87 88 TUNABLE_INT("hw.usb.uhci.debug", &uhcidebug); 89 TUNABLE_INT("hw.usb.uhci.loop", &uhcinoloop); 90 91 static void uhci_dumpregs(uhci_softc_t *sc); 92 static void uhci_dump_tds(uhci_td_t *td); 93 94 #endif 95 96 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 97 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 98 #define UWRITE1(sc, r, x) \ 99 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 100 } while (/*CONSTCOND*/0) 101 #define UWRITE2(sc, r, x) \ 102 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 103 } while (/*CONSTCOND*/0) 104 #define UWRITE4(sc, r, x) \ 105 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 106 } while (/*CONSTCOND*/0) 107 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 108 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 109 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 110 111 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 112 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 113 114 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 115 116 #define UHCI_INTR_ENDPT 1 117 118 struct uhci_mem_layout { 119 120 struct usb_page_search buf_res; 121 struct usb_page_search fix_res; 122 123 struct usb_page_cache *buf_pc; 124 struct usb_page_cache *fix_pc; 125 126 uint32_t buf_offset; 127 128 uint16_t max_frame_size; 129 }; 130 131 struct uhci_std_temp { 132 133 struct uhci_mem_layout ml; 134 uhci_td_t *td; 135 uhci_td_t *td_next; 136 uint32_t average; 137 uint32_t td_status; 138 uint32_t td_token; 139 uint32_t len; 140 uint16_t max_frame_size; 141 uint8_t shortpkt; 142 uint8_t setup_alt_next; 143 uint8_t last_frame; 144 }; 145 146 static const struct usb_bus_methods uhci_bus_methods; 147 static const struct usb_pipe_methods uhci_device_bulk_methods; 148 static const struct usb_pipe_methods uhci_device_ctrl_methods; 149 static const struct usb_pipe_methods uhci_device_intr_methods; 150 static const struct usb_pipe_methods uhci_device_isoc_methods; 151 152 static uint8_t uhci_restart(uhci_softc_t *sc); 153 static void uhci_do_poll(struct usb_bus *); 154 static void uhci_device_done(struct usb_xfer *, usb_error_t); 155 static void uhci_transfer_intr_enqueue(struct usb_xfer *); 156 static void uhci_timeout(void *); 157 static uint8_t uhci_check_transfer(struct usb_xfer *); 158 static void uhci_root_intr(uhci_softc_t *sc); 159 160 void 161 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 162 { 163 struct uhci_softc *sc = UHCI_BUS2SC(bus); 164 uint32_t i; 165 166 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 167 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 168 169 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 170 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 171 172 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 173 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 174 175 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 176 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 177 178 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 179 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 180 181 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 182 sizeof(uhci_td_t), UHCI_TD_ALIGN); 183 184 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 185 cb(bus, sc->sc_hw.isoc_start_pc + i, 186 sc->sc_hw.isoc_start_pg + i, 187 sizeof(uhci_td_t), UHCI_TD_ALIGN); 188 } 189 190 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 191 cb(bus, sc->sc_hw.intr_start_pc + i, 192 sc->sc_hw.intr_start_pg + i, 193 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 194 } 195 } 196 197 static void 198 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer) 199 { 200 ml->buf_pc = xfer->frbuffers + 0; 201 ml->fix_pc = xfer->buf_fixup; 202 203 ml->buf_offset = 0; 204 205 ml->max_frame_size = xfer->max_frame_size; 206 } 207 208 static void 209 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 210 { 211 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 212 213 if (ml->buf_res.length < td->len) { 214 215 /* need to do a fixup */ 216 217 usbd_get_page(ml->fix_pc, 0, &ml->fix_res); 218 219 td->td_buffer = htole32(ml->fix_res.physaddr); 220 221 /* 222 * The UHCI driver cannot handle 223 * page crossings, so a fixup is 224 * needed: 225 * 226 * +----+----+ - - - 227 * | YYY|Y | 228 * +----+----+ - - - 229 * \ \ 230 * \ \ 231 * +----+ 232 * |YYYY| (fixup) 233 * +----+ 234 */ 235 236 if ((td->td_token & htole32(UHCI_TD_PID)) == 237 htole32(UHCI_TD_PID_IN)) { 238 td->fix_pc = ml->fix_pc; 239 usb_pc_cpu_invalidate(ml->fix_pc); 240 241 } else { 242 td->fix_pc = NULL; 243 244 /* copy data to fixup location */ 245 246 usbd_copy_out(ml->buf_pc, ml->buf_offset, 247 ml->fix_res.buffer, td->len); 248 249 usb_pc_cpu_flush(ml->fix_pc); 250 } 251 252 /* prepare next fixup */ 253 254 ml->fix_pc++; 255 256 } else { 257 258 td->td_buffer = htole32(ml->buf_res.physaddr); 259 td->fix_pc = NULL; 260 } 261 262 /* prepare next data location */ 263 264 ml->buf_offset += td->len; 265 } 266 267 /* 268 * Return values: 269 * 0: Success 270 * Else: Failure 271 */ 272 static uint8_t 273 uhci_restart(uhci_softc_t *sc) 274 { 275 struct usb_page_search buf_res; 276 277 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 278 279 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) { 280 DPRINTFN(2, "Already started\n"); 281 return (0); 282 } 283 284 DPRINTFN(2, "Restarting\n"); 285 286 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 287 288 /* Reload fresh base address */ 289 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 290 291 /* 292 * Assume 64 byte packets at frame end and start HC controller: 293 */ 294 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 295 296 /* wait 10 milliseconds */ 297 298 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 100); 299 300 /* check that controller has started */ 301 302 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 303 DPRINTFN(2, "Failed\n"); 304 return (1); 305 } 306 return (0); 307 } 308 309 void 310 uhci_reset(uhci_softc_t *sc) 311 { 312 uint16_t n; 313 314 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 315 316 DPRINTF("resetting the HC\n"); 317 318 /* disable interrupts */ 319 320 UWRITE2(sc, UHCI_INTR, 0); 321 322 /* global reset */ 323 324 UHCICMD(sc, UHCI_CMD_GRESET); 325 326 /* wait */ 327 328 usb_pause_mtx(&sc->sc_bus.bus_lock, 329 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 330 331 /* terminate all transfers */ 332 333 UHCICMD(sc, UHCI_CMD_HCRESET); 334 335 /* the reset bit goes low when the controller is done */ 336 337 n = UHCI_RESET_TIMEOUT; 338 while (n--) { 339 /* wait one millisecond */ 340 341 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 1000); 342 343 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 344 goto done_1; 345 } 346 } 347 348 device_printf(sc->sc_bus.bdev, 349 "controller did not reset\n"); 350 351 done_1: 352 353 n = 10; 354 while (n--) { 355 /* wait one millisecond */ 356 357 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 1000); 358 359 /* check if HC is stopped */ 360 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 361 goto done_2; 362 } 363 } 364 365 device_printf(sc->sc_bus.bdev, 366 "controller did not stop\n"); 367 368 done_2: 369 370 /* reset frame number */ 371 UWRITE2(sc, UHCI_FRNUM, 0); 372 /* set default SOF value */ 373 UWRITE1(sc, UHCI_SOF, 0x40); 374 375 USB_BUS_UNLOCK(&sc->sc_bus); 376 377 /* stop root interrupt */ 378 usb_callout_drain(&sc->sc_root_intr); 379 380 USB_BUS_LOCK(&sc->sc_bus); 381 } 382 383 static void 384 uhci_start(uhci_softc_t *sc) 385 { 386 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 387 388 DPRINTFN(2, "enabling\n"); 389 390 /* enable interrupts */ 391 392 UWRITE2(sc, UHCI_INTR, 393 (UHCI_INTR_TOCRCIE | 394 UHCI_INTR_RIE | 395 UHCI_INTR_IOCE | 396 UHCI_INTR_SPIE)); 397 398 if (uhci_restart(sc)) { 399 device_printf(sc->sc_bus.bdev, 400 "cannot start HC controller\n"); 401 } 402 403 /* start root interrupt */ 404 uhci_root_intr(sc); 405 } 406 407 static struct uhci_qh * 408 uhci_init_qh(struct usb_page_cache *pc) 409 { 410 struct usb_page_search buf_res; 411 struct uhci_qh *qh; 412 413 usbd_get_page(pc, 0, &buf_res); 414 415 qh = buf_res.buffer; 416 417 qh->qh_self = 418 htole32(buf_res.physaddr) | 419 htole32(UHCI_PTR_QH); 420 421 qh->page_cache = pc; 422 423 return (qh); 424 } 425 426 static struct uhci_td * 427 uhci_init_td(struct usb_page_cache *pc) 428 { 429 struct usb_page_search buf_res; 430 struct uhci_td *td; 431 432 usbd_get_page(pc, 0, &buf_res); 433 434 td = buf_res.buffer; 435 436 td->td_self = 437 htole32(buf_res.physaddr) | 438 htole32(UHCI_PTR_TD); 439 440 td->page_cache = pc; 441 442 return (td); 443 } 444 445 usb_error_t 446 uhci_init(uhci_softc_t *sc) 447 { 448 uint16_t bit; 449 uint16_t x; 450 uint16_t y; 451 452 DPRINTF("start\n"); 453 454 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_lock, 0); 455 456 #ifdef USB_DEBUG 457 if (uhcidebug > 2) { 458 uhci_dumpregs(sc); 459 } 460 #endif 461 /* 462 * Setup QH's 463 */ 464 sc->sc_ls_ctl_p_last = 465 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 466 467 sc->sc_fs_ctl_p_last = 468 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 469 470 sc->sc_bulk_p_last = 471 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 472 #if 0 473 sc->sc_reclaim_qh_p = 474 sc->sc_fs_ctl_p_last; 475 #else 476 /* setup reclaim looping point */ 477 sc->sc_reclaim_qh_p = 478 sc->sc_bulk_p_last; 479 #endif 480 481 sc->sc_last_qh_p = 482 uhci_init_qh(&sc->sc_hw.last_qh_pc); 483 484 sc->sc_last_td_p = 485 uhci_init_td(&sc->sc_hw.last_td_pc); 486 487 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 488 sc->sc_isoc_p_last[x] = 489 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 490 } 491 492 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 493 sc->sc_intr_p_last[x] = 494 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 495 } 496 497 /* 498 * the QHs are arranged to give poll intervals that are 499 * powers of 2 times 1ms 500 */ 501 bit = UHCI_IFRAMELIST_COUNT / 2; 502 while (bit) { 503 x = bit; 504 while (x & bit) { 505 uhci_qh_t *qh_x; 506 uhci_qh_t *qh_y; 507 508 y = (x ^ bit) | (bit / 2); 509 510 /* 511 * the next QH has half the poll interval 512 */ 513 qh_x = sc->sc_intr_p_last[x]; 514 qh_y = sc->sc_intr_p_last[y]; 515 516 qh_x->h_next = NULL; 517 qh_x->qh_h_next = qh_y->qh_self; 518 qh_x->e_next = NULL; 519 qh_x->qh_e_next = htole32(UHCI_PTR_T); 520 x++; 521 } 522 bit >>= 1; 523 } 524 525 if (1) { 526 uhci_qh_t *qh_ls; 527 uhci_qh_t *qh_intr; 528 529 qh_ls = sc->sc_ls_ctl_p_last; 530 qh_intr = sc->sc_intr_p_last[0]; 531 532 /* start QH for interrupt traffic */ 533 qh_intr->h_next = qh_ls; 534 qh_intr->qh_h_next = qh_ls->qh_self; 535 qh_intr->e_next = 0; 536 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 537 } 538 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 539 540 uhci_td_t *td_x; 541 uhci_qh_t *qh_intr; 542 543 td_x = sc->sc_isoc_p_last[x]; 544 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 545 546 /* start TD for isochronous traffic */ 547 td_x->next = NULL; 548 td_x->td_next = qh_intr->qh_self; 549 td_x->td_status = htole32(UHCI_TD_IOS); 550 td_x->td_token = htole32(0); 551 td_x->td_buffer = htole32(0); 552 } 553 554 if (1) { 555 uhci_qh_t *qh_ls; 556 uhci_qh_t *qh_fs; 557 558 qh_ls = sc->sc_ls_ctl_p_last; 559 qh_fs = sc->sc_fs_ctl_p_last; 560 561 /* start QH where low speed control traffic will be queued */ 562 qh_ls->h_next = qh_fs; 563 qh_ls->qh_h_next = qh_fs->qh_self; 564 qh_ls->e_next = 0; 565 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 566 } 567 if (1) { 568 uhci_qh_t *qh_ctl; 569 uhci_qh_t *qh_blk; 570 uhci_qh_t *qh_lst; 571 uhci_td_t *td_lst; 572 573 qh_ctl = sc->sc_fs_ctl_p_last; 574 qh_blk = sc->sc_bulk_p_last; 575 576 /* start QH where full speed control traffic will be queued */ 577 qh_ctl->h_next = qh_blk; 578 qh_ctl->qh_h_next = qh_blk->qh_self; 579 qh_ctl->e_next = 0; 580 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 581 582 qh_lst = sc->sc_last_qh_p; 583 584 /* start QH where bulk traffic will be queued */ 585 qh_blk->h_next = qh_lst; 586 qh_blk->qh_h_next = qh_lst->qh_self; 587 qh_blk->e_next = 0; 588 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 589 590 td_lst = sc->sc_last_td_p; 591 592 /* end QH which is used for looping the QHs */ 593 qh_lst->h_next = 0; 594 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 595 qh_lst->e_next = td_lst; 596 qh_lst->qh_e_next = td_lst->td_self; 597 598 /* 599 * end TD which hangs from the last QH, to avoid a bug in the PIIX 600 * that makes it run berserk otherwise 601 */ 602 td_lst->next = 0; 603 td_lst->td_next = htole32(UHCI_PTR_T); 604 td_lst->td_status = htole32(0); /* inactive */ 605 td_lst->td_token = htole32(0); 606 td_lst->td_buffer = htole32(0); 607 } 608 if (1) { 609 struct usb_page_search buf_res; 610 uint32_t *pframes; 611 612 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 613 614 pframes = buf_res.buffer; 615 616 617 /* 618 * Setup UHCI framelist 619 * 620 * Execution order: 621 * 622 * pframes -> full speed isochronous -> interrupt QH's -> low 623 * speed control -> full speed control -> bulk transfers 624 * 625 */ 626 627 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 628 pframes[x] = 629 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 630 } 631 } 632 /* flush all cache into memory */ 633 634 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 635 636 /* set up the bus struct */ 637 sc->sc_bus.methods = &uhci_bus_methods; 638 639 USB_BUS_LOCK(&sc->sc_bus); 640 /* reset the controller */ 641 uhci_reset(sc); 642 643 /* start the controller */ 644 uhci_start(sc); 645 USB_BUS_UNLOCK(&sc->sc_bus); 646 647 /* catch lost interrupts */ 648 uhci_do_poll(&sc->sc_bus); 649 650 return (0); 651 } 652 653 static void 654 uhci_suspend(uhci_softc_t *sc) 655 { 656 #ifdef USB_DEBUG 657 if (uhcidebug > 2) { 658 uhci_dumpregs(sc); 659 } 660 #endif 661 662 USB_BUS_LOCK(&sc->sc_bus); 663 664 /* stop the controller */ 665 666 uhci_reset(sc); 667 668 /* enter global suspend */ 669 670 UHCICMD(sc, UHCI_CMD_EGSM); 671 672 USB_BUS_UNLOCK(&sc->sc_bus); 673 } 674 675 static void 676 uhci_resume(uhci_softc_t *sc) 677 { 678 USB_BUS_LOCK(&sc->sc_bus); 679 680 /* reset the controller */ 681 682 uhci_reset(sc); 683 684 /* force global resume */ 685 686 UHCICMD(sc, UHCI_CMD_FGR); 687 688 /* and start traffic again */ 689 690 uhci_start(sc); 691 692 USB_BUS_UNLOCK(&sc->sc_bus); 693 694 #ifdef USB_DEBUG 695 if (uhcidebug > 2) 696 uhci_dumpregs(sc); 697 #endif 698 699 /* catch lost interrupts */ 700 uhci_do_poll(&sc->sc_bus); 701 } 702 703 #ifdef USB_DEBUG 704 static void 705 uhci_dumpregs(uhci_softc_t *sc) 706 { 707 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 708 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 709 device_get_nameunit(sc->sc_bus.bdev), 710 UREAD2(sc, UHCI_CMD), 711 UREAD2(sc, UHCI_STS), 712 UREAD2(sc, UHCI_INTR), 713 UREAD2(sc, UHCI_FRNUM), 714 UREAD4(sc, UHCI_FLBASEADDR), 715 UREAD1(sc, UHCI_SOF), 716 UREAD2(sc, UHCI_PORTSC1), 717 UREAD2(sc, UHCI_PORTSC2)); 718 } 719 720 static uint8_t 721 uhci_dump_td(uhci_td_t *p) 722 { 723 uint32_t td_next; 724 uint32_t td_status; 725 uint32_t td_token; 726 uint8_t temp; 727 728 usb_pc_cpu_invalidate(p->page_cache); 729 730 td_next = le32toh(p->td_next); 731 td_status = le32toh(p->td_status); 732 td_token = le32toh(p->td_token); 733 734 /* 735 * Check whether the link pointer in this TD marks the link pointer 736 * as end of queue: 737 */ 738 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 739 740 kprintf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 741 "token=0x%08x buffer=0x%08x\n", 742 p, 743 le32toh(p->td_self), 744 td_next, 745 td_status, 746 td_token, 747 le32toh(p->td_buffer)); 748 749 kprintf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 750 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 751 p, 752 (td_next & 1) ? "-T" : "", 753 (td_next & 2) ? "-Q" : "", 754 (td_next & 4) ? "-VF" : "", 755 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 756 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 757 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 758 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 759 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 760 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 761 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 762 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 763 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 764 (td_status & UHCI_TD_LS) ? "-LS" : "", 765 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 766 UHCI_TD_GET_ERRCNT(td_status), 767 UHCI_TD_GET_ACTLEN(td_status), 768 UHCI_TD_GET_PID(td_token), 769 UHCI_TD_GET_DEVADDR(td_token), 770 UHCI_TD_GET_ENDPT(td_token), 771 UHCI_TD_GET_DT(td_token), 772 UHCI_TD_GET_MAXLEN(td_token)); 773 774 return (temp); 775 } 776 777 static uint8_t 778 uhci_dump_qh(uhci_qh_t *sqh) 779 { 780 uint8_t temp; 781 uint32_t qh_h_next; 782 uint32_t qh_e_next; 783 784 usb_pc_cpu_invalidate(sqh->page_cache); 785 786 qh_h_next = le32toh(sqh->qh_h_next); 787 qh_e_next = le32toh(sqh->qh_e_next); 788 789 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 790 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 791 792 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 793 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 794 795 return (temp); 796 } 797 798 static void 799 uhci_dump_all(uhci_softc_t *sc) 800 { 801 uhci_dumpregs(sc); 802 uhci_dump_qh(sc->sc_ls_ctl_p_last); 803 uhci_dump_qh(sc->sc_fs_ctl_p_last); 804 uhci_dump_qh(sc->sc_bulk_p_last); 805 uhci_dump_qh(sc->sc_last_qh_p); 806 } 807 808 static void 809 uhci_dump_tds(uhci_td_t *td) 810 { 811 for (; 812 td != NULL; 813 td = td->obj_next) { 814 if (uhci_dump_td(td)) { 815 break; 816 } 817 } 818 } 819 820 #endif 821 822 /* 823 * Let the last QH loop back to the full speed control transfer QH. 824 * This is what intel calls "bandwidth reclamation" and improves 825 * USB performance a lot for some devices. 826 * If we are already looping, just count it. 827 */ 828 static void 829 uhci_add_loop(uhci_softc_t *sc) 830 { 831 struct uhci_qh *qh_lst; 832 struct uhci_qh *qh_rec; 833 834 #ifdef USB_DEBUG 835 if (uhcinoloop) { 836 return; 837 } 838 #endif 839 if (++(sc->sc_loops) == 1) { 840 DPRINTFN(6, "add\n"); 841 842 qh_lst = sc->sc_last_qh_p; 843 qh_rec = sc->sc_reclaim_qh_p; 844 845 /* NOTE: we don't loop back the soft pointer */ 846 847 qh_lst->qh_h_next = qh_rec->qh_self; 848 usb_pc_cpu_flush(qh_lst->page_cache); 849 } 850 } 851 852 static void 853 uhci_rem_loop(uhci_softc_t *sc) 854 { 855 struct uhci_qh *qh_lst; 856 857 #ifdef USB_DEBUG 858 if (uhcinoloop) { 859 return; 860 } 861 #endif 862 if (--(sc->sc_loops) == 0) { 863 DPRINTFN(6, "remove\n"); 864 865 qh_lst = sc->sc_last_qh_p; 866 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 867 usb_pc_cpu_flush(qh_lst->page_cache); 868 } 869 } 870 871 static void 872 uhci_transfer_intr_enqueue(struct usb_xfer *xfer) 873 { 874 /* check for early completion */ 875 if (uhci_check_transfer(xfer)) { 876 return; 877 } 878 /* put transfer on interrupt queue */ 879 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 880 881 /* start timeout, if any */ 882 if (xfer->timeout != 0) { 883 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 884 } 885 } 886 887 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 888 static uhci_td_t * 889 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) 890 { 891 DPRINTFN(11, "%p to %p\n", std, last); 892 893 /* (sc->sc_bus.lock) must be locked */ 894 895 std->next = last->next; 896 std->td_next = last->td_next; 897 898 std->prev = last; 899 900 usb_pc_cpu_flush(std->page_cache); 901 902 /* 903 * the last->next->prev is never followed: std->next->prev = std; 904 */ 905 last->next = std; 906 last->td_next = std->td_self; 907 908 usb_pc_cpu_flush(last->page_cache); 909 910 return (std); 911 } 912 913 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 914 static uhci_qh_t * 915 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 916 { 917 DPRINTFN(11, "%p to %p\n", sqh, last); 918 919 if (sqh->h_prev != NULL) { 920 /* should not happen */ 921 DPRINTFN(0, "QH already linked!\n"); 922 return (last); 923 } 924 /* (sc->sc_bus.lock) must be locked */ 925 926 sqh->h_next = last->h_next; 927 sqh->qh_h_next = last->qh_h_next; 928 929 sqh->h_prev = last; 930 931 usb_pc_cpu_flush(sqh->page_cache); 932 933 /* 934 * The "last->h_next->h_prev" is never followed: 935 * 936 * "sqh->h_next->h_prev" = sqh; 937 */ 938 939 last->h_next = sqh; 940 last->qh_h_next = sqh->qh_self; 941 942 usb_pc_cpu_flush(last->page_cache); 943 944 return (sqh); 945 } 946 947 /**/ 948 949 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 950 static uhci_td_t * 951 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 952 { 953 DPRINTFN(11, "%p from %p\n", std, last); 954 955 /* (sc->sc_bus.lock) must be locked */ 956 957 std->prev->next = std->next; 958 std->prev->td_next = std->td_next; 959 960 usb_pc_cpu_flush(std->prev->page_cache); 961 962 if (std->next) { 963 std->next->prev = std->prev; 964 usb_pc_cpu_flush(std->next->page_cache); 965 } 966 return ((last == std) ? std->prev : last); 967 } 968 969 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 970 static uhci_qh_t * 971 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 972 { 973 DPRINTFN(11, "%p from %p\n", sqh, last); 974 975 /* (sc->sc_bus.lock) must be locked */ 976 977 /* only remove if not removed from a queue */ 978 if (sqh->h_prev) { 979 980 sqh->h_prev->h_next = sqh->h_next; 981 sqh->h_prev->qh_h_next = sqh->qh_h_next; 982 983 usb_pc_cpu_flush(sqh->h_prev->page_cache); 984 985 if (sqh->h_next) { 986 sqh->h_next->h_prev = sqh->h_prev; 987 usb_pc_cpu_flush(sqh->h_next->page_cache); 988 } 989 last = ((last == sqh) ? sqh->h_prev : last); 990 991 sqh->h_prev = 0; 992 993 usb_pc_cpu_flush(sqh->page_cache); 994 } 995 return (last); 996 } 997 998 static void 999 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer) 1000 { 1001 struct usb_page_search res; 1002 uint32_t nframes = xfer->nframes; 1003 uint32_t status; 1004 uint32_t offset = 0; 1005 uint32_t *plen = xfer->frlengths; 1006 uint16_t len = 0; 1007 uhci_td_t *td = xfer->td_transfer_first; 1008 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1009 1010 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1011 xfer, xfer->endpoint); 1012 1013 /* sync any DMA memory before doing fixups */ 1014 1015 usb_bdma_post_sync(xfer); 1016 1017 while (nframes--) { 1018 if (td == NULL) { 1019 panic("%s:%d: out of TD's\n", 1020 __func__, __LINE__); 1021 } 1022 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1023 pp_last = &sc->sc_isoc_p_last[0]; 1024 } 1025 #ifdef USB_DEBUG 1026 if (uhcidebug > 5) { 1027 DPRINTF("isoc TD\n"); 1028 uhci_dump_td(td); 1029 } 1030 #endif 1031 usb_pc_cpu_invalidate(td->page_cache); 1032 status = le32toh(td->td_status); 1033 1034 len = UHCI_TD_GET_ACTLEN(status); 1035 1036 if (len > *plen) { 1037 len = *plen; 1038 } 1039 if (td->fix_pc) { 1040 1041 usbd_get_page(td->fix_pc, 0, &res); 1042 1043 /* copy data from fixup location to real location */ 1044 1045 usb_pc_cpu_invalidate(td->fix_pc); 1046 1047 usbd_copy_in(xfer->frbuffers, offset, 1048 res.buffer, len); 1049 } 1050 offset += *plen; 1051 1052 *plen = len; 1053 1054 /* remove TD from schedule */ 1055 UHCI_REMOVE_TD(td, *pp_last); 1056 1057 pp_last++; 1058 plen++; 1059 td = td->obj_next; 1060 } 1061 1062 xfer->aframes = xfer->nframes; 1063 } 1064 1065 static usb_error_t 1066 uhci_non_isoc_done_sub(struct usb_xfer *xfer) 1067 { 1068 struct usb_page_search res; 1069 uhci_td_t *td; 1070 uhci_td_t *td_alt_next; 1071 uint32_t status; 1072 uint32_t token; 1073 uint16_t len; 1074 1075 td = xfer->td_transfer_cache; 1076 td_alt_next = td->alt_next; 1077 1078 if (xfer->aframes != xfer->nframes) { 1079 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1080 } 1081 while (1) { 1082 1083 usb_pc_cpu_invalidate(td->page_cache); 1084 status = le32toh(td->td_status); 1085 token = le32toh(td->td_token); 1086 1087 /* 1088 * Verify the status and add 1089 * up the actual length: 1090 */ 1091 1092 len = UHCI_TD_GET_ACTLEN(status); 1093 if (len > td->len) { 1094 /* should not happen */ 1095 DPRINTF("Invalid status length, " 1096 "0x%04x/0x%04x bytes\n", len, td->len); 1097 status |= UHCI_TD_STALLED; 1098 1099 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1100 1101 if (td->fix_pc) { 1102 1103 usbd_get_page(td->fix_pc, 0, &res); 1104 1105 /* 1106 * copy data from fixup location to real 1107 * location 1108 */ 1109 1110 usb_pc_cpu_invalidate(td->fix_pc); 1111 1112 usbd_copy_in(xfer->frbuffers + xfer->aframes, 1113 xfer->frlengths[xfer->aframes], res.buffer, len); 1114 } 1115 /* update actual length */ 1116 1117 xfer->frlengths[xfer->aframes] += len; 1118 } 1119 /* Check for last transfer */ 1120 if (((void *)td) == xfer->td_transfer_last) { 1121 td = NULL; 1122 break; 1123 } 1124 if (status & UHCI_TD_STALLED) { 1125 /* the transfer is finished */ 1126 td = NULL; 1127 break; 1128 } 1129 /* Check for short transfer */ 1130 if (len != td->len) { 1131 if (xfer->flags_int.short_frames_ok) { 1132 /* follow alt next */ 1133 td = td->alt_next; 1134 } else { 1135 /* the transfer is finished */ 1136 td = NULL; 1137 } 1138 break; 1139 } 1140 td = td->obj_next; 1141 1142 if (td->alt_next != td_alt_next) { 1143 /* this USB frame is complete */ 1144 break; 1145 } 1146 } 1147 1148 /* update transfer cache */ 1149 1150 xfer->td_transfer_cache = td; 1151 1152 /* update data toggle */ 1153 1154 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1155 1156 #ifdef USB_DEBUG 1157 if (status & UHCI_TD_ERROR) { 1158 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1159 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1160 xfer->address, xfer->endpointno, xfer->aframes, 1161 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1162 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1163 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1164 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1165 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1166 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1167 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1168 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1169 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1170 (status & UHCI_TD_LS) ? "[LS]" : "", 1171 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1172 } 1173 #endif 1174 return (status & UHCI_TD_STALLED) ? 1175 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION; 1176 } 1177 1178 static void 1179 uhci_non_isoc_done(struct usb_xfer *xfer) 1180 { 1181 usb_error_t err = 0; 1182 1183 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1184 xfer, xfer->endpoint); 1185 1186 #ifdef USB_DEBUG 1187 if (uhcidebug > 10) { 1188 uhci_dump_tds(xfer->td_transfer_first); 1189 } 1190 #endif 1191 1192 /* sync any DMA memory before doing fixups */ 1193 1194 usb_bdma_post_sync(xfer); 1195 1196 /* reset scanner */ 1197 1198 xfer->td_transfer_cache = xfer->td_transfer_first; 1199 1200 if (xfer->flags_int.control_xfr) { 1201 if (xfer->flags_int.control_hdr) { 1202 1203 err = uhci_non_isoc_done_sub(xfer); 1204 } 1205 xfer->aframes = 1; 1206 1207 if (xfer->td_transfer_cache == NULL) { 1208 goto done; 1209 } 1210 } 1211 while (xfer->aframes != xfer->nframes) { 1212 1213 err = uhci_non_isoc_done_sub(xfer); 1214 xfer->aframes++; 1215 1216 if (xfer->td_transfer_cache == NULL) { 1217 goto done; 1218 } 1219 } 1220 1221 if (xfer->flags_int.control_xfr && 1222 !xfer->flags_int.control_act) { 1223 1224 err = uhci_non_isoc_done_sub(xfer); 1225 } 1226 done: 1227 uhci_device_done(xfer, err); 1228 } 1229 1230 /*------------------------------------------------------------------------* 1231 * uhci_check_transfer_sub 1232 * 1233 * The main purpose of this function is to update the data-toggle 1234 * in case it is wrong. 1235 *------------------------------------------------------------------------*/ 1236 static void 1237 uhci_check_transfer_sub(struct usb_xfer *xfer) 1238 { 1239 uhci_qh_t *qh; 1240 uhci_td_t *td; 1241 uhci_td_t *td_alt_next; 1242 1243 uint32_t td_token; 1244 uint32_t td_self; 1245 1246 td = xfer->td_transfer_cache; 1247 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1248 1249 td_token = td->obj_next->td_token; 1250 td = td->alt_next; 1251 xfer->td_transfer_cache = td; 1252 td_self = td->td_self; 1253 td_alt_next = td->alt_next; 1254 1255 if (xfer->flags_int.control_xfr) 1256 goto skip; /* don't touch the DT value! */ 1257 1258 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1)))) 1259 goto skip; /* data toggle has correct value */ 1260 1261 /* 1262 * The data toggle is wrong and we need to toggle it ! 1263 */ 1264 while (1) { 1265 1266 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1267 usb_pc_cpu_flush(td->page_cache); 1268 1269 if (td == xfer->td_transfer_last) { 1270 /* last transfer */ 1271 break; 1272 } 1273 td = td->obj_next; 1274 1275 if (td->alt_next != td_alt_next) { 1276 /* next frame */ 1277 break; 1278 } 1279 } 1280 skip: 1281 1282 /* update the QH */ 1283 qh->qh_e_next = td_self; 1284 usb_pc_cpu_flush(qh->page_cache); 1285 1286 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1287 } 1288 1289 /*------------------------------------------------------------------------* 1290 * uhci_check_transfer 1291 * 1292 * Return values: 1293 * 0: USB transfer is not finished 1294 * Else: USB transfer is finished 1295 *------------------------------------------------------------------------*/ 1296 static uint8_t 1297 uhci_check_transfer(struct usb_xfer *xfer) 1298 { 1299 uint32_t status; 1300 uint32_t token; 1301 uhci_td_t *td; 1302 1303 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1304 1305 if (xfer->endpoint->methods == &uhci_device_isoc_methods) { 1306 /* isochronous transfer */ 1307 1308 td = xfer->td_transfer_last; 1309 1310 usb_pc_cpu_invalidate(td->page_cache); 1311 status = le32toh(td->td_status); 1312 1313 /* check also if the first is complete */ 1314 1315 td = xfer->td_transfer_first; 1316 1317 usb_pc_cpu_invalidate(td->page_cache); 1318 status |= le32toh(td->td_status); 1319 1320 if (!(status & UHCI_TD_ACTIVE)) { 1321 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1322 goto transferred; 1323 } 1324 } else { 1325 /* non-isochronous transfer */ 1326 1327 /* 1328 * check whether there is an error somewhere 1329 * in the middle, or whether there was a short 1330 * packet (SPD and not ACTIVE) 1331 */ 1332 td = xfer->td_transfer_cache; 1333 1334 while (1) { 1335 usb_pc_cpu_invalidate(td->page_cache); 1336 status = le32toh(td->td_status); 1337 token = le32toh(td->td_token); 1338 1339 /* 1340 * if there is an active TD the transfer isn't done 1341 */ 1342 if (status & UHCI_TD_ACTIVE) { 1343 /* update cache */ 1344 xfer->td_transfer_cache = td; 1345 goto done; 1346 } 1347 /* 1348 * last transfer descriptor makes the transfer done 1349 */ 1350 if (((void *)td) == xfer->td_transfer_last) { 1351 break; 1352 } 1353 /* 1354 * any kind of error makes the transfer done 1355 */ 1356 if (status & UHCI_TD_STALLED) { 1357 break; 1358 } 1359 /* 1360 * check if we reached the last packet 1361 * or if there is a short packet: 1362 */ 1363 if ((td->td_next == htole32(UHCI_PTR_T)) || 1364 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1365 1366 if (xfer->flags_int.short_frames_ok) { 1367 /* follow alt next */ 1368 if (td->alt_next) { 1369 /* update cache */ 1370 xfer->td_transfer_cache = td; 1371 uhci_check_transfer_sub(xfer); 1372 goto done; 1373 } 1374 } 1375 /* transfer is done */ 1376 break; 1377 } 1378 td = td->obj_next; 1379 } 1380 uhci_non_isoc_done(xfer); 1381 goto transferred; 1382 } 1383 1384 done: 1385 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1386 return (0); 1387 1388 transferred: 1389 return (1); 1390 } 1391 1392 static void 1393 uhci_interrupt_poll(uhci_softc_t *sc) 1394 { 1395 struct usb_xfer *xfer; 1396 1397 repeat: 1398 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1399 /* 1400 * check if transfer is transferred 1401 */ 1402 if (uhci_check_transfer(xfer)) { 1403 /* queue has been modified */ 1404 goto repeat; 1405 } 1406 } 1407 } 1408 1409 /*------------------------------------------------------------------------* 1410 * uhci_interrupt - UHCI interrupt handler 1411 * 1412 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1413 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1414 * is present ! 1415 *------------------------------------------------------------------------*/ 1416 void 1417 uhci_interrupt(uhci_softc_t *sc) 1418 { 1419 uint32_t status; 1420 1421 USB_BUS_LOCK(&sc->sc_bus); 1422 1423 DPRINTFN(16, "real interrupt\n"); 1424 1425 #ifdef USB_DEBUG 1426 if (uhcidebug > 15) { 1427 uhci_dumpregs(sc); 1428 } 1429 #endif 1430 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1431 if (status == 0) { 1432 /* the interrupt was not for us */ 1433 goto done; 1434 } 1435 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1436 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1437 1438 if (status & UHCI_STS_RD) { 1439 #ifdef USB_DEBUG 1440 kprintf("%s: resume detect\n", 1441 __func__); 1442 #endif 1443 } 1444 if (status & UHCI_STS_HSE) { 1445 kprintf("%s: host system error\n", 1446 __func__); 1447 } 1448 if (status & UHCI_STS_HCPE) { 1449 kprintf("%s: host controller process error\n", 1450 __func__); 1451 } 1452 if (status & UHCI_STS_HCH) { 1453 /* no acknowledge needed */ 1454 DPRINTF("%s: host controller halted\n", 1455 __func__); 1456 #ifdef USB_DEBUG 1457 if (uhcidebug > 0) { 1458 uhci_dump_all(sc); 1459 } 1460 #endif 1461 } 1462 } 1463 /* get acknowledge bits */ 1464 status &= (UHCI_STS_USBINT | 1465 UHCI_STS_USBEI | 1466 UHCI_STS_RD | 1467 UHCI_STS_HSE | 1468 UHCI_STS_HCPE); 1469 1470 if (status == 0) { 1471 /* nothing to acknowledge */ 1472 goto done; 1473 } 1474 /* acknowledge interrupts */ 1475 UWRITE2(sc, UHCI_STS, status); 1476 1477 /* poll all the USB transfers */ 1478 uhci_interrupt_poll(sc); 1479 1480 done: 1481 USB_BUS_UNLOCK(&sc->sc_bus); 1482 } 1483 1484 /* 1485 * called when a request does not complete 1486 */ 1487 static void 1488 uhci_timeout(void *arg) 1489 { 1490 struct usb_xfer *xfer = arg; 1491 1492 DPRINTF("xfer=%p\n", xfer); 1493 1494 USB_BUS_LOCK_ASSERT(xfer->xroot->bus); 1495 1496 /* transfer is transferred */ 1497 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1498 } 1499 1500 static void 1501 uhci_do_poll(struct usb_bus *bus) 1502 { 1503 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1504 1505 USB_BUS_LOCK(&sc->sc_bus); 1506 uhci_interrupt_poll(sc); 1507 USB_BUS_UNLOCK(&sc->sc_bus); 1508 } 1509 1510 static void 1511 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1512 { 1513 uhci_td_t *td; 1514 uhci_td_t *td_next; 1515 uhci_td_t *td_alt_next; 1516 uint32_t average; 1517 uint32_t len_old; 1518 uint8_t shortpkt_old; 1519 uint8_t precompute; 1520 1521 td_alt_next = NULL; 1522 shortpkt_old = temp->shortpkt; 1523 len_old = temp->len; 1524 precompute = 1; 1525 1526 /* software is used to detect short incoming transfers */ 1527 1528 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1529 temp->td_status |= htole32(UHCI_TD_SPD); 1530 } else { 1531 temp->td_status &= ~htole32(UHCI_TD_SPD); 1532 } 1533 1534 temp->ml.buf_offset = 0; 1535 1536 restart: 1537 1538 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1539 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1540 1541 td = temp->td; 1542 td_next = temp->td_next; 1543 1544 while (1) { 1545 1546 if (temp->len == 0) { 1547 1548 if (temp->shortpkt) { 1549 break; 1550 } 1551 /* send a Zero Length Packet, ZLP, last */ 1552 1553 temp->shortpkt = 1; 1554 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1555 average = 0; 1556 1557 } else { 1558 1559 average = temp->average; 1560 1561 if (temp->len < average) { 1562 temp->shortpkt = 1; 1563 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1564 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1565 average = temp->len; 1566 } 1567 } 1568 1569 if (td_next == NULL) { 1570 panic("%s: out of UHCI transfer descriptors!", __func__); 1571 } 1572 /* get next TD */ 1573 1574 td = td_next; 1575 td_next = td->obj_next; 1576 1577 /* check if we are pre-computing */ 1578 1579 if (precompute) { 1580 1581 /* update remaining length */ 1582 1583 temp->len -= average; 1584 1585 continue; 1586 } 1587 /* fill out current TD */ 1588 1589 td->td_status = temp->td_status; 1590 td->td_token = temp->td_token; 1591 1592 /* update data toggle */ 1593 1594 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1595 1596 if (average == 0) { 1597 1598 td->len = 0; 1599 td->td_buffer = 0; 1600 td->fix_pc = NULL; 1601 1602 } else { 1603 1604 /* update remaining length */ 1605 1606 temp->len -= average; 1607 1608 td->len = average; 1609 1610 /* fill out buffer pointer and do fixup, if any */ 1611 1612 uhci_mem_layout_fixup(&temp->ml, td); 1613 } 1614 1615 td->alt_next = td_alt_next; 1616 1617 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1618 /* we need to receive these frames one by one ! */ 1619 td->td_status |= htole32(UHCI_TD_IOC); 1620 td->td_next = htole32(UHCI_PTR_T); 1621 } else { 1622 if (td_next) { 1623 /* link the current TD with the next one */ 1624 td->td_next = td_next->td_self; 1625 } 1626 } 1627 1628 usb_pc_cpu_flush(td->page_cache); 1629 } 1630 1631 if (precompute) { 1632 precompute = 0; 1633 1634 /* setup alt next pointer, if any */ 1635 if (temp->last_frame) { 1636 td_alt_next = NULL; 1637 } else { 1638 /* we use this field internally */ 1639 td_alt_next = td_next; 1640 } 1641 1642 /* restore */ 1643 temp->shortpkt = shortpkt_old; 1644 temp->len = len_old; 1645 goto restart; 1646 } 1647 temp->td = td; 1648 temp->td_next = td_next; 1649 } 1650 1651 static uhci_td_t * 1652 uhci_setup_standard_chain(struct usb_xfer *xfer) 1653 { 1654 struct uhci_std_temp temp; 1655 uhci_td_t *td; 1656 uint32_t x; 1657 1658 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1659 xfer->address, UE_GET_ADDR(xfer->endpointno), 1660 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1661 1662 temp.average = xfer->max_frame_size; 1663 temp.max_frame_size = xfer->max_frame_size; 1664 1665 /* toggle the DMA set we are using */ 1666 xfer->flags_int.curr_dma_set ^= 1; 1667 1668 /* get next DMA set */ 1669 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1670 xfer->td_transfer_first = td; 1671 xfer->td_transfer_cache = td; 1672 1673 temp.td = NULL; 1674 temp.td_next = td; 1675 temp.last_frame = 0; 1676 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1677 1678 uhci_mem_layout_init(&temp.ml, xfer); 1679 1680 temp.td_status = 1681 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1682 UHCI_TD_ACTIVE)); 1683 1684 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1685 temp.td_status |= htole32(UHCI_TD_LS); 1686 } 1687 temp.td_token = 1688 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) | 1689 UHCI_TD_SET_DEVADDR(xfer->address)); 1690 1691 if (xfer->endpoint->toggle_next) { 1692 /* DATA1 is next */ 1693 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1694 } 1695 /* check if we should prepend a setup message */ 1696 1697 if (xfer->flags_int.control_xfr) { 1698 1699 if (xfer->flags_int.control_hdr) { 1700 1701 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1702 UHCI_TD_SET_ENDPT(0xF)); 1703 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1704 UHCI_TD_SET_DT(0)); 1705 1706 temp.len = xfer->frlengths[0]; 1707 temp.ml.buf_pc = xfer->frbuffers + 0; 1708 temp.shortpkt = temp.len ? 1 : 0; 1709 /* check for last frame */ 1710 if (xfer->nframes == 1) { 1711 /* no STATUS stage yet, SETUP is last */ 1712 if (xfer->flags_int.control_act) { 1713 temp.last_frame = 1; 1714 temp.setup_alt_next = 0; 1715 } 1716 } 1717 uhci_setup_standard_chain_sub(&temp); 1718 } 1719 x = 1; 1720 } else { 1721 x = 0; 1722 } 1723 1724 while (x != xfer->nframes) { 1725 1726 /* DATA0 / DATA1 message */ 1727 1728 temp.len = xfer->frlengths[x]; 1729 temp.ml.buf_pc = xfer->frbuffers + x; 1730 1731 x++; 1732 1733 if (x == xfer->nframes) { 1734 if (xfer->flags_int.control_xfr) { 1735 /* no STATUS stage yet, DATA is last */ 1736 if (xfer->flags_int.control_act) { 1737 temp.last_frame = 1; 1738 temp.setup_alt_next = 0; 1739 } 1740 } else { 1741 temp.last_frame = 1; 1742 temp.setup_alt_next = 0; 1743 } 1744 } 1745 /* 1746 * Keep previous data toggle, 1747 * device address and endpoint number: 1748 */ 1749 1750 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1751 UHCI_TD_SET_ENDPT(0xF) | 1752 UHCI_TD_SET_DT(1)); 1753 1754 if (temp.len == 0) { 1755 1756 /* make sure that we send an USB packet */ 1757 1758 temp.shortpkt = 0; 1759 1760 } else { 1761 1762 /* regular data transfer */ 1763 1764 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1765 } 1766 1767 /* set endpoint direction */ 1768 1769 temp.td_token |= 1770 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1771 htole32(UHCI_TD_PID_IN) : 1772 htole32(UHCI_TD_PID_OUT); 1773 1774 uhci_setup_standard_chain_sub(&temp); 1775 } 1776 1777 /* check if we should append a status stage */ 1778 1779 if (xfer->flags_int.control_xfr && 1780 !xfer->flags_int.control_act) { 1781 1782 /* 1783 * send a DATA1 message and reverse the current endpoint 1784 * direction 1785 */ 1786 1787 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1788 UHCI_TD_SET_ENDPT(0xF) | 1789 UHCI_TD_SET_DT(1)); 1790 temp.td_token |= 1791 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1792 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1793 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1794 1795 temp.len = 0; 1796 temp.ml.buf_pc = NULL; 1797 temp.shortpkt = 0; 1798 temp.last_frame = 1; 1799 temp.setup_alt_next = 0; 1800 1801 uhci_setup_standard_chain_sub(&temp); 1802 } 1803 td = temp.td; 1804 1805 /* Ensure that last TD is terminating: */ 1806 td->td_next = htole32(UHCI_PTR_T); 1807 1808 /* set interrupt bit */ 1809 1810 td->td_status |= htole32(UHCI_TD_IOC); 1811 1812 usb_pc_cpu_flush(td->page_cache); 1813 1814 /* must have at least one frame! */ 1815 1816 xfer->td_transfer_last = td; 1817 1818 #ifdef USB_DEBUG 1819 if (uhcidebug > 8) { 1820 DPRINTF("nexttog=%d; data before transfer:\n", 1821 xfer->endpoint->toggle_next); 1822 uhci_dump_tds(xfer->td_transfer_first); 1823 } 1824 #endif 1825 return (xfer->td_transfer_first); 1826 } 1827 1828 /* NOTE: "done" can be run two times in a row, 1829 * from close and from interrupt 1830 */ 1831 1832 static void 1833 uhci_device_done(struct usb_xfer *xfer, usb_error_t error) 1834 { 1835 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1836 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1837 uhci_qh_t *qh; 1838 1839 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 1840 1841 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1842 xfer, xfer->endpoint, error); 1843 1844 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1845 if (qh) { 1846 usb_pc_cpu_invalidate(qh->page_cache); 1847 } 1848 if (xfer->flags_int.bandwidth_reclaimed) { 1849 xfer->flags_int.bandwidth_reclaimed = 0; 1850 uhci_rem_loop(sc); 1851 } 1852 if (methods == &uhci_device_bulk_methods) { 1853 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1854 } 1855 if (methods == &uhci_device_ctrl_methods) { 1856 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1857 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1858 } else { 1859 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1860 } 1861 } 1862 if (methods == &uhci_device_intr_methods) { 1863 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1864 } 1865 /* 1866 * Only finish isochronous transfers once 1867 * which will update "xfer->frlengths". 1868 */ 1869 if (xfer->td_transfer_first && 1870 xfer->td_transfer_last) { 1871 if (methods == &uhci_device_isoc_methods) { 1872 uhci_isoc_done(sc, xfer); 1873 } 1874 xfer->td_transfer_first = NULL; 1875 xfer->td_transfer_last = NULL; 1876 } 1877 /* dequeue transfer and start next transfer */ 1878 usbd_transfer_done(xfer, error); 1879 } 1880 1881 /*------------------------------------------------------------------------* 1882 * uhci bulk support 1883 *------------------------------------------------------------------------*/ 1884 static void 1885 uhci_device_bulk_open(struct usb_xfer *xfer) 1886 { 1887 return; 1888 } 1889 1890 static void 1891 uhci_device_bulk_close(struct usb_xfer *xfer) 1892 { 1893 uhci_device_done(xfer, USB_ERR_CANCELLED); 1894 } 1895 1896 static void 1897 uhci_device_bulk_enter(struct usb_xfer *xfer) 1898 { 1899 return; 1900 } 1901 1902 static void 1903 uhci_device_bulk_start(struct usb_xfer *xfer) 1904 { 1905 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1906 uhci_td_t *td; 1907 uhci_qh_t *qh; 1908 1909 /* setup TD's */ 1910 td = uhci_setup_standard_chain(xfer); 1911 1912 /* setup QH */ 1913 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1914 1915 qh->e_next = td; 1916 qh->qh_e_next = td->td_self; 1917 1918 if (xfer->xroot->udev->flags.self_suspended == 0) { 1919 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1920 uhci_add_loop(sc); 1921 xfer->flags_int.bandwidth_reclaimed = 1; 1922 } else { 1923 usb_pc_cpu_flush(qh->page_cache); 1924 } 1925 1926 /* put transfer on interrupt queue */ 1927 uhci_transfer_intr_enqueue(xfer); 1928 } 1929 1930 static const struct usb_pipe_methods uhci_device_bulk_methods = 1931 { 1932 .open = uhci_device_bulk_open, 1933 .close = uhci_device_bulk_close, 1934 .enter = uhci_device_bulk_enter, 1935 .start = uhci_device_bulk_start, 1936 }; 1937 1938 /*------------------------------------------------------------------------* 1939 * uhci control support 1940 *------------------------------------------------------------------------*/ 1941 static void 1942 uhci_device_ctrl_open(struct usb_xfer *xfer) 1943 { 1944 return; 1945 } 1946 1947 static void 1948 uhci_device_ctrl_close(struct usb_xfer *xfer) 1949 { 1950 uhci_device_done(xfer, USB_ERR_CANCELLED); 1951 } 1952 1953 static void 1954 uhci_device_ctrl_enter(struct usb_xfer *xfer) 1955 { 1956 return; 1957 } 1958 1959 static void 1960 uhci_device_ctrl_start(struct usb_xfer *xfer) 1961 { 1962 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1963 uhci_qh_t *qh; 1964 uhci_td_t *td; 1965 1966 /* setup TD's */ 1967 td = uhci_setup_standard_chain(xfer); 1968 1969 /* setup QH */ 1970 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1971 1972 qh->e_next = td; 1973 qh->qh_e_next = td->td_self; 1974 1975 /* 1976 * NOTE: some devices choke on bandwidth- reclamation for control 1977 * transfers 1978 */ 1979 if (xfer->xroot->udev->flags.self_suspended == 0) { 1980 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1981 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 1982 } else { 1983 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 1984 } 1985 } else { 1986 usb_pc_cpu_flush(qh->page_cache); 1987 } 1988 /* put transfer on interrupt queue */ 1989 uhci_transfer_intr_enqueue(xfer); 1990 } 1991 1992 static const struct usb_pipe_methods uhci_device_ctrl_methods = 1993 { 1994 .open = uhci_device_ctrl_open, 1995 .close = uhci_device_ctrl_close, 1996 .enter = uhci_device_ctrl_enter, 1997 .start = uhci_device_ctrl_start, 1998 }; 1999 2000 /*------------------------------------------------------------------------* 2001 * uhci interrupt support 2002 *------------------------------------------------------------------------*/ 2003 static void 2004 uhci_device_intr_open(struct usb_xfer *xfer) 2005 { 2006 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2007 uint16_t best; 2008 uint16_t bit; 2009 uint16_t x; 2010 2011 best = 0; 2012 bit = UHCI_IFRAMELIST_COUNT / 2; 2013 while (bit) { 2014 if (xfer->interval >= bit) { 2015 x = bit; 2016 best = bit; 2017 while (x & bit) { 2018 if (sc->sc_intr_stat[x] < 2019 sc->sc_intr_stat[best]) { 2020 best = x; 2021 } 2022 x++; 2023 } 2024 break; 2025 } 2026 bit >>= 1; 2027 } 2028 2029 sc->sc_intr_stat[best]++; 2030 xfer->qh_pos = best; 2031 2032 DPRINTFN(3, "best=%d interval=%d\n", 2033 best, xfer->interval); 2034 } 2035 2036 static void 2037 uhci_device_intr_close(struct usb_xfer *xfer) 2038 { 2039 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2040 2041 sc->sc_intr_stat[xfer->qh_pos]--; 2042 2043 uhci_device_done(xfer, USB_ERR_CANCELLED); 2044 } 2045 2046 static void 2047 uhci_device_intr_enter(struct usb_xfer *xfer) 2048 { 2049 return; 2050 } 2051 2052 static void 2053 uhci_device_intr_start(struct usb_xfer *xfer) 2054 { 2055 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2056 uhci_qh_t *qh; 2057 uhci_td_t *td; 2058 2059 /* setup TD's */ 2060 td = uhci_setup_standard_chain(xfer); 2061 2062 /* setup QH */ 2063 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2064 2065 qh->e_next = td; 2066 qh->qh_e_next = td->td_self; 2067 2068 if (xfer->xroot->udev->flags.self_suspended == 0) { 2069 /* enter QHs into the controller data structures */ 2070 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2071 } else { 2072 usb_pc_cpu_flush(qh->page_cache); 2073 } 2074 2075 /* put transfer on interrupt queue */ 2076 uhci_transfer_intr_enqueue(xfer); 2077 } 2078 2079 static const struct usb_pipe_methods uhci_device_intr_methods = 2080 { 2081 .open = uhci_device_intr_open, 2082 .close = uhci_device_intr_close, 2083 .enter = uhci_device_intr_enter, 2084 .start = uhci_device_intr_start, 2085 }; 2086 2087 /*------------------------------------------------------------------------* 2088 * uhci isochronous support 2089 *------------------------------------------------------------------------*/ 2090 static void 2091 uhci_device_isoc_open(struct usb_xfer *xfer) 2092 { 2093 uhci_td_t *td; 2094 uint32_t td_token; 2095 uint8_t ds; 2096 2097 td_token = 2098 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 2099 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) : 2100 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0); 2101 2102 td_token = htole32(td_token); 2103 2104 /* initialize all TD's */ 2105 2106 for (ds = 0; ds != 2; ds++) { 2107 2108 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2109 2110 /* mark TD as inactive */ 2111 td->td_status = htole32(UHCI_TD_IOS); 2112 td->td_token = td_token; 2113 2114 usb_pc_cpu_flush(td->page_cache); 2115 } 2116 } 2117 } 2118 2119 static void 2120 uhci_device_isoc_close(struct usb_xfer *xfer) 2121 { 2122 uhci_device_done(xfer, USB_ERR_CANCELLED); 2123 } 2124 2125 static void 2126 uhci_device_isoc_enter(struct usb_xfer *xfer) 2127 { 2128 struct uhci_mem_layout ml; 2129 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2130 uint32_t nframes; 2131 uint32_t temp; 2132 uint32_t *plen; 2133 2134 #ifdef USB_DEBUG 2135 uint8_t once = 1; 2136 2137 #endif 2138 uhci_td_t *td; 2139 uhci_td_t *td_last = NULL; 2140 uhci_td_t **pp_last; 2141 2142 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2143 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2144 2145 nframes = UREAD2(sc, UHCI_FRNUM); 2146 2147 temp = (nframes - xfer->endpoint->isoc_next) & 2148 (UHCI_VFRAMELIST_COUNT - 1); 2149 2150 if ((xfer->endpoint->is_synced == 0) || 2151 (temp < xfer->nframes)) { 2152 /* 2153 * If there is data underflow or the pipe queue is empty we 2154 * schedule the transfer a few frames ahead of the current 2155 * frame position. Else two isochronous transfers might 2156 * overlap. 2157 */ 2158 xfer->endpoint->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2159 xfer->endpoint->is_synced = 1; 2160 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2161 } 2162 /* 2163 * compute how many milliseconds the insertion is ahead of the 2164 * current frame position: 2165 */ 2166 temp = (xfer->endpoint->isoc_next - nframes) & 2167 (UHCI_VFRAMELIST_COUNT - 1); 2168 2169 /* 2170 * pre-compute when the isochronous transfer will be finished: 2171 */ 2172 xfer->isoc_time_complete = 2173 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2174 xfer->nframes; 2175 2176 /* get the real number of frames */ 2177 2178 nframes = xfer->nframes; 2179 2180 uhci_mem_layout_init(&ml, xfer); 2181 2182 plen = xfer->frlengths; 2183 2184 /* toggle the DMA set we are using */ 2185 xfer->flags_int.curr_dma_set ^= 1; 2186 2187 /* get next DMA set */ 2188 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2189 xfer->td_transfer_first = td; 2190 2191 pp_last = &sc->sc_isoc_p_last[xfer->endpoint->isoc_next]; 2192 2193 /* store starting position */ 2194 2195 xfer->qh_pos = xfer->endpoint->isoc_next; 2196 2197 while (nframes--) { 2198 if (td == NULL) { 2199 panic("%s:%d: out of TD's\n", 2200 __func__, __LINE__); 2201 } 2202 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2203 pp_last = &sc->sc_isoc_p_last[0]; 2204 } 2205 if (*plen > xfer->max_frame_size) { 2206 #ifdef USB_DEBUG 2207 if (once) { 2208 once = 0; 2209 kprintf("%s: frame length(%d) exceeds %d " 2210 "bytes (frame truncated)\n", 2211 __func__, *plen, 2212 xfer->max_frame_size); 2213 } 2214 #endif 2215 *plen = xfer->max_frame_size; 2216 } 2217 /* reuse td_token from last transfer */ 2218 2219 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2220 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2221 2222 td->len = *plen; 2223 2224 if (td->len == 0) { 2225 /* 2226 * Do not call "uhci_mem_layout_fixup()" when the 2227 * length is zero! 2228 */ 2229 td->td_buffer = 0; 2230 td->fix_pc = NULL; 2231 2232 } else { 2233 2234 /* fill out buffer pointer and do fixup, if any */ 2235 2236 uhci_mem_layout_fixup(&ml, td); 2237 2238 } 2239 2240 /* update status */ 2241 if (nframes == 0) { 2242 td->td_status = htole32 2243 (UHCI_TD_ZERO_ACTLEN 2244 (UHCI_TD_SET_ERRCNT(0) | 2245 UHCI_TD_ACTIVE | 2246 UHCI_TD_IOS | 2247 UHCI_TD_IOC)); 2248 } else { 2249 td->td_status = htole32 2250 (UHCI_TD_ZERO_ACTLEN 2251 (UHCI_TD_SET_ERRCNT(0) | 2252 UHCI_TD_ACTIVE | 2253 UHCI_TD_IOS)); 2254 } 2255 2256 usb_pc_cpu_flush(td->page_cache); 2257 2258 #ifdef USB_DEBUG 2259 if (uhcidebug > 5) { 2260 DPRINTF("TD %d\n", nframes); 2261 uhci_dump_td(td); 2262 } 2263 #endif 2264 /* insert TD into schedule */ 2265 UHCI_APPEND_TD(td, *pp_last); 2266 pp_last++; 2267 2268 plen++; 2269 td_last = td; 2270 td = td->obj_next; 2271 } 2272 2273 xfer->td_transfer_last = td_last; 2274 2275 /* update isoc_next */ 2276 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2277 (UHCI_VFRAMELIST_COUNT - 1); 2278 } 2279 2280 static void 2281 uhci_device_isoc_start(struct usb_xfer *xfer) 2282 { 2283 /* put transfer on interrupt queue */ 2284 uhci_transfer_intr_enqueue(xfer); 2285 } 2286 2287 static const struct usb_pipe_methods uhci_device_isoc_methods = 2288 { 2289 .open = uhci_device_isoc_open, 2290 .close = uhci_device_isoc_close, 2291 .enter = uhci_device_isoc_enter, 2292 .start = uhci_device_isoc_start, 2293 }; 2294 2295 /*------------------------------------------------------------------------* 2296 * uhci root control support 2297 *------------------------------------------------------------------------* 2298 * Simulate a hardware hub by handling all the necessary requests. 2299 *------------------------------------------------------------------------*/ 2300 2301 static const 2302 struct usb_device_descriptor uhci_devd = 2303 { 2304 sizeof(struct usb_device_descriptor), 2305 UDESC_DEVICE, /* type */ 2306 {0x00, 0x01}, /* USB version */ 2307 UDCLASS_HUB, /* class */ 2308 UDSUBCLASS_HUB, /* subclass */ 2309 UDPROTO_FSHUB, /* protocol */ 2310 64, /* max packet */ 2311 {0}, {0}, {0x00, 0x01}, /* device id */ 2312 1, 2, 0, /* string indicies */ 2313 1 /* # of configurations */ 2314 }; 2315 2316 static const struct uhci_config_desc uhci_confd = { 2317 .confd = { 2318 .bLength = sizeof(struct usb_config_descriptor), 2319 .bDescriptorType = UDESC_CONFIG, 2320 .wTotalLength[0] = sizeof(uhci_confd), 2321 .bNumInterface = 1, 2322 .bConfigurationValue = 1, 2323 .iConfiguration = 0, 2324 .bmAttributes = UC_SELF_POWERED, 2325 .bMaxPower = 0 /* max power */ 2326 }, 2327 .ifcd = { 2328 .bLength = sizeof(struct usb_interface_descriptor), 2329 .bDescriptorType = UDESC_INTERFACE, 2330 .bNumEndpoints = 1, 2331 .bInterfaceClass = UICLASS_HUB, 2332 .bInterfaceSubClass = UISUBCLASS_HUB, 2333 .bInterfaceProtocol = UIPROTO_FSHUB, 2334 }, 2335 .endpd = { 2336 .bLength = sizeof(struct usb_endpoint_descriptor), 2337 .bDescriptorType = UDESC_ENDPOINT, 2338 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2339 .bmAttributes = UE_INTERRUPT, 2340 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2341 .bInterval = 255, 2342 }, 2343 }; 2344 2345 static const 2346 struct usb_hub_descriptor_min uhci_hubd_piix = 2347 { 2348 .bDescLength = sizeof(uhci_hubd_piix), 2349 .bDescriptorType = UDESC_HUB, 2350 .bNbrPorts = 2, 2351 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2352 .bPwrOn2PwrGood = 50, 2353 }; 2354 2355 /* 2356 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2357 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2358 * should not be used by the USB subsystem. As we cannot issue a 2359 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2360 * will be enabled as part of the reset. 2361 * 2362 * On the VT83C572, the port cannot be successfully enabled until the 2363 * outstanding "port enable change" and "connection status change" 2364 * events have been reset. 2365 */ 2366 static usb_error_t 2367 uhci_portreset(uhci_softc_t *sc, uint16_t index) 2368 { 2369 uint16_t port; 2370 uint16_t x; 2371 uint8_t lim; 2372 2373 if (index == 1) 2374 port = UHCI_PORTSC1; 2375 else if (index == 2) 2376 port = UHCI_PORTSC2; 2377 else 2378 return (USB_ERR_IOERROR); 2379 2380 /* 2381 * Before we do anything, turn on SOF messages on the USB 2382 * BUS. Some USB devices do not cope without them! 2383 */ 2384 uhci_restart(sc); 2385 2386 x = URWMASK(UREAD2(sc, port)); 2387 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2388 2389 usb_pause_mtx(&sc->sc_bus.bus_lock, 2390 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 2391 2392 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2393 index, UREAD2(sc, port)); 2394 2395 x = URWMASK(UREAD2(sc, port)); 2396 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2397 2398 2399 lockmgr(&sc->sc_bus.bus_lock, LK_RELEASE); 2400 2401 /* 2402 * This delay needs to be exactly 100us, else some USB devices 2403 * fail to attach! 2404 */ 2405 DELAY(100); 2406 2407 lockmgr(&sc->sc_bus.bus_lock, LK_EXCLUSIVE); 2408 2409 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2410 index, UREAD2(sc, port)); 2411 2412 x = URWMASK(UREAD2(sc, port)); 2413 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2414 2415 for (lim = 0; lim < 12; lim++) { 2416 2417 usb_pause_mtx(&sc->sc_bus.bus_lock, 2418 USB_MS_TO_TICKS(usb_port_reset_delay)); 2419 2420 x = UREAD2(sc, port); 2421 2422 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2423 index, lim, x); 2424 2425 if (!(x & UHCI_PORTSC_CCS)) { 2426 /* 2427 * No device is connected (or was disconnected 2428 * during reset). Consider the port reset. 2429 * The delay must be long enough to ensure on 2430 * the initial iteration that the device 2431 * connection will have been registered. 50ms 2432 * appears to be sufficient, but 20ms is not. 2433 */ 2434 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2435 index, lim); 2436 goto done; 2437 } 2438 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2439 /* 2440 * Port enabled changed and/or connection 2441 * status changed were set. Reset either or 2442 * both raised flags (by writing a 1 to that 2443 * bit), and wait again for state to settle. 2444 */ 2445 UWRITE2(sc, port, URWMASK(x) | 2446 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2447 continue; 2448 } 2449 if (x & UHCI_PORTSC_PE) { 2450 /* port is enabled */ 2451 goto done; 2452 } 2453 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2454 } 2455 2456 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2457 return (USB_ERR_TIMEOUT); 2458 2459 done: 2460 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2461 index, UREAD2(sc, port)); 2462 2463 sc->sc_isreset = 1; 2464 return (USB_ERR_NORMAL_COMPLETION); 2465 } 2466 2467 static usb_error_t 2468 uhci_roothub_exec(struct usb_device *udev, 2469 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2470 { 2471 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 2472 const void *ptr; 2473 const char *str_ptr; 2474 uint16_t x; 2475 uint16_t port; 2476 uint16_t value; 2477 uint16_t index; 2478 uint16_t status; 2479 uint16_t change; 2480 uint16_t len; 2481 usb_error_t err; 2482 2483 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2484 2485 /* buffer reset */ 2486 ptr = (const void *)&sc->sc_hub_desc.temp; 2487 len = 0; 2488 err = 0; 2489 2490 value = UGETW(req->wValue); 2491 index = UGETW(req->wIndex); 2492 2493 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2494 "wValue=0x%04x wIndex=0x%04x\n", 2495 req->bmRequestType, req->bRequest, 2496 UGETW(req->wLength), value, index); 2497 2498 #define C(x,y) ((x) | ((y) << 8)) 2499 switch (C(req->bRequest, req->bmRequestType)) { 2500 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2501 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2502 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2503 /* 2504 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2505 * for the integrated root hub. 2506 */ 2507 break; 2508 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2509 len = 1; 2510 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2511 break; 2512 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2513 switch (value >> 8) { 2514 case UDESC_DEVICE: 2515 if ((value & 0xff) != 0) { 2516 err = USB_ERR_IOERROR; 2517 goto done; 2518 } 2519 len = sizeof(uhci_devd); 2520 ptr = (const void *)&uhci_devd; 2521 break; 2522 2523 case UDESC_CONFIG: 2524 if ((value & 0xff) != 0) { 2525 err = USB_ERR_IOERROR; 2526 goto done; 2527 } 2528 len = sizeof(uhci_confd); 2529 ptr = (const void *)&uhci_confd; 2530 break; 2531 2532 case UDESC_STRING: 2533 switch (value & 0xff) { 2534 case 0: /* Language table */ 2535 str_ptr = "\001"; 2536 break; 2537 2538 case 1: /* Vendor */ 2539 str_ptr = sc->sc_vendor; 2540 break; 2541 2542 case 2: /* Product */ 2543 str_ptr = "UHCI root HUB"; 2544 break; 2545 2546 default: 2547 str_ptr = ""; 2548 break; 2549 } 2550 2551 len = usb_make_str_desc 2552 (sc->sc_hub_desc.temp, 2553 sizeof(sc->sc_hub_desc.temp), 2554 str_ptr); 2555 break; 2556 2557 default: 2558 err = USB_ERR_IOERROR; 2559 goto done; 2560 } 2561 break; 2562 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2563 len = 1; 2564 sc->sc_hub_desc.temp[0] = 0; 2565 break; 2566 case C(UR_GET_STATUS, UT_READ_DEVICE): 2567 len = 2; 2568 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2569 break; 2570 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2571 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2572 len = 2; 2573 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2574 break; 2575 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2576 if (value >= UHCI_MAX_DEVICES) { 2577 err = USB_ERR_IOERROR; 2578 goto done; 2579 } 2580 sc->sc_addr = value; 2581 break; 2582 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2583 if ((value != 0) && (value != 1)) { 2584 err = USB_ERR_IOERROR; 2585 goto done; 2586 } 2587 sc->sc_conf = value; 2588 break; 2589 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2590 break; 2591 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2592 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2593 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2594 err = USB_ERR_IOERROR; 2595 goto done; 2596 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2597 break; 2598 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2599 break; 2600 /* Hub requests */ 2601 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2602 break; 2603 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2604 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2605 "port=%d feature=%d\n", 2606 index, value); 2607 if (index == 1) 2608 port = UHCI_PORTSC1; 2609 else if (index == 2) 2610 port = UHCI_PORTSC2; 2611 else { 2612 err = USB_ERR_IOERROR; 2613 goto done; 2614 } 2615 switch (value) { 2616 case UHF_PORT_ENABLE: 2617 x = URWMASK(UREAD2(sc, port)); 2618 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2619 break; 2620 case UHF_PORT_SUSPEND: 2621 x = URWMASK(UREAD2(sc, port)); 2622 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2623 break; 2624 case UHF_PORT_RESET: 2625 x = URWMASK(UREAD2(sc, port)); 2626 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2627 break; 2628 case UHF_C_PORT_CONNECTION: 2629 x = URWMASK(UREAD2(sc, port)); 2630 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2631 break; 2632 case UHF_C_PORT_ENABLE: 2633 x = URWMASK(UREAD2(sc, port)); 2634 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2635 break; 2636 case UHF_C_PORT_OVER_CURRENT: 2637 x = URWMASK(UREAD2(sc, port)); 2638 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2639 break; 2640 case UHF_C_PORT_RESET: 2641 sc->sc_isreset = 0; 2642 err = USB_ERR_NORMAL_COMPLETION; 2643 goto done; 2644 case UHF_C_PORT_SUSPEND: 2645 sc->sc_isresumed &= ~(1 << index); 2646 break; 2647 case UHF_PORT_CONNECTION: 2648 case UHF_PORT_OVER_CURRENT: 2649 case UHF_PORT_POWER: 2650 case UHF_PORT_LOW_SPEED: 2651 default: 2652 err = USB_ERR_IOERROR; 2653 goto done; 2654 } 2655 break; 2656 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2657 if (index == 1) 2658 port = UHCI_PORTSC1; 2659 else if (index == 2) 2660 port = UHCI_PORTSC2; 2661 else { 2662 err = USB_ERR_IOERROR; 2663 goto done; 2664 } 2665 len = 1; 2666 sc->sc_hub_desc.temp[0] = 2667 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2668 UHCI_PORTSC_LS_SHIFT); 2669 break; 2670 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2671 if ((value & 0xff) != 0) { 2672 err = USB_ERR_IOERROR; 2673 goto done; 2674 } 2675 len = sizeof(uhci_hubd_piix); 2676 ptr = (const void *)&uhci_hubd_piix; 2677 break; 2678 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2679 len = 16; 2680 memset(sc->sc_hub_desc.temp, 0, 16); 2681 break; 2682 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2683 if (index == 1) 2684 port = UHCI_PORTSC1; 2685 else if (index == 2) 2686 port = UHCI_PORTSC2; 2687 else { 2688 err = USB_ERR_IOERROR; 2689 goto done; 2690 } 2691 x = UREAD2(sc, port); 2692 status = change = 0; 2693 if (x & UHCI_PORTSC_CCS) 2694 status |= UPS_CURRENT_CONNECT_STATUS; 2695 if (x & UHCI_PORTSC_CSC) 2696 change |= UPS_C_CONNECT_STATUS; 2697 if (x & UHCI_PORTSC_PE) 2698 status |= UPS_PORT_ENABLED; 2699 if (x & UHCI_PORTSC_POEDC) 2700 change |= UPS_C_PORT_ENABLED; 2701 if (x & UHCI_PORTSC_OCI) 2702 status |= UPS_OVERCURRENT_INDICATOR; 2703 if (x & UHCI_PORTSC_OCIC) 2704 change |= UPS_C_OVERCURRENT_INDICATOR; 2705 if (x & UHCI_PORTSC_LSDA) 2706 status |= UPS_LOW_SPEED; 2707 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2708 /* need to do a write back */ 2709 UWRITE2(sc, port, URWMASK(x)); 2710 2711 /* wait 20ms for resume sequence to complete */ 2712 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 50); 2713 2714 /* clear suspend and resume detect */ 2715 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2716 UHCI_PORTSC_SUSP)); 2717 2718 /* wait a little bit */ 2719 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 500); 2720 2721 sc->sc_isresumed |= (1 << index); 2722 2723 } else if (x & UHCI_PORTSC_SUSP) { 2724 status |= UPS_SUSPEND; 2725 } 2726 status |= UPS_PORT_POWER; 2727 if (sc->sc_isresumed & (1 << index)) 2728 change |= UPS_C_SUSPEND; 2729 if (sc->sc_isreset) 2730 change |= UPS_C_PORT_RESET; 2731 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2732 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2733 len = sizeof(sc->sc_hub_desc.ps); 2734 break; 2735 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2736 err = USB_ERR_IOERROR; 2737 goto done; 2738 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2739 break; 2740 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2741 if (index == 1) 2742 port = UHCI_PORTSC1; 2743 else if (index == 2) 2744 port = UHCI_PORTSC2; 2745 else { 2746 err = USB_ERR_IOERROR; 2747 goto done; 2748 } 2749 switch (value) { 2750 case UHF_PORT_ENABLE: 2751 x = URWMASK(UREAD2(sc, port)); 2752 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2753 break; 2754 case UHF_PORT_SUSPEND: 2755 x = URWMASK(UREAD2(sc, port)); 2756 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2757 break; 2758 case UHF_PORT_RESET: 2759 err = uhci_portreset(sc, index); 2760 goto done; 2761 case UHF_PORT_POWER: 2762 /* pretend we turned on power */ 2763 err = USB_ERR_NORMAL_COMPLETION; 2764 goto done; 2765 case UHF_C_PORT_CONNECTION: 2766 case UHF_C_PORT_ENABLE: 2767 case UHF_C_PORT_OVER_CURRENT: 2768 case UHF_PORT_CONNECTION: 2769 case UHF_PORT_OVER_CURRENT: 2770 case UHF_PORT_LOW_SPEED: 2771 case UHF_C_PORT_SUSPEND: 2772 case UHF_C_PORT_RESET: 2773 default: 2774 err = USB_ERR_IOERROR; 2775 goto done; 2776 } 2777 break; 2778 default: 2779 err = USB_ERR_IOERROR; 2780 goto done; 2781 } 2782 done: 2783 *plength = len; 2784 *pptr = ptr; 2785 return (err); 2786 } 2787 2788 /* 2789 * This routine is executed periodically and simulates interrupts from 2790 * the root controller interrupt pipe for port status change: 2791 */ 2792 static void 2793 uhci_root_intr(uhci_softc_t *sc) 2794 { 2795 DPRINTFN(21, "\n"); 2796 2797 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2798 2799 sc->sc_hub_idata[0] = 0; 2800 2801 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2802 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2803 sc->sc_hub_idata[0] |= 1 << 1; 2804 } 2805 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2806 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2807 sc->sc_hub_idata[0] |= 1 << 2; 2808 } 2809 2810 /* restart timer */ 2811 usb_callout_reset(&sc->sc_root_intr, hz, 2812 (void *)&uhci_root_intr, sc); 2813 2814 if (sc->sc_hub_idata[0] != 0) { 2815 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2816 sizeof(sc->sc_hub_idata)); 2817 } 2818 } 2819 2820 static void 2821 uhci_xfer_setup(struct usb_setup_params *parm) 2822 { 2823 struct usb_page_search page_info; 2824 struct usb_page_cache *pc; 2825 uhci_softc_t *sc; 2826 struct usb_xfer *xfer; 2827 void *last_obj; 2828 uint32_t ntd; 2829 uint32_t nqh; 2830 uint32_t nfixup; 2831 uint32_t n; 2832 uint16_t align; 2833 2834 sc = UHCI_BUS2SC(parm->udev->bus); 2835 xfer = parm->curr_xfer; 2836 2837 parm->hc_max_packet_size = 0x500; 2838 parm->hc_max_packet_count = 1; 2839 parm->hc_max_frame_size = 0x500; 2840 2841 /* 2842 * compute ntd and nqh 2843 */ 2844 if (parm->methods == &uhci_device_ctrl_methods) { 2845 xfer->flags_int.bdma_enable = 1; 2846 xfer->flags_int.bdma_no_post_sync = 1; 2847 2848 usbd_transfer_setup_sub(parm); 2849 2850 /* see EHCI HC driver for proof of "ntd" formula */ 2851 2852 nqh = 1; 2853 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2854 + (xfer->max_data_length / xfer->max_frame_size)); 2855 2856 } else if (parm->methods == &uhci_device_bulk_methods) { 2857 xfer->flags_int.bdma_enable = 1; 2858 xfer->flags_int.bdma_no_post_sync = 1; 2859 2860 usbd_transfer_setup_sub(parm); 2861 2862 nqh = 1; 2863 ntd = ((2 * xfer->nframes) 2864 + (xfer->max_data_length / xfer->max_frame_size)); 2865 2866 } else if (parm->methods == &uhci_device_intr_methods) { 2867 xfer->flags_int.bdma_enable = 1; 2868 xfer->flags_int.bdma_no_post_sync = 1; 2869 2870 usbd_transfer_setup_sub(parm); 2871 2872 nqh = 1; 2873 ntd = ((2 * xfer->nframes) 2874 + (xfer->max_data_length / xfer->max_frame_size)); 2875 2876 } else if (parm->methods == &uhci_device_isoc_methods) { 2877 xfer->flags_int.bdma_enable = 1; 2878 xfer->flags_int.bdma_no_post_sync = 1; 2879 2880 usbd_transfer_setup_sub(parm); 2881 2882 nqh = 0; 2883 ntd = xfer->nframes; 2884 2885 } else { 2886 2887 usbd_transfer_setup_sub(parm); 2888 2889 nqh = 0; 2890 ntd = 0; 2891 } 2892 2893 if (parm->err) { 2894 return; 2895 } 2896 /* 2897 * NOTE: the UHCI controller requires that 2898 * every packet must be contiguous on 2899 * the same USB memory page ! 2900 */ 2901 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 2902 2903 /* 2904 * Compute a suitable power of two alignment 2905 * for our "max_frame_size" fixup buffer(s): 2906 */ 2907 align = xfer->max_frame_size; 2908 n = 0; 2909 while (align) { 2910 align >>= 1; 2911 n++; 2912 } 2913 2914 /* check for power of two */ 2915 if (!(xfer->max_frame_size & 2916 (xfer->max_frame_size - 1))) { 2917 n--; 2918 } 2919 /* 2920 * We don't allow alignments of 2921 * less than 8 bytes: 2922 * 2923 * NOTE: Allocating using an aligment 2924 * of 1 byte has special meaning! 2925 */ 2926 if (n < 3) { 2927 n = 3; 2928 } 2929 align = (1 << n); 2930 2931 if (usbd_transfer_setup_sub_malloc( 2932 parm, &pc, xfer->max_frame_size, 2933 align, nfixup)) { 2934 parm->err = USB_ERR_NOMEM; 2935 return; 2936 } 2937 xfer->buf_fixup = pc; 2938 2939 alloc_dma_set: 2940 2941 if (parm->err) { 2942 return; 2943 } 2944 last_obj = NULL; 2945 2946 if (usbd_transfer_setup_sub_malloc( 2947 parm, &pc, sizeof(uhci_td_t), 2948 UHCI_TD_ALIGN, ntd)) { 2949 parm->err = USB_ERR_NOMEM; 2950 return; 2951 } 2952 if (parm->buf) { 2953 for (n = 0; n != ntd; n++) { 2954 uhci_td_t *td; 2955 2956 usbd_get_page(pc + n, 0, &page_info); 2957 2958 td = page_info.buffer; 2959 2960 /* init TD */ 2961 if ((parm->methods == &uhci_device_bulk_methods) || 2962 (parm->methods == &uhci_device_ctrl_methods) || 2963 (parm->methods == &uhci_device_intr_methods)) { 2964 /* set depth first bit */ 2965 td->td_self = htole32(page_info.physaddr | 2966 UHCI_PTR_TD | UHCI_PTR_VF); 2967 } else { 2968 td->td_self = htole32(page_info.physaddr | 2969 UHCI_PTR_TD); 2970 } 2971 2972 td->obj_next = last_obj; 2973 td->page_cache = pc + n; 2974 2975 last_obj = td; 2976 2977 usb_pc_cpu_flush(pc + n); 2978 } 2979 } 2980 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2981 2982 last_obj = NULL; 2983 2984 if (usbd_transfer_setup_sub_malloc( 2985 parm, &pc, sizeof(uhci_qh_t), 2986 UHCI_QH_ALIGN, nqh)) { 2987 parm->err = USB_ERR_NOMEM; 2988 return; 2989 } 2990 if (parm->buf) { 2991 for (n = 0; n != nqh; n++) { 2992 uhci_qh_t *qh; 2993 2994 usbd_get_page(pc + n, 0, &page_info); 2995 2996 qh = page_info.buffer; 2997 2998 /* init QH */ 2999 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3000 qh->obj_next = last_obj; 3001 qh->page_cache = pc + n; 3002 3003 last_obj = qh; 3004 3005 usb_pc_cpu_flush(pc + n); 3006 } 3007 } 3008 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3009 3010 if (!xfer->flags_int.curr_dma_set) { 3011 xfer->flags_int.curr_dma_set = 1; 3012 goto alloc_dma_set; 3013 } 3014 } 3015 3016 static void 3017 uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3018 struct usb_endpoint *ep) 3019 { 3020 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3021 3022 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3023 ep, udev->address, 3024 edesc->bEndpointAddress, udev->flags.usb_mode, 3025 sc->sc_addr); 3026 3027 if (udev->device_index != sc->sc_addr) { 3028 switch (edesc->bmAttributes & UE_XFERTYPE) { 3029 case UE_CONTROL: 3030 ep->methods = &uhci_device_ctrl_methods; 3031 break; 3032 case UE_INTERRUPT: 3033 ep->methods = &uhci_device_intr_methods; 3034 break; 3035 case UE_ISOCHRONOUS: 3036 if (udev->speed == USB_SPEED_FULL) { 3037 ep->methods = &uhci_device_isoc_methods; 3038 } 3039 break; 3040 case UE_BULK: 3041 ep->methods = &uhci_device_bulk_methods; 3042 break; 3043 default: 3044 /* do nothing */ 3045 break; 3046 } 3047 } 3048 } 3049 3050 static void 3051 uhci_xfer_unsetup(struct usb_xfer *xfer) 3052 { 3053 return; 3054 } 3055 3056 static void 3057 uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3058 { 3059 /* 3060 * Wait until hardware has finished any possible use of the 3061 * transfer descriptor(s) and QH 3062 */ 3063 *pus = (1125); /* microseconds */ 3064 } 3065 3066 static void 3067 uhci_device_resume(struct usb_device *udev) 3068 { 3069 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3070 struct usb_xfer *xfer; 3071 const struct usb_pipe_methods *methods; 3072 uhci_qh_t *qh; 3073 3074 DPRINTF("\n"); 3075 3076 USB_BUS_LOCK(udev->bus); 3077 3078 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3079 3080 if (xfer->xroot->udev == udev) { 3081 3082 methods = xfer->endpoint->methods; 3083 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3084 3085 if (methods == &uhci_device_bulk_methods) { 3086 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3087 uhci_add_loop(sc); 3088 xfer->flags_int.bandwidth_reclaimed = 1; 3089 } 3090 if (methods == &uhci_device_ctrl_methods) { 3091 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3092 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3093 } else { 3094 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3095 } 3096 } 3097 if (methods == &uhci_device_intr_methods) { 3098 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3099 } 3100 } 3101 } 3102 3103 USB_BUS_UNLOCK(udev->bus); 3104 3105 return; 3106 } 3107 3108 static void 3109 uhci_device_suspend(struct usb_device *udev) 3110 { 3111 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3112 struct usb_xfer *xfer; 3113 const struct usb_pipe_methods *methods; 3114 uhci_qh_t *qh; 3115 3116 DPRINTF("\n"); 3117 3118 USB_BUS_LOCK(udev->bus); 3119 3120 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3121 3122 if (xfer->xroot->udev == udev) { 3123 3124 methods = xfer->endpoint->methods; 3125 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3126 3127 if (xfer->flags_int.bandwidth_reclaimed) { 3128 xfer->flags_int.bandwidth_reclaimed = 0; 3129 uhci_rem_loop(sc); 3130 } 3131 if (methods == &uhci_device_bulk_methods) { 3132 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3133 } 3134 if (methods == &uhci_device_ctrl_methods) { 3135 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3136 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3137 } else { 3138 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3139 } 3140 } 3141 if (methods == &uhci_device_intr_methods) { 3142 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3143 } 3144 } 3145 } 3146 3147 USB_BUS_UNLOCK(udev->bus); 3148 3149 return; 3150 } 3151 3152 static void 3153 uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3154 { 3155 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3156 3157 switch (state) { 3158 case USB_HW_POWER_SUSPEND: 3159 case USB_HW_POWER_SHUTDOWN: 3160 uhci_suspend(sc); 3161 break; 3162 case USB_HW_POWER_RESUME: 3163 uhci_resume(sc); 3164 break; 3165 default: 3166 break; 3167 } 3168 } 3169 3170 static void 3171 uhci_set_hw_power(struct usb_bus *bus) 3172 { 3173 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3174 uint32_t flags; 3175 3176 DPRINTF("\n"); 3177 3178 USB_BUS_LOCK(bus); 3179 3180 flags = bus->hw_power_state; 3181 3182 /* 3183 * WARNING: Some FULL speed USB devices require periodic SOF 3184 * messages! If any USB devices are connected through the 3185 * UHCI, power save will be disabled! 3186 */ 3187 if (flags & (USB_HW_POWER_CONTROL | 3188 USB_HW_POWER_NON_ROOT_HUB | 3189 USB_HW_POWER_BULK | 3190 USB_HW_POWER_INTERRUPT | 3191 USB_HW_POWER_ISOC)) { 3192 DPRINTF("Some USB transfer is " 3193 "active on unit %u.\n", 3194 device_get_unit(sc->sc_bus.bdev)); 3195 uhci_restart(sc); 3196 } else { 3197 DPRINTF("Power save on unit %u.\n", 3198 device_get_unit(sc->sc_bus.bdev)); 3199 UHCICMD(sc, UHCI_CMD_MAXP); 3200 } 3201 3202 USB_BUS_UNLOCK(bus); 3203 3204 return; 3205 } 3206 3207 3208 static const struct usb_bus_methods uhci_bus_methods = 3209 { 3210 .endpoint_init = uhci_ep_init, 3211 .xfer_setup = uhci_xfer_setup, 3212 .xfer_unsetup = uhci_xfer_unsetup, 3213 .get_dma_delay = uhci_get_dma_delay, 3214 .device_resume = uhci_device_resume, 3215 .device_suspend = uhci_device_suspend, 3216 .set_hw_power = uhci_set_hw_power, 3217 .set_hw_power_sleep = uhci_set_hw_power_sleep, 3218 .roothub_exec = uhci_roothub_exec, 3219 .xfer_poll = uhci_do_poll, 3220 }; 3221