1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 28 * 29 * The XHCI 1.0 spec can be found at 30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 31 * and the USB 3.0 spec at 32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 33 */ 34 35 /* 36 * A few words about the design implementation: This driver emulates 37 * the concept about TDs which is found in EHCI specification. This 38 * way we avoid too much diveration among USB drivers. 39 */ 40 41 #include <sys/stdint.h> 42 #include <sys/param.h> 43 #include <sys/queue.h> 44 #include <sys/types.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/bus.h> 48 #include <sys/module.h> 49 #include <sys/lock.h> 50 #include <sys/condvar.h> 51 #include <sys/sysctl.h> 52 #include <sys/unistd.h> 53 #include <sys/callout.h> 54 #include <sys/malloc.h> 55 #include <sys/priv.h> 56 57 #include <bus/u4b/usb.h> 58 #include <bus/u4b/usbdi.h> 59 60 #define USB_DEBUG_VAR xhcidebug 61 62 #include <bus/u4b/usb_core.h> 63 #include <bus/u4b/usb_debug.h> 64 #include <bus/u4b/usb_busdma.h> 65 #include <bus/u4b/usb_process.h> 66 #include <bus/u4b/usb_transfer.h> 67 #include <bus/u4b/usb_device.h> 68 #include <bus/u4b/usb_hub.h> 69 #include <bus/u4b/usb_util.h> 70 71 #include <bus/u4b/usb_controller.h> 72 #include <bus/u4b/usb_bus.h> 73 #include <bus/u4b/controller/xhci.h> 74 #include <bus/u4b/controller/xhcireg.h> 75 76 #define XHCI_BUS2SC(bus) \ 77 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 78 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 79 80 #ifdef USB_DEBUG 81 static int xhcidebug = 0; 82 static int xhciroute = 0; 83 84 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 85 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW, 86 &xhcidebug, 0, "Debug level"); 87 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 88 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW, 89 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 90 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 91 #endif 92 93 #define XHCI_INTR_ENDPT 1 94 95 struct xhci_std_temp { 96 struct xhci_softc *sc; 97 struct usb_page_cache *pc; 98 struct xhci_td *td; 99 struct xhci_td *td_next; 100 uint32_t len; 101 uint32_t offset; 102 uint32_t max_packet_size; 103 uint32_t average; 104 uint16_t isoc_delta; 105 uint16_t isoc_frame; 106 uint8_t shortpkt; 107 uint8_t multishort; 108 uint8_t last_frame; 109 uint8_t trb_type; 110 uint8_t direction; 111 uint8_t tbc; 112 uint8_t tlbpc; 113 uint8_t step_td; 114 uint8_t do_isoc_sync; 115 }; 116 117 static void xhci_do_poll(struct usb_bus *); 118 static void xhci_device_done(struct usb_xfer *, usb_error_t); 119 static void xhci_root_intr(struct xhci_softc *); 120 static void xhci_free_device_ext(struct usb_device *); 121 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 122 struct usb_endpoint_descriptor *); 123 static usb_proc_callback_t xhci_configure_msg; 124 static usb_error_t xhci_configure_device(struct usb_device *); 125 static usb_error_t xhci_configure_endpoint(struct usb_device *, 126 struct usb_endpoint_descriptor *, uint64_t, uint16_t, 127 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, uint8_t); 128 static usb_error_t xhci_configure_mask(struct usb_device *, 129 uint32_t, uint8_t); 130 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 131 uint64_t, uint8_t); 132 static void xhci_endpoint_doorbell(struct usb_xfer *); 133 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 134 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 135 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 136 #ifdef USB_DEBUG 137 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 138 #endif 139 140 extern struct usb_bus_methods xhci_bus_methods; 141 142 #ifdef USB_DEBUG 143 static void 144 xhci_dump_trb(struct xhci_trb *trb) 145 { 146 DPRINTFN(5, "trb = %p\n", trb); 147 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 148 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 149 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 150 } 151 152 static void 153 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 154 { 155 DPRINTFN(5, "pep = %p\n", pep); 156 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 157 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 158 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 159 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 160 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 161 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 162 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 163 } 164 165 static void 166 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 167 { 168 DPRINTFN(5, "psl = %p\n", psl); 169 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 170 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 171 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 172 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 173 } 174 #endif 175 176 uint32_t 177 xhci_get_port_route(void) 178 { 179 #ifdef USB_DEBUG 180 return (0xFFFFFFFFU ^ ((uint32_t)xhciroute)); 181 #else 182 return (0xFFFFFFFFU); 183 #endif 184 } 185 186 static void 187 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 188 { 189 struct xhci_softc *sc = XHCI_BUS2SC(bus); 190 uint8_t i; 191 192 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 193 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 194 195 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 196 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 197 198 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 199 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 200 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 201 } 202 } 203 204 static void 205 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 206 { 207 if (sc->sc_ctx_is_64_byte) { 208 uint32_t offset; 209 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 210 /* all contexts are initially 32-bytes */ 211 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 212 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 213 } 214 *ptr = htole32(val); 215 } 216 217 static uint32_t 218 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 219 { 220 if (sc->sc_ctx_is_64_byte) { 221 uint32_t offset; 222 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 223 /* all contexts are initially 32-bytes */ 224 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 225 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 226 } 227 return (le32toh(*ptr)); 228 } 229 230 static void 231 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 232 { 233 if (sc->sc_ctx_is_64_byte) { 234 uint32_t offset; 235 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 236 /* all contexts are initially 32-bytes */ 237 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 238 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 239 } 240 *ptr = htole64(val); 241 } 242 243 #ifdef USB_DEBUG 244 static uint64_t 245 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 246 { 247 if (sc->sc_ctx_is_64_byte) { 248 uint32_t offset; 249 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 250 /* all contexts are initially 32-bytes */ 251 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 252 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 253 } 254 return (le64toh(*ptr)); 255 } 256 #endif 257 258 usb_error_t 259 xhci_start_controller(struct xhci_softc *sc) 260 { 261 struct usb_page_search buf_res; 262 struct xhci_hw_root *phwr; 263 struct xhci_dev_ctx_addr *pdctxa; 264 uint64_t addr; 265 uint32_t temp; 266 uint16_t i; 267 268 DPRINTF("\n"); 269 270 sc->sc_capa_off = 0; 271 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 272 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 273 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 274 275 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 276 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 277 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 278 279 sc->sc_event_ccs = 1; 280 sc->sc_event_idx = 0; 281 sc->sc_command_ccs = 1; 282 sc->sc_command_idx = 0; 283 284 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 285 286 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 287 288 DPRINTF("HCS0 = 0x%08x\n", temp); 289 290 if (XHCI_HCS0_CSZ(temp)) { 291 sc->sc_ctx_is_64_byte = 1; 292 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 293 } else { 294 sc->sc_ctx_is_64_byte = 0; 295 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 296 } 297 298 /* Reset controller */ 299 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 300 301 for (i = 0; i != 100; i++) { 302 usb_pause_mtx(NULL, hz / 100); 303 temp = XREAD4(sc, oper, XHCI_USBCMD) & 304 (XHCI_CMD_HCRST | XHCI_STS_CNR); 305 if (!temp) 306 break; 307 } 308 309 if (temp) { 310 device_printf(sc->sc_bus.parent, "Controller " 311 "reset timeout.\n"); 312 return (USB_ERR_IOERROR); 313 } 314 315 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 316 device_printf(sc->sc_bus.parent, "Controller does " 317 "not support 4K page size.\n"); 318 return (USB_ERR_IOERROR); 319 } 320 321 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 322 323 i = XHCI_HCS1_N_PORTS(temp); 324 325 if (i == 0) { 326 device_printf(sc->sc_bus.parent, "Invalid number " 327 "of ports: %u\n", i); 328 return (USB_ERR_IOERROR); 329 } 330 331 sc->sc_noport = i; 332 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 333 334 if (sc->sc_noslot > XHCI_MAX_DEVICES) 335 sc->sc_noslot = XHCI_MAX_DEVICES; 336 337 /* setup number of device slots */ 338 339 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 340 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 341 342 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 343 344 DPRINTF("Max slots: %u\n", sc->sc_noslot); 345 346 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 347 348 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 349 350 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 351 device_printf(sc->sc_bus.parent, "XHCI request " 352 "too many scratchpads\n"); 353 return (USB_ERR_NOMEM); 354 } 355 356 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 357 358 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 359 360 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 361 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 362 363 temp = XREAD4(sc, oper, XHCI_USBSTS); 364 365 /* clear interrupts */ 366 XWRITE4(sc, oper, XHCI_USBSTS, temp); 367 /* disable all device notifications */ 368 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 369 370 /* setup device context base address */ 371 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 372 pdctxa = buf_res.buffer; 373 memset(pdctxa, 0, sizeof(*pdctxa)); 374 375 addr = buf_res.physaddr; 376 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 377 378 /* slot 0 points to the table of scratchpad pointers */ 379 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 380 381 for (i = 0; i != sc->sc_noscratch; i++) { 382 struct usb_page_search buf_scp; 383 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 384 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 385 } 386 387 addr = buf_res.physaddr; 388 389 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 390 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 391 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 392 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 393 394 /* Setup event table size */ 395 396 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 397 398 DPRINTF("HCS2=0x%08x\n", temp); 399 400 temp = XHCI_HCS2_ERST_MAX(temp); 401 temp = 1U << temp; 402 if (temp > XHCI_MAX_RSEG) 403 temp = XHCI_MAX_RSEG; 404 405 sc->sc_erst_max = temp; 406 407 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 408 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 409 410 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 411 412 /* Setup interrupt rate */ 413 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 414 415 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 416 417 phwr = buf_res.buffer; 418 addr = buf_res.physaddr; 419 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 420 421 /* reset hardware root structure */ 422 memset(phwr, 0, sizeof(*phwr)); 423 424 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 425 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 426 427 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 428 429 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 430 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 431 432 addr = (uint64_t)buf_res.physaddr; 433 434 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 435 436 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 437 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 438 439 /* Setup interrupter registers */ 440 441 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 442 temp |= XHCI_IMAN_INTR_ENA; 443 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 444 445 /* setup command ring control base address */ 446 addr = buf_res.physaddr; 447 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 448 449 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 450 451 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 452 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 453 454 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 455 456 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 457 458 /* Go! */ 459 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 460 XHCI_CMD_INTE | XHCI_CMD_HSEE); 461 462 for (i = 0; i != 100; i++) { 463 usb_pause_mtx(NULL, hz / 100); 464 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 465 if (!temp) 466 break; 467 } 468 if (temp) { 469 XWRITE4(sc, oper, XHCI_USBCMD, 0); 470 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 471 return (USB_ERR_IOERROR); 472 } 473 474 /* catch any lost interrupts */ 475 xhci_do_poll(&sc->sc_bus); 476 477 return (0); 478 } 479 480 usb_error_t 481 xhci_halt_controller(struct xhci_softc *sc) 482 { 483 uint32_t temp; 484 uint16_t i; 485 486 DPRINTF("\n"); 487 488 sc->sc_capa_off = 0; 489 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 490 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 491 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 492 493 /* Halt controller */ 494 XWRITE4(sc, oper, XHCI_USBCMD, 0); 495 496 for (i = 0; i != 100; i++) { 497 usb_pause_mtx(NULL, hz / 100); 498 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 499 if (temp) 500 break; 501 } 502 503 if (!temp) { 504 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 505 return (USB_ERR_IOERROR); 506 } 507 return (0); 508 } 509 510 usb_error_t 511 xhci_init(struct xhci_softc *sc, device_t self) 512 { 513 /* initialise some bus fields */ 514 sc->sc_bus.parent = self; 515 516 /* set the bus revision */ 517 sc->sc_bus.usbrev = USB_REV_3_0; 518 519 /* set up the bus struct */ 520 sc->sc_bus.methods = &xhci_bus_methods; 521 522 /* setup devices array */ 523 sc->sc_bus.devices = sc->sc_devices; 524 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 525 526 /* setup command queue mutex and condition varible */ 527 cv_init(&sc->sc_cmd_cv, "CMDQ"); 528 lockinit(&sc->sc_cmd_lock, "CMDQ lock", 0, 0); 529 530 /* get all DMA memory */ 531 if (usb_bus_mem_alloc_all(&sc->sc_bus, 532 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 533 return (ENOMEM); 534 } 535 536 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 537 sc->sc_config_msg[0].bus = &sc->sc_bus; 538 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 539 sc->sc_config_msg[1].bus = &sc->sc_bus; 540 541 if (usb_proc_create(&sc->sc_config_proc, 542 &sc->sc_bus.bus_lock, device_get_nameunit(self), USB_PRI_MED)) { 543 kprintf("WARNING: Creation of XHCI configure " 544 "callback process failed.\n"); 545 } 546 return (0); 547 } 548 549 void 550 xhci_uninit(struct xhci_softc *sc) 551 { 552 usb_proc_free(&sc->sc_config_proc); 553 554 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 555 556 cv_destroy(&sc->sc_cmd_cv); 557 lockuninit(&sc->sc_cmd_lock); 558 } 559 560 static void 561 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 562 { 563 struct xhci_softc *sc = XHCI_BUS2SC(bus); 564 565 switch (state) { 566 case USB_HW_POWER_SUSPEND: 567 DPRINTF("Stopping the XHCI\n"); 568 xhci_halt_controller(sc); 569 break; 570 case USB_HW_POWER_SHUTDOWN: 571 DPRINTF("Stopping the XHCI\n"); 572 xhci_halt_controller(sc); 573 break; 574 case USB_HW_POWER_RESUME: 575 DPRINTF("Starting the XHCI\n"); 576 xhci_start_controller(sc); 577 break; 578 default: 579 break; 580 } 581 } 582 583 static usb_error_t 584 xhci_generic_done_sub(struct usb_xfer *xfer) 585 { 586 struct xhci_td *td; 587 struct xhci_td *td_alt_next; 588 uint32_t len; 589 uint8_t status; 590 591 td = xfer->td_transfer_cache; 592 td_alt_next = td->alt_next; 593 594 if (xfer->aframes != xfer->nframes) 595 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 596 597 while (1) { 598 599 usb_pc_cpu_invalidate(td->page_cache); 600 601 status = td->status; 602 len = td->remainder; 603 604 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 605 xfer, (unsigned int)xfer->aframes, 606 (unsigned int)xfer->nframes, 607 (unsigned int)len, (unsigned int)td->len, 608 (unsigned int)status); 609 610 /* 611 * Verify the status length and 612 * add the length to "frlengths[]": 613 */ 614 if (len > td->len) { 615 /* should not happen */ 616 DPRINTF("Invalid status length, " 617 "0x%04x/0x%04x bytes\n", len, td->len); 618 status = XHCI_TRB_ERROR_LENGTH; 619 } else if (xfer->aframes != xfer->nframes) { 620 xfer->frlengths[xfer->aframes] += td->len - len; 621 } 622 /* Check for last transfer */ 623 if (((void *)td) == xfer->td_transfer_last) { 624 td = NULL; 625 break; 626 } 627 /* Check for transfer error */ 628 if (status != XHCI_TRB_ERROR_SHORT_PKT && 629 status != XHCI_TRB_ERROR_SUCCESS) { 630 /* the transfer is finished */ 631 td = NULL; 632 break; 633 } 634 /* Check for short transfer */ 635 if (len > 0) { 636 if (xfer->flags_int.short_frames_ok || 637 xfer->flags_int.isochronous_xfr || 638 xfer->flags_int.control_xfr) { 639 /* follow alt next */ 640 td = td->alt_next; 641 } else { 642 /* the transfer is finished */ 643 td = NULL; 644 } 645 break; 646 } 647 td = td->obj_next; 648 649 if (td->alt_next != td_alt_next) { 650 /* this USB frame is complete */ 651 break; 652 } 653 } 654 655 /* update transfer cache */ 656 657 xfer->td_transfer_cache = td; 658 659 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 660 (status != XHCI_TRB_ERROR_SHORT_PKT && 661 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 662 USB_ERR_NORMAL_COMPLETION); 663 } 664 665 static void 666 xhci_generic_done(struct usb_xfer *xfer) 667 { 668 usb_error_t err = 0; 669 670 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 671 xfer, xfer->endpoint); 672 673 /* reset scanner */ 674 675 xfer->td_transfer_cache = xfer->td_transfer_first; 676 677 if (xfer->flags_int.control_xfr) { 678 679 if (xfer->flags_int.control_hdr) 680 err = xhci_generic_done_sub(xfer); 681 682 xfer->aframes = 1; 683 684 if (xfer->td_transfer_cache == NULL) 685 goto done; 686 } 687 688 while (xfer->aframes != xfer->nframes) { 689 690 err = xhci_generic_done_sub(xfer); 691 xfer->aframes++; 692 693 if (xfer->td_transfer_cache == NULL) 694 goto done; 695 } 696 697 if (xfer->flags_int.control_xfr && 698 !xfer->flags_int.control_act) 699 err = xhci_generic_done_sub(xfer); 700 done: 701 /* transfer is complete */ 702 xhci_device_done(xfer, err); 703 } 704 705 static void 706 xhci_activate_transfer(struct usb_xfer *xfer) 707 { 708 struct xhci_td *td; 709 710 td = xfer->td_transfer_cache; 711 712 usb_pc_cpu_invalidate(td->page_cache); 713 714 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 715 716 /* activate the transfer */ 717 718 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 719 usb_pc_cpu_flush(td->page_cache); 720 721 xhci_endpoint_doorbell(xfer); 722 } 723 } 724 725 static void 726 xhci_skip_transfer(struct usb_xfer *xfer) 727 { 728 struct xhci_td *td; 729 struct xhci_td *td_last; 730 731 td = xfer->td_transfer_cache; 732 td_last = xfer->td_transfer_last; 733 734 td = td->alt_next; 735 736 usb_pc_cpu_invalidate(td->page_cache); 737 738 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 739 740 usb_pc_cpu_invalidate(td_last->page_cache); 741 742 /* copy LINK TRB to current waiting location */ 743 744 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 745 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 746 usb_pc_cpu_flush(td->page_cache); 747 748 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 749 usb_pc_cpu_flush(td->page_cache); 750 751 xhci_endpoint_doorbell(xfer); 752 } 753 } 754 755 /*------------------------------------------------------------------------* 756 * xhci_check_transfer 757 *------------------------------------------------------------------------*/ 758 static void 759 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 760 { 761 int64_t offset; 762 uint64_t td_event; 763 uint32_t temp; 764 uint32_t remainder; 765 uint32_t length; 766 uint8_t status; 767 uint8_t halted; 768 uint8_t epno; 769 uint8_t index; 770 uint8_t i; 771 772 /* decode TRB */ 773 td_event = le64toh(trb->qwTrb0); 774 temp = le32toh(trb->dwTrb2); 775 776 length = XHCI_TRB_2_BYTES_GET(temp); 777 remainder = XHCI_TRB_2_REM_GET(temp); 778 status = XHCI_TRB_2_ERROR_GET(temp); 779 780 temp = le32toh(trb->dwTrb3); 781 epno = XHCI_TRB_3_EP_GET(temp); 782 index = XHCI_TRB_3_SLOT_GET(temp); 783 784 /* check if error means halted */ 785 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 786 status != XHCI_TRB_ERROR_SUCCESS); 787 788 DPRINTF("slot=%u epno=%u remainder=%u status=%u length=%u\n", 789 index, epno, remainder, status, length); 790 791 if (index > sc->sc_noslot) { 792 DPRINTF("Invalid slot.\n"); 793 return; 794 } 795 796 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 797 DPRINTF("Invalid endpoint.\n"); 798 return; 799 } 800 801 /* try to find the USB transfer that generated the event */ 802 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 803 struct usb_xfer *xfer; 804 struct xhci_td *td; 805 struct xhci_endpoint_ext *pepext; 806 807 pepext = &sc->sc_hw.devs[index].endp[epno]; 808 809 xfer = pepext->xfer[i]; 810 if (xfer == NULL) 811 continue; 812 813 td = xfer->td_transfer_cache; 814 815 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 816 (long long)td_event, 817 (long long)td->td_self, 818 (long long)td->td_self + sizeof(td->td_trb)); 819 820 /* 821 * NOTE: Some XHCI implementations might not trigger 822 * an event on the last LINK TRB so we need to 823 * consider both the last and second last event 824 * address as conditions for a successful transfer. 825 * 826 * NOTE: We assume that the XHCI will only trigger one 827 * event per chain of TRBs. 828 */ 829 830 offset = td_event - td->td_self; 831 832 if (offset >= 0 && 833 offset < (int64_t)sizeof(td->td_trb)) { 834 835 usb_pc_cpu_invalidate(td->page_cache); 836 837 /* compute rest of remainder, if any */ 838 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 839 temp = le32toh(td->td_trb[i].dwTrb2); 840 remainder += XHCI_TRB_2_BYTES_GET(temp); 841 } 842 843 DPRINTFN(5, "New remainder: %u\n", remainder); 844 845 /* clear isochronous transfer errors */ 846 if (xfer->flags_int.isochronous_xfr) { 847 if (halted) { 848 halted = 0; 849 status = XHCI_TRB_ERROR_SUCCESS; 850 remainder = td->len; 851 } 852 } 853 854 /* "td->remainder" is verified later */ 855 td->remainder = remainder; 856 td->status = status; 857 858 usb_pc_cpu_flush(td->page_cache); 859 860 /* 861 * 1) Last transfer descriptor makes the 862 * transfer done 863 */ 864 if (((void *)td) == xfer->td_transfer_last) { 865 DPRINTF("TD is last\n"); 866 xhci_generic_done(xfer); 867 break; 868 } 869 870 /* 871 * 2) Any kind of error makes the transfer 872 * done 873 */ 874 if (halted) { 875 DPRINTF("TD has I/O error\n"); 876 xhci_generic_done(xfer); 877 break; 878 } 879 880 /* 881 * 3) If there is no alternate next transfer, 882 * a short packet also makes the transfer done 883 */ 884 if (td->remainder > 0) { 885 DPRINTF("TD has short pkt\n"); 886 if (xfer->flags_int.short_frames_ok || 887 xfer->flags_int.isochronous_xfr || 888 xfer->flags_int.control_xfr) { 889 /* follow the alt next */ 890 xfer->td_transfer_cache = td->alt_next; 891 xhci_activate_transfer(xfer); 892 break; 893 } 894 xhci_skip_transfer(xfer); 895 xhci_generic_done(xfer); 896 break; 897 } 898 899 /* 900 * 4) Transfer complete - go to next TD 901 */ 902 DPRINTF("Following next TD\n"); 903 xfer->td_transfer_cache = td->obj_next; 904 xhci_activate_transfer(xfer); 905 break; /* there should only be one match */ 906 } 907 } 908 } 909 910 static void 911 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 912 { 913 if (sc->sc_cmd_addr == trb->qwTrb0) { 914 DPRINTF("Received command event\n"); 915 sc->sc_cmd_result[0] = trb->dwTrb2; 916 sc->sc_cmd_result[1] = trb->dwTrb3; 917 cv_signal(&sc->sc_cmd_cv); 918 } 919 } 920 921 static void 922 xhci_interrupt_poll(struct xhci_softc *sc) 923 { 924 struct usb_page_search buf_res; 925 struct xhci_hw_root *phwr; 926 uint64_t addr; 927 uint32_t temp; 928 uint16_t i; 929 uint8_t event; 930 uint8_t j; 931 uint8_t k; 932 uint8_t t; 933 934 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 935 936 phwr = buf_res.buffer; 937 938 /* Receive any events */ 939 940 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 941 942 i = sc->sc_event_idx; 943 j = sc->sc_event_ccs; 944 t = 2; 945 946 while (1) { 947 948 temp = le32toh(phwr->hwr_events[i].dwTrb3); 949 950 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 951 952 if (j != k) 953 break; 954 955 event = XHCI_TRB_3_TYPE_GET(temp); 956 957 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 958 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 959 (long)le32toh(phwr->hwr_events[i].dwTrb2), 960 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 961 962 switch (event) { 963 case XHCI_TRB_EVENT_TRANSFER: 964 xhci_check_transfer(sc, &phwr->hwr_events[i]); 965 break; 966 case XHCI_TRB_EVENT_CMD_COMPLETE: 967 xhci_check_command(sc, &phwr->hwr_events[i]); 968 break; 969 default: 970 DPRINTFN(10, "Unhandled event = %u\n", event); 971 break; 972 } 973 974 i++; 975 976 if (i == XHCI_MAX_EVENTS) { 977 i = 0; 978 j ^= 1; 979 980 /* check for timeout */ 981 if (!--t) 982 break; 983 } 984 } 985 986 sc->sc_event_idx = i; 987 sc->sc_event_ccs = j; 988 989 /* 990 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 991 * latched. That means to activate the register we need to 992 * write both the low and high double word of the 64-bit 993 * register. 994 */ 995 996 addr = (uint32_t)buf_res.physaddr; 997 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 998 999 /* try to clear busy bit */ 1000 addr |= XHCI_ERDP_LO_BUSY; 1001 1002 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1003 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1004 } 1005 1006 static usb_error_t 1007 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1008 uint16_t timeout_ms) 1009 { 1010 struct usb_page_search buf_res; 1011 struct xhci_hw_root *phwr; 1012 uint64_t addr; 1013 uint32_t temp; 1014 uint8_t i; 1015 uint8_t j; 1016 int err; 1017 1018 XHCI_CMD_ASSERT_LOCKED(sc); 1019 1020 /* get hardware root structure */ 1021 1022 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1023 1024 phwr = buf_res.buffer; 1025 1026 /* Queue command */ 1027 1028 USB_BUS_LOCK(&sc->sc_bus); 1029 1030 i = sc->sc_command_idx; 1031 j = sc->sc_command_ccs; 1032 1033 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1034 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1035 (long long)le64toh(trb->qwTrb0), 1036 (long)le32toh(trb->dwTrb2), 1037 (long)le32toh(trb->dwTrb3)); 1038 1039 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1040 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1041 1042 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1043 1044 temp = trb->dwTrb3; 1045 1046 if (j) 1047 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1048 else 1049 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1050 1051 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1052 1053 phwr->hwr_commands[i].dwTrb3 = temp; 1054 1055 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1056 1057 addr = buf_res.physaddr; 1058 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1059 1060 sc->sc_cmd_addr = htole64(addr); 1061 1062 i++; 1063 1064 if (i == (XHCI_MAX_COMMANDS - 1)) { 1065 1066 if (j) { 1067 temp = htole32(XHCI_TRB_3_TC_BIT | 1068 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1069 XHCI_TRB_3_CYCLE_BIT); 1070 } else { 1071 temp = htole32(XHCI_TRB_3_TC_BIT | 1072 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1073 } 1074 1075 phwr->hwr_commands[i].dwTrb3 = temp; 1076 1077 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1078 1079 i = 0; 1080 j ^= 1; 1081 } 1082 1083 sc->sc_command_idx = i; 1084 sc->sc_command_ccs = j; 1085 1086 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1087 1088 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_lock, 1089 USB_MS_TO_TICKS(timeout_ms)); 1090 1091 if (err) { 1092 DPRINTFN(0, "Command timeout!\n"); 1093 err = USB_ERR_TIMEOUT; 1094 trb->dwTrb2 = 0; 1095 trb->dwTrb3 = 0; 1096 } else { 1097 temp = le32toh(sc->sc_cmd_result[0]); 1098 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1099 err = USB_ERR_IOERROR; 1100 1101 trb->dwTrb2 = sc->sc_cmd_result[0]; 1102 trb->dwTrb3 = sc->sc_cmd_result[1]; 1103 } 1104 1105 USB_BUS_UNLOCK(&sc->sc_bus); 1106 1107 return (err); 1108 } 1109 1110 #if 0 1111 static usb_error_t 1112 xhci_cmd_nop(struct xhci_softc *sc) 1113 { 1114 struct xhci_trb trb; 1115 uint32_t temp; 1116 1117 DPRINTF("\n"); 1118 1119 trb.qwTrb0 = 0; 1120 trb.dwTrb2 = 0; 1121 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1122 1123 trb.dwTrb3 = htole32(temp); 1124 1125 return (xhci_do_command(sc, &trb, 250 /* ms */)); 1126 } 1127 #endif 1128 1129 static usb_error_t 1130 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1131 { 1132 struct xhci_trb trb; 1133 uint32_t temp; 1134 usb_error_t err; 1135 1136 DPRINTF("\n"); 1137 1138 trb.qwTrb0 = 0; 1139 trb.dwTrb2 = 0; 1140 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1141 1142 err = xhci_do_command(sc, &trb, 250 /* ms */); 1143 if (err) 1144 goto done; 1145 1146 temp = le32toh(trb.dwTrb3); 1147 1148 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1149 1150 done: 1151 return (err); 1152 } 1153 1154 static usb_error_t 1155 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1156 { 1157 struct xhci_trb trb; 1158 uint32_t temp; 1159 1160 DPRINTF("\n"); 1161 1162 trb.qwTrb0 = 0; 1163 trb.dwTrb2 = 0; 1164 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1165 XHCI_TRB_3_SLOT_SET(slot_id); 1166 1167 trb.dwTrb3 = htole32(temp); 1168 1169 return (xhci_do_command(sc, &trb, 250 /* ms */)); 1170 } 1171 1172 static usb_error_t 1173 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1174 uint8_t bsr, uint8_t slot_id) 1175 { 1176 struct xhci_trb trb; 1177 uint32_t temp; 1178 1179 DPRINTF("\n"); 1180 1181 trb.qwTrb0 = htole64(input_ctx); 1182 trb.dwTrb2 = 0; 1183 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1184 XHCI_TRB_3_SLOT_SET(slot_id); 1185 1186 if (bsr) 1187 temp |= XHCI_TRB_3_BSR_BIT; 1188 1189 trb.dwTrb3 = htole32(temp); 1190 1191 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1192 } 1193 1194 static usb_error_t 1195 xhci_set_address(struct usb_device *udev, struct lock *lock, uint16_t address) 1196 { 1197 struct usb_page_search buf_inp; 1198 struct usb_page_search buf_dev; 1199 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1200 struct xhci_hw_dev *hdev; 1201 struct xhci_dev_ctx *pdev; 1202 struct xhci_endpoint_ext *pepext; 1203 uint32_t temp; 1204 uint16_t mps; 1205 usb_error_t err; 1206 uint8_t index; 1207 1208 /* the root HUB case is not handled here */ 1209 if (udev->parent_hub == NULL) 1210 return (USB_ERR_INVAL); 1211 1212 index = udev->controller_slot_id; 1213 1214 hdev = &sc->sc_hw.devs[index]; 1215 1216 if (lock != NULL) 1217 lockmgr(lock, LK_RELEASE); 1218 1219 XHCI_CMD_LOCK(sc); 1220 1221 switch (hdev->state) { 1222 case XHCI_ST_DEFAULT: 1223 case XHCI_ST_ENABLED: 1224 1225 hdev->state = XHCI_ST_ENABLED; 1226 1227 /* set configure mask to slot and EP0 */ 1228 xhci_configure_mask(udev, 3, 0); 1229 1230 /* configure input slot context structure */ 1231 err = xhci_configure_device(udev); 1232 1233 if (err != 0) { 1234 DPRINTF("Could not configure device\n"); 1235 break; 1236 } 1237 1238 /* configure input endpoint context structure */ 1239 switch (udev->speed) { 1240 case USB_SPEED_LOW: 1241 case USB_SPEED_FULL: 1242 mps = 8; 1243 break; 1244 case USB_SPEED_HIGH: 1245 mps = 64; 1246 break; 1247 default: 1248 mps = 512; 1249 break; 1250 } 1251 1252 pepext = xhci_get_endpoint_ext(udev, 1253 &udev->ctrl_ep_desc); 1254 err = xhci_configure_endpoint(udev, 1255 &udev->ctrl_ep_desc, pepext->physaddr, 1256 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1257 1258 if (err != 0) { 1259 DPRINTF("Could not configure default endpoint\n"); 1260 break; 1261 } 1262 1263 /* execute set address command */ 1264 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1265 1266 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1267 (address == 0), index); 1268 1269 if (err != 0) { 1270 DPRINTF("Could not set address " 1271 "for slot %u.\n", index); 1272 if (address != 0) 1273 break; 1274 } 1275 1276 /* update device address to new value */ 1277 1278 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1279 pdev = buf_dev.buffer; 1280 usb_pc_cpu_invalidate(&hdev->device_pc); 1281 1282 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1283 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1284 1285 /* update device state to new value */ 1286 1287 if (address != 0) 1288 hdev->state = XHCI_ST_ADDRESSED; 1289 else 1290 hdev->state = XHCI_ST_DEFAULT; 1291 break; 1292 1293 default: 1294 DPRINTF("Wrong state for set address.\n"); 1295 err = USB_ERR_IOERROR; 1296 break; 1297 } 1298 XHCI_CMD_UNLOCK(sc); 1299 1300 if (lock != NULL) 1301 lockmgr(lock, LK_EXCLUSIVE); 1302 1303 return (err); 1304 } 1305 1306 static usb_error_t 1307 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1308 uint8_t deconfigure, uint8_t slot_id) 1309 { 1310 struct xhci_trb trb; 1311 uint32_t temp; 1312 1313 DPRINTF("\n"); 1314 1315 trb.qwTrb0 = htole64(input_ctx); 1316 trb.dwTrb2 = 0; 1317 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1318 XHCI_TRB_3_SLOT_SET(slot_id); 1319 1320 if (deconfigure) 1321 temp |= XHCI_TRB_3_DCEP_BIT; 1322 1323 trb.dwTrb3 = htole32(temp); 1324 1325 return (xhci_do_command(sc, &trb, 250 /* ms */)); 1326 } 1327 1328 static usb_error_t 1329 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1330 uint8_t slot_id) 1331 { 1332 struct xhci_trb trb; 1333 uint32_t temp; 1334 1335 DPRINTF("\n"); 1336 1337 trb.qwTrb0 = htole64(input_ctx); 1338 trb.dwTrb2 = 0; 1339 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1340 XHCI_TRB_3_SLOT_SET(slot_id); 1341 trb.dwTrb3 = htole32(temp); 1342 1343 return (xhci_do_command(sc, &trb, 250 /* ms */)); 1344 } 1345 1346 static usb_error_t 1347 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1348 uint8_t ep_id, uint8_t slot_id) 1349 { 1350 struct xhci_trb trb; 1351 uint32_t temp; 1352 1353 DPRINTF("\n"); 1354 1355 trb.qwTrb0 = 0; 1356 trb.dwTrb2 = 0; 1357 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1358 XHCI_TRB_3_SLOT_SET(slot_id) | 1359 XHCI_TRB_3_EP_SET(ep_id); 1360 1361 if (preserve) 1362 temp |= XHCI_TRB_3_PRSV_BIT; 1363 1364 trb.dwTrb3 = htole32(temp); 1365 1366 return (xhci_do_command(sc, &trb, 250 /* ms */)); 1367 } 1368 1369 static usb_error_t 1370 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1371 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1372 { 1373 struct xhci_trb trb; 1374 uint32_t temp; 1375 1376 DPRINTF("\n"); 1377 1378 trb.qwTrb0 = htole64(dequeue_ptr); 1379 1380 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1381 trb.dwTrb2 = htole32(temp); 1382 1383 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1384 XHCI_TRB_3_SLOT_SET(slot_id) | 1385 XHCI_TRB_3_EP_SET(ep_id); 1386 trb.dwTrb3 = htole32(temp); 1387 1388 return (xhci_do_command(sc, &trb, 250 /* ms */)); 1389 } 1390 1391 static usb_error_t 1392 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1393 uint8_t ep_id, uint8_t slot_id) 1394 { 1395 struct xhci_trb trb; 1396 uint32_t temp; 1397 1398 DPRINTF("\n"); 1399 1400 trb.qwTrb0 = 0; 1401 trb.dwTrb2 = 0; 1402 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1403 XHCI_TRB_3_SLOT_SET(slot_id) | 1404 XHCI_TRB_3_EP_SET(ep_id); 1405 1406 if (suspend) 1407 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1408 1409 trb.dwTrb3 = htole32(temp); 1410 1411 return (xhci_do_command(sc, &trb, 250 /* ms */)); 1412 } 1413 1414 static usb_error_t 1415 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1416 { 1417 struct xhci_trb trb; 1418 uint32_t temp; 1419 1420 DPRINTF("\n"); 1421 1422 trb.qwTrb0 = 0; 1423 trb.dwTrb2 = 0; 1424 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1425 XHCI_TRB_3_SLOT_SET(slot_id); 1426 1427 trb.dwTrb3 = htole32(temp); 1428 1429 return (xhci_do_command(sc, &trb, 250 /* ms */)); 1430 } 1431 1432 /*------------------------------------------------------------------------* 1433 * xhci_interrupt - XHCI interrupt handler 1434 *------------------------------------------------------------------------*/ 1435 void 1436 xhci_interrupt(struct xhci_softc *sc) 1437 { 1438 uint32_t status; 1439 uint32_t temp; 1440 1441 USB_BUS_LOCK(&sc->sc_bus); 1442 1443 status = XREAD4(sc, oper, XHCI_USBSTS); 1444 1445 /* acknowledge interrupts */ 1446 1447 XWRITE4(sc, oper, XHCI_USBSTS, status); 1448 1449 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1450 1451 /* acknowledge pending event */ 1452 1453 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1454 1455 DPRINTFN(16, "real interrupt (sts=0x%08x, " 1456 "iman=0x%08x)\n", status, temp); 1457 1458 if (status != 0) { 1459 if (status & XHCI_STS_PCD) { 1460 xhci_root_intr(sc); 1461 } 1462 1463 if (status & XHCI_STS_HCH) { 1464 kprintf("%s: host controller halted\n", 1465 __func__); 1466 } 1467 1468 if (status & XHCI_STS_HSE) { 1469 kprintf("%s: host system error\n", 1470 __func__); 1471 } 1472 1473 if (status & XHCI_STS_HCE) { 1474 kprintf("%s: host controller error\n", 1475 __func__); 1476 } 1477 } 1478 1479 xhci_interrupt_poll(sc); 1480 1481 USB_BUS_UNLOCK(&sc->sc_bus); 1482 } 1483 1484 /*------------------------------------------------------------------------* 1485 * xhci_timeout - XHCI timeout handler 1486 *------------------------------------------------------------------------*/ 1487 static void 1488 xhci_timeout(void *arg) 1489 { 1490 struct usb_xfer *xfer = arg; 1491 1492 DPRINTF("xfer=%p\n", xfer); 1493 1494 USB_BUS_LOCK_ASSERT(xfer->xroot->bus); 1495 1496 /* transfer is transferred */ 1497 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1498 } 1499 1500 static void 1501 xhci_do_poll(struct usb_bus *bus) 1502 { 1503 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1504 1505 USB_BUS_LOCK(&sc->sc_bus); 1506 xhci_interrupt_poll(sc); 1507 USB_BUS_UNLOCK(&sc->sc_bus); 1508 } 1509 1510 static void 1511 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1512 { 1513 struct usb_page_search buf_res; 1514 struct xhci_td *td; 1515 struct xhci_td *td_next; 1516 struct xhci_td *td_alt_next; 1517 uint32_t buf_offset; 1518 uint32_t average; 1519 uint32_t len_old; 1520 uint32_t dword; 1521 uint8_t shortpkt_old; 1522 uint8_t precompute; 1523 uint8_t x; 1524 1525 td_alt_next = NULL; 1526 buf_offset = 0; 1527 shortpkt_old = temp->shortpkt; 1528 len_old = temp->len; 1529 precompute = 1; 1530 1531 restart: 1532 1533 td = temp->td; 1534 td_next = temp->td_next; 1535 1536 while (1) { 1537 1538 if (temp->len == 0) { 1539 1540 if (temp->shortpkt) 1541 break; 1542 1543 /* send a Zero Length Packet, ZLP, last */ 1544 1545 temp->shortpkt = 1; 1546 average = 0; 1547 1548 } else { 1549 1550 average = temp->average; 1551 1552 if (temp->len < average) { 1553 if (temp->len % temp->max_packet_size) { 1554 temp->shortpkt = 1; 1555 } 1556 average = temp->len; 1557 } 1558 } 1559 1560 if (td_next == NULL) 1561 panic("%s: out of XHCI transfer descriptors!", __func__); 1562 1563 /* get next TD */ 1564 1565 td = td_next; 1566 td_next = td->obj_next; 1567 1568 /* check if we are pre-computing */ 1569 1570 if (precompute) { 1571 1572 /* update remaining length */ 1573 1574 temp->len -= average; 1575 1576 continue; 1577 } 1578 /* fill out current TD */ 1579 1580 td->len = average; 1581 td->remainder = 0; 1582 td->status = 0; 1583 1584 /* update remaining length */ 1585 1586 temp->len -= average; 1587 1588 /* reset TRB index */ 1589 1590 x = 0; 1591 1592 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1593 /* immediate data */ 1594 1595 if (average > 8) 1596 average = 8; 1597 1598 td->td_trb[0].qwTrb0 = 0; 1599 1600 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1601 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1602 average); 1603 1604 dword = XHCI_TRB_2_BYTES_SET(8) | 1605 XHCI_TRB_2_TDSZ_SET(0) | 1606 XHCI_TRB_2_IRQ_SET(0); 1607 1608 td->td_trb[0].dwTrb2 = htole32(dword); 1609 1610 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1611 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1612 1613 /* check wLength */ 1614 if (td->td_trb[0].qwTrb0 & 1615 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1616 if (td->td_trb[0].qwTrb0 & htole64(1)) 1617 dword |= XHCI_TRB_3_TRT_IN; 1618 else 1619 dword |= XHCI_TRB_3_TRT_OUT; 1620 } 1621 1622 td->td_trb[0].dwTrb3 = htole32(dword); 1623 #ifdef USB_DEBUG 1624 xhci_dump_trb(&td->td_trb[x]); 1625 #endif 1626 x++; 1627 1628 } else do { 1629 1630 uint32_t npkt; 1631 1632 /* fill out buffer pointers */ 1633 1634 if (average == 0) { 1635 npkt = 1; 1636 memset(&buf_res, 0, sizeof(buf_res)); 1637 } else { 1638 usbd_get_page(temp->pc, temp->offset + 1639 buf_offset, &buf_res); 1640 1641 /* get length to end of page */ 1642 if (buf_res.length > average) 1643 buf_res.length = average; 1644 1645 /* check for maximum length */ 1646 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1647 buf_res.length = XHCI_TD_PAGE_SIZE; 1648 1649 /* setup npkt */ 1650 npkt = (average + temp->max_packet_size - 1) / 1651 temp->max_packet_size; 1652 1653 if (npkt > 31) 1654 npkt = 31; 1655 } 1656 1657 /* fill out TRB's */ 1658 td->td_trb[x].qwTrb0 = 1659 htole64((uint64_t)buf_res.physaddr); 1660 1661 dword = 1662 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1663 XHCI_TRB_2_TDSZ_SET(npkt) | 1664 XHCI_TRB_2_IRQ_SET(0); 1665 1666 td->td_trb[x].dwTrb2 = htole32(dword); 1667 1668 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1669 XHCI_TRB_3_TYPE_SET(temp->trb_type) | 1670 (temp->do_isoc_sync ? 1671 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) : 1672 XHCI_TRB_3_ISO_SIA_BIT) | 1673 XHCI_TRB_3_TBC_SET(temp->tbc) | 1674 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1675 1676 temp->do_isoc_sync = 0; 1677 1678 if (temp->direction == UE_DIR_IN) { 1679 dword |= XHCI_TRB_3_DIR_IN; 1680 1681 /* 1682 * NOTE: Only the SETUP stage should 1683 * use the IDT bit. Else transactions 1684 * can be sent using the wrong data 1685 * toggle value. 1686 */ 1687 if (temp->trb_type != 1688 XHCI_TRB_TYPE_SETUP_STAGE && 1689 temp->trb_type != 1690 XHCI_TRB_TYPE_STATUS_STAGE) 1691 dword |= XHCI_TRB_3_ISP_BIT; 1692 } 1693 1694 td->td_trb[x].dwTrb3 = htole32(dword); 1695 1696 average -= buf_res.length; 1697 buf_offset += buf_res.length; 1698 #ifdef USB_DEBUG 1699 xhci_dump_trb(&td->td_trb[x]); 1700 #endif 1701 x++; 1702 1703 } while (average != 0); 1704 1705 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1706 1707 /* store number of data TRB's */ 1708 1709 td->ntrb = x; 1710 1711 DPRINTF("NTRB=%u\n", x); 1712 1713 /* fill out link TRB */ 1714 1715 if (td_next != NULL) { 1716 /* link the current TD with the next one */ 1717 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1718 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1719 } else { 1720 /* this field will get updated later */ 1721 DPRINTF("NOLINK\n"); 1722 } 1723 1724 dword = XHCI_TRB_2_IRQ_SET(0); 1725 1726 td->td_trb[x].dwTrb2 = htole32(dword); 1727 1728 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1729 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT; 1730 1731 td->td_trb[x].dwTrb3 = htole32(dword); 1732 1733 td->alt_next = td_alt_next; 1734 #ifdef USB_DEBUG 1735 xhci_dump_trb(&td->td_trb[x]); 1736 #endif 1737 usb_pc_cpu_flush(td->page_cache); 1738 } 1739 1740 if (precompute) { 1741 precompute = 0; 1742 1743 /* setup alt next pointer, if any */ 1744 if (temp->last_frame) { 1745 td_alt_next = NULL; 1746 } else { 1747 /* we use this field internally */ 1748 td_alt_next = td_next; 1749 } 1750 1751 /* restore */ 1752 temp->shortpkt = shortpkt_old; 1753 temp->len = len_old; 1754 goto restart; 1755 } 1756 1757 /* remove cycle bit from first if we are stepping the TRBs */ 1758 if (temp->step_td) 1759 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1760 1761 /* remove chain bit because this is the last TRB in the chain */ 1762 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1763 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1764 1765 usb_pc_cpu_flush(td->page_cache); 1766 1767 temp->td = td; 1768 temp->td_next = td_next; 1769 } 1770 1771 static void 1772 xhci_setup_generic_chain(struct usb_xfer *xfer) 1773 { 1774 struct xhci_std_temp temp; 1775 struct xhci_td *td; 1776 uint32_t x; 1777 uint32_t y; 1778 uint8_t mult; 1779 1780 temp.do_isoc_sync = 0; 1781 temp.step_td = 0; 1782 temp.tbc = 0; 1783 temp.tlbpc = 0; 1784 temp.average = xfer->max_hc_frame_size; 1785 temp.max_packet_size = xfer->max_packet_size; 1786 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1787 temp.pc = NULL; 1788 temp.last_frame = 0; 1789 temp.offset = 0; 1790 temp.multishort = xfer->flags_int.isochronous_xfr || 1791 xfer->flags_int.control_xfr || 1792 xfer->flags_int.short_frames_ok; 1793 1794 /* toggle the DMA set we are using */ 1795 xfer->flags_int.curr_dma_set ^= 1; 1796 1797 /* get next DMA set */ 1798 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1799 1800 temp.td = NULL; 1801 temp.td_next = td; 1802 1803 xfer->td_transfer_first = td; 1804 xfer->td_transfer_cache = td; 1805 1806 if (xfer->flags_int.isochronous_xfr) { 1807 uint8_t shift; 1808 1809 /* compute multiplier for ISOCHRONOUS transfers */ 1810 mult = xfer->endpoint->ecomp ? 1811 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) : 0; 1812 /* check for USB 2.0 multiplier */ 1813 if (mult == 0) { 1814 mult = (xfer->endpoint->edesc-> 1815 wMaxPacketSize[1] >> 3) & 3; 1816 } 1817 /* range check */ 1818 if (mult > 2) 1819 mult = 3; 1820 else 1821 mult++; 1822 1823 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 1824 1825 DPRINTF("MFINDEX=0x%08x\n", x); 1826 1827 switch (usbd_get_speed(xfer->xroot->udev)) { 1828 case USB_SPEED_FULL: 1829 shift = 3; 1830 temp.isoc_delta = 8; /* 1ms */ 1831 x += temp.isoc_delta - 1; 1832 x &= ~(temp.isoc_delta - 1); 1833 break; 1834 default: 1835 shift = usbd_xfer_get_fps_shift(xfer); 1836 temp.isoc_delta = 1U << shift; 1837 x += temp.isoc_delta - 1; 1838 x &= ~(temp.isoc_delta - 1); 1839 /* simple frame load balancing */ 1840 x += xfer->endpoint->usb_uframe; 1841 break; 1842 } 1843 1844 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 1845 1846 if ((xfer->endpoint->is_synced == 0) || 1847 (y < (xfer->nframes << shift)) || 1848 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 1849 /* 1850 * If there is data underflow or the pipe 1851 * queue is empty we schedule the transfer a 1852 * few frames ahead of the current frame 1853 * position. Else two isochronous transfers 1854 * might overlap. 1855 */ 1856 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 1857 xfer->endpoint->is_synced = 1; 1858 temp.do_isoc_sync = 1; 1859 1860 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1861 } 1862 1863 /* compute isochronous completion time */ 1864 1865 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 1866 1867 xfer->isoc_time_complete = 1868 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 1869 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 1870 1871 x = 0; 1872 temp.isoc_frame = xfer->endpoint->isoc_next; 1873 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 1874 1875 xfer->endpoint->isoc_next += xfer->nframes << shift; 1876 1877 } else if (xfer->flags_int.control_xfr) { 1878 1879 /* check if we should prepend a setup message */ 1880 1881 if (xfer->flags_int.control_hdr) { 1882 1883 temp.len = xfer->frlengths[0]; 1884 temp.pc = xfer->frbuffers + 0; 1885 temp.shortpkt = temp.len ? 1 : 0; 1886 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 1887 temp.direction = 0; 1888 1889 /* check for last frame */ 1890 if (xfer->nframes == 1) { 1891 /* no STATUS stage yet, SETUP is last */ 1892 if (xfer->flags_int.control_act) 1893 temp.last_frame = 1; 1894 } 1895 1896 xhci_setup_generic_chain_sub(&temp); 1897 } 1898 x = 1; 1899 mult = 1; 1900 temp.isoc_delta = 0; 1901 temp.isoc_frame = 0; 1902 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 1903 } else { 1904 x = 0; 1905 mult = 1; 1906 temp.isoc_delta = 0; 1907 temp.isoc_frame = 0; 1908 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 1909 } 1910 1911 if (x != xfer->nframes) { 1912 /* setup page_cache pointer */ 1913 temp.pc = xfer->frbuffers + x; 1914 /* set endpoint direction */ 1915 temp.direction = UE_GET_DIR(xfer->endpointno); 1916 } 1917 1918 while (x != xfer->nframes) { 1919 1920 /* DATA0 / DATA1 message */ 1921 1922 temp.len = xfer->frlengths[x]; 1923 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 1924 x != 0 && temp.multishort == 0); 1925 1926 x++; 1927 1928 if (x == xfer->nframes) { 1929 if (xfer->flags_int.control_xfr) { 1930 /* no STATUS stage yet, DATA is last */ 1931 if (xfer->flags_int.control_act) 1932 temp.last_frame = 1; 1933 } else { 1934 temp.last_frame = 1; 1935 } 1936 } 1937 if (temp.len == 0) { 1938 1939 /* make sure that we send an USB packet */ 1940 1941 temp.shortpkt = 0; 1942 1943 temp.tbc = 0; 1944 temp.tlbpc = mult - 1; 1945 1946 } else if (xfer->flags_int.isochronous_xfr) { 1947 1948 uint8_t tdpc; 1949 1950 /* isochronous transfers don't have short packet termination */ 1951 1952 temp.shortpkt = 1; 1953 1954 /* isochronous transfers have a transfer limit */ 1955 1956 if (temp.len > xfer->max_frame_size) 1957 temp.len = xfer->max_frame_size; 1958 1959 /* compute TD packet count */ 1960 tdpc = (temp.len + xfer->max_packet_size - 1) / 1961 xfer->max_packet_size; 1962 1963 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 1964 temp.tlbpc = (tdpc % mult); 1965 1966 if (temp.tlbpc == 0) 1967 temp.tlbpc = mult - 1; 1968 else 1969 temp.tlbpc--; 1970 } else { 1971 1972 /* regular data transfer */ 1973 1974 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 1975 } 1976 1977 xhci_setup_generic_chain_sub(&temp); 1978 1979 if (xfer->flags_int.isochronous_xfr) { 1980 temp.offset += xfer->frlengths[x - 1]; 1981 temp.isoc_frame += temp.isoc_delta; 1982 } else { 1983 /* get next Page Cache pointer */ 1984 temp.pc = xfer->frbuffers + x; 1985 } 1986 } 1987 1988 /* check if we should append a status stage */ 1989 1990 if (xfer->flags_int.control_xfr && 1991 !xfer->flags_int.control_act) { 1992 1993 /* 1994 * Send a DATA1 message and invert the current 1995 * endpoint direction. 1996 */ 1997 temp.step_td = (xfer->nframes != 0); 1998 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 1999 temp.len = 0; 2000 temp.pc = NULL; 2001 temp.shortpkt = 0; 2002 temp.last_frame = 1; 2003 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2004 2005 xhci_setup_generic_chain_sub(&temp); 2006 } 2007 2008 td = temp.td; 2009 2010 /* must have at least one frame! */ 2011 2012 xfer->td_transfer_last = td; 2013 2014 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2015 } 2016 2017 static void 2018 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2019 { 2020 struct usb_page_search buf_res; 2021 struct xhci_dev_ctx_addr *pdctxa; 2022 2023 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2024 2025 pdctxa = buf_res.buffer; 2026 2027 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2028 2029 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2030 2031 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2032 } 2033 2034 static usb_error_t 2035 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2036 { 2037 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2038 struct usb_page_search buf_inp; 2039 struct xhci_input_dev_ctx *pinp; 2040 uint32_t temp; 2041 uint8_t index; 2042 uint8_t x; 2043 2044 index = udev->controller_slot_id; 2045 2046 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2047 2048 pinp = buf_inp.buffer; 2049 2050 if (drop) { 2051 mask &= XHCI_INCTX_NON_CTRL_MASK; 2052 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2053 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2054 } else { 2055 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2056 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask | 1); 2057 2058 /* find most significant set bit */ 2059 for (x = 31; x != 1; x--) { 2060 if (mask & (1 << x)) 2061 break; 2062 } 2063 2064 /* adjust */ 2065 x--; 2066 2067 /* figure out maximum */ 2068 if (x > sc->sc_hw.devs[index].context_num) { 2069 sc->sc_hw.devs[index].context_num = x; 2070 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2071 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2072 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2073 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2074 } 2075 } 2076 return (0); 2077 } 2078 2079 static usb_error_t 2080 xhci_configure_endpoint(struct usb_device *udev, 2081 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr, 2082 uint16_t interval, uint8_t max_packet_count, uint8_t mult, 2083 uint8_t fps_shift, uint16_t max_packet_size, 2084 uint16_t max_frame_size, uint8_t ep_mode) 2085 { 2086 struct usb_page_search buf_inp; 2087 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2088 struct xhci_input_dev_ctx *pinp; 2089 uint32_t temp; 2090 uint8_t index; 2091 uint8_t epno; 2092 uint8_t type; 2093 2094 index = udev->controller_slot_id; 2095 2096 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2097 2098 pinp = buf_inp.buffer; 2099 2100 epno = edesc->bEndpointAddress; 2101 type = edesc->bmAttributes & UE_XFERTYPE; 2102 2103 if (type == UE_CONTROL) 2104 epno |= UE_DIR_IN; 2105 2106 epno = XHCI_EPNO2EPID(epno); 2107 2108 if (epno == 0) 2109 return (USB_ERR_NO_PIPE); /* invalid */ 2110 2111 if (max_packet_count == 0) 2112 return (USB_ERR_BAD_BUFSIZE); 2113 2114 max_packet_count--; 2115 2116 if (mult == 0) 2117 return (USB_ERR_BAD_BUFSIZE); 2118 2119 if (ep_mode == USB_EP_MODE_STREAMS) { 2120 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2121 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2122 XHCI_EPCTX_0_LSA_SET(1); 2123 2124 ring_addr += sizeof(struct xhci_trb) * 2125 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2126 } else { 2127 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2128 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2129 XHCI_EPCTX_0_LSA_SET(0); 2130 2131 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2132 } 2133 2134 switch (udev->speed) { 2135 case USB_SPEED_FULL: 2136 case USB_SPEED_LOW: 2137 /* 1ms -> 125us */ 2138 fps_shift += 3; 2139 break; 2140 default: 2141 break; 2142 } 2143 2144 switch (type) { 2145 case UE_INTERRUPT: 2146 if (fps_shift > 3) 2147 fps_shift--; 2148 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2149 break; 2150 case UE_ISOCHRONOUS: 2151 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2152 2153 switch (udev->speed) { 2154 case USB_SPEED_SUPER: 2155 if (mult > 3) 2156 mult = 3; 2157 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2158 max_packet_count /= mult; 2159 break; 2160 default: 2161 break; 2162 } 2163 break; 2164 default: 2165 break; 2166 } 2167 2168 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2169 2170 temp = 2171 XHCI_EPCTX_1_HID_SET(0) | 2172 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2173 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2174 2175 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2176 if (type != UE_ISOCHRONOUS) 2177 temp |= XHCI_EPCTX_1_CERR_SET(3); 2178 } 2179 2180 switch (type) { 2181 case UE_CONTROL: 2182 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2183 break; 2184 case UE_ISOCHRONOUS: 2185 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2186 break; 2187 case UE_BULK: 2188 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2189 break; 2190 default: 2191 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2192 break; 2193 } 2194 2195 /* check for IN direction */ 2196 if (epno & 1) 2197 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2198 2199 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2200 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2201 2202 switch (edesc->bmAttributes & UE_XFERTYPE) { 2203 case UE_INTERRUPT: 2204 case UE_ISOCHRONOUS: 2205 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2206 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2207 max_frame_size)); 2208 break; 2209 case UE_CONTROL: 2210 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2211 break; 2212 default: 2213 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2214 break; 2215 } 2216 2217 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2218 2219 #ifdef USB_DEBUG 2220 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2221 #endif 2222 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2223 2224 return (0); /* success */ 2225 } 2226 2227 static usb_error_t 2228 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2229 { 2230 struct xhci_endpoint_ext *pepext; 2231 struct usb_endpoint_ss_comp_descriptor *ecomp; 2232 usb_stream_t x; 2233 2234 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2235 xfer->endpoint->edesc); 2236 2237 ecomp = xfer->endpoint->ecomp; 2238 2239 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2240 uint64_t temp; 2241 2242 /* halt any transfers */ 2243 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2244 2245 /* compute start of TRB ring for stream "x" */ 2246 temp = pepext->physaddr + 2247 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2248 XHCI_SCTX_0_SCT_SEC_TR_RING; 2249 2250 /* make tree structure */ 2251 pepext->trb[(XHCI_MAX_TRANSFERS * 2252 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2253 2254 /* reserved fields */ 2255 pepext->trb[(XHCI_MAX_TRANSFERS * 2256 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2257 pepext->trb[(XHCI_MAX_TRANSFERS * 2258 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2259 } 2260 usb_pc_cpu_flush(pepext->page_cache); 2261 2262 return (xhci_configure_endpoint(xfer->xroot->udev, 2263 xfer->endpoint->edesc, pepext->physaddr, 2264 xfer->interval, xfer->max_packet_count, 2265 (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1, 2266 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2267 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2268 } 2269 2270 static usb_error_t 2271 xhci_configure_device(struct usb_device *udev) 2272 { 2273 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2274 struct usb_page_search buf_inp; 2275 struct usb_page_cache *pcinp; 2276 struct xhci_input_dev_ctx *pinp; 2277 struct usb_device *hubdev; 2278 uint32_t temp; 2279 uint32_t route; 2280 uint32_t rh_port; 2281 uint8_t is_hub; 2282 uint8_t index; 2283 uint8_t depth; 2284 2285 index = udev->controller_slot_id; 2286 2287 DPRINTF("index=%u\n", index); 2288 2289 pcinp = &sc->sc_hw.devs[index].input_pc; 2290 2291 usbd_get_page(pcinp, 0, &buf_inp); 2292 2293 pinp = buf_inp.buffer; 2294 2295 rh_port = 0; 2296 route = 0; 2297 2298 /* figure out route string and root HUB port number */ 2299 2300 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2301 2302 if (hubdev->parent_hub == NULL) 2303 break; 2304 2305 depth = hubdev->parent_hub->depth; 2306 2307 /* 2308 * NOTE: HS/FS/LS devices and the SS root HUB can have 2309 * more than 15 ports 2310 */ 2311 2312 rh_port = hubdev->port_no; 2313 2314 if (depth == 0) 2315 break; 2316 2317 if (rh_port > 15) 2318 rh_port = 15; 2319 2320 if (depth < 6) 2321 route |= rh_port << (4 * (depth - 1)); 2322 } 2323 2324 temp = XHCI_SCTX_0_ROUTE_SET(route) 2325 | XHCI_SCTX_0_CTX_NUM_SET( 2326 sc->sc_hw.devs[index].context_num + 1); 2327 2328 switch (udev->speed) { 2329 case USB_SPEED_LOW: 2330 temp |= XHCI_SCTX_0_SPEED_SET(2); 2331 if (udev->parent_hs_hub != NULL && 2332 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2333 UDPROTO_HSHUBMTT) { 2334 DPRINTF("Device inherits MTT\n"); 2335 temp |= XHCI_SCTX_0_MTT_SET(1); 2336 } 2337 break; 2338 case USB_SPEED_HIGH: 2339 temp |= XHCI_SCTX_0_SPEED_SET(3); 2340 if (sc->sc_hw.devs[index].nports != 0 && 2341 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2342 DPRINTF("HUB supports MTT\n"); 2343 temp |= XHCI_SCTX_0_MTT_SET(1); 2344 } 2345 break; 2346 case USB_SPEED_FULL: 2347 temp |= XHCI_SCTX_0_SPEED_SET(1); 2348 if (udev->parent_hs_hub != NULL && 2349 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2350 UDPROTO_HSHUBMTT) { 2351 DPRINTF("Device inherits MTT\n"); 2352 temp |= XHCI_SCTX_0_MTT_SET(1); 2353 } 2354 break; 2355 default: 2356 temp |= XHCI_SCTX_0_SPEED_SET(4); 2357 break; 2358 } 2359 2360 is_hub = sc->sc_hw.devs[index].nports != 0 && 2361 (udev->speed == USB_SPEED_SUPER || 2362 udev->speed == USB_SPEED_HIGH); 2363 2364 if (is_hub) { 2365 temp |= XHCI_SCTX_0_HUB_SET(1); 2366 } 2367 2368 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2369 2370 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2371 2372 if (is_hub) { 2373 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2374 sc->sc_hw.devs[index].nports); 2375 } 2376 2377 switch (udev->speed) { 2378 case USB_SPEED_SUPER: 2379 switch (sc->sc_hw.devs[index].state) { 2380 case XHCI_ST_ADDRESSED: 2381 case XHCI_ST_CONFIGURED: 2382 /* enable power save */ 2383 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2384 break; 2385 default: 2386 /* disable power save */ 2387 break; 2388 } 2389 break; 2390 default: 2391 break; 2392 } 2393 2394 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2395 2396 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2397 2398 if (is_hub) { 2399 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(sc->sc_hw.devs[index].tt); 2400 } 2401 2402 hubdev = udev->parent_hs_hub; 2403 2404 /* check if we should activate the transaction translator */ 2405 switch (udev->speed) { 2406 case USB_SPEED_FULL: 2407 case USB_SPEED_LOW: 2408 if (hubdev != NULL) { 2409 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2410 hubdev->controller_slot_id); 2411 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2412 udev->hs_port_no); 2413 } 2414 break; 2415 default: 2416 break; 2417 } 2418 2419 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2420 2421 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) | 2422 XHCI_SCTX_3_SLOT_STATE_SET(0); 2423 2424 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2425 2426 #ifdef USB_DEBUG 2427 xhci_dump_device(sc, &pinp->ctx_slot); 2428 #endif 2429 usb_pc_cpu_flush(pcinp); 2430 2431 return (0); /* success */ 2432 } 2433 2434 static usb_error_t 2435 xhci_alloc_device_ext(struct usb_device *udev) 2436 { 2437 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2438 struct usb_page_search buf_dev; 2439 struct usb_page_search buf_ep; 2440 struct xhci_trb *trb; 2441 struct usb_page_cache *pc; 2442 struct usb_page *pg; 2443 uint64_t addr; 2444 uint8_t index; 2445 uint8_t i; 2446 2447 index = udev->controller_slot_id; 2448 2449 pc = &sc->sc_hw.devs[index].device_pc; 2450 pg = &sc->sc_hw.devs[index].device_pg; 2451 2452 /* need to initialize the page cache */ 2453 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2454 2455 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2456 (2 * sizeof(struct xhci_dev_ctx)) : 2457 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2458 goto error; 2459 2460 usbd_get_page(pc, 0, &buf_dev); 2461 2462 pc = &sc->sc_hw.devs[index].input_pc; 2463 pg = &sc->sc_hw.devs[index].input_pg; 2464 2465 /* need to initialize the page cache */ 2466 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2467 2468 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2469 (2 * sizeof(struct xhci_input_dev_ctx)) : 2470 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2471 goto error; 2472 } 2473 2474 pc = &sc->sc_hw.devs[index].endpoint_pc; 2475 pg = &sc->sc_hw.devs[index].endpoint_pg; 2476 2477 /* need to initialize the page cache */ 2478 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2479 2480 if (usb_pc_alloc_mem(pc, pg, 2481 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2482 goto error; 2483 } 2484 2485 /* initialise all endpoint LINK TRBs */ 2486 2487 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2488 2489 /* lookup endpoint TRB ring */ 2490 usbd_get_page(pc, (uintptr_t)& 2491 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2492 2493 /* get TRB pointer */ 2494 trb = buf_ep.buffer; 2495 trb += XHCI_MAX_TRANSFERS - 1; 2496 2497 /* get TRB start address */ 2498 addr = buf_ep.physaddr; 2499 2500 /* create LINK TRB */ 2501 trb->qwTrb0 = htole64(addr); 2502 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2503 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2504 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2505 } 2506 2507 usb_pc_cpu_flush(pc); 2508 2509 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2510 2511 return (0); 2512 2513 error: 2514 xhci_free_device_ext(udev); 2515 2516 return (USB_ERR_NOMEM); 2517 } 2518 2519 static void 2520 xhci_free_device_ext(struct usb_device *udev) 2521 { 2522 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2523 uint8_t index; 2524 2525 index = udev->controller_slot_id; 2526 xhci_set_slot_pointer(sc, index, 0); 2527 2528 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2529 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2530 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2531 } 2532 2533 static struct xhci_endpoint_ext * 2534 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2535 { 2536 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2537 struct xhci_endpoint_ext *pepext; 2538 struct usb_page_cache *pc; 2539 struct usb_page_search buf_ep; 2540 uint8_t epno; 2541 uint8_t index; 2542 2543 epno = edesc->bEndpointAddress; 2544 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2545 epno |= UE_DIR_IN; 2546 2547 epno = XHCI_EPNO2EPID(epno); 2548 2549 index = udev->controller_slot_id; 2550 2551 pc = &sc->sc_hw.devs[index].endpoint_pc; 2552 2553 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2554 trb[epno][0], &buf_ep); 2555 2556 pepext = &sc->sc_hw.devs[index].endp[epno]; 2557 pepext->page_cache = pc; 2558 pepext->trb = buf_ep.buffer; 2559 pepext->physaddr = buf_ep.physaddr; 2560 2561 return (pepext); 2562 } 2563 2564 static void 2565 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2566 { 2567 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2568 uint8_t epno; 2569 uint8_t index; 2570 2571 epno = xfer->endpointno; 2572 if (xfer->flags_int.control_xfr) 2573 epno |= UE_DIR_IN; 2574 2575 epno = XHCI_EPNO2EPID(epno); 2576 index = xfer->xroot->udev->controller_slot_id; 2577 2578 if (xfer->xroot->udev->flags.self_suspended == 0) 2579 XWRITE4(sc, door, XHCI_DOORBELL(index), epno | XHCI_DB_SID_SET(0)); 2580 } 2581 2582 static void 2583 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2584 { 2585 struct xhci_endpoint_ext *pepext; 2586 2587 if (xfer->flags_int.bandwidth_reclaimed) { 2588 xfer->flags_int.bandwidth_reclaimed = 0; 2589 2590 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2591 xfer->endpoint->edesc); 2592 2593 pepext->trb_used[xfer->stream_id]--; 2594 2595 pepext->xfer[xfer->qh_pos] = NULL; 2596 2597 if (error && pepext->trb_running != 0) { 2598 pepext->trb_halted = 1; 2599 pepext->trb_running = 0; 2600 } 2601 } 2602 } 2603 2604 static usb_error_t 2605 xhci_transfer_insert(struct usb_xfer *xfer) 2606 { 2607 struct xhci_td *td_first; 2608 struct xhci_td *td_last; 2609 struct xhci_endpoint_ext *pepext; 2610 uint64_t addr; 2611 usb_stream_t id; 2612 uint8_t i; 2613 uint8_t inext; 2614 uint8_t trb_limit; 2615 2616 DPRINTFN(8, "\n"); 2617 2618 id = xfer->stream_id; 2619 2620 /* check if already inserted */ 2621 if (xfer->flags_int.bandwidth_reclaimed) { 2622 DPRINTFN(8, "Already in schedule\n"); 2623 return (0); 2624 } 2625 2626 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2627 xfer->endpoint->edesc); 2628 2629 td_first = xfer->td_transfer_first; 2630 td_last = xfer->td_transfer_last; 2631 addr = pepext->physaddr; 2632 2633 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2634 case UE_CONTROL: 2635 case UE_INTERRUPT: 2636 /* single buffered */ 2637 trb_limit = 1; 2638 break; 2639 default: 2640 /* multi buffered */ 2641 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2642 break; 2643 } 2644 2645 if (pepext->trb_used[id] >= trb_limit) { 2646 DPRINTFN(8, "Too many TDs queued.\n"); 2647 return (USB_ERR_NOMEM); 2648 } 2649 2650 /* check for stopped condition, after putting transfer on interrupt queue */ 2651 if (pepext->trb_running == 0) { 2652 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2653 2654 DPRINTFN(8, "Not running\n"); 2655 2656 /* start configuration */ 2657 (void)usb_proc_msignal(&sc->sc_config_proc, 2658 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2659 return (0); 2660 } 2661 2662 pepext->trb_used[id]++; 2663 2664 /* get current TRB index */ 2665 i = pepext->trb_index[id]; 2666 2667 /* get next TRB index */ 2668 inext = (i + 1); 2669 2670 /* the last entry of the ring is a hardcoded link TRB */ 2671 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2672 inext = 0; 2673 2674 /* offset for stream */ 2675 i += id * XHCI_MAX_TRANSFERS; 2676 inext += id * XHCI_MAX_TRANSFERS; 2677 2678 /* compute terminating return address */ 2679 addr += inext * sizeof(struct xhci_trb); 2680 2681 /* update next pointer of last link TRB */ 2682 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr); 2683 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2684 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2685 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2686 2687 #ifdef USB_DEBUG 2688 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2689 #endif 2690 usb_pc_cpu_flush(td_last->page_cache); 2691 2692 /* write ahead chain end marker */ 2693 2694 pepext->trb[inext].qwTrb0 = 0; 2695 pepext->trb[inext].dwTrb2 = 0; 2696 pepext->trb[inext].dwTrb3 = 0; 2697 2698 /* update next pointer of link TRB */ 2699 2700 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2701 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2702 2703 #ifdef USB_DEBUG 2704 xhci_dump_trb(&pepext->trb[i]); 2705 #endif 2706 usb_pc_cpu_flush(pepext->page_cache); 2707 2708 /* toggle cycle bit which activates the transfer chain */ 2709 2710 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2711 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2712 2713 usb_pc_cpu_flush(pepext->page_cache); 2714 2715 DPRINTF("qh_pos = %u\n", i); 2716 2717 pepext->xfer[i] = xfer; 2718 2719 xfer->qh_pos = i; 2720 2721 xfer->flags_int.bandwidth_reclaimed = 1; 2722 2723 pepext->trb_index[id] = inext; 2724 2725 xhci_endpoint_doorbell(xfer); 2726 2727 return (0); 2728 } 2729 2730 static void 2731 xhci_root_intr(struct xhci_softc *sc) 2732 { 2733 uint16_t i; 2734 2735 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2736 2737 /* clear any old interrupt data */ 2738 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2739 2740 for (i = 1; i <= sc->sc_noport; i++) { 2741 /* pick out CHANGE bits from the status register */ 2742 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2743 XHCI_PS_CSC | XHCI_PS_PEC | 2744 XHCI_PS_OCC | XHCI_PS_WRC | 2745 XHCI_PS_PRC | XHCI_PS_PLC | 2746 XHCI_PS_CEC)) { 2747 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2748 DPRINTF("port %d changed\n", i); 2749 } 2750 } 2751 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2752 sizeof(sc->sc_hub_idata)); 2753 } 2754 2755 /*------------------------------------------------------------------------* 2756 * xhci_device_done - XHCI done handler 2757 * 2758 * NOTE: This function can be called two times in a row on 2759 * the same USB transfer. From close and from interrupt. 2760 *------------------------------------------------------------------------*/ 2761 static void 2762 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2763 { 2764 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2765 xfer, xfer->endpoint, error); 2766 2767 /* remove transfer from HW queue */ 2768 xhci_transfer_remove(xfer, error); 2769 2770 /* dequeue transfer and start next transfer */ 2771 usbd_transfer_done(xfer, error); 2772 } 2773 2774 /*------------------------------------------------------------------------* 2775 * XHCI data transfer support (generic type) 2776 *------------------------------------------------------------------------*/ 2777 static void 2778 xhci_device_generic_open(struct usb_xfer *xfer) 2779 { 2780 if (xfer->flags_int.isochronous_xfr) { 2781 switch (xfer->xroot->udev->speed) { 2782 case USB_SPEED_FULL: 2783 break; 2784 default: 2785 usb_hs_bandwidth_alloc(xfer); 2786 break; 2787 } 2788 } 2789 } 2790 2791 static void 2792 xhci_device_generic_close(struct usb_xfer *xfer) 2793 { 2794 DPRINTF("\n"); 2795 2796 xhci_device_done(xfer, USB_ERR_CANCELLED); 2797 2798 if (xfer->flags_int.isochronous_xfr) { 2799 switch (xfer->xroot->udev->speed) { 2800 case USB_SPEED_FULL: 2801 break; 2802 default: 2803 usb_hs_bandwidth_free(xfer); 2804 break; 2805 } 2806 } 2807 } 2808 2809 static void 2810 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 2811 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 2812 { 2813 struct usb_xfer *xfer; 2814 2815 /* check if there is a current transfer */ 2816 xfer = ep->endpoint_q[stream_id].curr; 2817 if (xfer == NULL) 2818 return; 2819 2820 /* 2821 * Check if the current transfer is started and then pickup 2822 * the next one, if any. Else wait for next start event due to 2823 * block on failure feature. 2824 */ 2825 if (!xfer->flags_int.bandwidth_reclaimed) 2826 return; 2827 2828 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 2829 if (xfer == NULL) { 2830 /* 2831 * In case of enter we have to consider that the 2832 * transfer is queued by the USB core after the enter 2833 * method is called. 2834 */ 2835 xfer = enter_xfer; 2836 2837 if (xfer == NULL) 2838 return; 2839 } 2840 2841 /* try to multi buffer */ 2842 xhci_transfer_insert(xfer); 2843 } 2844 2845 static void 2846 xhci_device_generic_enter(struct usb_xfer *xfer) 2847 { 2848 DPRINTF("\n"); 2849 2850 /* setup TD's and QH */ 2851 xhci_setup_generic_chain(xfer); 2852 2853 xhci_device_generic_multi_enter(xfer->endpoint, 2854 xfer->stream_id, xfer); 2855 } 2856 2857 static void 2858 xhci_device_generic_start(struct usb_xfer *xfer) 2859 { 2860 DPRINTF("\n"); 2861 2862 /* try to insert xfer on HW queue */ 2863 xhci_transfer_insert(xfer); 2864 2865 /* try to multi buffer */ 2866 xhci_device_generic_multi_enter(xfer->endpoint, 2867 xfer->stream_id, NULL); 2868 2869 /* add transfer last on interrupt queue */ 2870 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2871 2872 /* start timeout, if any */ 2873 if (xfer->timeout != 0) 2874 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 2875 } 2876 2877 struct usb_pipe_methods xhci_device_generic_methods = 2878 { 2879 .open = xhci_device_generic_open, 2880 .close = xhci_device_generic_close, 2881 .enter = xhci_device_generic_enter, 2882 .start = xhci_device_generic_start, 2883 }; 2884 2885 /*------------------------------------------------------------------------* 2886 * xhci root HUB support 2887 *------------------------------------------------------------------------* 2888 * Simulate a hardware HUB by handling all the necessary requests. 2889 *------------------------------------------------------------------------*/ 2890 2891 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2892 2893 static const 2894 struct usb_device_descriptor xhci_devd = 2895 { 2896 .bLength = sizeof(xhci_devd), 2897 .bDescriptorType = UDESC_DEVICE, /* type */ 2898 HSETW(.bcdUSB, 0x0300), /* USB version */ 2899 .bDeviceClass = UDCLASS_HUB, /* class */ 2900 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 2901 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 2902 .bMaxPacketSize = 9, /* max packet size */ 2903 HSETW(.idVendor, 0x0000), /* vendor */ 2904 HSETW(.idProduct, 0x0000), /* product */ 2905 HSETW(.bcdDevice, 0x0100), /* device version */ 2906 .iManufacturer = 1, 2907 .iProduct = 2, 2908 .iSerialNumber = 0, 2909 .bNumConfigurations = 1, /* # of configurations */ 2910 }; 2911 2912 static const 2913 struct xhci_bos_desc xhci_bosd = { 2914 .bosd = { 2915 .bLength = sizeof(xhci_bosd.bosd), 2916 .bDescriptorType = UDESC_BOS, 2917 HSETW(.wTotalLength, sizeof(xhci_bosd)), 2918 .bNumDeviceCaps = 3, 2919 }, 2920 .usb2extd = { 2921 .bLength = sizeof(xhci_bosd.usb2extd), 2922 .bDescriptorType = 1, 2923 .bDevCapabilityType = 2, 2924 .bmAttributes[0] = 2, 2925 }, 2926 .usbdcd = { 2927 .bLength = sizeof(xhci_bosd.usbdcd), 2928 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 2929 .bDevCapabilityType = 3, 2930 .bmAttributes = 0, /* XXX */ 2931 HSETW(.wSpeedsSupported, 0x000C), 2932 .bFunctionalitySupport = 8, 2933 .bU1DevExitLat = 255, /* dummy - not used */ 2934 .wU2DevExitLat = { 0x00, 0x08 }, 2935 }, 2936 .cidd = { 2937 .bLength = sizeof(xhci_bosd.cidd), 2938 .bDescriptorType = 1, 2939 .bDevCapabilityType = 4, 2940 .bReserved = 0, 2941 .bContainerID = 0, /* XXX */ 2942 }, 2943 }; 2944 2945 static const 2946 struct xhci_config_desc xhci_confd = { 2947 .confd = { 2948 .bLength = sizeof(xhci_confd.confd), 2949 .bDescriptorType = UDESC_CONFIG, 2950 .wTotalLength[0] = sizeof(xhci_confd), 2951 .bNumInterface = 1, 2952 .bConfigurationValue = 1, 2953 .iConfiguration = 0, 2954 .bmAttributes = UC_SELF_POWERED, 2955 .bMaxPower = 0 /* max power */ 2956 }, 2957 .ifcd = { 2958 .bLength = sizeof(xhci_confd.ifcd), 2959 .bDescriptorType = UDESC_INTERFACE, 2960 .bNumEndpoints = 1, 2961 .bInterfaceClass = UICLASS_HUB, 2962 .bInterfaceSubClass = UISUBCLASS_HUB, 2963 .bInterfaceProtocol = 0, 2964 }, 2965 .endpd = { 2966 .bLength = sizeof(xhci_confd.endpd), 2967 .bDescriptorType = UDESC_ENDPOINT, 2968 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 2969 .bmAttributes = UE_INTERRUPT, 2970 .wMaxPacketSize[0] = 2, /* max 15 ports */ 2971 .bInterval = 255, 2972 }, 2973 .endpcd = { 2974 .bLength = sizeof(xhci_confd.endpcd), 2975 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 2976 .bMaxBurst = 0, 2977 .bmAttributes = 0, 2978 }, 2979 }; 2980 2981 static const 2982 struct usb_hub_ss_descriptor xhci_hubd = { 2983 .bLength = sizeof(xhci_hubd), 2984 .bDescriptorType = UDESC_SS_HUB, 2985 }; 2986 2987 static usb_error_t 2988 xhci_roothub_exec(struct usb_device *udev, 2989 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2990 { 2991 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2992 const char *str_ptr; 2993 const void *ptr; 2994 uint32_t port; 2995 uint32_t v; 2996 uint16_t len; 2997 uint16_t i; 2998 uint16_t value; 2999 uint16_t index; 3000 uint8_t j; 3001 usb_error_t err; 3002 3003 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 3004 3005 /* buffer reset */ 3006 ptr = (const void *)&sc->sc_hub_desc; 3007 len = 0; 3008 err = 0; 3009 3010 value = UGETW(req->wValue); 3011 index = UGETW(req->wIndex); 3012 3013 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3014 "wValue=0x%04x wIndex=0x%04x\n", 3015 req->bmRequestType, req->bRequest, 3016 UGETW(req->wLength), value, index); 3017 3018 #define C(x,y) ((x) | ((y) << 8)) 3019 switch (C(req->bRequest, req->bmRequestType)) { 3020 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3021 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3022 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3023 /* 3024 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3025 * for the integrated root hub. 3026 */ 3027 break; 3028 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3029 len = 1; 3030 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3031 break; 3032 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3033 switch (value >> 8) { 3034 case UDESC_DEVICE: 3035 if ((value & 0xff) != 0) { 3036 err = USB_ERR_IOERROR; 3037 goto done; 3038 } 3039 len = sizeof(xhci_devd); 3040 ptr = (const void *)&xhci_devd; 3041 break; 3042 3043 case UDESC_BOS: 3044 if ((value & 0xff) != 0) { 3045 err = USB_ERR_IOERROR; 3046 goto done; 3047 } 3048 len = sizeof(xhci_bosd); 3049 ptr = (const void *)&xhci_bosd; 3050 break; 3051 3052 case UDESC_CONFIG: 3053 if ((value & 0xff) != 0) { 3054 err = USB_ERR_IOERROR; 3055 goto done; 3056 } 3057 len = sizeof(xhci_confd); 3058 ptr = (const void *)&xhci_confd; 3059 break; 3060 3061 case UDESC_STRING: 3062 switch (value & 0xff) { 3063 case 0: /* Language table */ 3064 str_ptr = "\001"; 3065 break; 3066 3067 case 1: /* Vendor */ 3068 str_ptr = sc->sc_vendor; 3069 break; 3070 3071 case 2: /* Product */ 3072 str_ptr = "XHCI root HUB"; 3073 break; 3074 3075 default: 3076 str_ptr = ""; 3077 break; 3078 } 3079 3080 len = usb_make_str_desc( 3081 sc->sc_hub_desc.temp, 3082 sizeof(sc->sc_hub_desc.temp), 3083 str_ptr); 3084 break; 3085 3086 default: 3087 err = USB_ERR_IOERROR; 3088 goto done; 3089 } 3090 break; 3091 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3092 len = 1; 3093 sc->sc_hub_desc.temp[0] = 0; 3094 break; 3095 case C(UR_GET_STATUS, UT_READ_DEVICE): 3096 len = 2; 3097 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3098 break; 3099 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3100 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3101 len = 2; 3102 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3103 break; 3104 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3105 if (value >= XHCI_MAX_DEVICES) { 3106 err = USB_ERR_IOERROR; 3107 goto done; 3108 } 3109 break; 3110 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3111 if (value != 0 && value != 1) { 3112 err = USB_ERR_IOERROR; 3113 goto done; 3114 } 3115 sc->sc_conf = value; 3116 break; 3117 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3118 break; 3119 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3120 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3121 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3122 err = USB_ERR_IOERROR; 3123 goto done; 3124 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3125 break; 3126 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3127 break; 3128 /* Hub requests */ 3129 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3130 break; 3131 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3132 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3133 3134 if ((index < 1) || 3135 (index > sc->sc_noport)) { 3136 err = USB_ERR_IOERROR; 3137 goto done; 3138 } 3139 port = XHCI_PORTSC(index); 3140 3141 v = XREAD4(sc, oper, port); 3142 i = XHCI_PS_PLS_GET(v); 3143 v &= ~XHCI_PS_CLEAR; 3144 3145 switch (value) { 3146 case UHF_C_BH_PORT_RESET: 3147 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3148 break; 3149 case UHF_C_PORT_CONFIG_ERROR: 3150 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3151 break; 3152 case UHF_C_PORT_SUSPEND: 3153 case UHF_C_PORT_LINK_STATE: 3154 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3155 break; 3156 case UHF_C_PORT_CONNECTION: 3157 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3158 break; 3159 case UHF_C_PORT_ENABLE: 3160 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3161 break; 3162 case UHF_C_PORT_OVER_CURRENT: 3163 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3164 break; 3165 case UHF_C_PORT_RESET: 3166 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3167 break; 3168 case UHF_PORT_ENABLE: 3169 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3170 break; 3171 case UHF_PORT_POWER: 3172 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3173 break; 3174 case UHF_PORT_INDICATOR: 3175 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3176 break; 3177 case UHF_PORT_SUSPEND: 3178 3179 /* U3 -> U15 */ 3180 if (i == 3) { 3181 XWRITE4(sc, oper, port, v | 3182 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3183 } 3184 3185 /* wait 20ms for resume sequence to complete */ 3186 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 50); 3187 3188 /* U0 */ 3189 XWRITE4(sc, oper, port, v | 3190 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3191 break; 3192 default: 3193 err = USB_ERR_IOERROR; 3194 goto done; 3195 } 3196 break; 3197 3198 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3199 if ((value & 0xff) != 0) { 3200 err = USB_ERR_IOERROR; 3201 goto done; 3202 } 3203 3204 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3205 3206 sc->sc_hub_desc.hubd = xhci_hubd; 3207 3208 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3209 3210 if (XHCI_HCS0_PPC(v)) 3211 i = UHD_PWR_INDIVIDUAL; 3212 else 3213 i = UHD_PWR_GANGED; 3214 3215 if (XHCI_HCS0_PIND(v)) 3216 i |= UHD_PORT_IND; 3217 3218 i |= UHD_OC_INDIVIDUAL; 3219 3220 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3221 3222 /* see XHCI section 5.4.9: */ 3223 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3224 3225 for (j = 1; j <= sc->sc_noport; j++) { 3226 3227 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3228 if (v & XHCI_PS_DR) { 3229 sc->sc_hub_desc.hubd. 3230 DeviceRemovable[j / 8] |= 1U << (j % 8); 3231 } 3232 } 3233 len = sc->sc_hub_desc.hubd.bLength; 3234 break; 3235 3236 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3237 len = 16; 3238 memset(sc->sc_hub_desc.temp, 0, 16); 3239 break; 3240 3241 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3242 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3243 3244 if ((index < 1) || 3245 (index > sc->sc_noport)) { 3246 err = USB_ERR_IOERROR; 3247 goto done; 3248 } 3249 3250 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3251 3252 DPRINTFN(9, "port status=0x%08x\n", v); 3253 3254 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3255 3256 switch (XHCI_PS_SPEED_GET(v)) { 3257 case 3: 3258 i |= UPS_HIGH_SPEED; 3259 break; 3260 case 2: 3261 i |= UPS_LOW_SPEED; 3262 break; 3263 case 1: 3264 /* FULL speed */ 3265 break; 3266 default: 3267 i |= UPS_OTHER_SPEED; 3268 break; 3269 } 3270 3271 if (v & XHCI_PS_CCS) 3272 i |= UPS_CURRENT_CONNECT_STATUS; 3273 if (v & XHCI_PS_PED) 3274 i |= UPS_PORT_ENABLED; 3275 if (v & XHCI_PS_OCA) 3276 i |= UPS_OVERCURRENT_INDICATOR; 3277 if (v & XHCI_PS_PR) 3278 i |= UPS_RESET; 3279 if (v & XHCI_PS_PP) { 3280 /* 3281 * The USB 3.0 RH is using the 3282 * USB 2.0's power bit 3283 */ 3284 i |= UPS_PORT_POWER; 3285 } 3286 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3287 3288 i = 0; 3289 if (v & XHCI_PS_CSC) 3290 i |= UPS_C_CONNECT_STATUS; 3291 if (v & XHCI_PS_PEC) 3292 i |= UPS_C_PORT_ENABLED; 3293 if (v & XHCI_PS_OCC) 3294 i |= UPS_C_OVERCURRENT_INDICATOR; 3295 if (v & XHCI_PS_WRC) 3296 i |= UPS_C_BH_PORT_RESET; 3297 if (v & XHCI_PS_PRC) 3298 i |= UPS_C_PORT_RESET; 3299 if (v & XHCI_PS_PLC) 3300 i |= UPS_C_PORT_LINK_STATE; 3301 if (v & XHCI_PS_CEC) 3302 i |= UPS_C_PORT_CONFIG_ERROR; 3303 3304 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3305 len = sizeof(sc->sc_hub_desc.ps); 3306 break; 3307 3308 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3309 err = USB_ERR_IOERROR; 3310 goto done; 3311 3312 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3313 break; 3314 3315 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3316 3317 i = index >> 8; 3318 index &= 0x00FF; 3319 3320 if ((index < 1) || 3321 (index > sc->sc_noport)) { 3322 err = USB_ERR_IOERROR; 3323 goto done; 3324 } 3325 3326 port = XHCI_PORTSC(index); 3327 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3328 3329 switch (value) { 3330 case UHF_PORT_U1_TIMEOUT: 3331 if (XHCI_PS_SPEED_GET(v) != 4) { 3332 err = USB_ERR_IOERROR; 3333 goto done; 3334 } 3335 port = XHCI_PORTPMSC(index); 3336 v = XREAD4(sc, oper, port); 3337 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3338 v |= XHCI_PM3_U1TO_SET(i); 3339 XWRITE4(sc, oper, port, v); 3340 break; 3341 case UHF_PORT_U2_TIMEOUT: 3342 if (XHCI_PS_SPEED_GET(v) != 4) { 3343 err = USB_ERR_IOERROR; 3344 goto done; 3345 } 3346 port = XHCI_PORTPMSC(index); 3347 v = XREAD4(sc, oper, port); 3348 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3349 v |= XHCI_PM3_U2TO_SET(i); 3350 XWRITE4(sc, oper, port, v); 3351 break; 3352 case UHF_BH_PORT_RESET: 3353 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3354 break; 3355 case UHF_PORT_LINK_STATE: 3356 XWRITE4(sc, oper, port, v | 3357 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3358 /* 4ms settle time */ 3359 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 250); 3360 break; 3361 case UHF_PORT_ENABLE: 3362 DPRINTFN(3, "set port enable %d\n", index); 3363 break; 3364 case UHF_PORT_SUSPEND: 3365 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3366 j = XHCI_PS_SPEED_GET(v); 3367 if ((j < 1) || (j > 3)) { 3368 /* non-supported speed */ 3369 err = USB_ERR_IOERROR; 3370 goto done; 3371 } 3372 XWRITE4(sc, oper, port, v | 3373 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3374 break; 3375 case UHF_PORT_RESET: 3376 DPRINTFN(6, "reset port %d\n", index); 3377 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3378 break; 3379 case UHF_PORT_POWER: 3380 DPRINTFN(3, "set port power %d\n", index); 3381 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3382 break; 3383 case UHF_PORT_TEST: 3384 DPRINTFN(3, "set port test %d\n", index); 3385 break; 3386 case UHF_PORT_INDICATOR: 3387 DPRINTFN(3, "set port indicator %d\n", index); 3388 3389 v &= ~XHCI_PS_PIC_SET(3); 3390 v |= XHCI_PS_PIC_SET(1); 3391 3392 XWRITE4(sc, oper, port, v); 3393 break; 3394 default: 3395 err = USB_ERR_IOERROR; 3396 goto done; 3397 } 3398 break; 3399 3400 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3401 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3402 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3403 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3404 break; 3405 default: 3406 err = USB_ERR_IOERROR; 3407 goto done; 3408 } 3409 done: 3410 *plength = len; 3411 *pptr = ptr; 3412 return (err); 3413 } 3414 3415 static void 3416 xhci_xfer_setup(struct usb_setup_params *parm) 3417 { 3418 struct usb_page_search page_info; 3419 struct usb_page_cache *pc; 3420 struct xhci_softc *sc; 3421 struct usb_xfer *xfer; 3422 void *last_obj; 3423 uint32_t ntd; 3424 uint32_t n; 3425 3426 sc = XHCI_BUS2SC(parm->udev->bus); 3427 xfer = parm->curr_xfer; 3428 3429 /* 3430 * The proof for the "ntd" formula is illustrated like this: 3431 * 3432 * +------------------------------------+ 3433 * | | 3434 * | |remainder -> | 3435 * | +-----+---+ | 3436 * | | xxx | x | frm 0 | 3437 * | +-----+---++ | 3438 * | | xxx | xx | frm 1 | 3439 * | +-----+----+ | 3440 * | ... | 3441 * +------------------------------------+ 3442 * 3443 * "xxx" means a completely full USB transfer descriptor 3444 * 3445 * "x" and "xx" means a short USB packet 3446 * 3447 * For the remainder of an USB transfer modulo 3448 * "max_data_length" we need two USB transfer descriptors. 3449 * One to transfer the remaining data and one to finalise with 3450 * a zero length packet in case the "force_short_xfer" flag is 3451 * set. We only need two USB transfer descriptors in the case 3452 * where the transfer length of the first one is a factor of 3453 * "max_frame_size". The rest of the needed USB transfer 3454 * descriptors is given by the buffer size divided by the 3455 * maximum data payload. 3456 */ 3457 parm->hc_max_packet_size = 0x400; 3458 parm->hc_max_packet_count = 16 * 3; 3459 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3460 3461 xfer->flags_int.bdma_enable = 1; 3462 3463 usbd_transfer_setup_sub(parm); 3464 3465 if (xfer->flags_int.isochronous_xfr) { 3466 ntd = ((1 * xfer->nframes) 3467 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3468 } else if (xfer->flags_int.control_xfr) { 3469 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3470 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3471 } else { 3472 ntd = ((2 * xfer->nframes) 3473 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3474 } 3475 3476 alloc_dma_set: 3477 3478 if (parm->err) 3479 return; 3480 3481 /* 3482 * Allocate queue heads and transfer descriptors 3483 */ 3484 last_obj = NULL; 3485 3486 if (usbd_transfer_setup_sub_malloc( 3487 parm, &pc, sizeof(struct xhci_td), 3488 XHCI_TD_ALIGN, ntd)) { 3489 parm->err = USB_ERR_NOMEM; 3490 return; 3491 } 3492 if (parm->buf) { 3493 for (n = 0; n != ntd; n++) { 3494 struct xhci_td *td; 3495 3496 usbd_get_page(pc + n, 0, &page_info); 3497 3498 td = page_info.buffer; 3499 3500 /* init TD */ 3501 td->td_self = page_info.physaddr; 3502 td->obj_next = last_obj; 3503 td->page_cache = pc + n; 3504 3505 last_obj = td; 3506 3507 usb_pc_cpu_flush(pc + n); 3508 } 3509 } 3510 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3511 3512 if (!xfer->flags_int.curr_dma_set) { 3513 xfer->flags_int.curr_dma_set = 1; 3514 goto alloc_dma_set; 3515 } 3516 } 3517 3518 static usb_error_t 3519 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3520 { 3521 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3522 struct usb_page_search buf_inp; 3523 struct usb_device *udev; 3524 struct xhci_endpoint_ext *pepext; 3525 struct usb_endpoint_descriptor *edesc; 3526 struct usb_page_cache *pcinp; 3527 usb_error_t err; 3528 usb_stream_t stream_id; 3529 uint8_t index; 3530 uint8_t epno; 3531 3532 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3533 xfer->endpoint->edesc); 3534 3535 udev = xfer->xroot->udev; 3536 index = udev->controller_slot_id; 3537 3538 pcinp = &sc->sc_hw.devs[index].input_pc; 3539 3540 usbd_get_page(pcinp, 0, &buf_inp); 3541 3542 edesc = xfer->endpoint->edesc; 3543 3544 epno = edesc->bEndpointAddress; 3545 stream_id = xfer->stream_id; 3546 3547 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3548 epno |= UE_DIR_IN; 3549 3550 epno = XHCI_EPNO2EPID(epno); 3551 3552 if (epno == 0) 3553 return (USB_ERR_NO_PIPE); /* invalid */ 3554 3555 XHCI_CMD_LOCK(sc); 3556 3557 /* configure endpoint */ 3558 3559 err = xhci_configure_endpoint_by_xfer(xfer); 3560 3561 if (err != 0) { 3562 XHCI_CMD_UNLOCK(sc); 3563 return (err); 3564 } 3565 3566 /* 3567 * Get the endpoint into the stopped state according to the 3568 * endpoint context state diagram in the XHCI specification: 3569 */ 3570 3571 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3572 3573 if (err != 0) 3574 DPRINTF("Could not stop endpoint %u\n", epno); 3575 3576 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3577 3578 if (err != 0) 3579 DPRINTF("Could not reset endpoint %u\n", epno); 3580 3581 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3582 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3583 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3584 stream_id, epno, index); 3585 3586 if (err != 0) 3587 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3588 3589 /* 3590 * Get the endpoint into the running state according to the 3591 * endpoint context state diagram in the XHCI specification: 3592 */ 3593 3594 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3595 3596 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3597 3598 if (err != 0) 3599 DPRINTF("Could not configure endpoint %u\n", epno); 3600 3601 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3602 3603 if (err != 0) 3604 DPRINTF("Could not configure endpoint %u\n", epno); 3605 3606 XHCI_CMD_UNLOCK(sc); 3607 3608 return (0); 3609 } 3610 3611 static void 3612 xhci_xfer_unsetup(struct usb_xfer *xfer) 3613 { 3614 return; 3615 } 3616 3617 static void 3618 xhci_start_dma_delay(struct usb_xfer *xfer) 3619 { 3620 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3621 3622 /* put transfer on interrupt queue (again) */ 3623 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3624 3625 (void)usb_proc_msignal(&sc->sc_config_proc, 3626 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3627 } 3628 3629 static void 3630 xhci_configure_msg(struct usb_proc_msg *pm) 3631 { 3632 struct xhci_softc *sc; 3633 struct xhci_endpoint_ext *pepext; 3634 struct usb_xfer *xfer; 3635 3636 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3637 3638 restart: 3639 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3640 3641 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3642 xfer->endpoint->edesc); 3643 3644 if ((pepext->trb_halted != 0) || 3645 (pepext->trb_running == 0)) { 3646 3647 uint8_t i; 3648 3649 /* clear halted and running */ 3650 pepext->trb_halted = 0; 3651 pepext->trb_running = 0; 3652 3653 /* nuke remaining buffered transfers */ 3654 3655 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 3656 /* 3657 * NOTE: We need to use the timeout 3658 * error code here else existing 3659 * isochronous clients can get 3660 * confused: 3661 */ 3662 if (pepext->xfer[i] != NULL) { 3663 xhci_device_done(pepext->xfer[i], 3664 USB_ERR_TIMEOUT); 3665 } 3666 } 3667 3668 /* 3669 * NOTE: The USB transfer cannot vanish in 3670 * this state! 3671 */ 3672 3673 USB_BUS_UNLOCK(&sc->sc_bus); 3674 3675 xhci_configure_reset_endpoint(xfer); 3676 3677 USB_BUS_LOCK(&sc->sc_bus); 3678 3679 /* check if halted is still cleared */ 3680 if (pepext->trb_halted == 0) { 3681 pepext->trb_running = 1; 3682 memset(pepext->trb_index, 0, 3683 sizeof(pepext->trb_index)); 3684 } 3685 goto restart; 3686 } 3687 3688 if (xfer->flags_int.did_dma_delay) { 3689 3690 /* remove transfer from interrupt queue (again) */ 3691 usbd_transfer_dequeue(xfer); 3692 3693 /* we are finally done */ 3694 usb_dma_delay_done_cb(xfer); 3695 3696 /* queue changed - restart */ 3697 goto restart; 3698 } 3699 } 3700 3701 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3702 3703 /* try to insert xfer on HW queue */ 3704 xhci_transfer_insert(xfer); 3705 3706 /* try to multi buffer */ 3707 xhci_device_generic_multi_enter(xfer->endpoint, 3708 xfer->stream_id, NULL); 3709 } 3710 } 3711 3712 static void 3713 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3714 struct usb_endpoint *ep) 3715 { 3716 struct xhci_endpoint_ext *pepext; 3717 3718 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3719 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3720 3721 if (udev->parent_hub == NULL) { 3722 /* root HUB has special endpoint handling */ 3723 return; 3724 } 3725 3726 ep->methods = &xhci_device_generic_methods; 3727 3728 pepext = xhci_get_endpoint_ext(udev, edesc); 3729 3730 USB_BUS_LOCK(udev->bus); 3731 pepext->trb_halted = 1; 3732 pepext->trb_running = 0; 3733 USB_BUS_UNLOCK(udev->bus); 3734 } 3735 3736 static void 3737 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3738 { 3739 3740 } 3741 3742 static void 3743 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3744 { 3745 struct xhci_endpoint_ext *pepext; 3746 3747 DPRINTF("\n"); 3748 3749 if (udev->flags.usb_mode != USB_MODE_HOST) { 3750 /* not supported */ 3751 return; 3752 } 3753 if (udev->parent_hub == NULL) { 3754 /* root HUB has special endpoint handling */ 3755 return; 3756 } 3757 3758 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3759 3760 USB_BUS_LOCK(udev->bus); 3761 pepext->trb_halted = 1; 3762 pepext->trb_running = 0; 3763 USB_BUS_UNLOCK(udev->bus); 3764 } 3765 3766 static usb_error_t 3767 xhci_device_init(struct usb_device *udev) 3768 { 3769 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3770 usb_error_t err; 3771 uint8_t temp; 3772 3773 /* no init for root HUB */ 3774 if (udev->parent_hub == NULL) 3775 return (0); 3776 3777 XHCI_CMD_LOCK(sc); 3778 3779 /* set invalid default */ 3780 3781 udev->controller_slot_id = sc->sc_noslot + 1; 3782 3783 /* try to get a new slot ID from the XHCI */ 3784 3785 err = xhci_cmd_enable_slot(sc, &temp); 3786 3787 if (err) { 3788 XHCI_CMD_UNLOCK(sc); 3789 return (err); 3790 } 3791 3792 if (temp > sc->sc_noslot) { 3793 XHCI_CMD_UNLOCK(sc); 3794 return (USB_ERR_BAD_ADDRESS); 3795 } 3796 3797 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 3798 DPRINTF("slot %u already allocated.\n", temp); 3799 XHCI_CMD_UNLOCK(sc); 3800 return (USB_ERR_BAD_ADDRESS); 3801 } 3802 3803 /* store slot ID for later reference */ 3804 3805 udev->controller_slot_id = temp; 3806 3807 /* reset data structure */ 3808 3809 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 3810 3811 /* set mark slot allocated */ 3812 3813 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 3814 3815 err = xhci_alloc_device_ext(udev); 3816 3817 XHCI_CMD_UNLOCK(sc); 3818 3819 /* get device into default state */ 3820 3821 if (err == 0) 3822 err = xhci_set_address(udev, NULL, 0); 3823 3824 return (err); 3825 } 3826 3827 static void 3828 xhci_device_uninit(struct usb_device *udev) 3829 { 3830 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3831 uint8_t index; 3832 3833 /* no init for root HUB */ 3834 if (udev->parent_hub == NULL) 3835 return; 3836 3837 XHCI_CMD_LOCK(sc); 3838 3839 index = udev->controller_slot_id; 3840 3841 if (index <= sc->sc_noslot) { 3842 xhci_cmd_disable_slot(sc, index); 3843 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 3844 3845 /* free device extension */ 3846 xhci_free_device_ext(udev); 3847 } 3848 3849 XHCI_CMD_UNLOCK(sc); 3850 } 3851 3852 static void 3853 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3854 { 3855 /* 3856 * Wait until the hardware has finished any possible use of 3857 * the transfer descriptor(s) 3858 */ 3859 *pus = 2048; /* microseconds */ 3860 } 3861 3862 static void 3863 xhci_device_resume(struct usb_device *udev) 3864 { 3865 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3866 uint8_t index; 3867 uint8_t n; 3868 3869 DPRINTF("\n"); 3870 3871 /* check for root HUB */ 3872 if (udev->parent_hub == NULL) 3873 return; 3874 3875 index = udev->controller_slot_id; 3876 3877 XHCI_CMD_LOCK(sc); 3878 3879 /* blindly resume all endpoints */ 3880 3881 USB_BUS_LOCK(udev->bus); 3882 3883 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) 3884 XWRITE4(sc, door, XHCI_DOORBELL(index), n | XHCI_DB_SID_SET(0)); 3885 3886 USB_BUS_UNLOCK(udev->bus); 3887 3888 XHCI_CMD_UNLOCK(sc); 3889 } 3890 3891 static void 3892 xhci_device_suspend(struct usb_device *udev) 3893 { 3894 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3895 uint8_t index; 3896 uint8_t n; 3897 usb_error_t err; 3898 3899 DPRINTF("\n"); 3900 3901 /* check for root HUB */ 3902 if (udev->parent_hub == NULL) 3903 return; 3904 3905 index = udev->controller_slot_id; 3906 3907 XHCI_CMD_LOCK(sc); 3908 3909 /* blindly suspend all endpoints */ 3910 3911 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3912 err = xhci_cmd_stop_ep(sc, 1, n, index); 3913 if (err != 0) { 3914 DPRINTF("Failed to suspend endpoint " 3915 "%u on slot %u (ignored).\n", n, index); 3916 } 3917 } 3918 3919 XHCI_CMD_UNLOCK(sc); 3920 } 3921 3922 static void 3923 xhci_set_hw_power(struct usb_bus *bus) 3924 { 3925 DPRINTF("\n"); 3926 } 3927 3928 static void 3929 xhci_device_state_change(struct usb_device *udev) 3930 { 3931 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3932 struct usb_page_search buf_inp; 3933 usb_error_t err; 3934 uint8_t index; 3935 3936 /* check for root HUB */ 3937 if (udev->parent_hub == NULL) 3938 return; 3939 3940 index = udev->controller_slot_id; 3941 3942 DPRINTF("\n"); 3943 3944 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 3945 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 3946 &sc->sc_hw.devs[index].tt); 3947 if (err != 0) 3948 sc->sc_hw.devs[index].nports = 0; 3949 } 3950 3951 XHCI_CMD_LOCK(sc); 3952 3953 switch (usb_get_device_state(udev)) { 3954 case USB_STATE_POWERED: 3955 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 3956 break; 3957 3958 /* set default state */ 3959 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 3960 3961 /* reset number of contexts */ 3962 sc->sc_hw.devs[index].context_num = 0; 3963 3964 err = xhci_cmd_reset_dev(sc, index); 3965 3966 if (err != 0) { 3967 DPRINTF("Device reset failed " 3968 "for slot %u.\n", index); 3969 } 3970 break; 3971 3972 case USB_STATE_ADDRESSED: 3973 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 3974 break; 3975 3976 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 3977 3978 err = xhci_cmd_configure_ep(sc, 0, 1, index); 3979 3980 if (err) { 3981 DPRINTF("Failed to deconfigure " 3982 "slot %u.\n", index); 3983 } 3984 break; 3985 3986 case USB_STATE_CONFIGURED: 3987 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 3988 break; 3989 3990 /* set configured state */ 3991 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 3992 3993 /* reset number of contexts */ 3994 sc->sc_hw.devs[index].context_num = 0; 3995 3996 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 3997 3998 xhci_configure_mask(udev, 3, 0); 3999 4000 err = xhci_configure_device(udev); 4001 if (err != 0) { 4002 DPRINTF("Could not configure device " 4003 "at slot %u.\n", index); 4004 } 4005 4006 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4007 if (err != 0) { 4008 DPRINTF("Could not evaluate device " 4009 "context at slot %u.\n", index); 4010 } 4011 break; 4012 4013 default: 4014 break; 4015 } 4016 XHCI_CMD_UNLOCK(sc); 4017 } 4018 4019 static usb_error_t 4020 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4021 uint8_t ep_mode) 4022 { 4023 switch (ep_mode) { 4024 case USB_EP_MODE_DEFAULT: 4025 return (0); 4026 case USB_EP_MODE_STREAMS: 4027 if ((ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4028 udev->speed != USB_SPEED_SUPER) 4029 return (USB_ERR_INVAL); 4030 return (0); 4031 default: 4032 return (USB_ERR_INVAL); 4033 } 4034 } 4035 4036 4037 struct usb_bus_methods xhci_bus_methods = { 4038 .endpoint_init = xhci_ep_init, 4039 .endpoint_uninit = xhci_ep_uninit, 4040 .xfer_setup = xhci_xfer_setup, 4041 .xfer_unsetup = xhci_xfer_unsetup, 4042 .get_dma_delay = xhci_get_dma_delay, 4043 .device_init = xhci_device_init, 4044 .device_uninit = xhci_device_uninit, 4045 .device_resume = xhci_device_resume, 4046 .device_suspend = xhci_device_suspend, 4047 .set_hw_power = xhci_set_hw_power, 4048 .roothub_exec = xhci_roothub_exec, 4049 .xfer_poll = xhci_do_poll, 4050 .start_dma_delay = xhci_start_dma_delay, 4051 .set_address = xhci_set_address, 4052 .clear_stall = xhci_ep_clear_stall, 4053 .device_state_change = xhci_device_state_change, 4054 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4055 .set_endpoint_mode = xhci_set_endpoint_mode, 4056 }; 4057