1 /* $FreeBSD: head/sys/dev/usb/controller/xhci.c 278477 2015-02-09 21:47:12Z hselasky $ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #include <sys/stdint.h> 44 #include <sys/param.h> 45 #include <sys/queue.h> 46 #include <sys/types.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/module.h> 51 #include <sys/lock.h> 52 #include <sys/condvar.h> 53 #include <sys/sysctl.h> 54 #include <sys/unistd.h> 55 #include <sys/callout.h> 56 #include <sys/malloc.h> 57 #include <sys/priv.h> 58 59 #include <bus/u4b/usb.h> 60 #include <bus/u4b/usbdi.h> 61 62 #define USB_DEBUG_VAR xhcidebug 63 64 #include <bus/u4b/usb_core.h> 65 #include <bus/u4b/usb_debug.h> 66 #include <bus/u4b/usb_busdma.h> 67 #include <bus/u4b/usb_process.h> 68 #include <bus/u4b/usb_transfer.h> 69 #include <bus/u4b/usb_device.h> 70 #include <bus/u4b/usb_hub.h> 71 #include <bus/u4b/usb_util.h> 72 73 #include <bus/u4b/usb_controller.h> 74 #include <bus/u4b/usb_bus.h> 75 #include <bus/u4b/controller/xhci.h> 76 #include <bus/u4b/controller/xhcireg.h> 77 78 #define XHCI_BUS2SC(bus) \ 79 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 80 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 81 82 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 83 84 static int xhcistreams; 85 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW, 86 &xhcistreams, 0, "Set to enable streams mode support"); 87 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams); 88 89 static int xhcipolling = 0; 90 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW, 91 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 92 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling); 93 94 #ifdef USB_DEBUG 95 static int xhcidebug = 0; 96 static int xhciroute = 0; 97 static int xhcidma32; 98 99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW, 100 &xhcidebug, 0, "Debug level"); 101 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW, 103 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 104 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 105 106 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RW, 107 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller"); 108 TUNABLE_INT("hw.usb.xhci.dma32", &xhcidma32); 109 110 #else 111 #define xhciroute 0 112 #define xhcidma32 0 113 #endif 114 115 #define XHCI_INTR_ENDPT 1 116 117 struct xhci_std_temp { 118 struct xhci_softc *sc; 119 struct usb_page_cache *pc; 120 struct xhci_td *td; 121 struct xhci_td *td_next; 122 uint32_t len; 123 uint32_t offset; 124 uint32_t max_packet_size; 125 uint32_t average; 126 uint16_t isoc_delta; 127 uint16_t isoc_frame; 128 uint8_t shortpkt; 129 uint8_t multishort; 130 uint8_t last_frame; 131 uint8_t trb_type; 132 uint8_t direction; 133 uint8_t tbc; 134 uint8_t tlbpc; 135 uint8_t step_td; 136 uint8_t do_isoc_sync; 137 }; 138 139 static void xhci_do_poll(struct usb_bus *); 140 static void xhci_device_done(struct usb_xfer *, usb_error_t); 141 static void xhci_root_intr(struct xhci_softc *); 142 static void xhci_free_device_ext(struct usb_device *); 143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 144 struct usb_endpoint_descriptor *); 145 static usb_proc_callback_t xhci_configure_msg; 146 static usb_error_t xhci_configure_device(struct usb_device *); 147 static usb_error_t xhci_configure_endpoint(struct usb_device *, 148 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 149 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 150 uint8_t); 151 static usb_error_t xhci_configure_mask(struct usb_device *, 152 uint32_t, uint8_t); 153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 154 uint64_t, uint8_t); 155 static void xhci_endpoint_doorbell(struct usb_xfer *); 156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 159 #ifdef USB_DEBUG 160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 161 #endif 162 163 static const struct usb_bus_methods xhci_bus_methods; 164 165 #ifdef USB_DEBUG 166 static void 167 xhci_dump_trb(struct xhci_trb *trb) 168 { 169 DPRINTFN(5, "trb = %p\n", trb); 170 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 171 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 172 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 173 } 174 175 static void 176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 177 { 178 DPRINTFN(5, "pep = %p\n", pep); 179 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 180 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 181 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 182 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 183 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 184 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 185 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 186 } 187 188 static void 189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 190 { 191 DPRINTFN(5, "psl = %p\n", psl); 192 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 193 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 194 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 195 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 196 } 197 #endif 198 199 /* 200 * hw.usb.xhci.use_polling=1 201 */ 202 uint8_t 203 xhci_use_polling(void) 204 { 205 return (xhcipolling != 0); 206 } 207 208 static void 209 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 210 { 211 struct xhci_softc *sc = XHCI_BUS2SC(bus); 212 uint8_t i; 213 214 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 215 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 216 217 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 218 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 219 220 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 221 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 222 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 223 } 224 } 225 226 static void 227 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 228 { 229 if (sc->sc_ctx_is_64_byte) { 230 uint32_t offset; 231 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 232 /* all contexts are initially 32-bytes */ 233 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 234 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 235 } 236 *ptr = htole32(val); 237 } 238 239 static uint32_t 240 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 241 { 242 if (sc->sc_ctx_is_64_byte) { 243 uint32_t offset; 244 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 245 /* all contexts are initially 32-bytes */ 246 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 247 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 248 } 249 return (le32toh(*ptr)); 250 } 251 252 static void 253 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 254 { 255 if (sc->sc_ctx_is_64_byte) { 256 uint32_t offset; 257 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 258 /* all contexts are initially 32-bytes */ 259 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 260 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 261 } 262 *ptr = htole64(val); 263 } 264 265 #ifdef USB_DEBUG 266 static uint64_t 267 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 268 { 269 if (sc->sc_ctx_is_64_byte) { 270 uint32_t offset; 271 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 272 /* all contexts are initially 32-bytes */ 273 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 274 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 275 } 276 return (le64toh(*ptr)); 277 } 278 #endif 279 280 static int 281 xhci_reset_command_queue_locked(struct xhci_softc *sc) 282 { 283 struct usb_page_search buf_res; 284 struct xhci_hw_root *phwr; 285 uint64_t addr; 286 uint32_t temp; 287 288 DPRINTF("\n"); 289 290 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 291 if (temp & XHCI_CRCR_LO_CRR) { 292 DPRINTF("Command ring running\n"); 293 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 294 295 /* 296 * Try to abort the last command as per section 297 * 4.6.1.2 "Aborting a Command" of the XHCI 298 * specification: 299 */ 300 301 /* stop and cancel */ 302 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 303 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 304 305 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 306 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 307 308 /* wait 250ms */ 309 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 4); 310 311 /* check if command ring is still running */ 312 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 313 if (temp & XHCI_CRCR_LO_CRR) { 314 DPRINTF("Command ring still running\n"); 315 return (USB_ERR_IOERROR); 316 } 317 } 318 319 /* reset command ring */ 320 sc->sc_command_ccs = 1; 321 sc->sc_command_idx = 0; 322 323 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 324 325 /* set up command ring control base address */ 326 addr = buf_res.physaddr; 327 phwr = buf_res.buffer; 328 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 329 330 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 331 332 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 333 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 334 335 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 336 337 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 338 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 339 340 return (0); 341 } 342 343 usb_error_t 344 xhci_start_controller(struct xhci_softc *sc) 345 { 346 struct usb_page_search buf_res; 347 struct xhci_hw_root *phwr; 348 struct xhci_dev_ctx_addr *pdctxa; 349 uint64_t addr; 350 uint32_t temp; 351 uint16_t i; 352 353 DPRINTF("\n"); 354 355 sc->sc_event_ccs = 1; 356 sc->sc_event_idx = 0; 357 sc->sc_command_ccs = 1; 358 sc->sc_command_idx = 0; 359 360 /* Reset controller */ 361 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 362 363 for (i = 0; i != 100; i++) { 364 usb_pause_mtx(NULL, hz / 100); 365 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 366 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 367 if (!temp) 368 break; 369 } 370 371 if (temp) { 372 device_printf(sc->sc_bus.parent, "Controller " 373 "reset timeout.\n"); 374 return (USB_ERR_IOERROR); 375 } 376 377 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 378 device_printf(sc->sc_bus.parent, "Controller does " 379 "not support 4K page size.\n"); 380 return (USB_ERR_IOERROR); 381 } 382 383 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 384 385 i = XHCI_HCS1_N_PORTS(temp); 386 387 if (i == 0) { 388 device_printf(sc->sc_bus.parent, "Invalid number " 389 "of ports: %u\n", i); 390 return (USB_ERR_IOERROR); 391 } 392 393 sc->sc_noport = i; 394 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 395 396 if (sc->sc_noslot > XHCI_MAX_DEVICES) 397 sc->sc_noslot = XHCI_MAX_DEVICES; 398 399 /* set up number of device slots */ 400 401 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 402 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 403 404 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 405 406 DPRINTF("Max slots: %u\n", sc->sc_noslot); 407 408 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 409 410 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 411 412 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 413 device_printf(sc->sc_bus.parent, "XHCI request " 414 "too many scratchpads\n"); 415 return (USB_ERR_NOMEM); 416 } 417 418 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 419 420 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 421 422 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 423 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 424 425 temp = XREAD4(sc, oper, XHCI_USBSTS); 426 427 /* clear interrupts */ 428 XWRITE4(sc, oper, XHCI_USBSTS, temp); 429 /* disable all device notifications */ 430 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 431 432 /* set up device context base address */ 433 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 434 pdctxa = buf_res.buffer; 435 memset(pdctxa, 0, sizeof(*pdctxa)); 436 437 addr = buf_res.physaddr; 438 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 439 440 /* slot 0 points to the table of scratchpad pointers */ 441 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 442 443 for (i = 0; i != sc->sc_noscratch; i++) { 444 struct usb_page_search buf_scp; 445 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 446 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 447 } 448 449 addr = buf_res.physaddr; 450 451 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 452 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 453 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 454 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 455 456 /* Setup event table size */ 457 458 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 459 460 DPRINTF("HCS2=0x%08x\n", temp); 461 462 temp = XHCI_HCS2_ERST_MAX(temp); 463 temp = 1U << temp; 464 if (temp > XHCI_MAX_RSEG) 465 temp = XHCI_MAX_RSEG; 466 467 sc->sc_erst_max = temp; 468 469 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 470 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 471 472 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 473 474 /* Check if we should use the default IMOD value */ 475 if (sc->sc_imod_default == 0) 476 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 477 478 /* Setup interrupt rate */ 479 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 480 481 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 482 483 phwr = buf_res.buffer; 484 addr = buf_res.physaddr; 485 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 486 487 /* reset hardware root structure */ 488 memset(phwr, 0, sizeof(*phwr)); 489 490 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 491 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 492 493 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 494 495 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 496 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 497 498 addr = buf_res.physaddr; 499 500 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 501 502 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 503 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 504 505 /* Setup interrupter registers */ 506 507 if (xhci_use_polling() == 0) { 508 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 509 temp |= XHCI_IMAN_INTR_ENA; 510 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 511 } 512 513 /* set up command ring control base address */ 514 addr = buf_res.physaddr; 515 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 516 517 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 518 519 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 520 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 521 522 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 523 524 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 525 526 /* Go! */ 527 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 528 XHCI_CMD_INTE | XHCI_CMD_HSEE); 529 530 for (i = 0; i != 100; i++) { 531 usb_pause_mtx(NULL, hz / 100); 532 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 533 if (!temp) 534 break; 535 } 536 if (temp) { 537 XWRITE4(sc, oper, XHCI_USBCMD, 0); 538 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 539 return (USB_ERR_IOERROR); 540 } 541 542 /* catch any lost interrupts */ 543 xhci_do_poll(&sc->sc_bus); 544 545 if (sc->sc_port_route != NULL) { 546 /* Route all ports to the XHCI by default */ 547 sc->sc_port_route(sc->sc_bus.parent, 548 ~xhciroute, xhciroute); 549 } 550 return (0); 551 } 552 553 usb_error_t 554 xhci_halt_controller(struct xhci_softc *sc) 555 { 556 uint32_t temp; 557 uint16_t i; 558 559 DPRINTF("\n"); 560 561 sc->sc_event_ccs = 1; 562 sc->sc_event_idx = 0; 563 sc->sc_command_ccs = 1; 564 sc->sc_command_idx = 0; 565 566 /* Halt controller */ 567 XWRITE4(sc, oper, XHCI_USBCMD, 0); 568 569 for (i = 0; i != 100; i++) { 570 usb_pause_mtx(NULL, hz / 100); 571 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 572 if (temp) 573 break; 574 } 575 576 if (!temp) { 577 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 578 return (USB_ERR_IOERROR); 579 } 580 return (0); 581 } 582 583 usb_error_t 584 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) 585 { 586 uint32_t temp; 587 588 DPRINTF("\n"); 589 590 /* initialise some bus fields */ 591 sc->sc_bus.parent = self; 592 593 /* set the bus revision */ 594 sc->sc_bus.usbrev = USB_REV_3_0; 595 596 /* set up the bus struct */ 597 sc->sc_bus.methods = &xhci_bus_methods; 598 599 /* set up devices array */ 600 sc->sc_bus.devices = sc->sc_devices; 601 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 602 603 /* set default cycle state in case of early interrupts */ 604 sc->sc_event_ccs = 1; 605 sc->sc_command_ccs = 1; 606 607 /* set up bus space offsets */ 608 sc->sc_capa_off = 0; 609 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 610 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 611 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 612 613 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 614 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 615 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 616 617 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 618 619 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 620 621 DPRINTF("HCS0 = 0x%08x\n", temp); 622 623 /* set up context size */ 624 if (XHCI_HCS0_CSZ(temp)) { 625 sc->sc_ctx_is_64_byte = 1; 626 } else { 627 sc->sc_ctx_is_64_byte = 0; 628 } 629 630 /* get DMA bits */ 631 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && 632 xhcidma32 == 0 && dma32 == 0) ? 64 : 32; 633 634 device_printf(self, "%d bytes context size, %d-bit DMA\n", 635 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 636 637 /* get all DMA memory */ 638 if (usb_bus_mem_alloc_all(&sc->sc_bus, 639 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 640 return (ENOMEM); 641 } 642 643 /* setup command queue mutex and condition varible */ 644 cv_init(&sc->sc_cmd_cv, "CMDQ"); 645 lockinit(&sc->sc_cmd_lock, "CMDQ lock", 0, LK_CANRECURSE); 646 647 /* set up command queue mutex and condition varible */ 648 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 649 sc->sc_config_msg[0].bus = &sc->sc_bus; 650 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 651 sc->sc_config_msg[1].bus = &sc->sc_bus; 652 653 return (0); 654 } 655 656 void 657 xhci_uninit(struct xhci_softc *sc) 658 { 659 /* 660 * NOTE: At this point the control transfer process is gone 661 * and "xhci_configure_msg" is no longer called. Consequently 662 * waiting for the configuration messages to complete is not 663 * needed. 664 */ 665 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 666 667 cv_destroy(&sc->sc_cmd_cv); 668 lockuninit(&sc->sc_cmd_lock); 669 } 670 671 static void 672 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 673 { 674 struct xhci_softc *sc = XHCI_BUS2SC(bus); 675 676 switch (state) { 677 case USB_HW_POWER_SUSPEND: 678 DPRINTF("Stopping the XHCI\n"); 679 xhci_halt_controller(sc); 680 break; 681 case USB_HW_POWER_SHUTDOWN: 682 DPRINTF("Stopping the XHCI\n"); 683 xhci_halt_controller(sc); 684 break; 685 case USB_HW_POWER_RESUME: 686 DPRINTF("Starting the XHCI\n"); 687 xhci_start_controller(sc); 688 break; 689 default: 690 break; 691 } 692 } 693 694 static usb_error_t 695 xhci_generic_done_sub(struct usb_xfer *xfer) 696 { 697 struct xhci_td *td; 698 struct xhci_td *td_alt_next; 699 uint32_t len; 700 uint8_t status; 701 702 td = xfer->td_transfer_cache; 703 td_alt_next = td->alt_next; 704 705 if (xfer->aframes != xfer->nframes) 706 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 707 708 while (1) { 709 710 usb_pc_cpu_invalidate(td->page_cache); 711 712 status = td->status; 713 len = td->remainder; 714 715 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 716 xfer, (unsigned int)xfer->aframes, 717 (unsigned int)xfer->nframes, 718 (unsigned int)len, (unsigned int)td->len, 719 (unsigned int)status); 720 721 /* 722 * Verify the status length and 723 * add the length to "frlengths[]": 724 */ 725 if (len > td->len) { 726 /* should not happen */ 727 DPRINTF("Invalid status length, " 728 "0x%04x/0x%04x bytes\n", len, td->len); 729 status = XHCI_TRB_ERROR_LENGTH; 730 } else if (xfer->aframes != xfer->nframes) { 731 xfer->frlengths[xfer->aframes] += td->len - len; 732 } 733 /* Check for last transfer */ 734 if (((void *)td) == xfer->td_transfer_last) { 735 td = NULL; 736 break; 737 } 738 /* Check for transfer error */ 739 if (status != XHCI_TRB_ERROR_SHORT_PKT && 740 status != XHCI_TRB_ERROR_SUCCESS) { 741 /* the transfer is finished */ 742 td = NULL; 743 break; 744 } 745 /* Check for short transfer */ 746 if (len > 0) { 747 if (xfer->flags_int.short_frames_ok || 748 xfer->flags_int.isochronous_xfr || 749 xfer->flags_int.control_xfr) { 750 /* follow alt next */ 751 td = td->alt_next; 752 } else { 753 /* the transfer is finished */ 754 td = NULL; 755 } 756 break; 757 } 758 td = td->obj_next; 759 760 if (td->alt_next != td_alt_next) { 761 /* this USB frame is complete */ 762 break; 763 } 764 } 765 766 /* update transfer cache */ 767 768 xfer->td_transfer_cache = td; 769 770 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 771 (status != XHCI_TRB_ERROR_SHORT_PKT && 772 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 773 USB_ERR_NORMAL_COMPLETION); 774 } 775 776 static void 777 xhci_generic_done(struct usb_xfer *xfer) 778 { 779 usb_error_t err = 0; 780 781 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 782 xfer, xfer->endpoint); 783 784 /* reset scanner */ 785 786 xfer->td_transfer_cache = xfer->td_transfer_first; 787 788 if (xfer->flags_int.control_xfr) { 789 790 if (xfer->flags_int.control_hdr) 791 err = xhci_generic_done_sub(xfer); 792 793 xfer->aframes = 1; 794 795 if (xfer->td_transfer_cache == NULL) 796 goto done; 797 } 798 799 while (xfer->aframes != xfer->nframes) { 800 801 err = xhci_generic_done_sub(xfer); 802 xfer->aframes++; 803 804 if (xfer->td_transfer_cache == NULL) 805 goto done; 806 } 807 808 if (xfer->flags_int.control_xfr && 809 !xfer->flags_int.control_act) 810 err = xhci_generic_done_sub(xfer); 811 done: 812 /* transfer is complete */ 813 xhci_device_done(xfer, err); 814 } 815 816 static void 817 xhci_activate_transfer(struct usb_xfer *xfer) 818 { 819 struct xhci_td *td; 820 821 td = xfer->td_transfer_cache; 822 823 usb_pc_cpu_invalidate(td->page_cache); 824 825 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 826 827 /* activate the transfer */ 828 829 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 830 usb_pc_cpu_flush(td->page_cache); 831 832 xhci_endpoint_doorbell(xfer); 833 } 834 } 835 836 static void 837 xhci_skip_transfer(struct usb_xfer *xfer) 838 { 839 struct xhci_td *td; 840 struct xhci_td *td_last; 841 842 td = xfer->td_transfer_cache; 843 td_last = xfer->td_transfer_last; 844 845 td = td->alt_next; 846 847 usb_pc_cpu_invalidate(td->page_cache); 848 849 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 850 851 usb_pc_cpu_invalidate(td_last->page_cache); 852 853 /* copy LINK TRB to current waiting location */ 854 855 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 856 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 857 usb_pc_cpu_flush(td->page_cache); 858 859 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 860 usb_pc_cpu_flush(td->page_cache); 861 862 xhci_endpoint_doorbell(xfer); 863 } 864 } 865 866 /*------------------------------------------------------------------------* 867 * xhci_check_transfer 868 *------------------------------------------------------------------------*/ 869 static void 870 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 871 { 872 struct xhci_endpoint_ext *pepext; 873 int64_t offset; 874 uint64_t td_event; 875 uint32_t temp; 876 uint32_t remainder; 877 uint16_t stream_id; 878 uint16_t i; 879 uint8_t status; 880 uint8_t halted; 881 uint8_t epno; 882 uint8_t index; 883 884 /* decode TRB */ 885 td_event = le64toh(trb->qwTrb0); 886 temp = le32toh(trb->dwTrb2); 887 888 remainder = XHCI_TRB_2_REM_GET(temp); 889 status = XHCI_TRB_2_ERROR_GET(temp); 890 stream_id = XHCI_TRB_2_STREAM_GET(temp); 891 892 temp = le32toh(trb->dwTrb3); 893 epno = XHCI_TRB_3_EP_GET(temp); 894 index = XHCI_TRB_3_SLOT_GET(temp); 895 896 /* check if error means halted */ 897 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 898 status != XHCI_TRB_ERROR_SUCCESS); 899 900 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 901 index, epno, stream_id, remainder, status); 902 903 if (index > sc->sc_noslot) { 904 DPRINTF("Invalid slot.\n"); 905 return; 906 } 907 908 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 909 DPRINTF("Invalid endpoint.\n"); 910 return; 911 } 912 913 pepext = &sc->sc_hw.devs[index].endp[epno]; 914 915 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 916 stream_id = 0; 917 DPRINTF("stream_id=0\n"); 918 } else if (stream_id >= XHCI_MAX_STREAMS) { 919 DPRINTF("Invalid stream ID.\n"); 920 return; 921 } 922 923 /* try to find the USB transfer that generated the event */ 924 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 925 struct usb_xfer *xfer; 926 struct xhci_td *td; 927 928 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 929 if (xfer == NULL) 930 continue; 931 932 td = xfer->td_transfer_cache; 933 934 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 935 (long long)td_event, 936 (long long)td->td_self, 937 (long long)td->td_self + sizeof(td->td_trb)); 938 939 /* 940 * NOTE: Some XHCI implementations might not trigger 941 * an event on the last LINK TRB so we need to 942 * consider both the last and second last event 943 * address as conditions for a successful transfer. 944 * 945 * NOTE: We assume that the XHCI will only trigger one 946 * event per chain of TRBs. 947 */ 948 949 offset = td_event - td->td_self; 950 951 if (offset >= 0 && 952 offset < (int64_t)sizeof(td->td_trb)) { 953 954 usb_pc_cpu_invalidate(td->page_cache); 955 956 /* compute rest of remainder, if any */ 957 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 958 temp = le32toh(td->td_trb[i].dwTrb2); 959 remainder += XHCI_TRB_2_BYTES_GET(temp); 960 } 961 962 DPRINTFN(5, "New remainder: %u\n", remainder); 963 964 /* clear isochronous transfer errors */ 965 if (xfer->flags_int.isochronous_xfr) { 966 if (halted) { 967 halted = 0; 968 status = XHCI_TRB_ERROR_SUCCESS; 969 remainder = td->len; 970 } 971 } 972 973 /* "td->remainder" is verified later */ 974 td->remainder = remainder; 975 td->status = status; 976 977 usb_pc_cpu_flush(td->page_cache); 978 979 /* 980 * 1) Last transfer descriptor makes the 981 * transfer done 982 */ 983 if (((void *)td) == xfer->td_transfer_last) { 984 DPRINTF("TD is last\n"); 985 xhci_generic_done(xfer); 986 break; 987 } 988 989 /* 990 * 2) Any kind of error makes the transfer 991 * done 992 */ 993 if (halted) { 994 DPRINTF("TD has I/O error\n"); 995 xhci_generic_done(xfer); 996 break; 997 } 998 999 /* 1000 * 3) If there is no alternate next transfer, 1001 * a short packet also makes the transfer done 1002 */ 1003 if (td->remainder > 0) { 1004 if (td->alt_next == NULL) { 1005 DPRINTF( 1006 "short TD has no alternate next\n"); 1007 xhci_generic_done(xfer); 1008 break; 1009 } 1010 DPRINTF("TD has short pkt\n"); 1011 if (xfer->flags_int.short_frames_ok || 1012 xfer->flags_int.isochronous_xfr || 1013 xfer->flags_int.control_xfr) { 1014 /* follow the alt next */ 1015 xfer->td_transfer_cache = td->alt_next; 1016 xhci_activate_transfer(xfer); 1017 break; 1018 } 1019 xhci_skip_transfer(xfer); 1020 xhci_generic_done(xfer); 1021 break; 1022 } 1023 1024 /* 1025 * 4) Transfer complete - go to next TD 1026 */ 1027 DPRINTF("Following next TD\n"); 1028 xfer->td_transfer_cache = td->obj_next; 1029 xhci_activate_transfer(xfer); 1030 break; /* there should only be one match */ 1031 } 1032 } 1033 } 1034 1035 static int 1036 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1037 { 1038 if (sc->sc_cmd_addr == trb->qwTrb0) { 1039 DPRINTF("Received command event\n"); 1040 sc->sc_cmd_result[0] = trb->dwTrb2; 1041 sc->sc_cmd_result[1] = trb->dwTrb3; 1042 cv_signal(&sc->sc_cmd_cv); 1043 return (1); /* command match */ 1044 } 1045 return (0); 1046 } 1047 1048 static int 1049 xhci_interrupt_poll(struct xhci_softc *sc) 1050 { 1051 struct usb_page_search buf_res; 1052 struct xhci_hw_root *phwr; 1053 uint64_t addr; 1054 uint32_t temp; 1055 int retval = 0; 1056 uint16_t i; 1057 uint8_t event; 1058 uint8_t j; 1059 uint8_t k; 1060 uint8_t t; 1061 1062 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1063 1064 phwr = buf_res.buffer; 1065 1066 /* Receive any events */ 1067 1068 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1069 1070 i = sc->sc_event_idx; 1071 j = sc->sc_event_ccs; 1072 t = 2; 1073 1074 while (1) { 1075 1076 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1077 1078 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1079 1080 if (j != k) 1081 break; 1082 1083 event = XHCI_TRB_3_TYPE_GET(temp); 1084 1085 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1086 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1087 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1088 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1089 1090 switch (event) { 1091 case XHCI_TRB_EVENT_TRANSFER: 1092 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1093 break; 1094 case XHCI_TRB_EVENT_CMD_COMPLETE: 1095 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1096 break; 1097 default: 1098 DPRINTF("Unhandled event = %u\n", event); 1099 break; 1100 } 1101 1102 i++; 1103 1104 if (i == XHCI_MAX_EVENTS) { 1105 i = 0; 1106 j ^= 1; 1107 1108 /* check for timeout */ 1109 if (!--t) 1110 break; 1111 } 1112 } 1113 1114 sc->sc_event_idx = i; 1115 sc->sc_event_ccs = j; 1116 1117 /* 1118 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1119 * latched. That means to activate the register we need to 1120 * write both the low and high double word of the 64-bit 1121 * register. 1122 */ 1123 1124 addr = buf_res.physaddr; 1125 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1126 1127 /* try to clear busy bit */ 1128 addr |= XHCI_ERDP_LO_BUSY; 1129 1130 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1131 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1132 1133 return (retval); 1134 } 1135 1136 static usb_error_t 1137 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1138 uint16_t timeout_ms) 1139 { 1140 struct usb_page_search buf_res; 1141 struct xhci_hw_root *phwr; 1142 uint64_t addr; 1143 uint32_t temp; 1144 uint8_t i; 1145 uint8_t j; 1146 uint8_t timeout = 0; 1147 int err; 1148 1149 XHCI_CMD_ASSERT_LOCKED(sc); 1150 1151 /* get hardware root structure */ 1152 1153 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1154 1155 phwr = buf_res.buffer; 1156 1157 /* Queue command */ 1158 1159 USB_BUS_LOCK(&sc->sc_bus); 1160 retry: 1161 i = sc->sc_command_idx; 1162 j = sc->sc_command_ccs; 1163 1164 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1165 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1166 (long long)le64toh(trb->qwTrb0), 1167 (long)le32toh(trb->dwTrb2), 1168 (long)le32toh(trb->dwTrb3)); 1169 1170 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1171 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1172 1173 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1174 1175 temp = trb->dwTrb3; 1176 1177 if (j) 1178 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1179 else 1180 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1181 1182 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1183 1184 phwr->hwr_commands[i].dwTrb3 = temp; 1185 1186 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1187 1188 addr = buf_res.physaddr; 1189 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1190 1191 sc->sc_cmd_addr = htole64(addr); 1192 1193 i++; 1194 1195 if (i == (XHCI_MAX_COMMANDS - 1)) { 1196 1197 if (j) { 1198 temp = htole32(XHCI_TRB_3_TC_BIT | 1199 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1200 XHCI_TRB_3_CYCLE_BIT); 1201 } else { 1202 temp = htole32(XHCI_TRB_3_TC_BIT | 1203 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1204 } 1205 1206 phwr->hwr_commands[i].dwTrb3 = temp; 1207 1208 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1209 1210 i = 0; 1211 j ^= 1; 1212 } 1213 1214 sc->sc_command_idx = i; 1215 sc->sc_command_ccs = j; 1216 1217 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1218 1219 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_lock, 1220 USB_MS_TO_TICKS(timeout_ms)); 1221 1222 /* 1223 * In some error cases event interrupts are not generated. 1224 * Poll one time to see if the command has completed. 1225 */ 1226 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1227 DPRINTF("Command was completed when polling\n"); 1228 err = 0; 1229 } 1230 if (err != 0) { 1231 DPRINTF("Command timeout!\n"); 1232 /* 1233 * After some weeks of continuous operation, it has 1234 * been observed that the ASMedia Technology, ASM1042 1235 * SuperSpeed USB Host Controller can suddenly stop 1236 * accepting commands via the command queue. Try to 1237 * first reset the command queue. If that fails do a 1238 * host controller reset. 1239 */ 1240 if (timeout == 0 && 1241 xhci_reset_command_queue_locked(sc) == 0) { 1242 temp = le32toh(trb->dwTrb3); 1243 1244 /* 1245 * Avoid infinite XHCI reset loops if the set 1246 * address command fails to respond due to a 1247 * non-enumerating device: 1248 */ 1249 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1250 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1251 DPRINTF("Set address timeout\n"); 1252 } else { 1253 timeout = 1; 1254 goto retry; 1255 } 1256 } else { 1257 DPRINTF("Controller reset!\n"); 1258 usb_bus_reset_async_locked(&sc->sc_bus); 1259 } 1260 err = USB_ERR_TIMEOUT; 1261 trb->dwTrb2 = 0; 1262 trb->dwTrb3 = 0; 1263 } else { 1264 temp = le32toh(sc->sc_cmd_result[0]); 1265 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1266 err = USB_ERR_IOERROR; 1267 1268 trb->dwTrb2 = sc->sc_cmd_result[0]; 1269 trb->dwTrb3 = sc->sc_cmd_result[1]; 1270 } 1271 1272 USB_BUS_UNLOCK(&sc->sc_bus); 1273 1274 return (err); 1275 } 1276 1277 #if 0 1278 static usb_error_t 1279 xhci_cmd_nop(struct xhci_softc *sc) 1280 { 1281 struct xhci_trb trb; 1282 uint32_t temp; 1283 1284 DPRINTF("\n"); 1285 1286 trb.qwTrb0 = 0; 1287 trb.dwTrb2 = 0; 1288 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1289 1290 trb.dwTrb3 = htole32(temp); 1291 1292 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1293 } 1294 #endif 1295 1296 static usb_error_t 1297 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1298 { 1299 struct xhci_trb trb; 1300 uint32_t temp; 1301 usb_error_t err; 1302 1303 DPRINTF("\n"); 1304 1305 trb.qwTrb0 = 0; 1306 trb.dwTrb2 = 0; 1307 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1308 1309 err = xhci_do_command(sc, &trb, 100 /* ms */); 1310 if (err) 1311 goto done; 1312 1313 temp = le32toh(trb.dwTrb3); 1314 1315 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1316 1317 done: 1318 return (err); 1319 } 1320 1321 static usb_error_t 1322 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1323 { 1324 struct xhci_trb trb; 1325 uint32_t temp; 1326 1327 DPRINTF("\n"); 1328 1329 trb.qwTrb0 = 0; 1330 trb.dwTrb2 = 0; 1331 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1332 XHCI_TRB_3_SLOT_SET(slot_id); 1333 1334 trb.dwTrb3 = htole32(temp); 1335 1336 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1337 } 1338 1339 static usb_error_t 1340 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1341 uint8_t bsr, uint8_t slot_id) 1342 { 1343 struct xhci_trb trb; 1344 uint32_t temp; 1345 1346 DPRINTF("\n"); 1347 1348 trb.qwTrb0 = htole64(input_ctx); 1349 trb.dwTrb2 = 0; 1350 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1351 XHCI_TRB_3_SLOT_SET(slot_id); 1352 1353 if (bsr) 1354 temp |= XHCI_TRB_3_BSR_BIT; 1355 1356 trb.dwTrb3 = htole32(temp); 1357 1358 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1359 } 1360 1361 static usb_error_t 1362 xhci_set_address(struct usb_device *udev, struct lock *lock, uint16_t address) 1363 { 1364 struct usb_page_search buf_inp; 1365 struct usb_page_search buf_dev; 1366 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1367 struct xhci_hw_dev *hdev; 1368 struct xhci_dev_ctx *pdev; 1369 struct xhci_endpoint_ext *pepext; 1370 uint32_t temp; 1371 uint16_t mps; 1372 usb_error_t err; 1373 uint8_t index; 1374 1375 /* the root HUB case is not handled here */ 1376 if (udev->parent_hub == NULL) 1377 return (USB_ERR_INVAL); 1378 1379 index = udev->controller_slot_id; 1380 1381 hdev = &sc->sc_hw.devs[index]; 1382 1383 if (lock != NULL) 1384 lockmgr(lock, LK_RELEASE); 1385 1386 XHCI_CMD_LOCK(sc); 1387 1388 switch (hdev->state) { 1389 case XHCI_ST_DEFAULT: 1390 case XHCI_ST_ENABLED: 1391 1392 hdev->state = XHCI_ST_ENABLED; 1393 1394 /* set configure mask to slot and EP0 */ 1395 xhci_configure_mask(udev, 3, 0); 1396 1397 /* configure input slot context structure */ 1398 err = xhci_configure_device(udev); 1399 1400 if (err != 0) { 1401 DPRINTF("Could not configure device\n"); 1402 break; 1403 } 1404 1405 /* configure input endpoint context structure */ 1406 switch (udev->speed) { 1407 case USB_SPEED_LOW: 1408 case USB_SPEED_FULL: 1409 mps = 8; 1410 break; 1411 case USB_SPEED_HIGH: 1412 mps = 64; 1413 break; 1414 default: 1415 mps = 512; 1416 break; 1417 } 1418 1419 pepext = xhci_get_endpoint_ext(udev, 1420 &udev->ctrl_ep_desc); 1421 1422 /* ensure the control endpoint is setup again */ 1423 USB_BUS_LOCK(udev->bus); 1424 pepext->trb_halted = 1; 1425 pepext->trb_running = 0; 1426 USB_BUS_UNLOCK(udev->bus); 1427 1428 err = xhci_configure_endpoint(udev, 1429 &udev->ctrl_ep_desc, pepext, 1430 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1431 1432 if (err != 0) { 1433 DPRINTF("Could not configure default endpoint\n"); 1434 break; 1435 } 1436 1437 /* execute set address command */ 1438 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1439 1440 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1441 (address == 0), index); 1442 1443 if (err != 0) { 1444 temp = le32toh(sc->sc_cmd_result[0]); 1445 if (address == 0 && sc->sc_port_route != NULL && 1446 XHCI_TRB_2_ERROR_GET(temp) == 1447 XHCI_TRB_ERROR_PARAMETER) { 1448 /* LynxPoint XHCI - ports are not switchable */ 1449 /* Un-route all ports from the XHCI */ 1450 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1451 } 1452 DPRINTF("Could not set address " 1453 "for slot %u.\n", index); 1454 if (address != 0) 1455 break; 1456 } 1457 1458 /* update device address to new value */ 1459 1460 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1461 pdev = buf_dev.buffer; 1462 usb_pc_cpu_invalidate(&hdev->device_pc); 1463 1464 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1465 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1466 1467 /* update device state to new value */ 1468 1469 if (address != 0) 1470 hdev->state = XHCI_ST_ADDRESSED; 1471 else 1472 hdev->state = XHCI_ST_DEFAULT; 1473 break; 1474 1475 default: 1476 DPRINTF("Wrong state for set address.\n"); 1477 err = USB_ERR_IOERROR; 1478 break; 1479 } 1480 XHCI_CMD_UNLOCK(sc); 1481 1482 if (lock != NULL) 1483 lockmgr(lock, LK_EXCLUSIVE); 1484 1485 return (err); 1486 } 1487 1488 static usb_error_t 1489 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1490 uint8_t deconfigure, uint8_t slot_id) 1491 { 1492 struct xhci_trb trb; 1493 uint32_t temp; 1494 1495 DPRINTF("\n"); 1496 1497 trb.qwTrb0 = htole64(input_ctx); 1498 trb.dwTrb2 = 0; 1499 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1500 XHCI_TRB_3_SLOT_SET(slot_id); 1501 1502 if (deconfigure) 1503 temp |= XHCI_TRB_3_DCEP_BIT; 1504 1505 trb.dwTrb3 = htole32(temp); 1506 1507 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1508 } 1509 1510 static usb_error_t 1511 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1512 uint8_t slot_id) 1513 { 1514 struct xhci_trb trb; 1515 uint32_t temp; 1516 1517 DPRINTF("\n"); 1518 1519 trb.qwTrb0 = htole64(input_ctx); 1520 trb.dwTrb2 = 0; 1521 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1522 XHCI_TRB_3_SLOT_SET(slot_id); 1523 trb.dwTrb3 = htole32(temp); 1524 1525 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1526 } 1527 1528 static usb_error_t 1529 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1530 uint8_t ep_id, uint8_t slot_id) 1531 { 1532 struct xhci_trb trb; 1533 uint32_t temp; 1534 1535 DPRINTF("\n"); 1536 1537 trb.qwTrb0 = 0; 1538 trb.dwTrb2 = 0; 1539 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1540 XHCI_TRB_3_SLOT_SET(slot_id) | 1541 XHCI_TRB_3_EP_SET(ep_id); 1542 1543 if (preserve) 1544 temp |= XHCI_TRB_3_PRSV_BIT; 1545 1546 trb.dwTrb3 = htole32(temp); 1547 1548 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1549 } 1550 1551 static usb_error_t 1552 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1553 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1554 { 1555 struct xhci_trb trb; 1556 uint32_t temp; 1557 1558 DPRINTF("\n"); 1559 1560 trb.qwTrb0 = htole64(dequeue_ptr); 1561 1562 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1563 trb.dwTrb2 = htole32(temp); 1564 1565 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1566 XHCI_TRB_3_SLOT_SET(slot_id) | 1567 XHCI_TRB_3_EP_SET(ep_id); 1568 trb.dwTrb3 = htole32(temp); 1569 1570 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1571 } 1572 1573 static usb_error_t 1574 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1575 uint8_t ep_id, uint8_t slot_id) 1576 { 1577 struct xhci_trb trb; 1578 uint32_t temp; 1579 1580 DPRINTF("\n"); 1581 1582 trb.qwTrb0 = 0; 1583 trb.dwTrb2 = 0; 1584 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1585 XHCI_TRB_3_SLOT_SET(slot_id) | 1586 XHCI_TRB_3_EP_SET(ep_id); 1587 1588 if (suspend) 1589 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1590 1591 trb.dwTrb3 = htole32(temp); 1592 1593 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1594 } 1595 1596 static usb_error_t 1597 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1598 { 1599 struct xhci_trb trb; 1600 uint32_t temp; 1601 1602 DPRINTF("\n"); 1603 1604 trb.qwTrb0 = 0; 1605 trb.dwTrb2 = 0; 1606 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1607 XHCI_TRB_3_SLOT_SET(slot_id); 1608 1609 trb.dwTrb3 = htole32(temp); 1610 1611 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1612 } 1613 1614 /*------------------------------------------------------------------------* 1615 * xhci_interrupt - XHCI interrupt handler 1616 *------------------------------------------------------------------------*/ 1617 void 1618 xhci_interrupt(struct xhci_softc *sc) 1619 { 1620 uint32_t status; 1621 uint32_t temp; 1622 1623 USB_BUS_LOCK(&sc->sc_bus); 1624 1625 status = XREAD4(sc, oper, XHCI_USBSTS); 1626 1627 /* acknowledge interrupts, if any */ 1628 if (status != 0) { 1629 XWRITE4(sc, oper, XHCI_USBSTS, status); 1630 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1631 } 1632 1633 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1634 1635 /* force clearing of pending interrupts */ 1636 if (temp & XHCI_IMAN_INTR_PEND) 1637 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1638 1639 /* check for event(s) */ 1640 xhci_interrupt_poll(sc); 1641 1642 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1643 XHCI_STS_HSE | XHCI_STS_HCE)) { 1644 1645 if (status & XHCI_STS_PCD) { 1646 xhci_root_intr(sc); 1647 } 1648 1649 if (status & XHCI_STS_HCH) { 1650 kprintf("%s: host controller halted\n", 1651 __func__); 1652 } 1653 1654 if (status & XHCI_STS_HSE) { 1655 kprintf("%s: host system error\n", 1656 __func__); 1657 } 1658 1659 if (status & XHCI_STS_HCE) { 1660 kprintf("%s: host controller error\n", 1661 __func__); 1662 } 1663 } 1664 USB_BUS_UNLOCK(&sc->sc_bus); 1665 } 1666 1667 /*------------------------------------------------------------------------* 1668 * xhci_timeout - XHCI timeout handler 1669 *------------------------------------------------------------------------*/ 1670 static void 1671 xhci_timeout(void *arg) 1672 { 1673 struct usb_xfer *xfer = arg; 1674 1675 DPRINTF("xfer=%p\n", xfer); 1676 1677 USB_BUS_LOCK_ASSERT(xfer->xroot->bus); 1678 1679 /* transfer is transferred */ 1680 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1681 } 1682 1683 static void 1684 xhci_do_poll(struct usb_bus *bus) 1685 { 1686 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1687 1688 USB_BUS_LOCK(&sc->sc_bus); 1689 xhci_interrupt_poll(sc); 1690 USB_BUS_UNLOCK(&sc->sc_bus); 1691 } 1692 1693 static void 1694 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1695 { 1696 struct usb_page_search buf_res; 1697 struct xhci_td *td; 1698 struct xhci_td *td_next; 1699 struct xhci_td *td_alt_next; 1700 struct xhci_td *td_first; 1701 uint32_t buf_offset; 1702 uint32_t average; 1703 uint32_t len_old; 1704 uint32_t npkt_off; 1705 uint32_t dword; 1706 uint8_t shortpkt_old; 1707 uint8_t precompute; 1708 uint8_t x; 1709 1710 td_alt_next = NULL; 1711 buf_offset = 0; 1712 shortpkt_old = temp->shortpkt; 1713 len_old = temp->len; 1714 npkt_off = 0; 1715 precompute = 1; 1716 1717 restart: 1718 1719 td = temp->td; 1720 td_next = td_first = temp->td_next; 1721 1722 while (1) { 1723 1724 if (temp->len == 0) { 1725 1726 if (temp->shortpkt) 1727 break; 1728 1729 /* send a Zero Length Packet, ZLP, last */ 1730 1731 temp->shortpkt = 1; 1732 average = 0; 1733 1734 } else { 1735 1736 average = temp->average; 1737 1738 if (temp->len < average) { 1739 if (temp->len % temp->max_packet_size) { 1740 temp->shortpkt = 1; 1741 } 1742 average = temp->len; 1743 } 1744 } 1745 1746 if (td_next == NULL) 1747 panic("%s: out of XHCI transfer descriptors!", __func__); 1748 1749 /* get next TD */ 1750 1751 td = td_next; 1752 td_next = td->obj_next; 1753 1754 /* check if we are pre-computing */ 1755 1756 if (precompute) { 1757 1758 /* update remaining length */ 1759 1760 temp->len -= average; 1761 1762 continue; 1763 } 1764 /* fill out current TD */ 1765 1766 td->len = average; 1767 td->remainder = 0; 1768 td->status = 0; 1769 1770 /* update remaining length */ 1771 1772 temp->len -= average; 1773 1774 /* reset TRB index */ 1775 1776 x = 0; 1777 1778 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1779 /* immediate data */ 1780 1781 if (average > 8) 1782 average = 8; 1783 1784 td->td_trb[0].qwTrb0 = 0; 1785 1786 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1787 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1788 average); 1789 1790 dword = XHCI_TRB_2_BYTES_SET(8) | 1791 XHCI_TRB_2_TDSZ_SET(0) | 1792 XHCI_TRB_2_IRQ_SET(0); 1793 1794 td->td_trb[0].dwTrb2 = htole32(dword); 1795 1796 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1797 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1798 1799 /* check wLength */ 1800 if (td->td_trb[0].qwTrb0 & 1801 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1802 if (td->td_trb[0].qwTrb0 & 1803 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1804 dword |= XHCI_TRB_3_TRT_IN; 1805 else 1806 dword |= XHCI_TRB_3_TRT_OUT; 1807 } 1808 1809 td->td_trb[0].dwTrb3 = htole32(dword); 1810 #ifdef USB_DEBUG 1811 xhci_dump_trb(&td->td_trb[x]); 1812 #endif 1813 x++; 1814 1815 } else do { 1816 1817 uint32_t npkt; 1818 1819 /* fill out buffer pointers */ 1820 1821 if (average == 0) { 1822 memset(&buf_res, 0, sizeof(buf_res)); 1823 } else { 1824 usbd_get_page(temp->pc, temp->offset + 1825 buf_offset, &buf_res); 1826 1827 /* get length to end of page */ 1828 if (buf_res.length > average) 1829 buf_res.length = average; 1830 1831 /* check for maximum length */ 1832 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1833 buf_res.length = XHCI_TD_PAGE_SIZE; 1834 1835 npkt_off += buf_res.length; 1836 } 1837 1838 /* set up npkt */ 1839 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1840 temp->max_packet_size; 1841 1842 if (npkt == 0) 1843 npkt = 1; 1844 else if (npkt > 31) 1845 npkt = 31; 1846 1847 /* fill out TRB's */ 1848 td->td_trb[x].qwTrb0 = 1849 htole64((uint64_t)buf_res.physaddr); 1850 1851 dword = 1852 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1853 XHCI_TRB_2_TDSZ_SET(npkt) | 1854 XHCI_TRB_2_IRQ_SET(0); 1855 1856 td->td_trb[x].dwTrb2 = htole32(dword); 1857 1858 switch (temp->trb_type) { 1859 case XHCI_TRB_TYPE_ISOCH: 1860 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1861 XHCI_TRB_3_TBC_SET(temp->tbc) | 1862 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1863 if (td != td_first) { 1864 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1865 } else if (temp->do_isoc_sync != 0) { 1866 temp->do_isoc_sync = 0; 1867 /* wait until "isoc_frame" */ 1868 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1869 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1870 } else { 1871 /* start data transfer at next interval */ 1872 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1873 XHCI_TRB_3_ISO_SIA_BIT; 1874 } 1875 if (temp->direction == UE_DIR_IN) 1876 dword |= XHCI_TRB_3_ISP_BIT; 1877 break; 1878 case XHCI_TRB_TYPE_DATA_STAGE: 1879 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1880 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1881 if (temp->direction == UE_DIR_IN) 1882 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1883 /* 1884 * Section 3.2.9 in the XHCI 1885 * specification about control 1886 * transfers says that we should use a 1887 * normal-TRB if there are more TRBs 1888 * extending the data-stage 1889 * TRB. Update the "trb_type". 1890 */ 1891 temp->trb_type = XHCI_TRB_TYPE_NORMAL; 1892 break; 1893 case XHCI_TRB_TYPE_STATUS_STAGE: 1894 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1895 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1896 if (temp->direction == UE_DIR_IN) 1897 dword |= XHCI_TRB_3_DIR_IN; 1898 break; 1899 default: /* XHCI_TRB_TYPE_NORMAL */ 1900 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1901 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1902 if (temp->direction == UE_DIR_IN) 1903 dword |= XHCI_TRB_3_ISP_BIT; 1904 break; 1905 } 1906 td->td_trb[x].dwTrb3 = htole32(dword); 1907 1908 average -= buf_res.length; 1909 buf_offset += buf_res.length; 1910 #ifdef USB_DEBUG 1911 xhci_dump_trb(&td->td_trb[x]); 1912 #endif 1913 x++; 1914 1915 } while (average != 0); 1916 1917 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1918 1919 /* store number of data TRB's */ 1920 1921 td->ntrb = x; 1922 1923 DPRINTF("NTRB=%u\n", x); 1924 1925 /* fill out link TRB */ 1926 1927 if (td_next != NULL) { 1928 /* link the current TD with the next one */ 1929 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1930 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1931 } else { 1932 /* this field will get updated later */ 1933 DPRINTF("NOLINK\n"); 1934 } 1935 1936 dword = XHCI_TRB_2_IRQ_SET(0); 1937 1938 td->td_trb[x].dwTrb2 = htole32(dword); 1939 1940 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1941 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1942 /* 1943 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1944 * frame only receives a single short packet event 1945 * by setting the CHAIN bit in the LINK field. In 1946 * addition some XHCI controllers have problems 1947 * sending a ZLP unless the CHAIN-BIT is set in 1948 * the LINK TRB. 1949 */ 1950 XHCI_TRB_3_CHAIN_BIT; 1951 1952 td->td_trb[x].dwTrb3 = htole32(dword); 1953 1954 td->alt_next = td_alt_next; 1955 #ifdef USB_DEBUG 1956 xhci_dump_trb(&td->td_trb[x]); 1957 #endif 1958 usb_pc_cpu_flush(td->page_cache); 1959 } 1960 1961 if (precompute) { 1962 precompute = 0; 1963 1964 /* set up alt next pointer, if any */ 1965 if (temp->last_frame) { 1966 td_alt_next = NULL; 1967 } else { 1968 /* we use this field internally */ 1969 td_alt_next = td_next; 1970 } 1971 1972 /* restore */ 1973 temp->shortpkt = shortpkt_old; 1974 temp->len = len_old; 1975 goto restart; 1976 } 1977 1978 /* 1979 * Remove cycle bit from the first TRB if we are 1980 * stepping them: 1981 */ 1982 if (temp->step_td != 0) { 1983 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1984 usb_pc_cpu_flush(td_first->page_cache); 1985 } 1986 1987 /* clear TD SIZE to zero, hence this is the last TRB */ 1988 /* remove chain bit because this is the last data TRB in the chain */ 1989 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1990 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1991 /* remove CHAIN-BIT from last LINK TRB */ 1992 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1993 1994 usb_pc_cpu_flush(td->page_cache); 1995 1996 temp->td = td; 1997 temp->td_next = td_next; 1998 } 1999 2000 static void 2001 xhci_setup_generic_chain(struct usb_xfer *xfer) 2002 { 2003 struct xhci_std_temp temp; 2004 struct xhci_td *td; 2005 uint32_t x; 2006 uint32_t y; 2007 uint8_t mult; 2008 2009 temp.do_isoc_sync = 0; 2010 temp.step_td = 0; 2011 temp.tbc = 0; 2012 temp.tlbpc = 0; 2013 temp.average = xfer->max_hc_frame_size; 2014 temp.max_packet_size = xfer->max_packet_size; 2015 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 2016 temp.pc = NULL; 2017 temp.last_frame = 0; 2018 temp.offset = 0; 2019 temp.multishort = xfer->flags_int.isochronous_xfr || 2020 xfer->flags_int.control_xfr || 2021 xfer->flags_int.short_frames_ok; 2022 2023 /* toggle the DMA set we are using */ 2024 xfer->flags_int.curr_dma_set ^= 1; 2025 2026 /* get next DMA set */ 2027 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2028 2029 temp.td = NULL; 2030 temp.td_next = td; 2031 2032 xfer->td_transfer_first = td; 2033 xfer->td_transfer_cache = td; 2034 2035 if (xfer->flags_int.isochronous_xfr) { 2036 uint8_t shift; 2037 2038 /* compute multiplier for ISOCHRONOUS transfers */ 2039 mult = xfer->endpoint->ecomp ? 2040 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2041 : 0; 2042 /* check for USB 2.0 multiplier */ 2043 if (mult == 0) { 2044 mult = (xfer->endpoint->edesc-> 2045 wMaxPacketSize[1] >> 3) & 3; 2046 } 2047 /* range check */ 2048 if (mult > 2) 2049 mult = 3; 2050 else 2051 mult++; 2052 2053 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2054 2055 DPRINTF("MFINDEX=0x%08x\n", x); 2056 2057 switch (usbd_get_speed(xfer->xroot->udev)) { 2058 case USB_SPEED_FULL: 2059 shift = 3; 2060 temp.isoc_delta = 8; /* 1ms */ 2061 x += temp.isoc_delta - 1; 2062 x &= ~(temp.isoc_delta - 1); 2063 break; 2064 default: 2065 shift = usbd_xfer_get_fps_shift(xfer); 2066 temp.isoc_delta = 1U << shift; 2067 x += temp.isoc_delta - 1; 2068 x &= ~(temp.isoc_delta - 1); 2069 /* simple frame load balancing */ 2070 x += xfer->endpoint->usb_uframe; 2071 break; 2072 } 2073 2074 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2075 2076 if ((xfer->endpoint->is_synced == 0) || 2077 (y < (xfer->nframes << shift)) || 2078 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2079 /* 2080 * If there is data underflow or the pipe 2081 * queue is empty we schedule the transfer a 2082 * few frames ahead of the current frame 2083 * position. Else two isochronous transfers 2084 * might overlap. 2085 */ 2086 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2087 xfer->endpoint->is_synced = 1; 2088 temp.do_isoc_sync = 1; 2089 2090 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2091 } 2092 2093 /* compute isochronous completion time */ 2094 2095 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2096 2097 xfer->isoc_time_complete = 2098 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2099 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2100 2101 x = 0; 2102 temp.isoc_frame = xfer->endpoint->isoc_next; 2103 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2104 2105 xfer->endpoint->isoc_next += xfer->nframes << shift; 2106 2107 } else if (xfer->flags_int.control_xfr) { 2108 2109 /* check if we should prepend a setup message */ 2110 2111 if (xfer->flags_int.control_hdr) { 2112 2113 temp.len = xfer->frlengths[0]; 2114 temp.pc = xfer->frbuffers + 0; 2115 temp.shortpkt = temp.len ? 1 : 0; 2116 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2117 temp.direction = 0; 2118 2119 /* check for last frame */ 2120 if (xfer->nframes == 1) { 2121 /* no STATUS stage yet, SETUP is last */ 2122 if (xfer->flags_int.control_act) 2123 temp.last_frame = 1; 2124 } 2125 2126 xhci_setup_generic_chain_sub(&temp); 2127 } 2128 x = 1; 2129 mult = 1; 2130 temp.isoc_delta = 0; 2131 temp.isoc_frame = 0; 2132 temp.trb_type = xfer->flags_int.control_did_data ? 2133 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE; 2134 } else { 2135 x = 0; 2136 mult = 1; 2137 temp.isoc_delta = 0; 2138 temp.isoc_frame = 0; 2139 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2140 } 2141 2142 if (x != xfer->nframes) { 2143 /* set up page_cache pointer */ 2144 temp.pc = xfer->frbuffers + x; 2145 /* set endpoint direction */ 2146 temp.direction = UE_GET_DIR(xfer->endpointno); 2147 } 2148 2149 while (x != xfer->nframes) { 2150 2151 /* DATA0 / DATA1 message */ 2152 2153 temp.len = xfer->frlengths[x]; 2154 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2155 x != 0 && temp.multishort == 0); 2156 2157 x++; 2158 2159 if (x == xfer->nframes) { 2160 if (xfer->flags_int.control_xfr) { 2161 /* no STATUS stage yet, DATA is last */ 2162 if (xfer->flags_int.control_act) 2163 temp.last_frame = 1; 2164 } else { 2165 temp.last_frame = 1; 2166 } 2167 } 2168 if (temp.len == 0) { 2169 2170 /* make sure that we send an USB packet */ 2171 2172 temp.shortpkt = 0; 2173 2174 temp.tbc = 0; 2175 temp.tlbpc = mult - 1; 2176 2177 } else if (xfer->flags_int.isochronous_xfr) { 2178 2179 uint8_t tdpc; 2180 2181 /* 2182 * Isochronous transfers don't have short 2183 * packet termination: 2184 */ 2185 2186 temp.shortpkt = 1; 2187 2188 /* isochronous transfers have a transfer limit */ 2189 2190 if (temp.len > xfer->max_frame_size) 2191 temp.len = xfer->max_frame_size; 2192 2193 /* compute TD packet count */ 2194 tdpc = (temp.len + xfer->max_packet_size - 1) / 2195 xfer->max_packet_size; 2196 2197 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2198 temp.tlbpc = (tdpc % mult); 2199 2200 if (temp.tlbpc == 0) 2201 temp.tlbpc = mult - 1; 2202 else 2203 temp.tlbpc--; 2204 } else { 2205 2206 /* regular data transfer */ 2207 2208 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2209 } 2210 2211 xhci_setup_generic_chain_sub(&temp); 2212 2213 if (xfer->flags_int.isochronous_xfr) { 2214 temp.offset += xfer->frlengths[x - 1]; 2215 temp.isoc_frame += temp.isoc_delta; 2216 } else { 2217 /* get next Page Cache pointer */ 2218 temp.pc = xfer->frbuffers + x; 2219 } 2220 } 2221 2222 /* check if we should append a status stage */ 2223 2224 if (xfer->flags_int.control_xfr && 2225 !xfer->flags_int.control_act) { 2226 2227 /* 2228 * Send a DATA1 message and invert the current 2229 * endpoint direction. 2230 */ 2231 temp.step_td = (xfer->nframes != 0); 2232 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2233 temp.len = 0; 2234 temp.pc = NULL; 2235 temp.shortpkt = 0; 2236 temp.last_frame = 1; 2237 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2238 2239 xhci_setup_generic_chain_sub(&temp); 2240 } 2241 2242 td = temp.td; 2243 2244 /* must have at least one frame! */ 2245 2246 xfer->td_transfer_last = td; 2247 2248 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2249 } 2250 2251 static void 2252 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2253 { 2254 struct usb_page_search buf_res; 2255 struct xhci_dev_ctx_addr *pdctxa; 2256 2257 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2258 2259 pdctxa = buf_res.buffer; 2260 2261 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2262 2263 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2264 2265 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2266 } 2267 2268 static usb_error_t 2269 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2270 { 2271 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2272 struct usb_page_search buf_inp; 2273 struct xhci_input_dev_ctx *pinp; 2274 uint32_t temp; 2275 uint8_t index; 2276 uint8_t x; 2277 2278 index = udev->controller_slot_id; 2279 2280 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2281 2282 pinp = buf_inp.buffer; 2283 2284 if (drop) { 2285 mask &= XHCI_INCTX_NON_CTRL_MASK; 2286 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2287 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2288 } else { 2289 /* 2290 * Some hardware requires that we drop the endpoint 2291 * context before adding it again: 2292 */ 2293 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 2294 mask & XHCI_INCTX_NON_CTRL_MASK); 2295 2296 /* Add new endpoint context */ 2297 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2298 2299 /* find most significant set bit */ 2300 for (x = 31; x != 1; x--) { 2301 if (mask & (1 << x)) 2302 break; 2303 } 2304 2305 /* adjust */ 2306 x--; 2307 2308 /* figure out the maximum number of contexts */ 2309 if (x > sc->sc_hw.devs[index].context_num) 2310 sc->sc_hw.devs[index].context_num = x; 2311 else 2312 x = sc->sc_hw.devs[index].context_num; 2313 2314 /* update number of contexts */ 2315 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2316 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2317 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2318 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2319 } 2320 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2321 return (0); 2322 } 2323 2324 static usb_error_t 2325 xhci_configure_endpoint(struct usb_device *udev, 2326 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2327 uint16_t interval, uint8_t max_packet_count, 2328 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2329 uint16_t max_frame_size, uint8_t ep_mode) 2330 { 2331 struct usb_page_search buf_inp; 2332 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2333 struct xhci_input_dev_ctx *pinp; 2334 uint64_t ring_addr = pepext->physaddr; 2335 uint32_t temp; 2336 uint8_t index; 2337 uint8_t epno; 2338 uint8_t type; 2339 2340 index = udev->controller_slot_id; 2341 2342 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2343 2344 pinp = buf_inp.buffer; 2345 2346 epno = edesc->bEndpointAddress; 2347 type = edesc->bmAttributes & UE_XFERTYPE; 2348 2349 if (type == UE_CONTROL) 2350 epno |= UE_DIR_IN; 2351 2352 epno = XHCI_EPNO2EPID(epno); 2353 2354 if (epno == 0) 2355 return (USB_ERR_NO_PIPE); /* invalid */ 2356 2357 if (max_packet_count == 0) 2358 return (USB_ERR_BAD_BUFSIZE); 2359 2360 max_packet_count--; 2361 2362 if (mult == 0) 2363 return (USB_ERR_BAD_BUFSIZE); 2364 2365 /* store endpoint mode */ 2366 pepext->trb_ep_mode = ep_mode; 2367 usb_pc_cpu_flush(pepext->page_cache); 2368 2369 if (ep_mode == USB_EP_MODE_STREAMS) { 2370 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2371 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2372 XHCI_EPCTX_0_LSA_SET(1); 2373 2374 ring_addr += sizeof(struct xhci_trb) * 2375 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2376 } else { 2377 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2378 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2379 XHCI_EPCTX_0_LSA_SET(0); 2380 2381 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2382 } 2383 2384 switch (udev->speed) { 2385 case USB_SPEED_FULL: 2386 case USB_SPEED_LOW: 2387 /* 1ms -> 125us */ 2388 fps_shift += 3; 2389 break; 2390 default: 2391 break; 2392 } 2393 2394 switch (type) { 2395 case UE_INTERRUPT: 2396 if (fps_shift > 3) 2397 fps_shift--; 2398 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2399 break; 2400 case UE_ISOCHRONOUS: 2401 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2402 2403 switch (udev->speed) { 2404 case USB_SPEED_SUPER: 2405 if (mult > 3) 2406 mult = 3; 2407 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2408 max_packet_count /= mult; 2409 break; 2410 default: 2411 break; 2412 } 2413 break; 2414 default: 2415 break; 2416 } 2417 2418 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2419 2420 temp = 2421 XHCI_EPCTX_1_HID_SET(0) | 2422 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2423 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2424 2425 /* 2426 * Always enable the "three strikes and you are gone" feature 2427 * except for ISOCHRONOUS endpoints. This is suggested by 2428 * section 4.3.3 in the XHCI specification about device slot 2429 * initialisation. 2430 */ 2431 if (type != UE_ISOCHRONOUS) 2432 temp |= XHCI_EPCTX_1_CERR_SET(3); 2433 2434 switch (type) { 2435 case UE_CONTROL: 2436 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2437 break; 2438 case UE_ISOCHRONOUS: 2439 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2440 break; 2441 case UE_BULK: 2442 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2443 break; 2444 default: 2445 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2446 break; 2447 } 2448 2449 /* check for IN direction */ 2450 if (epno & 1) 2451 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2452 2453 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2454 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2455 2456 switch (edesc->bmAttributes & UE_XFERTYPE) { 2457 case UE_INTERRUPT: 2458 case UE_ISOCHRONOUS: 2459 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2460 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2461 max_frame_size)); 2462 break; 2463 case UE_CONTROL: 2464 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2465 break; 2466 default: 2467 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2468 break; 2469 } 2470 2471 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2472 2473 #ifdef USB_DEBUG 2474 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2475 #endif 2476 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2477 2478 return (0); /* success */ 2479 } 2480 2481 static usb_error_t 2482 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2483 { 2484 struct xhci_endpoint_ext *pepext; 2485 struct usb_endpoint_ss_comp_descriptor *ecomp; 2486 usb_stream_t x; 2487 2488 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2489 xfer->endpoint->edesc); 2490 2491 ecomp = xfer->endpoint->ecomp; 2492 2493 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2494 uint64_t temp; 2495 2496 /* halt any transfers */ 2497 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2498 2499 /* compute start of TRB ring for stream "x" */ 2500 temp = pepext->physaddr + 2501 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2502 XHCI_SCTX_0_SCT_SEC_TR_RING; 2503 2504 /* make tree structure */ 2505 pepext->trb[(XHCI_MAX_TRANSFERS * 2506 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2507 2508 /* reserved fields */ 2509 pepext->trb[(XHCI_MAX_TRANSFERS * 2510 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2511 pepext->trb[(XHCI_MAX_TRANSFERS * 2512 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2513 } 2514 usb_pc_cpu_flush(pepext->page_cache); 2515 2516 return (xhci_configure_endpoint(xfer->xroot->udev, 2517 xfer->endpoint->edesc, pepext, 2518 xfer->interval, xfer->max_packet_count, 2519 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2520 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2521 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2522 } 2523 2524 static usb_error_t 2525 xhci_configure_device(struct usb_device *udev) 2526 { 2527 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2528 struct usb_page_search buf_inp; 2529 struct usb_page_cache *pcinp; 2530 struct xhci_input_dev_ctx *pinp; 2531 struct usb_device *hubdev; 2532 uint32_t temp; 2533 uint32_t route; 2534 uint32_t rh_port; 2535 uint8_t is_hub; 2536 uint8_t index; 2537 uint8_t depth; 2538 2539 index = udev->controller_slot_id; 2540 2541 DPRINTF("index=%u\n", index); 2542 2543 pcinp = &sc->sc_hw.devs[index].input_pc; 2544 2545 usbd_get_page(pcinp, 0, &buf_inp); 2546 2547 pinp = buf_inp.buffer; 2548 2549 rh_port = 0; 2550 route = 0; 2551 2552 /* figure out route string and root HUB port number */ 2553 2554 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2555 2556 if (hubdev->parent_hub == NULL) 2557 break; 2558 2559 depth = hubdev->parent_hub->depth; 2560 2561 /* 2562 * NOTE: HS/FS/LS devices and the SS root HUB can have 2563 * more than 15 ports 2564 */ 2565 2566 rh_port = hubdev->port_no; 2567 2568 if (depth == 0) 2569 break; 2570 2571 if (rh_port > 15) 2572 rh_port = 15; 2573 2574 if (depth < 6) 2575 route |= rh_port << (4 * (depth - 1)); 2576 } 2577 2578 DPRINTF("Route=0x%08x\n", route); 2579 2580 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2581 XHCI_SCTX_0_CTX_NUM_SET( 2582 sc->sc_hw.devs[index].context_num + 1); 2583 2584 switch (udev->speed) { 2585 case USB_SPEED_LOW: 2586 temp |= XHCI_SCTX_0_SPEED_SET(2); 2587 if (udev->parent_hs_hub != NULL && 2588 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2589 UDPROTO_HSHUBMTT) { 2590 DPRINTF("Device inherits MTT\n"); 2591 temp |= XHCI_SCTX_0_MTT_SET(1); 2592 } 2593 break; 2594 case USB_SPEED_HIGH: 2595 temp |= XHCI_SCTX_0_SPEED_SET(3); 2596 if (sc->sc_hw.devs[index].nports != 0 && 2597 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2598 DPRINTF("HUB supports MTT\n"); 2599 temp |= XHCI_SCTX_0_MTT_SET(1); 2600 } 2601 break; 2602 case USB_SPEED_FULL: 2603 temp |= XHCI_SCTX_0_SPEED_SET(1); 2604 if (udev->parent_hs_hub != NULL && 2605 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2606 UDPROTO_HSHUBMTT) { 2607 DPRINTF("Device inherits MTT\n"); 2608 temp |= XHCI_SCTX_0_MTT_SET(1); 2609 } 2610 break; 2611 default: 2612 temp |= XHCI_SCTX_0_SPEED_SET(4); 2613 break; 2614 } 2615 2616 is_hub = sc->sc_hw.devs[index].nports != 0 && 2617 (udev->speed == USB_SPEED_SUPER || 2618 udev->speed == USB_SPEED_HIGH); 2619 2620 if (is_hub) { 2621 temp |= XHCI_SCTX_0_HUB_SET(1); 2622 } 2623 2624 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2625 2626 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2627 2628 if (is_hub) { 2629 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2630 sc->sc_hw.devs[index].nports); 2631 } 2632 2633 switch (udev->speed) { 2634 case USB_SPEED_SUPER: 2635 switch (sc->sc_hw.devs[index].state) { 2636 case XHCI_ST_ADDRESSED: 2637 case XHCI_ST_CONFIGURED: 2638 /* enable power save */ 2639 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2640 break; 2641 default: 2642 /* disable power save */ 2643 break; 2644 } 2645 break; 2646 default: 2647 break; 2648 } 2649 2650 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2651 2652 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2653 2654 if (is_hub) { 2655 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2656 sc->sc_hw.devs[index].tt); 2657 } 2658 2659 hubdev = udev->parent_hs_hub; 2660 2661 /* check if we should activate the transaction translator */ 2662 switch (udev->speed) { 2663 case USB_SPEED_FULL: 2664 case USB_SPEED_LOW: 2665 if (hubdev != NULL) { 2666 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2667 hubdev->controller_slot_id); 2668 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2669 udev->hs_port_no); 2670 } 2671 break; 2672 default: 2673 break; 2674 } 2675 2676 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2677 2678 /* 2679 * These fields should be initialized to zero, according to 2680 * XHCI section 6.2.2 - slot context: 2681 */ 2682 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2683 XHCI_SCTX_3_SLOT_STATE_SET(0); 2684 2685 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2686 2687 #ifdef USB_DEBUG 2688 xhci_dump_device(sc, &pinp->ctx_slot); 2689 #endif 2690 usb_pc_cpu_flush(pcinp); 2691 2692 return (0); /* success */ 2693 } 2694 2695 static usb_error_t 2696 xhci_alloc_device_ext(struct usb_device *udev) 2697 { 2698 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2699 struct usb_page_search buf_dev; 2700 struct usb_page_search buf_ep; 2701 struct xhci_trb *trb; 2702 struct usb_page_cache *pc; 2703 struct usb_page *pg; 2704 uint64_t addr; 2705 uint8_t index; 2706 uint8_t i; 2707 2708 index = udev->controller_slot_id; 2709 2710 pc = &sc->sc_hw.devs[index].device_pc; 2711 pg = &sc->sc_hw.devs[index].device_pg; 2712 2713 /* need to initialize the page cache */ 2714 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2715 2716 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2717 (2 * sizeof(struct xhci_dev_ctx)) : 2718 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2719 goto error; 2720 2721 usbd_get_page(pc, 0, &buf_dev); 2722 2723 pc = &sc->sc_hw.devs[index].input_pc; 2724 pg = &sc->sc_hw.devs[index].input_pg; 2725 2726 /* need to initialize the page cache */ 2727 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2728 2729 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2730 (2 * sizeof(struct xhci_input_dev_ctx)) : 2731 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2732 goto error; 2733 } 2734 2735 /* initialize all endpoint LINK TRBs */ 2736 2737 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2738 2739 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2740 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2741 2742 /* need to initialize the page cache */ 2743 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2744 2745 if (usb_pc_alloc_mem(pc, pg, 2746 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2747 goto error; 2748 } 2749 2750 /* lookup endpoint TRB ring */ 2751 usbd_get_page(pc, 0, &buf_ep); 2752 2753 /* get TRB pointer */ 2754 trb = buf_ep.buffer; 2755 trb += XHCI_MAX_TRANSFERS - 1; 2756 2757 /* get TRB start address */ 2758 addr = buf_ep.physaddr; 2759 2760 /* create LINK TRB */ 2761 trb->qwTrb0 = htole64(addr); 2762 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2763 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2764 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2765 2766 usb_pc_cpu_flush(pc); 2767 } 2768 2769 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2770 2771 return (0); 2772 2773 error: 2774 xhci_free_device_ext(udev); 2775 2776 return (USB_ERR_NOMEM); 2777 } 2778 2779 static void 2780 xhci_free_device_ext(struct usb_device *udev) 2781 { 2782 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2783 uint8_t index; 2784 uint8_t i; 2785 2786 index = udev->controller_slot_id; 2787 xhci_set_slot_pointer(sc, index, 0); 2788 2789 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2790 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2791 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2792 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2793 } 2794 2795 static struct xhci_endpoint_ext * 2796 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2797 { 2798 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2799 struct xhci_endpoint_ext *pepext; 2800 struct usb_page_cache *pc; 2801 struct usb_page_search buf_ep; 2802 uint8_t epno; 2803 uint8_t index; 2804 2805 epno = edesc->bEndpointAddress; 2806 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2807 epno |= UE_DIR_IN; 2808 2809 epno = XHCI_EPNO2EPID(epno); 2810 2811 index = udev->controller_slot_id; 2812 2813 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2814 2815 usbd_get_page(pc, 0, &buf_ep); 2816 2817 pepext = &sc->sc_hw.devs[index].endp[epno]; 2818 pepext->page_cache = pc; 2819 pepext->trb = buf_ep.buffer; 2820 pepext->physaddr = buf_ep.physaddr; 2821 2822 return (pepext); 2823 } 2824 2825 static void 2826 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2827 { 2828 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2829 uint8_t epno; 2830 uint8_t index; 2831 2832 epno = xfer->endpointno; 2833 if (xfer->flags_int.control_xfr) 2834 epno |= UE_DIR_IN; 2835 2836 epno = XHCI_EPNO2EPID(epno); 2837 index = xfer->xroot->udev->controller_slot_id; 2838 2839 if (xfer->xroot->udev->flags.self_suspended == 0) { 2840 XWRITE4(sc, door, XHCI_DOORBELL(index), 2841 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2842 } 2843 } 2844 2845 static void 2846 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2847 { 2848 struct xhci_endpoint_ext *pepext; 2849 2850 if (xfer->flags_int.bandwidth_reclaimed) { 2851 xfer->flags_int.bandwidth_reclaimed = 0; 2852 2853 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2854 xfer->endpoint->edesc); 2855 2856 pepext->trb_used[xfer->stream_id]--; 2857 2858 pepext->xfer[xfer->qh_pos] = NULL; 2859 2860 if (error && pepext->trb_running != 0) { 2861 pepext->trb_halted = 1; 2862 pepext->trb_running = 0; 2863 } 2864 } 2865 } 2866 2867 static usb_error_t 2868 xhci_transfer_insert(struct usb_xfer *xfer) 2869 { 2870 struct xhci_td *td_first; 2871 struct xhci_td *td_last; 2872 struct xhci_trb *trb_link; 2873 struct xhci_endpoint_ext *pepext; 2874 uint64_t addr; 2875 usb_stream_t id; 2876 uint8_t i; 2877 uint8_t inext; 2878 uint8_t trb_limit; 2879 2880 DPRINTFN(8, "\n"); 2881 2882 id = xfer->stream_id; 2883 2884 /* check if already inserted */ 2885 if (xfer->flags_int.bandwidth_reclaimed) { 2886 DPRINTFN(8, "Already in schedule\n"); 2887 return (0); 2888 } 2889 2890 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2891 xfer->endpoint->edesc); 2892 2893 td_first = xfer->td_transfer_first; 2894 td_last = xfer->td_transfer_last; 2895 addr = pepext->physaddr; 2896 2897 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2898 case UE_CONTROL: 2899 case UE_INTERRUPT: 2900 /* single buffered */ 2901 trb_limit = 1; 2902 break; 2903 default: 2904 /* multi buffered */ 2905 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2906 break; 2907 } 2908 2909 if (pepext->trb_used[id] >= trb_limit) { 2910 DPRINTFN(8, "Too many TDs queued.\n"); 2911 return (USB_ERR_NOMEM); 2912 } 2913 2914 /* check for stopped condition, after putting transfer on interrupt queue */ 2915 if (pepext->trb_running == 0) { 2916 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2917 2918 DPRINTFN(8, "Not running\n"); 2919 2920 /* start configuration */ 2921 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2922 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2923 return (0); 2924 } 2925 2926 pepext->trb_used[id]++; 2927 2928 /* get current TRB index */ 2929 i = pepext->trb_index[id]; 2930 2931 /* get next TRB index */ 2932 inext = (i + 1); 2933 2934 /* the last entry of the ring is a hardcoded link TRB */ 2935 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2936 inext = 0; 2937 2938 /* store next TRB index, before stream ID offset is added */ 2939 pepext->trb_index[id] = inext; 2940 2941 /* offset for stream */ 2942 i += id * XHCI_MAX_TRANSFERS; 2943 inext += id * XHCI_MAX_TRANSFERS; 2944 2945 /* compute terminating return address */ 2946 addr += (inext * sizeof(struct xhci_trb)); 2947 2948 /* compute link TRB pointer */ 2949 trb_link = td_last->td_trb + td_last->ntrb; 2950 2951 /* update next pointer of last link TRB */ 2952 trb_link->qwTrb0 = htole64(addr); 2953 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2954 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2955 XHCI_TRB_3_CYCLE_BIT | 2956 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2957 2958 #ifdef USB_DEBUG 2959 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2960 #endif 2961 usb_pc_cpu_flush(td_last->page_cache); 2962 2963 /* write ahead chain end marker */ 2964 2965 pepext->trb[inext].qwTrb0 = 0; 2966 pepext->trb[inext].dwTrb2 = 0; 2967 pepext->trb[inext].dwTrb3 = 0; 2968 2969 /* update next pointer of link TRB */ 2970 2971 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2972 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2973 2974 #ifdef USB_DEBUG 2975 xhci_dump_trb(&pepext->trb[i]); 2976 #endif 2977 usb_pc_cpu_flush(pepext->page_cache); 2978 2979 /* toggle cycle bit which activates the transfer chain */ 2980 2981 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2982 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2983 2984 usb_pc_cpu_flush(pepext->page_cache); 2985 2986 DPRINTF("qh_pos = %u\n", i); 2987 2988 pepext->xfer[i] = xfer; 2989 2990 xfer->qh_pos = i; 2991 2992 xfer->flags_int.bandwidth_reclaimed = 1; 2993 2994 xhci_endpoint_doorbell(xfer); 2995 2996 return (0); 2997 } 2998 2999 static void 3000 xhci_root_intr(struct xhci_softc *sc) 3001 { 3002 uint16_t i; 3003 3004 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 3005 3006 /* clear any old interrupt data */ 3007 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 3008 3009 for (i = 1; i <= sc->sc_noport; i++) { 3010 /* pick out CHANGE bits from the status register */ 3011 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 3012 XHCI_PS_CSC | XHCI_PS_PEC | 3013 XHCI_PS_OCC | XHCI_PS_WRC | 3014 XHCI_PS_PRC | XHCI_PS_PLC | 3015 XHCI_PS_CEC)) { 3016 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 3017 DPRINTF("port %d changed\n", i); 3018 } 3019 } 3020 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3021 sizeof(sc->sc_hub_idata)); 3022 } 3023 3024 /*------------------------------------------------------------------------* 3025 * xhci_device_done - XHCI done handler 3026 * 3027 * NOTE: This function can be called two times in a row on 3028 * the same USB transfer. From close and from interrupt. 3029 *------------------------------------------------------------------------*/ 3030 static void 3031 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3032 { 3033 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3034 xfer, xfer->endpoint, error); 3035 3036 /* remove transfer from HW queue */ 3037 xhci_transfer_remove(xfer, error); 3038 3039 /* dequeue transfer and start next transfer */ 3040 usbd_transfer_done(xfer, error); 3041 } 3042 3043 /*------------------------------------------------------------------------* 3044 * XHCI data transfer support (generic type) 3045 *------------------------------------------------------------------------*/ 3046 static void 3047 xhci_device_generic_open(struct usb_xfer *xfer) 3048 { 3049 if (xfer->flags_int.isochronous_xfr) { 3050 switch (xfer->xroot->udev->speed) { 3051 case USB_SPEED_FULL: 3052 break; 3053 default: 3054 usb_hs_bandwidth_alloc(xfer); 3055 break; 3056 } 3057 } 3058 } 3059 3060 static void 3061 xhci_device_generic_close(struct usb_xfer *xfer) 3062 { 3063 DPRINTF("\n"); 3064 3065 xhci_device_done(xfer, USB_ERR_CANCELLED); 3066 3067 if (xfer->flags_int.isochronous_xfr) { 3068 switch (xfer->xroot->udev->speed) { 3069 case USB_SPEED_FULL: 3070 break; 3071 default: 3072 usb_hs_bandwidth_free(xfer); 3073 break; 3074 } 3075 } 3076 } 3077 3078 static void 3079 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3080 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3081 { 3082 struct usb_xfer *xfer; 3083 3084 /* check if there is a current transfer */ 3085 xfer = ep->endpoint_q[stream_id].curr; 3086 if (xfer == NULL) 3087 return; 3088 3089 /* 3090 * Check if the current transfer is started and then pickup 3091 * the next one, if any. Else wait for next start event due to 3092 * block on failure feature. 3093 */ 3094 if (!xfer->flags_int.bandwidth_reclaimed) 3095 return; 3096 3097 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3098 if (xfer == NULL) { 3099 /* 3100 * In case of enter we have to consider that the 3101 * transfer is queued by the USB core after the enter 3102 * method is called. 3103 */ 3104 xfer = enter_xfer; 3105 3106 if (xfer == NULL) 3107 return; 3108 } 3109 3110 /* try to multi buffer */ 3111 xhci_transfer_insert(xfer); 3112 } 3113 3114 static void 3115 xhci_device_generic_enter(struct usb_xfer *xfer) 3116 { 3117 DPRINTF("\n"); 3118 3119 /* set up TD's and QH */ 3120 xhci_setup_generic_chain(xfer); 3121 3122 xhci_device_generic_multi_enter(xfer->endpoint, 3123 xfer->stream_id, xfer); 3124 } 3125 3126 static void 3127 xhci_device_generic_start(struct usb_xfer *xfer) 3128 { 3129 DPRINTF("\n"); 3130 3131 /* try to insert xfer on HW queue */ 3132 xhci_transfer_insert(xfer); 3133 3134 /* try to multi buffer */ 3135 xhci_device_generic_multi_enter(xfer->endpoint, 3136 xfer->stream_id, NULL); 3137 3138 /* add transfer last on interrupt queue */ 3139 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3140 3141 /* start timeout, if any */ 3142 if (xfer->timeout != 0) 3143 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3144 } 3145 3146 static const struct usb_pipe_methods xhci_device_generic_methods = 3147 { 3148 .open = xhci_device_generic_open, 3149 .close = xhci_device_generic_close, 3150 .enter = xhci_device_generic_enter, 3151 .start = xhci_device_generic_start, 3152 }; 3153 3154 /*------------------------------------------------------------------------* 3155 * xhci root HUB support 3156 *------------------------------------------------------------------------* 3157 * Simulate a hardware HUB by handling all the necessary requests. 3158 *------------------------------------------------------------------------*/ 3159 3160 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3161 3162 static const 3163 struct usb_device_descriptor xhci_devd = 3164 { 3165 .bLength = sizeof(xhci_devd), 3166 .bDescriptorType = UDESC_DEVICE, /* type */ 3167 HSETW(.bcdUSB, 0x0300), /* USB version */ 3168 .bDeviceClass = UDCLASS_HUB, /* class */ 3169 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3170 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3171 .bMaxPacketSize = 9, /* max packet size */ 3172 HSETW(.idVendor, 0x0000), /* vendor */ 3173 HSETW(.idProduct, 0x0000), /* product */ 3174 HSETW(.bcdDevice, 0x0100), /* device version */ 3175 .iManufacturer = 1, 3176 .iProduct = 2, 3177 .iSerialNumber = 0, 3178 .bNumConfigurations = 1, /* # of configurations */ 3179 }; 3180 3181 static const 3182 struct xhci_bos_desc xhci_bosd = { 3183 .bosd = { 3184 .bLength = sizeof(xhci_bosd.bosd), 3185 .bDescriptorType = UDESC_BOS, 3186 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3187 .bNumDeviceCaps = 3, 3188 }, 3189 .usb2extd = { 3190 .bLength = sizeof(xhci_bosd.usb2extd), 3191 .bDescriptorType = 1, 3192 .bDevCapabilityType = 2, 3193 .bmAttributes[0] = 2, 3194 }, 3195 .usbdcd = { 3196 .bLength = sizeof(xhci_bosd.usbdcd), 3197 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3198 .bDevCapabilityType = 3, 3199 .bmAttributes = 0, /* XXX */ 3200 HSETW(.wSpeedsSupported, 0x000C), 3201 .bFunctionalitySupport = 8, 3202 .bU1DevExitLat = 255, /* dummy - not used */ 3203 .wU2DevExitLat = { 0x00, 0x08 }, 3204 }, 3205 .cidd = { 3206 .bLength = sizeof(xhci_bosd.cidd), 3207 .bDescriptorType = 1, 3208 .bDevCapabilityType = 4, 3209 .bReserved = 0, 3210 .bContainerID = 0, /* XXX */ 3211 }, 3212 }; 3213 3214 static const 3215 struct xhci_config_desc xhci_confd = { 3216 .confd = { 3217 .bLength = sizeof(xhci_confd.confd), 3218 .bDescriptorType = UDESC_CONFIG, 3219 .wTotalLength[0] = sizeof(xhci_confd), 3220 .bNumInterface = 1, 3221 .bConfigurationValue = 1, 3222 .iConfiguration = 0, 3223 .bmAttributes = UC_SELF_POWERED, 3224 .bMaxPower = 0 /* max power */ 3225 }, 3226 .ifcd = { 3227 .bLength = sizeof(xhci_confd.ifcd), 3228 .bDescriptorType = UDESC_INTERFACE, 3229 .bNumEndpoints = 1, 3230 .bInterfaceClass = UICLASS_HUB, 3231 .bInterfaceSubClass = UISUBCLASS_HUB, 3232 .bInterfaceProtocol = 0, 3233 }, 3234 .endpd = { 3235 .bLength = sizeof(xhci_confd.endpd), 3236 .bDescriptorType = UDESC_ENDPOINT, 3237 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3238 .bmAttributes = UE_INTERRUPT, 3239 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3240 .bInterval = 255, 3241 }, 3242 .endpcd = { 3243 .bLength = sizeof(xhci_confd.endpcd), 3244 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3245 .bMaxBurst = 0, 3246 .bmAttributes = 0, 3247 }, 3248 }; 3249 3250 static const 3251 struct usb_hub_ss_descriptor xhci_hubd = { 3252 .bLength = sizeof(xhci_hubd), 3253 .bDescriptorType = UDESC_SS_HUB, 3254 }; 3255 3256 static usb_error_t 3257 xhci_roothub_exec(struct usb_device *udev, 3258 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3259 { 3260 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3261 const char *str_ptr; 3262 const void *ptr; 3263 uint32_t port; 3264 uint32_t v; 3265 uint16_t len; 3266 uint16_t i; 3267 uint16_t value; 3268 uint16_t index; 3269 uint8_t j; 3270 usb_error_t err; 3271 3272 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 3273 3274 /* buffer reset */ 3275 ptr = (const void *)&sc->sc_hub_desc; 3276 len = 0; 3277 err = 0; 3278 3279 value = UGETW(req->wValue); 3280 index = UGETW(req->wIndex); 3281 3282 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3283 "wValue=0x%04x wIndex=0x%04x\n", 3284 req->bmRequestType, req->bRequest, 3285 UGETW(req->wLength), value, index); 3286 3287 #define C(x,y) ((x) | ((y) << 8)) 3288 switch (C(req->bRequest, req->bmRequestType)) { 3289 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3290 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3291 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3292 /* 3293 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3294 * for the integrated root hub. 3295 */ 3296 break; 3297 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3298 len = 1; 3299 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3300 break; 3301 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3302 switch (value >> 8) { 3303 case UDESC_DEVICE: 3304 if ((value & 0xff) != 0) { 3305 err = USB_ERR_IOERROR; 3306 goto done; 3307 } 3308 len = sizeof(xhci_devd); 3309 ptr = (const void *)&xhci_devd; 3310 break; 3311 3312 case UDESC_BOS: 3313 if ((value & 0xff) != 0) { 3314 err = USB_ERR_IOERROR; 3315 goto done; 3316 } 3317 len = sizeof(xhci_bosd); 3318 ptr = (const void *)&xhci_bosd; 3319 break; 3320 3321 case UDESC_CONFIG: 3322 if ((value & 0xff) != 0) { 3323 err = USB_ERR_IOERROR; 3324 goto done; 3325 } 3326 len = sizeof(xhci_confd); 3327 ptr = (const void *)&xhci_confd; 3328 break; 3329 3330 case UDESC_STRING: 3331 switch (value & 0xff) { 3332 case 0: /* Language table */ 3333 str_ptr = "\001"; 3334 break; 3335 3336 case 1: /* Vendor */ 3337 str_ptr = sc->sc_vendor; 3338 break; 3339 3340 case 2: /* Product */ 3341 str_ptr = "XHCI root HUB"; 3342 break; 3343 3344 default: 3345 str_ptr = ""; 3346 break; 3347 } 3348 3349 len = usb_make_str_desc( 3350 sc->sc_hub_desc.temp, 3351 sizeof(sc->sc_hub_desc.temp), 3352 str_ptr); 3353 break; 3354 3355 default: 3356 err = USB_ERR_IOERROR; 3357 goto done; 3358 } 3359 break; 3360 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3361 len = 1; 3362 sc->sc_hub_desc.temp[0] = 0; 3363 break; 3364 case C(UR_GET_STATUS, UT_READ_DEVICE): 3365 len = 2; 3366 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3367 break; 3368 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3369 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3370 len = 2; 3371 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3372 break; 3373 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3374 if (value >= XHCI_MAX_DEVICES) { 3375 err = USB_ERR_IOERROR; 3376 goto done; 3377 } 3378 break; 3379 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3380 if (value != 0 && value != 1) { 3381 err = USB_ERR_IOERROR; 3382 goto done; 3383 } 3384 sc->sc_conf = value; 3385 break; 3386 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3387 break; 3388 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3389 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3390 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3391 err = USB_ERR_IOERROR; 3392 goto done; 3393 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3394 break; 3395 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3396 break; 3397 /* Hub requests */ 3398 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3399 break; 3400 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3401 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3402 3403 if ((index < 1) || 3404 (index > sc->sc_noport)) { 3405 err = USB_ERR_IOERROR; 3406 goto done; 3407 } 3408 port = XHCI_PORTSC(index); 3409 3410 v = XREAD4(sc, oper, port); 3411 i = XHCI_PS_PLS_GET(v); 3412 v &= ~XHCI_PS_CLEAR; 3413 3414 switch (value) { 3415 case UHF_C_BH_PORT_RESET: 3416 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3417 break; 3418 case UHF_C_PORT_CONFIG_ERROR: 3419 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3420 break; 3421 case UHF_C_PORT_SUSPEND: 3422 case UHF_C_PORT_LINK_STATE: 3423 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3424 break; 3425 case UHF_C_PORT_CONNECTION: 3426 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3427 break; 3428 case UHF_C_PORT_ENABLE: 3429 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3430 break; 3431 case UHF_C_PORT_OVER_CURRENT: 3432 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3433 break; 3434 case UHF_C_PORT_RESET: 3435 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3436 break; 3437 case UHF_PORT_ENABLE: 3438 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3439 break; 3440 case UHF_PORT_POWER: 3441 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3442 break; 3443 case UHF_PORT_INDICATOR: 3444 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3445 break; 3446 case UHF_PORT_SUSPEND: 3447 3448 /* U3 -> U15 */ 3449 if (i == 3) { 3450 XWRITE4(sc, oper, port, v | 3451 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3452 } 3453 3454 /* wait 20ms for resume sequence to complete */ 3455 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 50); 3456 3457 /* U0 */ 3458 XWRITE4(sc, oper, port, v | 3459 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3460 break; 3461 default: 3462 err = USB_ERR_IOERROR; 3463 goto done; 3464 } 3465 break; 3466 3467 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3468 if ((value & 0xff) != 0) { 3469 err = USB_ERR_IOERROR; 3470 goto done; 3471 } 3472 3473 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3474 3475 sc->sc_hub_desc.hubd = xhci_hubd; 3476 3477 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3478 3479 if (XHCI_HCS0_PPC(v)) 3480 i = UHD_PWR_INDIVIDUAL; 3481 else 3482 i = UHD_PWR_GANGED; 3483 3484 if (XHCI_HCS0_PIND(v)) 3485 i |= UHD_PORT_IND; 3486 3487 i |= UHD_OC_INDIVIDUAL; 3488 3489 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3490 3491 /* see XHCI section 5.4.9: */ 3492 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3493 3494 for (j = 1; j <= sc->sc_noport; j++) { 3495 3496 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3497 if (v & XHCI_PS_DR) { 3498 sc->sc_hub_desc.hubd. 3499 DeviceRemovable[j / 8] |= 1U << (j % 8); 3500 } 3501 } 3502 len = sc->sc_hub_desc.hubd.bLength; 3503 break; 3504 3505 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3506 len = 16; 3507 memset(sc->sc_hub_desc.temp, 0, 16); 3508 break; 3509 3510 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3511 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3512 3513 if ((index < 1) || 3514 (index > sc->sc_noport)) { 3515 err = USB_ERR_IOERROR; 3516 goto done; 3517 } 3518 3519 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3520 3521 DPRINTFN(9, "port status=0x%08x\n", v); 3522 3523 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3524 3525 switch (XHCI_PS_SPEED_GET(v)) { 3526 case 3: 3527 i |= UPS_HIGH_SPEED; 3528 break; 3529 case 2: 3530 i |= UPS_LOW_SPEED; 3531 break; 3532 case 1: 3533 /* FULL speed */ 3534 break; 3535 default: 3536 i |= UPS_OTHER_SPEED; 3537 break; 3538 } 3539 3540 if (v & XHCI_PS_CCS) 3541 i |= UPS_CURRENT_CONNECT_STATUS; 3542 if (v & XHCI_PS_PED) 3543 i |= UPS_PORT_ENABLED; 3544 if (v & XHCI_PS_OCA) 3545 i |= UPS_OVERCURRENT_INDICATOR; 3546 if (v & XHCI_PS_PR) 3547 i |= UPS_RESET; 3548 if (v & XHCI_PS_PP) { 3549 /* 3550 * The USB 3.0 RH is using the 3551 * USB 2.0's power bit 3552 */ 3553 i |= UPS_PORT_POWER; 3554 } 3555 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3556 3557 i = 0; 3558 if (v & XHCI_PS_CSC) 3559 i |= UPS_C_CONNECT_STATUS; 3560 if (v & XHCI_PS_PEC) 3561 i |= UPS_C_PORT_ENABLED; 3562 if (v & XHCI_PS_OCC) 3563 i |= UPS_C_OVERCURRENT_INDICATOR; 3564 if (v & XHCI_PS_WRC) 3565 i |= UPS_C_BH_PORT_RESET; 3566 if (v & XHCI_PS_PRC) 3567 i |= UPS_C_PORT_RESET; 3568 if (v & XHCI_PS_PLC) 3569 i |= UPS_C_PORT_LINK_STATE; 3570 if (v & XHCI_PS_CEC) 3571 i |= UPS_C_PORT_CONFIG_ERROR; 3572 3573 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3574 len = sizeof(sc->sc_hub_desc.ps); 3575 break; 3576 3577 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3578 err = USB_ERR_IOERROR; 3579 goto done; 3580 3581 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3582 break; 3583 3584 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3585 3586 i = index >> 8; 3587 index &= 0x00FF; 3588 3589 if ((index < 1) || 3590 (index > sc->sc_noport)) { 3591 err = USB_ERR_IOERROR; 3592 goto done; 3593 } 3594 3595 port = XHCI_PORTSC(index); 3596 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3597 3598 switch (value) { 3599 case UHF_PORT_U1_TIMEOUT: 3600 if (XHCI_PS_SPEED_GET(v) != 4) { 3601 err = USB_ERR_IOERROR; 3602 goto done; 3603 } 3604 port = XHCI_PORTPMSC(index); 3605 v = XREAD4(sc, oper, port); 3606 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3607 v |= XHCI_PM3_U1TO_SET(i); 3608 XWRITE4(sc, oper, port, v); 3609 break; 3610 case UHF_PORT_U2_TIMEOUT: 3611 if (XHCI_PS_SPEED_GET(v) != 4) { 3612 err = USB_ERR_IOERROR; 3613 goto done; 3614 } 3615 port = XHCI_PORTPMSC(index); 3616 v = XREAD4(sc, oper, port); 3617 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3618 v |= XHCI_PM3_U2TO_SET(i); 3619 XWRITE4(sc, oper, port, v); 3620 break; 3621 case UHF_BH_PORT_RESET: 3622 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3623 break; 3624 case UHF_PORT_LINK_STATE: 3625 XWRITE4(sc, oper, port, v | 3626 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3627 /* 4ms settle time */ 3628 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 250); 3629 break; 3630 case UHF_PORT_ENABLE: 3631 DPRINTFN(3, "set port enable %d\n", index); 3632 break; 3633 case UHF_PORT_SUSPEND: 3634 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3635 j = XHCI_PS_SPEED_GET(v); 3636 if ((j < 1) || (j > 3)) { 3637 /* non-supported speed */ 3638 err = USB_ERR_IOERROR; 3639 goto done; 3640 } 3641 XWRITE4(sc, oper, port, v | 3642 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3643 break; 3644 case UHF_PORT_RESET: 3645 DPRINTFN(6, "reset port %d\n", index); 3646 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3647 break; 3648 case UHF_PORT_POWER: 3649 DPRINTFN(3, "set port power %d\n", index); 3650 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3651 break; 3652 case UHF_PORT_TEST: 3653 DPRINTFN(3, "set port test %d\n", index); 3654 break; 3655 case UHF_PORT_INDICATOR: 3656 DPRINTFN(3, "set port indicator %d\n", index); 3657 3658 v &= ~XHCI_PS_PIC_SET(3); 3659 v |= XHCI_PS_PIC_SET(1); 3660 3661 XWRITE4(sc, oper, port, v); 3662 break; 3663 default: 3664 err = USB_ERR_IOERROR; 3665 goto done; 3666 } 3667 break; 3668 3669 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3670 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3671 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3672 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3673 break; 3674 default: 3675 err = USB_ERR_IOERROR; 3676 goto done; 3677 } 3678 done: 3679 *plength = len; 3680 *pptr = ptr; 3681 return (err); 3682 } 3683 3684 static void 3685 xhci_xfer_setup(struct usb_setup_params *parm) 3686 { 3687 struct usb_page_search page_info; 3688 struct usb_page_cache *pc; 3689 struct xhci_softc *sc; 3690 struct usb_xfer *xfer; 3691 void *last_obj; 3692 uint32_t ntd; 3693 uint32_t n; 3694 3695 sc = XHCI_BUS2SC(parm->udev->bus); 3696 xfer = parm->curr_xfer; 3697 3698 /* 3699 * The proof for the "ntd" formula is illustrated like this: 3700 * 3701 * +------------------------------------+ 3702 * | | 3703 * | |remainder -> | 3704 * | +-----+---+ | 3705 * | | xxx | x | frm 0 | 3706 * | +-----+---++ | 3707 * | | xxx | xx | frm 1 | 3708 * | +-----+----+ | 3709 * | ... | 3710 * +------------------------------------+ 3711 * 3712 * "xxx" means a completely full USB transfer descriptor 3713 * 3714 * "x" and "xx" means a short USB packet 3715 * 3716 * For the remainder of an USB transfer modulo 3717 * "max_data_length" we need two USB transfer descriptors. 3718 * One to transfer the remaining data and one to finalise with 3719 * a zero length packet in case the "force_short_xfer" flag is 3720 * set. We only need two USB transfer descriptors in the case 3721 * where the transfer length of the first one is a factor of 3722 * "max_frame_size". The rest of the needed USB transfer 3723 * descriptors is given by the buffer size divided by the 3724 * maximum data payload. 3725 */ 3726 parm->hc_max_packet_size = 0x400; 3727 parm->hc_max_packet_count = 16 * 3; 3728 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3729 3730 xfer->flags_int.bdma_enable = 1; 3731 3732 usbd_transfer_setup_sub(parm); 3733 3734 if (xfer->flags_int.isochronous_xfr) { 3735 ntd = ((1 * xfer->nframes) 3736 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3737 } else if (xfer->flags_int.control_xfr) { 3738 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3739 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3740 } else { 3741 ntd = ((2 * xfer->nframes) 3742 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3743 } 3744 3745 alloc_dma_set: 3746 3747 if (parm->err) 3748 return; 3749 3750 /* 3751 * Allocate queue heads and transfer descriptors 3752 */ 3753 last_obj = NULL; 3754 3755 if (usbd_transfer_setup_sub_malloc( 3756 parm, &pc, sizeof(struct xhci_td), 3757 XHCI_TD_ALIGN, ntd)) { 3758 parm->err = USB_ERR_NOMEM; 3759 return; 3760 } 3761 if (parm->buf) { 3762 for (n = 0; n != ntd; n++) { 3763 struct xhci_td *td; 3764 3765 usbd_get_page(pc + n, 0, &page_info); 3766 3767 td = page_info.buffer; 3768 3769 /* init TD */ 3770 td->td_self = page_info.physaddr; 3771 td->obj_next = last_obj; 3772 td->page_cache = pc + n; 3773 3774 last_obj = td; 3775 3776 usb_pc_cpu_flush(pc + n); 3777 } 3778 } 3779 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3780 3781 if (!xfer->flags_int.curr_dma_set) { 3782 xfer->flags_int.curr_dma_set = 1; 3783 goto alloc_dma_set; 3784 } 3785 } 3786 3787 static usb_error_t 3788 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3789 { 3790 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3791 struct usb_page_search buf_inp; 3792 struct usb_device *udev; 3793 struct xhci_endpoint_ext *pepext; 3794 struct usb_endpoint_descriptor *edesc; 3795 struct usb_page_cache *pcinp; 3796 usb_error_t err; 3797 usb_stream_t stream_id; 3798 uint8_t index; 3799 uint8_t epno; 3800 3801 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3802 xfer->endpoint->edesc); 3803 3804 udev = xfer->xroot->udev; 3805 index = udev->controller_slot_id; 3806 3807 pcinp = &sc->sc_hw.devs[index].input_pc; 3808 3809 usbd_get_page(pcinp, 0, &buf_inp); 3810 3811 edesc = xfer->endpoint->edesc; 3812 3813 epno = edesc->bEndpointAddress; 3814 stream_id = xfer->stream_id; 3815 3816 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3817 epno |= UE_DIR_IN; 3818 3819 epno = XHCI_EPNO2EPID(epno); 3820 3821 if (epno == 0) 3822 return (USB_ERR_NO_PIPE); /* invalid */ 3823 3824 XHCI_CMD_LOCK(sc); 3825 3826 /* configure endpoint */ 3827 3828 err = xhci_configure_endpoint_by_xfer(xfer); 3829 3830 if (err != 0) { 3831 XHCI_CMD_UNLOCK(sc); 3832 return (err); 3833 } 3834 3835 /* 3836 * Get the endpoint into the stopped state according to the 3837 * endpoint context state diagram in the XHCI specification: 3838 */ 3839 3840 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3841 3842 if (err != 0) 3843 DPRINTF("Could not stop endpoint %u\n", epno); 3844 3845 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3846 3847 if (err != 0) 3848 DPRINTF("Could not reset endpoint %u\n", epno); 3849 3850 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3851 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3852 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3853 stream_id, epno, index); 3854 3855 if (err != 0) 3856 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3857 3858 /* 3859 * Get the endpoint into the running state according to the 3860 * endpoint context state diagram in the XHCI specification: 3861 */ 3862 3863 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3864 3865 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3866 3867 if (err != 0) 3868 DPRINTF("Could not configure endpoint %u\n", epno); 3869 3870 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3871 3872 if (err != 0) 3873 DPRINTF("Could not configure endpoint %u\n", epno); 3874 3875 XHCI_CMD_UNLOCK(sc); 3876 3877 return (0); 3878 } 3879 3880 static void 3881 xhci_xfer_unsetup(struct usb_xfer *xfer) 3882 { 3883 return; 3884 } 3885 3886 static void 3887 xhci_start_dma_delay(struct usb_xfer *xfer) 3888 { 3889 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3890 3891 /* put transfer on interrupt queue (again) */ 3892 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3893 3894 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3895 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3896 } 3897 3898 static void 3899 xhci_configure_msg(struct usb_proc_msg *pm) 3900 { 3901 struct xhci_softc *sc; 3902 struct xhci_endpoint_ext *pepext; 3903 struct usb_xfer *xfer; 3904 3905 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3906 3907 restart: 3908 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3909 3910 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3911 xfer->endpoint->edesc); 3912 3913 if ((pepext->trb_halted != 0) || 3914 (pepext->trb_running == 0)) { 3915 3916 uint16_t i; 3917 3918 /* clear halted and running */ 3919 pepext->trb_halted = 0; 3920 pepext->trb_running = 0; 3921 3922 /* nuke remaining buffered transfers */ 3923 3924 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3925 XHCI_MAX_STREAMS); i++) { 3926 /* 3927 * NOTE: We need to use the timeout 3928 * error code here else existing 3929 * isochronous clients can get 3930 * confused: 3931 */ 3932 if (pepext->xfer[i] != NULL) { 3933 xhci_device_done(pepext->xfer[i], 3934 USB_ERR_TIMEOUT); 3935 } 3936 } 3937 3938 /* 3939 * NOTE: The USB transfer cannot vanish in 3940 * this state! 3941 */ 3942 3943 USB_BUS_UNLOCK(&sc->sc_bus); 3944 3945 xhci_configure_reset_endpoint(xfer); 3946 3947 USB_BUS_LOCK(&sc->sc_bus); 3948 3949 /* check if halted is still cleared */ 3950 if (pepext->trb_halted == 0) { 3951 pepext->trb_running = 1; 3952 memset(pepext->trb_index, 0, 3953 sizeof(pepext->trb_index)); 3954 } 3955 goto restart; 3956 } 3957 3958 if (xfer->flags_int.did_dma_delay) { 3959 3960 /* remove transfer from interrupt queue (again) */ 3961 usbd_transfer_dequeue(xfer); 3962 3963 /* we are finally done */ 3964 usb_dma_delay_done_cb(xfer); 3965 3966 /* queue changed - restart */ 3967 goto restart; 3968 } 3969 } 3970 3971 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3972 3973 /* try to insert xfer on HW queue */ 3974 xhci_transfer_insert(xfer); 3975 3976 /* try to multi buffer */ 3977 xhci_device_generic_multi_enter(xfer->endpoint, 3978 xfer->stream_id, NULL); 3979 } 3980 } 3981 3982 static void 3983 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3984 struct usb_endpoint *ep) 3985 { 3986 struct xhci_endpoint_ext *pepext; 3987 3988 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3989 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3990 3991 if (udev->parent_hub == NULL) { 3992 /* root HUB has special endpoint handling */ 3993 return; 3994 } 3995 3996 ep->methods = &xhci_device_generic_methods; 3997 3998 pepext = xhci_get_endpoint_ext(udev, edesc); 3999 4000 USB_BUS_LOCK(udev->bus); 4001 pepext->trb_halted = 1; 4002 pepext->trb_running = 0; 4003 USB_BUS_UNLOCK(udev->bus); 4004 } 4005 4006 static void 4007 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 4008 { 4009 4010 } 4011 4012 static void 4013 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 4014 { 4015 struct xhci_endpoint_ext *pepext; 4016 4017 DPRINTF("\n"); 4018 4019 if (udev->flags.usb_mode != USB_MODE_HOST) { 4020 /* not supported */ 4021 return; 4022 } 4023 if (udev->parent_hub == NULL) { 4024 /* root HUB has special endpoint handling */ 4025 return; 4026 } 4027 4028 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4029 4030 USB_BUS_LOCK(udev->bus); 4031 pepext->trb_halted = 1; 4032 pepext->trb_running = 0; 4033 USB_BUS_UNLOCK(udev->bus); 4034 } 4035 4036 static usb_error_t 4037 xhci_device_init(struct usb_device *udev) 4038 { 4039 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4040 usb_error_t err; 4041 uint8_t temp; 4042 4043 /* no init for root HUB */ 4044 if (udev->parent_hub == NULL) 4045 return (0); 4046 4047 XHCI_CMD_LOCK(sc); 4048 4049 /* set invalid default */ 4050 4051 udev->controller_slot_id = sc->sc_noslot + 1; 4052 4053 /* try to get a new slot ID from the XHCI */ 4054 4055 err = xhci_cmd_enable_slot(sc, &temp); 4056 4057 if (err) { 4058 XHCI_CMD_UNLOCK(sc); 4059 return (err); 4060 } 4061 4062 if (temp > sc->sc_noslot) { 4063 XHCI_CMD_UNLOCK(sc); 4064 return (USB_ERR_BAD_ADDRESS); 4065 } 4066 4067 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4068 DPRINTF("slot %u already allocated.\n", temp); 4069 XHCI_CMD_UNLOCK(sc); 4070 return (USB_ERR_BAD_ADDRESS); 4071 } 4072 4073 /* store slot ID for later reference */ 4074 4075 udev->controller_slot_id = temp; 4076 4077 /* reset data structure */ 4078 4079 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4080 4081 /* set mark slot allocated */ 4082 4083 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4084 4085 err = xhci_alloc_device_ext(udev); 4086 4087 XHCI_CMD_UNLOCK(sc); 4088 4089 /* get device into default state */ 4090 4091 if (err == 0) 4092 err = xhci_set_address(udev, NULL, 0); 4093 4094 return (err); 4095 } 4096 4097 static void 4098 xhci_device_uninit(struct usb_device *udev) 4099 { 4100 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4101 uint8_t index; 4102 4103 /* no init for root HUB */ 4104 if (udev->parent_hub == NULL) 4105 return; 4106 4107 XHCI_CMD_LOCK(sc); 4108 4109 index = udev->controller_slot_id; 4110 4111 if (index <= sc->sc_noslot) { 4112 xhci_cmd_disable_slot(sc, index); 4113 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4114 4115 /* free device extension */ 4116 xhci_free_device_ext(udev); 4117 } 4118 4119 XHCI_CMD_UNLOCK(sc); 4120 } 4121 4122 static void 4123 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4124 { 4125 /* 4126 * Wait until the hardware has finished any possible use of 4127 * the transfer descriptor(s) 4128 */ 4129 *pus = 2048; /* microseconds */ 4130 } 4131 4132 static void 4133 xhci_device_resume(struct usb_device *udev) 4134 { 4135 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4136 uint8_t index; 4137 uint8_t n; 4138 uint8_t p; 4139 4140 DPRINTF("\n"); 4141 4142 /* check for root HUB */ 4143 if (udev->parent_hub == NULL) 4144 return; 4145 4146 index = udev->controller_slot_id; 4147 4148 XHCI_CMD_LOCK(sc); 4149 4150 /* blindly resume all endpoints */ 4151 4152 USB_BUS_LOCK(udev->bus); 4153 4154 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4155 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4156 XWRITE4(sc, door, XHCI_DOORBELL(index), 4157 n | XHCI_DB_SID_SET(p)); 4158 } 4159 } 4160 4161 USB_BUS_UNLOCK(udev->bus); 4162 4163 XHCI_CMD_UNLOCK(sc); 4164 } 4165 4166 static void 4167 xhci_device_suspend(struct usb_device *udev) 4168 { 4169 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4170 uint8_t index; 4171 uint8_t n; 4172 usb_error_t err; 4173 4174 DPRINTF("\n"); 4175 4176 /* check for root HUB */ 4177 if (udev->parent_hub == NULL) 4178 return; 4179 4180 index = udev->controller_slot_id; 4181 4182 XHCI_CMD_LOCK(sc); 4183 4184 /* blindly suspend all endpoints */ 4185 4186 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4187 err = xhci_cmd_stop_ep(sc, 1, n, index); 4188 if (err != 0) { 4189 DPRINTF("Failed to suspend endpoint " 4190 "%u on slot %u (ignored).\n", n, index); 4191 } 4192 } 4193 4194 XHCI_CMD_UNLOCK(sc); 4195 } 4196 4197 static void 4198 xhci_set_hw_power(struct usb_bus *bus) 4199 { 4200 DPRINTF("\n"); 4201 } 4202 4203 static void 4204 xhci_device_state_change(struct usb_device *udev) 4205 { 4206 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4207 struct usb_page_search buf_inp; 4208 usb_error_t err; 4209 uint8_t index; 4210 4211 /* check for root HUB */ 4212 if (udev->parent_hub == NULL) 4213 return; 4214 4215 index = udev->controller_slot_id; 4216 4217 DPRINTF("\n"); 4218 4219 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4220 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4221 &sc->sc_hw.devs[index].tt); 4222 if (err != 0) 4223 sc->sc_hw.devs[index].nports = 0; 4224 } 4225 4226 XHCI_CMD_LOCK(sc); 4227 4228 switch (usb_get_device_state(udev)) { 4229 case USB_STATE_POWERED: 4230 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4231 break; 4232 4233 /* set default state */ 4234 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4235 4236 /* reset number of contexts */ 4237 sc->sc_hw.devs[index].context_num = 0; 4238 4239 err = xhci_cmd_reset_dev(sc, index); 4240 4241 if (err != 0) { 4242 DPRINTF("Device reset failed " 4243 "for slot %u.\n", index); 4244 } 4245 break; 4246 4247 case USB_STATE_ADDRESSED: 4248 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4249 break; 4250 4251 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4252 4253 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4254 4255 if (err) { 4256 DPRINTF("Failed to deconfigure " 4257 "slot %u.\n", index); 4258 } 4259 break; 4260 4261 case USB_STATE_CONFIGURED: 4262 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4263 break; 4264 4265 /* set configured state */ 4266 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4267 4268 /* reset number of contexts */ 4269 sc->sc_hw.devs[index].context_num = 0; 4270 4271 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4272 4273 xhci_configure_mask(udev, 3, 0); 4274 4275 err = xhci_configure_device(udev); 4276 if (err != 0) { 4277 DPRINTF("Could not configure device " 4278 "at slot %u.\n", index); 4279 } 4280 4281 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4282 if (err != 0) { 4283 DPRINTF("Could not evaluate device " 4284 "context at slot %u.\n", index); 4285 } 4286 break; 4287 4288 default: 4289 break; 4290 } 4291 XHCI_CMD_UNLOCK(sc); 4292 } 4293 4294 static usb_error_t 4295 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4296 uint8_t ep_mode) 4297 { 4298 switch (ep_mode) { 4299 case USB_EP_MODE_DEFAULT: 4300 return (0); 4301 case USB_EP_MODE_STREAMS: 4302 if (xhcistreams == 0 || 4303 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4304 udev->speed != USB_SPEED_SUPER) 4305 return (USB_ERR_INVAL); 4306 return (0); 4307 default: 4308 return (USB_ERR_INVAL); 4309 } 4310 } 4311 4312 static const struct usb_bus_methods xhci_bus_methods = { 4313 .endpoint_init = xhci_ep_init, 4314 .endpoint_uninit = xhci_ep_uninit, 4315 .xfer_setup = xhci_xfer_setup, 4316 .xfer_unsetup = xhci_xfer_unsetup, 4317 .get_dma_delay = xhci_get_dma_delay, 4318 .device_init = xhci_device_init, 4319 .device_uninit = xhci_device_uninit, 4320 .device_resume = xhci_device_resume, 4321 .device_suspend = xhci_device_suspend, 4322 .set_hw_power = xhci_set_hw_power, 4323 .roothub_exec = xhci_roothub_exec, 4324 .xfer_poll = xhci_do_poll, 4325 .start_dma_delay = xhci_start_dma_delay, 4326 .set_address = xhci_set_address, 4327 .clear_stall = xhci_ep_clear_stall, 4328 .device_state_change = xhci_device_state_change, 4329 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4330 .set_endpoint_mode = xhci_set_endpoint_mode, 4331 }; 4332