1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 28 * 29 * The XHCI 1.0 spec can be found at 30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 31 * and the USB 3.0 spec at 32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 33 */ 34 35 /* 36 * A few words about the design implementation: This driver emulates 37 * the concept about TDs which is found in EHCI specification. This 38 * way we achieve that the USB controller drivers look similar to 39 * eachother which makes it easier to understand the code. 40 */ 41 42 #include <sys/stdint.h> 43 #include <sys/param.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/module.h> 50 #include <sys/lock.h> 51 #include <sys/condvar.h> 52 #include <sys/sysctl.h> 53 #include <sys/unistd.h> 54 #include <sys/callout.h> 55 #include <sys/malloc.h> 56 #include <sys/priv.h> 57 58 #include <bus/u4b/usb.h> 59 #include <bus/u4b/usbdi.h> 60 61 #define USB_DEBUG_VAR xhcidebug 62 63 #include <bus/u4b/usb_core.h> 64 #include <bus/u4b/usb_debug.h> 65 #include <bus/u4b/usb_busdma.h> 66 #include <bus/u4b/usb_process.h> 67 #include <bus/u4b/usb_transfer.h> 68 #include <bus/u4b/usb_device.h> 69 #include <bus/u4b/usb_hub.h> 70 #include <bus/u4b/usb_util.h> 71 72 #include <bus/u4b/usb_controller.h> 73 #include <bus/u4b/usb_bus.h> 74 #include <bus/u4b/controller/xhci.h> 75 #include <bus/u4b/controller/xhcireg.h> 76 77 #define XHCI_BUS2SC(bus) \ 78 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 79 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 80 81 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 82 83 static int xhcistreams; 84 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW, 85 &xhcistreams, 0, "Set to enable streams mode support"); 86 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams); 87 88 89 #ifdef USB_DEBUG 90 static int xhcidebug = 0; 91 static int xhciroute = 0; 92 static int xhcipolling = 0; 93 94 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW, 96 &xhcidebug, 0, "Debug level"); 97 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 98 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW, 99 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 100 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 101 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW, 102 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 103 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling); 104 #else 105 #define xhciroute 0 106 #endif 107 108 #define XHCI_INTR_ENDPT 1 109 110 struct xhci_std_temp { 111 struct xhci_softc *sc; 112 struct usb_page_cache *pc; 113 struct xhci_td *td; 114 struct xhci_td *td_next; 115 uint32_t len; 116 uint32_t offset; 117 uint32_t max_packet_size; 118 uint32_t average; 119 uint16_t isoc_delta; 120 uint16_t isoc_frame; 121 uint8_t shortpkt; 122 uint8_t multishort; 123 uint8_t last_frame; 124 uint8_t trb_type; 125 uint8_t direction; 126 uint8_t tbc; 127 uint8_t tlbpc; 128 uint8_t step_td; 129 uint8_t do_isoc_sync; 130 }; 131 132 static void xhci_do_poll(struct usb_bus *); 133 static void xhci_device_done(struct usb_xfer *, usb_error_t); 134 static void xhci_root_intr(struct xhci_softc *); 135 static void xhci_free_device_ext(struct usb_device *); 136 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 137 struct usb_endpoint_descriptor *); 138 static usb_proc_callback_t xhci_configure_msg; 139 static usb_error_t xhci_configure_device(struct usb_device *); 140 static usb_error_t xhci_configure_endpoint(struct usb_device *, 141 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 142 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 143 uint8_t); 144 static usb_error_t xhci_configure_mask(struct usb_device *, 145 uint32_t, uint8_t); 146 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 147 uint64_t, uint8_t); 148 static void xhci_endpoint_doorbell(struct usb_xfer *); 149 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 150 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 151 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 152 #ifdef USB_DEBUG 153 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 154 #endif 155 156 static const struct usb_bus_methods xhci_bus_methods; 157 158 #ifdef USB_DEBUG 159 static void 160 xhci_dump_trb(struct xhci_trb *trb) 161 { 162 DPRINTFN(5, "trb = %p\n", trb); 163 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 164 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 165 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 166 } 167 168 static void 169 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 170 { 171 DPRINTFN(5, "pep = %p\n", pep); 172 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 173 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 174 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 175 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 176 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 177 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 178 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 179 } 180 181 static void 182 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 183 { 184 DPRINTFN(5, "psl = %p\n", psl); 185 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 186 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 187 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 188 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 189 } 190 #endif 191 192 uint8_t 193 xhci_use_polling(void) 194 { 195 #ifdef USB_DEBUG 196 return (xhcipolling != 0); 197 #else 198 return (0); 199 #endif 200 } 201 202 static void 203 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 204 { 205 struct xhci_softc *sc = XHCI_BUS2SC(bus); 206 uint8_t i; 207 208 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 209 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 210 211 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 212 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 213 214 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 215 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 216 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 217 } 218 } 219 220 static void 221 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 222 { 223 if (sc->sc_ctx_is_64_byte) { 224 uint32_t offset; 225 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 226 /* all contexts are initially 32-bytes */ 227 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 228 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 229 } 230 *ptr = htole32(val); 231 } 232 233 static uint32_t 234 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 235 { 236 if (sc->sc_ctx_is_64_byte) { 237 uint32_t offset; 238 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 239 /* all contexts are initially 32-bytes */ 240 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 241 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 242 } 243 return (le32toh(*ptr)); 244 } 245 246 static void 247 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 248 { 249 if (sc->sc_ctx_is_64_byte) { 250 uint32_t offset; 251 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 252 /* all contexts are initially 32-bytes */ 253 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 254 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 255 } 256 *ptr = htole64(val); 257 } 258 259 #ifdef USB_DEBUG 260 static uint64_t 261 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 262 { 263 if (sc->sc_ctx_is_64_byte) { 264 uint32_t offset; 265 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 266 /* all contexts are initially 32-bytes */ 267 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 268 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 269 } 270 return (le64toh(*ptr)); 271 } 272 #endif 273 274 static int 275 xhci_reset_command_queue_locked(struct xhci_softc *sc) 276 { 277 struct usb_page_search buf_res; 278 struct xhci_hw_root *phwr; 279 uint64_t addr; 280 uint32_t temp; 281 282 DPRINTF("\n"); 283 284 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 285 if (temp & XHCI_CRCR_LO_CRR) { 286 DPRINTF("Command ring running\n"); 287 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 288 289 /* 290 * Try to abort the last command as per section 291 * 4.6.1.2 "Aborting a Command" of the XHCI 292 * specification: 293 */ 294 295 /* stop and cancel */ 296 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 297 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 298 299 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 300 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 301 302 /* wait 250ms */ 303 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 4); 304 305 /* check if command ring is still running */ 306 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 307 if (temp & XHCI_CRCR_LO_CRR) { 308 DPRINTF("Comand ring still running\n"); 309 return (USB_ERR_IOERROR); 310 } 311 } 312 313 /* reset command ring */ 314 sc->sc_command_ccs = 1; 315 sc->sc_command_idx = 0; 316 317 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 318 319 /* setup command ring control base address */ 320 addr = buf_res.physaddr; 321 phwr = buf_res.buffer; 322 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 323 324 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 325 326 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 327 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 328 329 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 330 331 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 332 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 333 334 return (0); 335 } 336 337 usb_error_t 338 xhci_start_controller(struct xhci_softc *sc) 339 { 340 struct usb_page_search buf_res; 341 struct xhci_hw_root *phwr; 342 struct xhci_dev_ctx_addr *pdctxa; 343 uint64_t addr; 344 uint32_t temp; 345 uint16_t i; 346 347 DPRINTF("\n"); 348 349 sc->sc_capa_off = 0; 350 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 351 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 352 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 353 354 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 355 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 356 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 357 358 sc->sc_event_ccs = 1; 359 sc->sc_event_idx = 0; 360 sc->sc_command_ccs = 1; 361 sc->sc_command_idx = 0; 362 363 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 364 365 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 366 367 DPRINTF("HCS0 = 0x%08x\n", temp); 368 369 if (XHCI_HCS0_CSZ(temp)) { 370 sc->sc_ctx_is_64_byte = 1; 371 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 372 } else { 373 sc->sc_ctx_is_64_byte = 0; 374 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 375 } 376 377 /* Reset controller */ 378 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 379 380 for (i = 0; i != 100; i++) { 381 usb_pause_mtx(NULL, hz / 100); 382 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 383 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 384 if (!temp) 385 break; 386 } 387 388 if (temp) { 389 device_printf(sc->sc_bus.parent, "Controller " 390 "reset timeout.\n"); 391 return (USB_ERR_IOERROR); 392 } 393 394 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 395 device_printf(sc->sc_bus.parent, "Controller does " 396 "not support 4K page size.\n"); 397 return (USB_ERR_IOERROR); 398 } 399 400 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 401 402 i = XHCI_HCS1_N_PORTS(temp); 403 404 if (i == 0) { 405 device_printf(sc->sc_bus.parent, "Invalid number " 406 "of ports: %u\n", i); 407 return (USB_ERR_IOERROR); 408 } 409 410 sc->sc_noport = i; 411 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 412 413 if (sc->sc_noslot > XHCI_MAX_DEVICES) 414 sc->sc_noslot = XHCI_MAX_DEVICES; 415 416 /* setup number of device slots */ 417 418 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 419 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 420 421 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 422 423 DPRINTF("Max slots: %u\n", sc->sc_noslot); 424 425 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 426 427 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 428 429 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 430 device_printf(sc->sc_bus.parent, "XHCI request " 431 "too many scratchpads\n"); 432 return (USB_ERR_NOMEM); 433 } 434 435 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 436 437 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 438 439 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 440 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 441 442 temp = XREAD4(sc, oper, XHCI_USBSTS); 443 444 /* clear interrupts */ 445 XWRITE4(sc, oper, XHCI_USBSTS, temp); 446 /* disable all device notifications */ 447 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 448 449 /* setup device context base address */ 450 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 451 pdctxa = buf_res.buffer; 452 memset(pdctxa, 0, sizeof(*pdctxa)); 453 454 addr = buf_res.physaddr; 455 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 456 457 /* slot 0 points to the table of scratchpad pointers */ 458 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 459 460 for (i = 0; i != sc->sc_noscratch; i++) { 461 struct usb_page_search buf_scp; 462 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 463 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 464 } 465 466 addr = buf_res.physaddr; 467 468 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 469 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 470 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 471 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 472 473 /* Setup event table size */ 474 475 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 476 477 DPRINTF("HCS2=0x%08x\n", temp); 478 479 temp = XHCI_HCS2_ERST_MAX(temp); 480 temp = 1U << temp; 481 if (temp > XHCI_MAX_RSEG) 482 temp = XHCI_MAX_RSEG; 483 484 sc->sc_erst_max = temp; 485 486 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 487 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 488 489 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 490 491 /* Setup interrupt rate */ 492 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 493 494 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 495 496 phwr = buf_res.buffer; 497 addr = buf_res.physaddr; 498 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 499 500 /* reset hardware root structure */ 501 memset(phwr, 0, sizeof(*phwr)); 502 503 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 504 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 505 506 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 507 508 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 509 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 510 511 addr = (uint64_t)buf_res.physaddr; 512 513 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 514 515 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 516 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 517 518 /* Setup interrupter registers */ 519 520 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 521 temp |= XHCI_IMAN_INTR_ENA; 522 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 523 524 /* setup command ring control base address */ 525 addr = buf_res.physaddr; 526 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 527 528 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 529 530 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 531 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 532 533 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 534 535 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 536 537 /* Go! */ 538 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 539 XHCI_CMD_INTE | XHCI_CMD_HSEE); 540 541 for (i = 0; i != 100; i++) { 542 usb_pause_mtx(NULL, hz / 100); 543 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 544 if (!temp) 545 break; 546 } 547 if (temp) { 548 XWRITE4(sc, oper, XHCI_USBCMD, 0); 549 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 550 return (USB_ERR_IOERROR); 551 } 552 553 /* catch any lost interrupts */ 554 xhci_do_poll(&sc->sc_bus); 555 556 if (sc->sc_port_route != NULL) { 557 /* Route all ports to the XHCI by default */ 558 sc->sc_port_route(sc->sc_bus.parent, 559 ~xhciroute, xhciroute); 560 } 561 return (0); 562 } 563 564 usb_error_t 565 xhci_halt_controller(struct xhci_softc *sc) 566 { 567 uint32_t temp; 568 uint16_t i; 569 570 DPRINTF("\n"); 571 572 sc->sc_capa_off = 0; 573 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 574 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 575 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 576 577 /* Halt controller */ 578 XWRITE4(sc, oper, XHCI_USBCMD, 0); 579 580 for (i = 0; i != 100; i++) { 581 usb_pause_mtx(NULL, hz / 100); 582 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 583 if (temp) 584 break; 585 } 586 587 if (!temp) { 588 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 589 return (USB_ERR_IOERROR); 590 } 591 return (0); 592 } 593 594 usb_error_t 595 xhci_init(struct xhci_softc *sc, device_t self) 596 { 597 /* initialise some bus fields */ 598 sc->sc_bus.parent = self; 599 600 /* set the bus revision */ 601 sc->sc_bus.usbrev = USB_REV_3_0; 602 603 /* set up the bus struct */ 604 sc->sc_bus.methods = &xhci_bus_methods; 605 606 /* setup devices array */ 607 sc->sc_bus.devices = sc->sc_devices; 608 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 609 610 /* setup command queue mutex and condition varible */ 611 cv_init(&sc->sc_cmd_cv, "CMDQ"); 612 lockinit(&sc->sc_cmd_lock, "CMDQ lock", 0, 0); 613 614 /* get all DMA memory */ 615 if (usb_bus_mem_alloc_all(&sc->sc_bus, 616 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 617 return (ENOMEM); 618 } 619 620 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 621 sc->sc_config_msg[0].bus = &sc->sc_bus; 622 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 623 sc->sc_config_msg[1].bus = &sc->sc_bus; 624 625 return (0); 626 } 627 628 void 629 xhci_uninit(struct xhci_softc *sc) 630 { 631 /* 632 * NOTE: At this point the control transfer process is gone 633 * and "xhci_configure_msg" is no longer called. Consequently 634 * waiting for the configuration messages to complete is not 635 * needed. 636 */ 637 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 638 639 cv_destroy(&sc->sc_cmd_cv); 640 lockuninit(&sc->sc_cmd_lock); 641 } 642 643 static void 644 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 645 { 646 struct xhci_softc *sc = XHCI_BUS2SC(bus); 647 648 switch (state) { 649 case USB_HW_POWER_SUSPEND: 650 DPRINTF("Stopping the XHCI\n"); 651 xhci_halt_controller(sc); 652 break; 653 case USB_HW_POWER_SHUTDOWN: 654 DPRINTF("Stopping the XHCI\n"); 655 xhci_halt_controller(sc); 656 break; 657 case USB_HW_POWER_RESUME: 658 DPRINTF("Starting the XHCI\n"); 659 xhci_start_controller(sc); 660 break; 661 default: 662 break; 663 } 664 } 665 666 static usb_error_t 667 xhci_generic_done_sub(struct usb_xfer *xfer) 668 { 669 struct xhci_td *td; 670 struct xhci_td *td_alt_next; 671 uint32_t len; 672 uint8_t status; 673 674 td = xfer->td_transfer_cache; 675 td_alt_next = td->alt_next; 676 677 if (xfer->aframes != xfer->nframes) 678 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 679 680 while (1) { 681 682 usb_pc_cpu_invalidate(td->page_cache); 683 684 status = td->status; 685 len = td->remainder; 686 687 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 688 xfer, (unsigned int)xfer->aframes, 689 (unsigned int)xfer->nframes, 690 (unsigned int)len, (unsigned int)td->len, 691 (unsigned int)status); 692 693 /* 694 * Verify the status length and 695 * add the length to "frlengths[]": 696 */ 697 if (len > td->len) { 698 /* should not happen */ 699 DPRINTF("Invalid status length, " 700 "0x%04x/0x%04x bytes\n", len, td->len); 701 status = XHCI_TRB_ERROR_LENGTH; 702 } else if (xfer->aframes != xfer->nframes) { 703 xfer->frlengths[xfer->aframes] += td->len - len; 704 } 705 /* Check for last transfer */ 706 if (((void *)td) == xfer->td_transfer_last) { 707 td = NULL; 708 break; 709 } 710 /* Check for transfer error */ 711 if (status != XHCI_TRB_ERROR_SHORT_PKT && 712 status != XHCI_TRB_ERROR_SUCCESS) { 713 /* the transfer is finished */ 714 td = NULL; 715 break; 716 } 717 /* Check for short transfer */ 718 if (len > 0) { 719 if (xfer->flags_int.short_frames_ok || 720 xfer->flags_int.isochronous_xfr || 721 xfer->flags_int.control_xfr) { 722 /* follow alt next */ 723 td = td->alt_next; 724 } else { 725 /* the transfer is finished */ 726 td = NULL; 727 } 728 break; 729 } 730 td = td->obj_next; 731 732 if (td->alt_next != td_alt_next) { 733 /* this USB frame is complete */ 734 break; 735 } 736 } 737 738 /* update transfer cache */ 739 740 xfer->td_transfer_cache = td; 741 742 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 743 (status != XHCI_TRB_ERROR_SHORT_PKT && 744 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 745 USB_ERR_NORMAL_COMPLETION); 746 } 747 748 static void 749 xhci_generic_done(struct usb_xfer *xfer) 750 { 751 usb_error_t err = 0; 752 753 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 754 xfer, xfer->endpoint); 755 756 /* reset scanner */ 757 758 xfer->td_transfer_cache = xfer->td_transfer_first; 759 760 if (xfer->flags_int.control_xfr) { 761 762 if (xfer->flags_int.control_hdr) 763 err = xhci_generic_done_sub(xfer); 764 765 xfer->aframes = 1; 766 767 if (xfer->td_transfer_cache == NULL) 768 goto done; 769 } 770 771 while (xfer->aframes != xfer->nframes) { 772 773 err = xhci_generic_done_sub(xfer); 774 xfer->aframes++; 775 776 if (xfer->td_transfer_cache == NULL) 777 goto done; 778 } 779 780 if (xfer->flags_int.control_xfr && 781 !xfer->flags_int.control_act) 782 err = xhci_generic_done_sub(xfer); 783 done: 784 /* transfer is complete */ 785 xhci_device_done(xfer, err); 786 } 787 788 static void 789 xhci_activate_transfer(struct usb_xfer *xfer) 790 { 791 struct xhci_td *td; 792 793 td = xfer->td_transfer_cache; 794 795 usb_pc_cpu_invalidate(td->page_cache); 796 797 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 798 799 /* activate the transfer */ 800 801 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 802 usb_pc_cpu_flush(td->page_cache); 803 804 xhci_endpoint_doorbell(xfer); 805 } 806 } 807 808 static void 809 xhci_skip_transfer(struct usb_xfer *xfer) 810 { 811 struct xhci_td *td; 812 struct xhci_td *td_last; 813 814 td = xfer->td_transfer_cache; 815 td_last = xfer->td_transfer_last; 816 817 td = td->alt_next; 818 819 usb_pc_cpu_invalidate(td->page_cache); 820 821 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 822 823 usb_pc_cpu_invalidate(td_last->page_cache); 824 825 /* copy LINK TRB to current waiting location */ 826 827 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 828 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 829 usb_pc_cpu_flush(td->page_cache); 830 831 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 832 usb_pc_cpu_flush(td->page_cache); 833 834 xhci_endpoint_doorbell(xfer); 835 } 836 } 837 838 /*------------------------------------------------------------------------* 839 * xhci_check_transfer 840 *------------------------------------------------------------------------*/ 841 static void 842 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 843 { 844 struct xhci_endpoint_ext *pepext; 845 int64_t offset; 846 uint64_t td_event; 847 uint32_t temp; 848 uint32_t remainder; 849 uint16_t stream_id; 850 uint16_t i; 851 uint8_t status; 852 uint8_t halted; 853 uint8_t epno; 854 uint8_t index; 855 856 /* decode TRB */ 857 td_event = le64toh(trb->qwTrb0); 858 temp = le32toh(trb->dwTrb2); 859 860 remainder = XHCI_TRB_2_REM_GET(temp); 861 status = XHCI_TRB_2_ERROR_GET(temp); 862 stream_id = XHCI_TRB_2_STREAM_GET(temp); 863 864 temp = le32toh(trb->dwTrb3); 865 epno = XHCI_TRB_3_EP_GET(temp); 866 index = XHCI_TRB_3_SLOT_GET(temp); 867 868 /* check if error means halted */ 869 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 870 status != XHCI_TRB_ERROR_SUCCESS); 871 872 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 873 index, epno, stream_id, remainder, status); 874 875 if (index > sc->sc_noslot) { 876 DPRINTF("Invalid slot.\n"); 877 return; 878 } 879 880 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 881 DPRINTF("Invalid endpoint.\n"); 882 return; 883 } 884 885 pepext = &sc->sc_hw.devs[index].endp[epno]; 886 887 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 888 stream_id = 0; 889 DPRINTF("stream_id=0\n"); 890 } else if (stream_id >= XHCI_MAX_STREAMS) { 891 DPRINTF("Invalid stream ID.\n"); 892 return; 893 } 894 895 /* try to find the USB transfer that generated the event */ 896 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 897 struct usb_xfer *xfer; 898 struct xhci_td *td; 899 900 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 901 if (xfer == NULL) 902 continue; 903 904 td = xfer->td_transfer_cache; 905 906 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 907 (long long)td_event, 908 (long long)td->td_self, 909 (long long)td->td_self + sizeof(td->td_trb)); 910 911 /* 912 * NOTE: Some XHCI implementations might not trigger 913 * an event on the last LINK TRB so we need to 914 * consider both the last and second last event 915 * address as conditions for a successful transfer. 916 * 917 * NOTE: We assume that the XHCI will only trigger one 918 * event per chain of TRBs. 919 */ 920 921 offset = td_event - td->td_self; 922 923 if (offset >= 0 && 924 offset < (int64_t)sizeof(td->td_trb)) { 925 926 usb_pc_cpu_invalidate(td->page_cache); 927 928 /* compute rest of remainder, if any */ 929 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 930 temp = le32toh(td->td_trb[i].dwTrb2); 931 remainder += XHCI_TRB_2_BYTES_GET(temp); 932 } 933 934 DPRINTFN(5, "New remainder: %u\n", remainder); 935 936 /* clear isochronous transfer errors */ 937 if (xfer->flags_int.isochronous_xfr) { 938 if (halted) { 939 halted = 0; 940 status = XHCI_TRB_ERROR_SUCCESS; 941 remainder = td->len; 942 } 943 } 944 945 /* "td->remainder" is verified later */ 946 td->remainder = remainder; 947 td->status = status; 948 949 usb_pc_cpu_flush(td->page_cache); 950 951 /* 952 * 1) Last transfer descriptor makes the 953 * transfer done 954 */ 955 if (((void *)td) == xfer->td_transfer_last) { 956 DPRINTF("TD is last\n"); 957 xhci_generic_done(xfer); 958 break; 959 } 960 961 /* 962 * 2) Any kind of error makes the transfer 963 * done 964 */ 965 if (halted) { 966 DPRINTF("TD has I/O error\n"); 967 xhci_generic_done(xfer); 968 break; 969 } 970 971 /* 972 * 3) If there is no alternate next transfer, 973 * a short packet also makes the transfer done 974 */ 975 if (td->remainder > 0) { 976 if (td->alt_next == NULL) { 977 DPRINTF( 978 "short TD has no alternate next\n"); 979 xhci_generic_done(xfer); 980 break; 981 } 982 DPRINTF("TD has short pkt\n"); 983 if (xfer->flags_int.short_frames_ok || 984 xfer->flags_int.isochronous_xfr || 985 xfer->flags_int.control_xfr) { 986 /* follow the alt next */ 987 xfer->td_transfer_cache = td->alt_next; 988 xhci_activate_transfer(xfer); 989 break; 990 } 991 xhci_skip_transfer(xfer); 992 xhci_generic_done(xfer); 993 break; 994 } 995 996 /* 997 * 4) Transfer complete - go to next TD 998 */ 999 DPRINTF("Following next TD\n"); 1000 xfer->td_transfer_cache = td->obj_next; 1001 xhci_activate_transfer(xfer); 1002 break; /* there should only be one match */ 1003 } 1004 } 1005 } 1006 1007 static int 1008 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1009 { 1010 if (sc->sc_cmd_addr == trb->qwTrb0) { 1011 DPRINTF("Received command event\n"); 1012 sc->sc_cmd_result[0] = trb->dwTrb2; 1013 sc->sc_cmd_result[1] = trb->dwTrb3; 1014 cv_signal(&sc->sc_cmd_cv); 1015 return (1); /* command match */ 1016 } 1017 return (0); 1018 } 1019 1020 static int 1021 xhci_interrupt_poll(struct xhci_softc *sc) 1022 { 1023 struct usb_page_search buf_res; 1024 struct xhci_hw_root *phwr; 1025 uint64_t addr; 1026 uint32_t temp; 1027 int retval = 0; 1028 uint16_t i; 1029 uint8_t event; 1030 uint8_t j; 1031 uint8_t k; 1032 uint8_t t; 1033 1034 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1035 1036 phwr = buf_res.buffer; 1037 1038 /* Receive any events */ 1039 1040 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1041 1042 i = sc->sc_event_idx; 1043 j = sc->sc_event_ccs; 1044 t = 2; 1045 1046 while (1) { 1047 1048 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1049 1050 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1051 1052 if (j != k) 1053 break; 1054 1055 event = XHCI_TRB_3_TYPE_GET(temp); 1056 1057 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1058 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1059 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1060 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1061 1062 switch (event) { 1063 case XHCI_TRB_EVENT_TRANSFER: 1064 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1065 break; 1066 case XHCI_TRB_EVENT_CMD_COMPLETE: 1067 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1068 break; 1069 default: 1070 DPRINTF("Unhandled event = %u\n", event); 1071 break; 1072 } 1073 1074 i++; 1075 1076 if (i == XHCI_MAX_EVENTS) { 1077 i = 0; 1078 j ^= 1; 1079 1080 /* check for timeout */ 1081 if (!--t) 1082 break; 1083 } 1084 } 1085 1086 sc->sc_event_idx = i; 1087 sc->sc_event_ccs = j; 1088 1089 /* 1090 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1091 * latched. That means to activate the register we need to 1092 * write both the low and high double word of the 64-bit 1093 * register. 1094 */ 1095 1096 addr = (uint32_t)buf_res.physaddr; 1097 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1098 1099 /* try to clear busy bit */ 1100 addr |= XHCI_ERDP_LO_BUSY; 1101 1102 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1103 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1104 1105 return (retval); 1106 } 1107 1108 static usb_error_t 1109 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1110 uint16_t timeout_ms) 1111 { 1112 struct usb_page_search buf_res; 1113 struct xhci_hw_root *phwr; 1114 uint64_t addr; 1115 uint32_t temp; 1116 uint8_t i; 1117 uint8_t j; 1118 uint8_t timeout = 0; 1119 int err; 1120 1121 XHCI_CMD_ASSERT_LOCKED(sc); 1122 1123 /* get hardware root structure */ 1124 1125 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1126 1127 phwr = buf_res.buffer; 1128 1129 /* Queue command */ 1130 1131 USB_BUS_LOCK(&sc->sc_bus); 1132 retry: 1133 i = sc->sc_command_idx; 1134 j = sc->sc_command_ccs; 1135 1136 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1137 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1138 (long long)le64toh(trb->qwTrb0), 1139 (long)le32toh(trb->dwTrb2), 1140 (long)le32toh(trb->dwTrb3)); 1141 1142 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1143 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1144 1145 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1146 1147 temp = trb->dwTrb3; 1148 1149 if (j) 1150 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1151 else 1152 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1153 1154 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1155 1156 phwr->hwr_commands[i].dwTrb3 = temp; 1157 1158 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1159 1160 addr = buf_res.physaddr; 1161 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1162 1163 sc->sc_cmd_addr = htole64(addr); 1164 1165 i++; 1166 1167 if (i == (XHCI_MAX_COMMANDS - 1)) { 1168 1169 if (j) { 1170 temp = htole32(XHCI_TRB_3_TC_BIT | 1171 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1172 XHCI_TRB_3_CYCLE_BIT); 1173 } else { 1174 temp = htole32(XHCI_TRB_3_TC_BIT | 1175 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1176 } 1177 1178 phwr->hwr_commands[i].dwTrb3 = temp; 1179 1180 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1181 1182 i = 0; 1183 j ^= 1; 1184 } 1185 1186 sc->sc_command_idx = i; 1187 sc->sc_command_ccs = j; 1188 1189 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1190 1191 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_lock, 1192 USB_MS_TO_TICKS(timeout_ms)); 1193 1194 /* 1195 * In some error cases event interrupts are not generated. 1196 * Poll one time to see if the command has completed. 1197 */ 1198 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1199 DPRINTF("Command was completed when polling\n"); 1200 err = 0; 1201 } 1202 if (err != 0) { 1203 DPRINTF("Command timeout!\n"); 1204 /* 1205 * After some weeks of continuous operation, it has 1206 * been observed that the ASMedia Technology, ASM1042 1207 * SuperSpeed USB Host Controller can suddenly stop 1208 * accepting commands via the command queue. Try to 1209 * first reset the command queue. If that fails do a 1210 * host controller reset. 1211 */ 1212 if (timeout == 0 && 1213 xhci_reset_command_queue_locked(sc) == 0) { 1214 timeout = 1; 1215 goto retry; 1216 } else { 1217 DPRINTF("Controller reset!\n"); 1218 usb_bus_reset_async_locked(&sc->sc_bus); 1219 } 1220 err = USB_ERR_TIMEOUT; 1221 trb->dwTrb2 = 0; 1222 trb->dwTrb3 = 0; 1223 } else { 1224 temp = le32toh(sc->sc_cmd_result[0]); 1225 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1226 err = USB_ERR_IOERROR; 1227 1228 trb->dwTrb2 = sc->sc_cmd_result[0]; 1229 trb->dwTrb3 = sc->sc_cmd_result[1]; 1230 } 1231 1232 USB_BUS_UNLOCK(&sc->sc_bus); 1233 1234 return (err); 1235 } 1236 1237 #if 0 1238 static usb_error_t 1239 xhci_cmd_nop(struct xhci_softc *sc) 1240 { 1241 struct xhci_trb trb; 1242 uint32_t temp; 1243 1244 DPRINTF("\n"); 1245 1246 trb.qwTrb0 = 0; 1247 trb.dwTrb2 = 0; 1248 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1249 1250 trb.dwTrb3 = htole32(temp); 1251 1252 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1253 } 1254 #endif 1255 1256 static usb_error_t 1257 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1258 { 1259 struct xhci_trb trb; 1260 uint32_t temp; 1261 usb_error_t err; 1262 1263 DPRINTF("\n"); 1264 1265 trb.qwTrb0 = 0; 1266 trb.dwTrb2 = 0; 1267 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1268 1269 err = xhci_do_command(sc, &trb, 100 /* ms */); 1270 if (err) 1271 goto done; 1272 1273 temp = le32toh(trb.dwTrb3); 1274 1275 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1276 1277 done: 1278 return (err); 1279 } 1280 1281 static usb_error_t 1282 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1283 { 1284 struct xhci_trb trb; 1285 uint32_t temp; 1286 1287 DPRINTF("\n"); 1288 1289 trb.qwTrb0 = 0; 1290 trb.dwTrb2 = 0; 1291 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1292 XHCI_TRB_3_SLOT_SET(slot_id); 1293 1294 trb.dwTrb3 = htole32(temp); 1295 1296 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1297 } 1298 1299 static usb_error_t 1300 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1301 uint8_t bsr, uint8_t slot_id) 1302 { 1303 struct xhci_trb trb; 1304 uint32_t temp; 1305 1306 DPRINTF("\n"); 1307 1308 trb.qwTrb0 = htole64(input_ctx); 1309 trb.dwTrb2 = 0; 1310 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1311 XHCI_TRB_3_SLOT_SET(slot_id); 1312 1313 if (bsr) 1314 temp |= XHCI_TRB_3_BSR_BIT; 1315 1316 trb.dwTrb3 = htole32(temp); 1317 1318 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1319 } 1320 1321 static usb_error_t 1322 xhci_set_address(struct usb_device *udev, struct lock *lock, uint16_t address) 1323 { 1324 struct usb_page_search buf_inp; 1325 struct usb_page_search buf_dev; 1326 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1327 struct xhci_hw_dev *hdev; 1328 struct xhci_dev_ctx *pdev; 1329 struct xhci_endpoint_ext *pepext; 1330 uint32_t temp; 1331 uint16_t mps; 1332 usb_error_t err; 1333 uint8_t index; 1334 1335 /* the root HUB case is not handled here */ 1336 if (udev->parent_hub == NULL) 1337 return (USB_ERR_INVAL); 1338 1339 index = udev->controller_slot_id; 1340 1341 hdev = &sc->sc_hw.devs[index]; 1342 1343 if (lock != NULL) 1344 lockmgr(lock, LK_RELEASE); 1345 1346 XHCI_CMD_LOCK(sc); 1347 1348 switch (hdev->state) { 1349 case XHCI_ST_DEFAULT: 1350 case XHCI_ST_ENABLED: 1351 1352 hdev->state = XHCI_ST_ENABLED; 1353 1354 /* set configure mask to slot and EP0 */ 1355 xhci_configure_mask(udev, 3, 0); 1356 1357 /* configure input slot context structure */ 1358 err = xhci_configure_device(udev); 1359 1360 if (err != 0) { 1361 DPRINTF("Could not configure device\n"); 1362 break; 1363 } 1364 1365 /* configure input endpoint context structure */ 1366 switch (udev->speed) { 1367 case USB_SPEED_LOW: 1368 case USB_SPEED_FULL: 1369 mps = 8; 1370 break; 1371 case USB_SPEED_HIGH: 1372 mps = 64; 1373 break; 1374 default: 1375 mps = 512; 1376 break; 1377 } 1378 1379 pepext = xhci_get_endpoint_ext(udev, 1380 &udev->ctrl_ep_desc); 1381 err = xhci_configure_endpoint(udev, 1382 &udev->ctrl_ep_desc, pepext, 1383 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1384 1385 if (err != 0) { 1386 DPRINTF("Could not configure default endpoint\n"); 1387 break; 1388 } 1389 1390 /* execute set address command */ 1391 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1392 1393 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1394 (address == 0), index); 1395 1396 if (err != 0) { 1397 temp = le32toh(sc->sc_cmd_result[0]); 1398 if (address == 0 && sc->sc_port_route != NULL && 1399 XHCI_TRB_2_ERROR_GET(temp) == 1400 XHCI_TRB_ERROR_PARAMETER) { 1401 /* LynxPoint XHCI - ports are not switchable */ 1402 /* Un-route all ports from the XHCI */ 1403 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1404 } 1405 DPRINTF("Could not set address " 1406 "for slot %u.\n", index); 1407 if (address != 0) 1408 break; 1409 } 1410 1411 /* update device address to new value */ 1412 1413 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1414 pdev = buf_dev.buffer; 1415 usb_pc_cpu_invalidate(&hdev->device_pc); 1416 1417 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1418 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1419 1420 /* update device state to new value */ 1421 1422 if (address != 0) 1423 hdev->state = XHCI_ST_ADDRESSED; 1424 else 1425 hdev->state = XHCI_ST_DEFAULT; 1426 break; 1427 1428 default: 1429 DPRINTF("Wrong state for set address.\n"); 1430 err = USB_ERR_IOERROR; 1431 break; 1432 } 1433 XHCI_CMD_UNLOCK(sc); 1434 1435 if (lock != NULL) 1436 lockmgr(lock, LK_EXCLUSIVE); 1437 1438 return (err); 1439 } 1440 1441 static usb_error_t 1442 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1443 uint8_t deconfigure, uint8_t slot_id) 1444 { 1445 struct xhci_trb trb; 1446 uint32_t temp; 1447 1448 DPRINTF("\n"); 1449 1450 trb.qwTrb0 = htole64(input_ctx); 1451 trb.dwTrb2 = 0; 1452 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1453 XHCI_TRB_3_SLOT_SET(slot_id); 1454 1455 if (deconfigure) 1456 temp |= XHCI_TRB_3_DCEP_BIT; 1457 1458 trb.dwTrb3 = htole32(temp); 1459 1460 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1461 } 1462 1463 static usb_error_t 1464 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1465 uint8_t slot_id) 1466 { 1467 struct xhci_trb trb; 1468 uint32_t temp; 1469 1470 DPRINTF("\n"); 1471 1472 trb.qwTrb0 = htole64(input_ctx); 1473 trb.dwTrb2 = 0; 1474 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1475 XHCI_TRB_3_SLOT_SET(slot_id); 1476 trb.dwTrb3 = htole32(temp); 1477 1478 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1479 } 1480 1481 static usb_error_t 1482 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1483 uint8_t ep_id, uint8_t slot_id) 1484 { 1485 struct xhci_trb trb; 1486 uint32_t temp; 1487 1488 DPRINTF("\n"); 1489 1490 trb.qwTrb0 = 0; 1491 trb.dwTrb2 = 0; 1492 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1493 XHCI_TRB_3_SLOT_SET(slot_id) | 1494 XHCI_TRB_3_EP_SET(ep_id); 1495 1496 if (preserve) 1497 temp |= XHCI_TRB_3_PRSV_BIT; 1498 1499 trb.dwTrb3 = htole32(temp); 1500 1501 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1502 } 1503 1504 static usb_error_t 1505 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1506 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1507 { 1508 struct xhci_trb trb; 1509 uint32_t temp; 1510 1511 DPRINTF("\n"); 1512 1513 trb.qwTrb0 = htole64(dequeue_ptr); 1514 1515 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1516 trb.dwTrb2 = htole32(temp); 1517 1518 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1519 XHCI_TRB_3_SLOT_SET(slot_id) | 1520 XHCI_TRB_3_EP_SET(ep_id); 1521 trb.dwTrb3 = htole32(temp); 1522 1523 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1524 } 1525 1526 static usb_error_t 1527 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1528 uint8_t ep_id, uint8_t slot_id) 1529 { 1530 struct xhci_trb trb; 1531 uint32_t temp; 1532 1533 DPRINTF("\n"); 1534 1535 trb.qwTrb0 = 0; 1536 trb.dwTrb2 = 0; 1537 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1538 XHCI_TRB_3_SLOT_SET(slot_id) | 1539 XHCI_TRB_3_EP_SET(ep_id); 1540 1541 if (suspend) 1542 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1543 1544 trb.dwTrb3 = htole32(temp); 1545 1546 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1547 } 1548 1549 static usb_error_t 1550 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1551 { 1552 struct xhci_trb trb; 1553 uint32_t temp; 1554 1555 DPRINTF("\n"); 1556 1557 trb.qwTrb0 = 0; 1558 trb.dwTrb2 = 0; 1559 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1560 XHCI_TRB_3_SLOT_SET(slot_id); 1561 1562 trb.dwTrb3 = htole32(temp); 1563 1564 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1565 } 1566 1567 /*------------------------------------------------------------------------* 1568 * xhci_interrupt - XHCI interrupt handler 1569 *------------------------------------------------------------------------*/ 1570 void 1571 xhci_interrupt(struct xhci_softc *sc) 1572 { 1573 uint32_t status; 1574 1575 USB_BUS_LOCK(&sc->sc_bus); 1576 1577 status = XREAD4(sc, oper, XHCI_USBSTS); 1578 if (status == 0) { 1579 goto done; 1580 } 1581 1582 /* acknowledge interrupts */ 1583 1584 XWRITE4(sc, oper, XHCI_USBSTS, status); 1585 1586 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1587 1588 if (status & XHCI_STS_EINT) { 1589 /* check for event(s) */ 1590 xhci_interrupt_poll(sc); 1591 } 1592 1593 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1594 XHCI_STS_HSE | XHCI_STS_HCE)) { 1595 1596 if (status & XHCI_STS_PCD) { 1597 xhci_root_intr(sc); 1598 } 1599 1600 if (status & XHCI_STS_HCH) { 1601 kprintf("%s: host controller halted\n", 1602 __FUNCTION__); 1603 } 1604 1605 if (status & XHCI_STS_HSE) { 1606 kprintf("%s: host system error\n", 1607 __FUNCTION__); 1608 } 1609 1610 if (status & XHCI_STS_HCE) { 1611 kprintf("%s: host controller error\n", 1612 __FUNCTION__); 1613 } 1614 } 1615 done: 1616 USB_BUS_UNLOCK(&sc->sc_bus); 1617 } 1618 1619 /*------------------------------------------------------------------------* 1620 * xhci_timeout - XHCI timeout handler 1621 *------------------------------------------------------------------------*/ 1622 static void 1623 xhci_timeout(void *arg) 1624 { 1625 struct usb_xfer *xfer = arg; 1626 1627 DPRINTF("xfer=%p\n", xfer); 1628 1629 USB_BUS_LOCK_ASSERT(xfer->xroot->bus); 1630 1631 /* transfer is transferred */ 1632 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1633 } 1634 1635 static void 1636 xhci_do_poll(struct usb_bus *bus) 1637 { 1638 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1639 1640 USB_BUS_LOCK(&sc->sc_bus); 1641 xhci_interrupt_poll(sc); 1642 USB_BUS_UNLOCK(&sc->sc_bus); 1643 } 1644 1645 static void 1646 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1647 { 1648 struct usb_page_search buf_res; 1649 struct xhci_td *td; 1650 struct xhci_td *td_next; 1651 struct xhci_td *td_alt_next; 1652 struct xhci_td *td_first; 1653 uint32_t buf_offset; 1654 uint32_t average; 1655 uint32_t len_old; 1656 uint32_t npkt_off; 1657 uint32_t dword; 1658 uint8_t shortpkt_old; 1659 uint8_t precompute; 1660 uint8_t x; 1661 1662 td_alt_next = NULL; 1663 buf_offset = 0; 1664 shortpkt_old = temp->shortpkt; 1665 len_old = temp->len; 1666 npkt_off = 0; 1667 precompute = 1; 1668 1669 restart: 1670 1671 td = temp->td; 1672 td_next = td_first = temp->td_next; 1673 1674 while (1) { 1675 1676 if (temp->len == 0) { 1677 1678 if (temp->shortpkt) 1679 break; 1680 1681 /* send a Zero Length Packet, ZLP, last */ 1682 1683 temp->shortpkt = 1; 1684 average = 0; 1685 1686 } else { 1687 1688 average = temp->average; 1689 1690 if (temp->len < average) { 1691 if (temp->len % temp->max_packet_size) { 1692 temp->shortpkt = 1; 1693 } 1694 average = temp->len; 1695 } 1696 } 1697 1698 if (td_next == NULL) 1699 panic("%s: out of XHCI transfer descriptors!", __func__); 1700 1701 /* get next TD */ 1702 1703 td = td_next; 1704 td_next = td->obj_next; 1705 1706 /* check if we are pre-computing */ 1707 1708 if (precompute) { 1709 1710 /* update remaining length */ 1711 1712 temp->len -= average; 1713 1714 continue; 1715 } 1716 /* fill out current TD */ 1717 1718 td->len = average; 1719 td->remainder = 0; 1720 td->status = 0; 1721 1722 /* update remaining length */ 1723 1724 temp->len -= average; 1725 1726 /* reset TRB index */ 1727 1728 x = 0; 1729 1730 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1731 /* immediate data */ 1732 1733 if (average > 8) 1734 average = 8; 1735 1736 td->td_trb[0].qwTrb0 = 0; 1737 1738 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1739 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1740 average); 1741 1742 dword = XHCI_TRB_2_BYTES_SET(8) | 1743 XHCI_TRB_2_TDSZ_SET(0) | 1744 XHCI_TRB_2_IRQ_SET(0); 1745 1746 td->td_trb[0].dwTrb2 = htole32(dword); 1747 1748 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1749 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1750 1751 /* check wLength */ 1752 if (td->td_trb[0].qwTrb0 & 1753 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1754 if (td->td_trb[0].qwTrb0 & htole64(1)) 1755 dword |= XHCI_TRB_3_TRT_IN; 1756 else 1757 dword |= XHCI_TRB_3_TRT_OUT; 1758 } 1759 1760 td->td_trb[0].dwTrb3 = htole32(dword); 1761 #ifdef USB_DEBUG 1762 xhci_dump_trb(&td->td_trb[x]); 1763 #endif 1764 x++; 1765 1766 } else do { 1767 1768 uint32_t npkt; 1769 1770 /* fill out buffer pointers */ 1771 1772 if (average == 0) { 1773 memset(&buf_res, 0, sizeof(buf_res)); 1774 } else { 1775 usbd_get_page(temp->pc, temp->offset + 1776 buf_offset, &buf_res); 1777 1778 /* get length to end of page */ 1779 if (buf_res.length > average) 1780 buf_res.length = average; 1781 1782 /* check for maximum length */ 1783 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1784 buf_res.length = XHCI_TD_PAGE_SIZE; 1785 1786 npkt_off += buf_res.length; 1787 } 1788 1789 /* setup npkt */ 1790 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1791 temp->max_packet_size; 1792 1793 if (npkt == 0) 1794 npkt = 1; 1795 else if (npkt > 31) 1796 npkt = 31; 1797 1798 /* fill out TRB's */ 1799 td->td_trb[x].qwTrb0 = 1800 htole64((uint64_t)buf_res.physaddr); 1801 1802 dword = 1803 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1804 XHCI_TRB_2_TDSZ_SET(npkt) | 1805 XHCI_TRB_2_IRQ_SET(0); 1806 1807 td->td_trb[x].dwTrb2 = htole32(dword); 1808 1809 switch (temp->trb_type) { 1810 case XHCI_TRB_TYPE_ISOCH: 1811 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1812 XHCI_TRB_3_TBC_SET(temp->tbc) | 1813 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1814 if (td != td_first) { 1815 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1816 } else if (temp->do_isoc_sync != 0) { 1817 temp->do_isoc_sync = 0; 1818 /* wait until "isoc_frame" */ 1819 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1820 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1821 } else { 1822 /* start data transfer at next interval */ 1823 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1824 XHCI_TRB_3_ISO_SIA_BIT; 1825 } 1826 if (temp->direction == UE_DIR_IN) 1827 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1828 break; 1829 case XHCI_TRB_TYPE_DATA_STAGE: 1830 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1831 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 1832 XHCI_TRB_3_TBC_SET(temp->tbc) | 1833 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1834 if (temp->direction == UE_DIR_IN) 1835 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1836 break; 1837 case XHCI_TRB_TYPE_STATUS_STAGE: 1838 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1839 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 1840 XHCI_TRB_3_TBC_SET(temp->tbc) | 1841 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1842 if (temp->direction == UE_DIR_IN) 1843 dword |= XHCI_TRB_3_DIR_IN; 1844 break; 1845 default: /* XHCI_TRB_TYPE_NORMAL */ 1846 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1847 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 1848 XHCI_TRB_3_TBC_SET(temp->tbc) | 1849 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1850 if (temp->direction == UE_DIR_IN) 1851 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1852 break; 1853 } 1854 td->td_trb[x].dwTrb3 = htole32(dword); 1855 1856 average -= buf_res.length; 1857 buf_offset += buf_res.length; 1858 #ifdef USB_DEBUG 1859 xhci_dump_trb(&td->td_trb[x]); 1860 #endif 1861 x++; 1862 1863 } while (average != 0); 1864 1865 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1866 1867 /* store number of data TRB's */ 1868 1869 td->ntrb = x; 1870 1871 DPRINTF("NTRB=%u\n", x); 1872 1873 /* fill out link TRB */ 1874 1875 if (td_next != NULL) { 1876 /* link the current TD with the next one */ 1877 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1878 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1879 } else { 1880 /* this field will get updated later */ 1881 DPRINTF("NOLINK\n"); 1882 } 1883 1884 dword = XHCI_TRB_2_IRQ_SET(0); 1885 1886 td->td_trb[x].dwTrb2 = htole32(dword); 1887 1888 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1889 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1890 /* 1891 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1892 * frame only receives a single short packet event 1893 * by setting the CHAIN bit in the LINK field. In 1894 * addition some XHCI controllers have problems 1895 * sending a ZLP unless the CHAIN-BIT is set in 1896 * the LINK TRB. 1897 */ 1898 XHCI_TRB_3_CHAIN_BIT; 1899 1900 td->td_trb[x].dwTrb3 = htole32(dword); 1901 1902 td->alt_next = td_alt_next; 1903 #ifdef USB_DEBUG 1904 xhci_dump_trb(&td->td_trb[x]); 1905 #endif 1906 usb_pc_cpu_flush(td->page_cache); 1907 } 1908 1909 if (precompute) { 1910 precompute = 0; 1911 1912 /* setup alt next pointer, if any */ 1913 if (temp->last_frame) { 1914 td_alt_next = NULL; 1915 } else { 1916 /* we use this field internally */ 1917 td_alt_next = td_next; 1918 } 1919 1920 /* restore */ 1921 temp->shortpkt = shortpkt_old; 1922 temp->len = len_old; 1923 goto restart; 1924 } 1925 1926 /* 1927 * Remove cycle bit from the first TRB if we are 1928 * stepping them: 1929 */ 1930 if (temp->step_td != 0) { 1931 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1932 usb_pc_cpu_flush(td_first->page_cache); 1933 } 1934 1935 /* clear TD SIZE to zero, hence this is the last TRB */ 1936 /* remove chain bit because this is the last data TRB in the chain */ 1937 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1938 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1939 /* remove CHAIN-BIT from last LINK TRB */ 1940 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1941 1942 usb_pc_cpu_flush(td->page_cache); 1943 1944 temp->td = td; 1945 temp->td_next = td_next; 1946 } 1947 1948 static void 1949 xhci_setup_generic_chain(struct usb_xfer *xfer) 1950 { 1951 struct xhci_std_temp temp; 1952 struct xhci_td *td; 1953 uint32_t x; 1954 uint32_t y; 1955 uint8_t mult; 1956 1957 temp.do_isoc_sync = 0; 1958 temp.step_td = 0; 1959 temp.tbc = 0; 1960 temp.tlbpc = 0; 1961 temp.average = xfer->max_hc_frame_size; 1962 temp.max_packet_size = xfer->max_packet_size; 1963 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1964 temp.pc = NULL; 1965 temp.last_frame = 0; 1966 temp.offset = 0; 1967 temp.multishort = xfer->flags_int.isochronous_xfr || 1968 xfer->flags_int.control_xfr || 1969 xfer->flags_int.short_frames_ok; 1970 1971 /* toggle the DMA set we are using */ 1972 xfer->flags_int.curr_dma_set ^= 1; 1973 1974 /* get next DMA set */ 1975 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1976 1977 temp.td = NULL; 1978 temp.td_next = td; 1979 1980 xfer->td_transfer_first = td; 1981 xfer->td_transfer_cache = td; 1982 1983 if (xfer->flags_int.isochronous_xfr) { 1984 uint8_t shift; 1985 1986 /* compute multiplier for ISOCHRONOUS transfers */ 1987 mult = xfer->endpoint->ecomp ? 1988 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 1989 : 0; 1990 /* check for USB 2.0 multiplier */ 1991 if (mult == 0) { 1992 mult = (xfer->endpoint->edesc-> 1993 wMaxPacketSize[1] >> 3) & 3; 1994 } 1995 /* range check */ 1996 if (mult > 2) 1997 mult = 3; 1998 else 1999 mult++; 2000 2001 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2002 2003 DPRINTF("MFINDEX=0x%08x\n", x); 2004 2005 switch (usbd_get_speed(xfer->xroot->udev)) { 2006 case USB_SPEED_FULL: 2007 shift = 3; 2008 temp.isoc_delta = 8; /* 1ms */ 2009 x += temp.isoc_delta - 1; 2010 x &= ~(temp.isoc_delta - 1); 2011 break; 2012 default: 2013 shift = usbd_xfer_get_fps_shift(xfer); 2014 temp.isoc_delta = 1U << shift; 2015 x += temp.isoc_delta - 1; 2016 x &= ~(temp.isoc_delta - 1); 2017 /* simple frame load balancing */ 2018 x += xfer->endpoint->usb_uframe; 2019 break; 2020 } 2021 2022 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2023 2024 if ((xfer->endpoint->is_synced == 0) || 2025 (y < (xfer->nframes << shift)) || 2026 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2027 /* 2028 * If there is data underflow or the pipe 2029 * queue is empty we schedule the transfer a 2030 * few frames ahead of the current frame 2031 * position. Else two isochronous transfers 2032 * might overlap. 2033 */ 2034 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2035 xfer->endpoint->is_synced = 1; 2036 temp.do_isoc_sync = 1; 2037 2038 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2039 } 2040 2041 /* compute isochronous completion time */ 2042 2043 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2044 2045 xfer->isoc_time_complete = 2046 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2047 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2048 2049 x = 0; 2050 temp.isoc_frame = xfer->endpoint->isoc_next; 2051 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2052 2053 xfer->endpoint->isoc_next += xfer->nframes << shift; 2054 2055 } else if (xfer->flags_int.control_xfr) { 2056 2057 /* check if we should prepend a setup message */ 2058 2059 if (xfer->flags_int.control_hdr) { 2060 2061 temp.len = xfer->frlengths[0]; 2062 temp.pc = xfer->frbuffers + 0; 2063 temp.shortpkt = temp.len ? 1 : 0; 2064 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2065 temp.direction = 0; 2066 2067 /* check for last frame */ 2068 if (xfer->nframes == 1) { 2069 /* no STATUS stage yet, SETUP is last */ 2070 if (xfer->flags_int.control_act) 2071 temp.last_frame = 1; 2072 } 2073 2074 xhci_setup_generic_chain_sub(&temp); 2075 } 2076 x = 1; 2077 mult = 1; 2078 temp.isoc_delta = 0; 2079 temp.isoc_frame = 0; 2080 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 2081 } else { 2082 x = 0; 2083 mult = 1; 2084 temp.isoc_delta = 0; 2085 temp.isoc_frame = 0; 2086 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2087 } 2088 2089 if (x != xfer->nframes) { 2090 /* setup page_cache pointer */ 2091 temp.pc = xfer->frbuffers + x; 2092 /* set endpoint direction */ 2093 temp.direction = UE_GET_DIR(xfer->endpointno); 2094 } 2095 2096 while (x != xfer->nframes) { 2097 2098 /* DATA0 / DATA1 message */ 2099 2100 temp.len = xfer->frlengths[x]; 2101 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2102 x != 0 && temp.multishort == 0); 2103 2104 x++; 2105 2106 if (x == xfer->nframes) { 2107 if (xfer->flags_int.control_xfr) { 2108 /* no STATUS stage yet, DATA is last */ 2109 if (xfer->flags_int.control_act) 2110 temp.last_frame = 1; 2111 } else { 2112 temp.last_frame = 1; 2113 } 2114 } 2115 if (temp.len == 0) { 2116 2117 /* make sure that we send an USB packet */ 2118 2119 temp.shortpkt = 0; 2120 2121 temp.tbc = 0; 2122 temp.tlbpc = mult - 1; 2123 2124 } else if (xfer->flags_int.isochronous_xfr) { 2125 2126 uint8_t tdpc; 2127 2128 /* 2129 * Isochronous transfers don't have short 2130 * packet termination: 2131 */ 2132 2133 temp.shortpkt = 1; 2134 2135 /* isochronous transfers have a transfer limit */ 2136 2137 if (temp.len > xfer->max_frame_size) 2138 temp.len = xfer->max_frame_size; 2139 2140 /* compute TD packet count */ 2141 tdpc = (temp.len + xfer->max_packet_size - 1) / 2142 xfer->max_packet_size; 2143 2144 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2145 temp.tlbpc = (tdpc % mult); 2146 2147 if (temp.tlbpc == 0) 2148 temp.tlbpc = mult - 1; 2149 else 2150 temp.tlbpc--; 2151 } else { 2152 2153 /* regular data transfer */ 2154 2155 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2156 } 2157 2158 xhci_setup_generic_chain_sub(&temp); 2159 2160 if (xfer->flags_int.isochronous_xfr) { 2161 temp.offset += xfer->frlengths[x - 1]; 2162 temp.isoc_frame += temp.isoc_delta; 2163 } else { 2164 /* get next Page Cache pointer */ 2165 temp.pc = xfer->frbuffers + x; 2166 } 2167 } 2168 2169 /* check if we should append a status stage */ 2170 2171 if (xfer->flags_int.control_xfr && 2172 !xfer->flags_int.control_act) { 2173 2174 /* 2175 * Send a DATA1 message and invert the current 2176 * endpoint direction. 2177 */ 2178 temp.step_td = (xfer->nframes != 0); 2179 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2180 temp.len = 0; 2181 temp.pc = NULL; 2182 temp.shortpkt = 0; 2183 temp.last_frame = 1; 2184 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2185 2186 xhci_setup_generic_chain_sub(&temp); 2187 } 2188 2189 td = temp.td; 2190 2191 /* must have at least one frame! */ 2192 2193 xfer->td_transfer_last = td; 2194 2195 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2196 } 2197 2198 static void 2199 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2200 { 2201 struct usb_page_search buf_res; 2202 struct xhci_dev_ctx_addr *pdctxa; 2203 2204 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2205 2206 pdctxa = buf_res.buffer; 2207 2208 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2209 2210 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2211 2212 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2213 } 2214 2215 static usb_error_t 2216 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2217 { 2218 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2219 struct usb_page_search buf_inp; 2220 struct xhci_input_dev_ctx *pinp; 2221 uint32_t temp; 2222 uint8_t index; 2223 uint8_t x; 2224 2225 index = udev->controller_slot_id; 2226 2227 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2228 2229 pinp = buf_inp.buffer; 2230 2231 if (drop) { 2232 mask &= XHCI_INCTX_NON_CTRL_MASK; 2233 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2234 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2235 } else { 2236 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2237 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2238 2239 /* find most significant set bit */ 2240 for (x = 31; x != 1; x--) { 2241 if (mask & (1 << x)) 2242 break; 2243 } 2244 2245 /* adjust */ 2246 x--; 2247 2248 /* figure out maximum */ 2249 if (x > sc->sc_hw.devs[index].context_num) { 2250 sc->sc_hw.devs[index].context_num = x; 2251 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2252 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2253 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2254 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2255 } 2256 } 2257 return (0); 2258 } 2259 2260 static usb_error_t 2261 xhci_configure_endpoint(struct usb_device *udev, 2262 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2263 uint16_t interval, uint8_t max_packet_count, 2264 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2265 uint16_t max_frame_size, uint8_t ep_mode) 2266 { 2267 struct usb_page_search buf_inp; 2268 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2269 struct xhci_input_dev_ctx *pinp; 2270 uint64_t ring_addr = pepext->physaddr; 2271 uint32_t temp; 2272 uint8_t index; 2273 uint8_t epno; 2274 uint8_t type; 2275 2276 index = udev->controller_slot_id; 2277 2278 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2279 2280 pinp = buf_inp.buffer; 2281 2282 epno = edesc->bEndpointAddress; 2283 type = edesc->bmAttributes & UE_XFERTYPE; 2284 2285 if (type == UE_CONTROL) 2286 epno |= UE_DIR_IN; 2287 2288 epno = XHCI_EPNO2EPID(epno); 2289 2290 if (epno == 0) 2291 return (USB_ERR_NO_PIPE); /* invalid */ 2292 2293 if (max_packet_count == 0) 2294 return (USB_ERR_BAD_BUFSIZE); 2295 2296 max_packet_count--; 2297 2298 if (mult == 0) 2299 return (USB_ERR_BAD_BUFSIZE); 2300 2301 /* store endpoint mode */ 2302 pepext->trb_ep_mode = ep_mode; 2303 usb_pc_cpu_flush(pepext->page_cache); 2304 2305 if (ep_mode == USB_EP_MODE_STREAMS) { 2306 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2307 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2308 XHCI_EPCTX_0_LSA_SET(1); 2309 2310 ring_addr += sizeof(struct xhci_trb) * 2311 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2312 } else { 2313 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2314 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2315 XHCI_EPCTX_0_LSA_SET(0); 2316 2317 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2318 } 2319 2320 switch (udev->speed) { 2321 case USB_SPEED_FULL: 2322 case USB_SPEED_LOW: 2323 /* 1ms -> 125us */ 2324 fps_shift += 3; 2325 break; 2326 default: 2327 break; 2328 } 2329 2330 switch (type) { 2331 case UE_INTERRUPT: 2332 if (fps_shift > 3) 2333 fps_shift--; 2334 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2335 break; 2336 case UE_ISOCHRONOUS: 2337 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2338 2339 switch (udev->speed) { 2340 case USB_SPEED_SUPER: 2341 if (mult > 3) 2342 mult = 3; 2343 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2344 max_packet_count /= mult; 2345 break; 2346 default: 2347 break; 2348 } 2349 break; 2350 default: 2351 break; 2352 } 2353 2354 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2355 2356 temp = 2357 XHCI_EPCTX_1_HID_SET(0) | 2358 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2359 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2360 2361 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2362 if (type != UE_ISOCHRONOUS) 2363 temp |= XHCI_EPCTX_1_CERR_SET(3); 2364 } 2365 2366 switch (type) { 2367 case UE_CONTROL: 2368 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2369 break; 2370 case UE_ISOCHRONOUS: 2371 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2372 break; 2373 case UE_BULK: 2374 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2375 break; 2376 default: 2377 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2378 break; 2379 } 2380 2381 /* check for IN direction */ 2382 if (epno & 1) 2383 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2384 2385 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2386 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2387 2388 switch (edesc->bmAttributes & UE_XFERTYPE) { 2389 case UE_INTERRUPT: 2390 case UE_ISOCHRONOUS: 2391 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2392 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2393 max_frame_size)); 2394 break; 2395 case UE_CONTROL: 2396 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2397 break; 2398 default: 2399 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2400 break; 2401 } 2402 2403 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2404 2405 #ifdef USB_DEBUG 2406 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2407 #endif 2408 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2409 2410 return (0); /* success */ 2411 } 2412 2413 static usb_error_t 2414 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2415 { 2416 struct xhci_endpoint_ext *pepext; 2417 struct usb_endpoint_ss_comp_descriptor *ecomp; 2418 usb_stream_t x; 2419 2420 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2421 xfer->endpoint->edesc); 2422 2423 ecomp = xfer->endpoint->ecomp; 2424 2425 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2426 uint64_t temp; 2427 2428 /* halt any transfers */ 2429 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2430 2431 /* compute start of TRB ring for stream "x" */ 2432 temp = pepext->physaddr + 2433 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2434 XHCI_SCTX_0_SCT_SEC_TR_RING; 2435 2436 /* make tree structure */ 2437 pepext->trb[(XHCI_MAX_TRANSFERS * 2438 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2439 2440 /* reserved fields */ 2441 pepext->trb[(XHCI_MAX_TRANSFERS * 2442 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2443 pepext->trb[(XHCI_MAX_TRANSFERS * 2444 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2445 } 2446 usb_pc_cpu_flush(pepext->page_cache); 2447 2448 return (xhci_configure_endpoint(xfer->xroot->udev, 2449 xfer->endpoint->edesc, pepext, 2450 xfer->interval, xfer->max_packet_count, 2451 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2452 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2453 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2454 } 2455 2456 static usb_error_t 2457 xhci_configure_device(struct usb_device *udev) 2458 { 2459 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2460 struct usb_page_search buf_inp; 2461 struct usb_page_cache *pcinp; 2462 struct xhci_input_dev_ctx *pinp; 2463 struct usb_device *hubdev; 2464 uint32_t temp; 2465 uint32_t route; 2466 uint32_t rh_port; 2467 uint8_t is_hub; 2468 uint8_t index; 2469 uint8_t depth; 2470 2471 index = udev->controller_slot_id; 2472 2473 DPRINTF("index=%u\n", index); 2474 2475 pcinp = &sc->sc_hw.devs[index].input_pc; 2476 2477 usbd_get_page(pcinp, 0, &buf_inp); 2478 2479 pinp = buf_inp.buffer; 2480 2481 rh_port = 0; 2482 route = 0; 2483 2484 /* figure out route string and root HUB port number */ 2485 2486 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2487 2488 if (hubdev->parent_hub == NULL) 2489 break; 2490 2491 depth = hubdev->parent_hub->depth; 2492 2493 /* 2494 * NOTE: HS/FS/LS devices and the SS root HUB can have 2495 * more than 15 ports 2496 */ 2497 2498 rh_port = hubdev->port_no; 2499 2500 if (depth == 0) 2501 break; 2502 2503 if (rh_port > 15) 2504 rh_port = 15; 2505 2506 if (depth < 6) 2507 route |= rh_port << (4 * (depth - 1)); 2508 } 2509 2510 DPRINTF("Route=0x%08x\n", route); 2511 2512 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2513 XHCI_SCTX_0_CTX_NUM_SET( 2514 sc->sc_hw.devs[index].context_num + 1); 2515 2516 switch (udev->speed) { 2517 case USB_SPEED_LOW: 2518 temp |= XHCI_SCTX_0_SPEED_SET(2); 2519 if (udev->parent_hs_hub != NULL && 2520 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2521 UDPROTO_HSHUBMTT) { 2522 DPRINTF("Device inherits MTT\n"); 2523 temp |= XHCI_SCTX_0_MTT_SET(1); 2524 } 2525 break; 2526 case USB_SPEED_HIGH: 2527 temp |= XHCI_SCTX_0_SPEED_SET(3); 2528 if (sc->sc_hw.devs[index].nports != 0 && 2529 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2530 DPRINTF("HUB supports MTT\n"); 2531 temp |= XHCI_SCTX_0_MTT_SET(1); 2532 } 2533 break; 2534 case USB_SPEED_FULL: 2535 temp |= XHCI_SCTX_0_SPEED_SET(1); 2536 if (udev->parent_hs_hub != NULL && 2537 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2538 UDPROTO_HSHUBMTT) { 2539 DPRINTF("Device inherits MTT\n"); 2540 temp |= XHCI_SCTX_0_MTT_SET(1); 2541 } 2542 break; 2543 default: 2544 temp |= XHCI_SCTX_0_SPEED_SET(4); 2545 break; 2546 } 2547 2548 is_hub = sc->sc_hw.devs[index].nports != 0 && 2549 (udev->speed == USB_SPEED_SUPER || 2550 udev->speed == USB_SPEED_HIGH); 2551 2552 if (is_hub) { 2553 temp |= XHCI_SCTX_0_HUB_SET(1); 2554 } 2555 2556 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2557 2558 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2559 2560 if (is_hub) { 2561 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2562 sc->sc_hw.devs[index].nports); 2563 } 2564 2565 switch (udev->speed) { 2566 case USB_SPEED_SUPER: 2567 switch (sc->sc_hw.devs[index].state) { 2568 case XHCI_ST_ADDRESSED: 2569 case XHCI_ST_CONFIGURED: 2570 /* enable power save */ 2571 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2572 break; 2573 default: 2574 /* disable power save */ 2575 break; 2576 } 2577 break; 2578 default: 2579 break; 2580 } 2581 2582 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2583 2584 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2585 2586 if (is_hub) { 2587 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2588 sc->sc_hw.devs[index].tt); 2589 } 2590 2591 hubdev = udev->parent_hs_hub; 2592 2593 /* check if we should activate the transaction translator */ 2594 switch (udev->speed) { 2595 case USB_SPEED_FULL: 2596 case USB_SPEED_LOW: 2597 if (hubdev != NULL) { 2598 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2599 hubdev->controller_slot_id); 2600 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2601 udev->hs_port_no); 2602 } 2603 break; 2604 default: 2605 break; 2606 } 2607 2608 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2609 2610 /* 2611 * These fields should be initialized to zero, according to 2612 * XHCI section 6.2.2 - slot context: 2613 */ 2614 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2615 XHCI_SCTX_3_SLOT_STATE_SET(0); 2616 2617 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2618 2619 #ifdef USB_DEBUG 2620 xhci_dump_device(sc, &pinp->ctx_slot); 2621 #endif 2622 usb_pc_cpu_flush(pcinp); 2623 2624 return (0); /* success */ 2625 } 2626 2627 static usb_error_t 2628 xhci_alloc_device_ext(struct usb_device *udev) 2629 { 2630 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2631 struct usb_page_search buf_dev; 2632 struct usb_page_search buf_ep; 2633 struct xhci_trb *trb; 2634 struct usb_page_cache *pc; 2635 struct usb_page *pg; 2636 uint64_t addr; 2637 uint8_t index; 2638 uint8_t i; 2639 2640 index = udev->controller_slot_id; 2641 2642 pc = &sc->sc_hw.devs[index].device_pc; 2643 pg = &sc->sc_hw.devs[index].device_pg; 2644 2645 /* need to initialize the page cache */ 2646 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2647 2648 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2649 (2 * sizeof(struct xhci_dev_ctx)) : 2650 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2651 goto error; 2652 2653 usbd_get_page(pc, 0, &buf_dev); 2654 2655 pc = &sc->sc_hw.devs[index].input_pc; 2656 pg = &sc->sc_hw.devs[index].input_pg; 2657 2658 /* need to initialize the page cache */ 2659 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2660 2661 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2662 (2 * sizeof(struct xhci_input_dev_ctx)) : 2663 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2664 goto error; 2665 } 2666 2667 pc = &sc->sc_hw.devs[index].endpoint_pc; 2668 pg = &sc->sc_hw.devs[index].endpoint_pg; 2669 2670 /* need to initialize the page cache */ 2671 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2672 2673 if (usb_pc_alloc_mem(pc, pg, 2674 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2675 goto error; 2676 } 2677 2678 /* initialise all endpoint LINK TRBs */ 2679 2680 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2681 2682 /* lookup endpoint TRB ring */ 2683 usbd_get_page(pc, (uintptr_t)& 2684 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2685 2686 /* get TRB pointer */ 2687 trb = buf_ep.buffer; 2688 trb += XHCI_MAX_TRANSFERS - 1; 2689 2690 /* get TRB start address */ 2691 addr = buf_ep.physaddr; 2692 2693 /* create LINK TRB */ 2694 trb->qwTrb0 = htole64(addr); 2695 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2696 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2697 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2698 } 2699 2700 usb_pc_cpu_flush(pc); 2701 2702 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2703 2704 return (0); 2705 2706 error: 2707 xhci_free_device_ext(udev); 2708 2709 return (USB_ERR_NOMEM); 2710 } 2711 2712 static void 2713 xhci_free_device_ext(struct usb_device *udev) 2714 { 2715 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2716 uint8_t index; 2717 2718 index = udev->controller_slot_id; 2719 xhci_set_slot_pointer(sc, index, 0); 2720 2721 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2722 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2723 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2724 } 2725 2726 static struct xhci_endpoint_ext * 2727 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2728 { 2729 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2730 struct xhci_endpoint_ext *pepext; 2731 struct usb_page_cache *pc; 2732 struct usb_page_search buf_ep; 2733 uint8_t epno; 2734 uint8_t index; 2735 2736 epno = edesc->bEndpointAddress; 2737 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2738 epno |= UE_DIR_IN; 2739 2740 epno = XHCI_EPNO2EPID(epno); 2741 2742 index = udev->controller_slot_id; 2743 2744 pc = &sc->sc_hw.devs[index].endpoint_pc; 2745 2746 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2747 trb[epno][0], &buf_ep); 2748 2749 pepext = &sc->sc_hw.devs[index].endp[epno]; 2750 pepext->page_cache = pc; 2751 pepext->trb = buf_ep.buffer; 2752 pepext->physaddr = buf_ep.physaddr; 2753 2754 return (pepext); 2755 } 2756 2757 static void 2758 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2759 { 2760 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2761 uint8_t epno; 2762 uint8_t index; 2763 2764 epno = xfer->endpointno; 2765 if (xfer->flags_int.control_xfr) 2766 epno |= UE_DIR_IN; 2767 2768 epno = XHCI_EPNO2EPID(epno); 2769 index = xfer->xroot->udev->controller_slot_id; 2770 2771 if (xfer->xroot->udev->flags.self_suspended == 0) { 2772 XWRITE4(sc, door, XHCI_DOORBELL(index), 2773 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2774 } 2775 } 2776 2777 static void 2778 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2779 { 2780 struct xhci_endpoint_ext *pepext; 2781 2782 if (xfer->flags_int.bandwidth_reclaimed) { 2783 xfer->flags_int.bandwidth_reclaimed = 0; 2784 2785 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2786 xfer->endpoint->edesc); 2787 2788 pepext->trb_used[xfer->stream_id]--; 2789 2790 pepext->xfer[xfer->qh_pos] = NULL; 2791 2792 if (error && pepext->trb_running != 0) { 2793 pepext->trb_halted = 1; 2794 pepext->trb_running = 0; 2795 } 2796 } 2797 } 2798 2799 static usb_error_t 2800 xhci_transfer_insert(struct usb_xfer *xfer) 2801 { 2802 struct xhci_td *td_first; 2803 struct xhci_td *td_last; 2804 struct xhci_trb *trb_link; 2805 struct xhci_endpoint_ext *pepext; 2806 uint64_t addr; 2807 usb_stream_t id; 2808 uint8_t i; 2809 uint8_t inext; 2810 uint8_t trb_limit; 2811 2812 DPRINTFN(8, "\n"); 2813 2814 id = xfer->stream_id; 2815 2816 /* check if already inserted */ 2817 if (xfer->flags_int.bandwidth_reclaimed) { 2818 DPRINTFN(8, "Already in schedule\n"); 2819 return (0); 2820 } 2821 2822 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2823 xfer->endpoint->edesc); 2824 2825 td_first = xfer->td_transfer_first; 2826 td_last = xfer->td_transfer_last; 2827 addr = pepext->physaddr; 2828 2829 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2830 case UE_CONTROL: 2831 case UE_INTERRUPT: 2832 /* single buffered */ 2833 trb_limit = 1; 2834 break; 2835 default: 2836 /* multi buffered */ 2837 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2838 break; 2839 } 2840 2841 if (pepext->trb_used[id] >= trb_limit) { 2842 DPRINTFN(8, "Too many TDs queued.\n"); 2843 return (USB_ERR_NOMEM); 2844 } 2845 2846 /* check for stopped condition, after putting transfer on interrupt queue */ 2847 if (pepext->trb_running == 0) { 2848 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2849 2850 DPRINTFN(8, "Not running\n"); 2851 2852 /* start configuration */ 2853 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2854 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2855 return (0); 2856 } 2857 2858 pepext->trb_used[id]++; 2859 2860 /* get current TRB index */ 2861 i = pepext->trb_index[id]; 2862 2863 /* get next TRB index */ 2864 inext = (i + 1); 2865 2866 /* the last entry of the ring is a hardcoded link TRB */ 2867 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2868 inext = 0; 2869 2870 /* store next TRB index, before stream ID offset is added */ 2871 pepext->trb_index[id] = inext; 2872 2873 /* offset for stream */ 2874 i += id * XHCI_MAX_TRANSFERS; 2875 inext += id * XHCI_MAX_TRANSFERS; 2876 2877 /* compute terminating return address */ 2878 addr += (inext * sizeof(struct xhci_trb)); 2879 2880 /* compute link TRB pointer */ 2881 trb_link = td_last->td_trb + td_last->ntrb; 2882 2883 /* update next pointer of last link TRB */ 2884 trb_link->qwTrb0 = htole64(addr); 2885 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2886 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2887 XHCI_TRB_3_CYCLE_BIT | 2888 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2889 2890 #ifdef USB_DEBUG 2891 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2892 #endif 2893 usb_pc_cpu_flush(td_last->page_cache); 2894 2895 /* write ahead chain end marker */ 2896 2897 pepext->trb[inext].qwTrb0 = 0; 2898 pepext->trb[inext].dwTrb2 = 0; 2899 pepext->trb[inext].dwTrb3 = 0; 2900 2901 /* update next pointer of link TRB */ 2902 2903 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2904 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2905 2906 #ifdef USB_DEBUG 2907 xhci_dump_trb(&pepext->trb[i]); 2908 #endif 2909 usb_pc_cpu_flush(pepext->page_cache); 2910 2911 /* toggle cycle bit which activates the transfer chain */ 2912 2913 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2914 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2915 2916 usb_pc_cpu_flush(pepext->page_cache); 2917 2918 DPRINTF("qh_pos = %u\n", i); 2919 2920 pepext->xfer[i] = xfer; 2921 2922 xfer->qh_pos = i; 2923 2924 xfer->flags_int.bandwidth_reclaimed = 1; 2925 2926 xhci_endpoint_doorbell(xfer); 2927 2928 return (0); 2929 } 2930 2931 static void 2932 xhci_root_intr(struct xhci_softc *sc) 2933 { 2934 uint16_t i; 2935 2936 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2937 2938 /* clear any old interrupt data */ 2939 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2940 2941 for (i = 1; i <= sc->sc_noport; i++) { 2942 /* pick out CHANGE bits from the status register */ 2943 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2944 XHCI_PS_CSC | XHCI_PS_PEC | 2945 XHCI_PS_OCC | XHCI_PS_WRC | 2946 XHCI_PS_PRC | XHCI_PS_PLC | 2947 XHCI_PS_CEC)) { 2948 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2949 DPRINTF("port %d changed\n", i); 2950 } 2951 } 2952 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2953 sizeof(sc->sc_hub_idata)); 2954 } 2955 2956 /*------------------------------------------------------------------------* 2957 * xhci_device_done - XHCI done handler 2958 * 2959 * NOTE: This function can be called two times in a row on 2960 * the same USB transfer. From close and from interrupt. 2961 *------------------------------------------------------------------------*/ 2962 static void 2963 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2964 { 2965 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2966 xfer, xfer->endpoint, error); 2967 2968 /* remove transfer from HW queue */ 2969 xhci_transfer_remove(xfer, error); 2970 2971 /* dequeue transfer and start next transfer */ 2972 usbd_transfer_done(xfer, error); 2973 } 2974 2975 /*------------------------------------------------------------------------* 2976 * XHCI data transfer support (generic type) 2977 *------------------------------------------------------------------------*/ 2978 static void 2979 xhci_device_generic_open(struct usb_xfer *xfer) 2980 { 2981 if (xfer->flags_int.isochronous_xfr) { 2982 switch (xfer->xroot->udev->speed) { 2983 case USB_SPEED_FULL: 2984 break; 2985 default: 2986 usb_hs_bandwidth_alloc(xfer); 2987 break; 2988 } 2989 } 2990 } 2991 2992 static void 2993 xhci_device_generic_close(struct usb_xfer *xfer) 2994 { 2995 DPRINTF("\n"); 2996 2997 xhci_device_done(xfer, USB_ERR_CANCELLED); 2998 2999 if (xfer->flags_int.isochronous_xfr) { 3000 switch (xfer->xroot->udev->speed) { 3001 case USB_SPEED_FULL: 3002 break; 3003 default: 3004 usb_hs_bandwidth_free(xfer); 3005 break; 3006 } 3007 } 3008 } 3009 3010 static void 3011 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3012 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3013 { 3014 struct usb_xfer *xfer; 3015 3016 /* check if there is a current transfer */ 3017 xfer = ep->endpoint_q[stream_id].curr; 3018 if (xfer == NULL) 3019 return; 3020 3021 /* 3022 * Check if the current transfer is started and then pickup 3023 * the next one, if any. Else wait for next start event due to 3024 * block on failure feature. 3025 */ 3026 if (!xfer->flags_int.bandwidth_reclaimed) 3027 return; 3028 3029 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3030 if (xfer == NULL) { 3031 /* 3032 * In case of enter we have to consider that the 3033 * transfer is queued by the USB core after the enter 3034 * method is called. 3035 */ 3036 xfer = enter_xfer; 3037 3038 if (xfer == NULL) 3039 return; 3040 } 3041 3042 /* try to multi buffer */ 3043 xhci_transfer_insert(xfer); 3044 } 3045 3046 static void 3047 xhci_device_generic_enter(struct usb_xfer *xfer) 3048 { 3049 DPRINTF("\n"); 3050 3051 /* setup TD's and QH */ 3052 xhci_setup_generic_chain(xfer); 3053 3054 xhci_device_generic_multi_enter(xfer->endpoint, 3055 xfer->stream_id, xfer); 3056 } 3057 3058 static void 3059 xhci_device_generic_start(struct usb_xfer *xfer) 3060 { 3061 DPRINTF("\n"); 3062 3063 /* try to insert xfer on HW queue */ 3064 xhci_transfer_insert(xfer); 3065 3066 /* try to multi buffer */ 3067 xhci_device_generic_multi_enter(xfer->endpoint, 3068 xfer->stream_id, NULL); 3069 3070 /* add transfer last on interrupt queue */ 3071 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3072 3073 /* start timeout, if any */ 3074 if (xfer->timeout != 0) 3075 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3076 } 3077 3078 static const struct usb_pipe_methods xhci_device_generic_methods = 3079 { 3080 .open = xhci_device_generic_open, 3081 .close = xhci_device_generic_close, 3082 .enter = xhci_device_generic_enter, 3083 .start = xhci_device_generic_start, 3084 }; 3085 3086 /*------------------------------------------------------------------------* 3087 * xhci root HUB support 3088 *------------------------------------------------------------------------* 3089 * Simulate a hardware HUB by handling all the necessary requests. 3090 *------------------------------------------------------------------------*/ 3091 3092 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3093 3094 static const 3095 struct usb_device_descriptor xhci_devd = 3096 { 3097 .bLength = sizeof(xhci_devd), 3098 .bDescriptorType = UDESC_DEVICE, /* type */ 3099 HSETW(.bcdUSB, 0x0300), /* USB version */ 3100 .bDeviceClass = UDCLASS_HUB, /* class */ 3101 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3102 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3103 .bMaxPacketSize = 9, /* max packet size */ 3104 HSETW(.idVendor, 0x0000), /* vendor */ 3105 HSETW(.idProduct, 0x0000), /* product */ 3106 HSETW(.bcdDevice, 0x0100), /* device version */ 3107 .iManufacturer = 1, 3108 .iProduct = 2, 3109 .iSerialNumber = 0, 3110 .bNumConfigurations = 1, /* # of configurations */ 3111 }; 3112 3113 static const 3114 struct xhci_bos_desc xhci_bosd = { 3115 .bosd = { 3116 .bLength = sizeof(xhci_bosd.bosd), 3117 .bDescriptorType = UDESC_BOS, 3118 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3119 .bNumDeviceCaps = 3, 3120 }, 3121 .usb2extd = { 3122 .bLength = sizeof(xhci_bosd.usb2extd), 3123 .bDescriptorType = 1, 3124 .bDevCapabilityType = 2, 3125 .bmAttributes[0] = 2, 3126 }, 3127 .usbdcd = { 3128 .bLength = sizeof(xhci_bosd.usbdcd), 3129 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3130 .bDevCapabilityType = 3, 3131 .bmAttributes = 0, /* XXX */ 3132 HSETW(.wSpeedsSupported, 0x000C), 3133 .bFunctionalitySupport = 8, 3134 .bU1DevExitLat = 255, /* dummy - not used */ 3135 .wU2DevExitLat = { 0x00, 0x08 }, 3136 }, 3137 .cidd = { 3138 .bLength = sizeof(xhci_bosd.cidd), 3139 .bDescriptorType = 1, 3140 .bDevCapabilityType = 4, 3141 .bReserved = 0, 3142 .bContainerID = 0, /* XXX */ 3143 }, 3144 }; 3145 3146 static const 3147 struct xhci_config_desc xhci_confd = { 3148 .confd = { 3149 .bLength = sizeof(xhci_confd.confd), 3150 .bDescriptorType = UDESC_CONFIG, 3151 .wTotalLength[0] = sizeof(xhci_confd), 3152 .bNumInterface = 1, 3153 .bConfigurationValue = 1, 3154 .iConfiguration = 0, 3155 .bmAttributes = UC_SELF_POWERED, 3156 .bMaxPower = 0 /* max power */ 3157 }, 3158 .ifcd = { 3159 .bLength = sizeof(xhci_confd.ifcd), 3160 .bDescriptorType = UDESC_INTERFACE, 3161 .bNumEndpoints = 1, 3162 .bInterfaceClass = UICLASS_HUB, 3163 .bInterfaceSubClass = UISUBCLASS_HUB, 3164 .bInterfaceProtocol = 0, 3165 }, 3166 .endpd = { 3167 .bLength = sizeof(xhci_confd.endpd), 3168 .bDescriptorType = UDESC_ENDPOINT, 3169 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3170 .bmAttributes = UE_INTERRUPT, 3171 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3172 .bInterval = 255, 3173 }, 3174 .endpcd = { 3175 .bLength = sizeof(xhci_confd.endpcd), 3176 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3177 .bMaxBurst = 0, 3178 .bmAttributes = 0, 3179 }, 3180 }; 3181 3182 static const 3183 struct usb_hub_ss_descriptor xhci_hubd = { 3184 .bLength = sizeof(xhci_hubd), 3185 .bDescriptorType = UDESC_SS_HUB, 3186 }; 3187 3188 static usb_error_t 3189 xhci_roothub_exec(struct usb_device *udev, 3190 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3191 { 3192 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3193 const char *str_ptr; 3194 const void *ptr; 3195 uint32_t port; 3196 uint32_t v; 3197 uint16_t len; 3198 uint16_t i; 3199 uint16_t value; 3200 uint16_t index; 3201 uint8_t j; 3202 usb_error_t err; 3203 3204 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 3205 3206 /* buffer reset */ 3207 ptr = (const void *)&sc->sc_hub_desc; 3208 len = 0; 3209 err = 0; 3210 3211 value = UGETW(req->wValue); 3212 index = UGETW(req->wIndex); 3213 3214 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3215 "wValue=0x%04x wIndex=0x%04x\n", 3216 req->bmRequestType, req->bRequest, 3217 UGETW(req->wLength), value, index); 3218 3219 #define C(x,y) ((x) | ((y) << 8)) 3220 switch (C(req->bRequest, req->bmRequestType)) { 3221 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3222 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3223 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3224 /* 3225 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3226 * for the integrated root hub. 3227 */ 3228 break; 3229 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3230 len = 1; 3231 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3232 break; 3233 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3234 switch (value >> 8) { 3235 case UDESC_DEVICE: 3236 if ((value & 0xff) != 0) { 3237 err = USB_ERR_IOERROR; 3238 goto done; 3239 } 3240 len = sizeof(xhci_devd); 3241 ptr = (const void *)&xhci_devd; 3242 break; 3243 3244 case UDESC_BOS: 3245 if ((value & 0xff) != 0) { 3246 err = USB_ERR_IOERROR; 3247 goto done; 3248 } 3249 len = sizeof(xhci_bosd); 3250 ptr = (const void *)&xhci_bosd; 3251 break; 3252 3253 case UDESC_CONFIG: 3254 if ((value & 0xff) != 0) { 3255 err = USB_ERR_IOERROR; 3256 goto done; 3257 } 3258 len = sizeof(xhci_confd); 3259 ptr = (const void *)&xhci_confd; 3260 break; 3261 3262 case UDESC_STRING: 3263 switch (value & 0xff) { 3264 case 0: /* Language table */ 3265 str_ptr = "\001"; 3266 break; 3267 3268 case 1: /* Vendor */ 3269 str_ptr = sc->sc_vendor; 3270 break; 3271 3272 case 2: /* Product */ 3273 str_ptr = "XHCI root HUB"; 3274 break; 3275 3276 default: 3277 str_ptr = ""; 3278 break; 3279 } 3280 3281 len = usb_make_str_desc( 3282 sc->sc_hub_desc.temp, 3283 sizeof(sc->sc_hub_desc.temp), 3284 str_ptr); 3285 break; 3286 3287 default: 3288 err = USB_ERR_IOERROR; 3289 goto done; 3290 } 3291 break; 3292 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3293 len = 1; 3294 sc->sc_hub_desc.temp[0] = 0; 3295 break; 3296 case C(UR_GET_STATUS, UT_READ_DEVICE): 3297 len = 2; 3298 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3299 break; 3300 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3301 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3302 len = 2; 3303 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3304 break; 3305 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3306 if (value >= XHCI_MAX_DEVICES) { 3307 err = USB_ERR_IOERROR; 3308 goto done; 3309 } 3310 break; 3311 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3312 if (value != 0 && value != 1) { 3313 err = USB_ERR_IOERROR; 3314 goto done; 3315 } 3316 sc->sc_conf = value; 3317 break; 3318 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3319 break; 3320 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3321 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3322 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3323 err = USB_ERR_IOERROR; 3324 goto done; 3325 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3326 break; 3327 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3328 break; 3329 /* Hub requests */ 3330 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3331 break; 3332 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3333 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3334 3335 if ((index < 1) || 3336 (index > sc->sc_noport)) { 3337 err = USB_ERR_IOERROR; 3338 goto done; 3339 } 3340 port = XHCI_PORTSC(index); 3341 3342 v = XREAD4(sc, oper, port); 3343 i = XHCI_PS_PLS_GET(v); 3344 v &= ~XHCI_PS_CLEAR; 3345 3346 switch (value) { 3347 case UHF_C_BH_PORT_RESET: 3348 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3349 break; 3350 case UHF_C_PORT_CONFIG_ERROR: 3351 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3352 break; 3353 case UHF_C_PORT_SUSPEND: 3354 case UHF_C_PORT_LINK_STATE: 3355 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3356 break; 3357 case UHF_C_PORT_CONNECTION: 3358 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3359 break; 3360 case UHF_C_PORT_ENABLE: 3361 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3362 break; 3363 case UHF_C_PORT_OVER_CURRENT: 3364 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3365 break; 3366 case UHF_C_PORT_RESET: 3367 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3368 break; 3369 case UHF_PORT_ENABLE: 3370 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3371 break; 3372 case UHF_PORT_POWER: 3373 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3374 break; 3375 case UHF_PORT_INDICATOR: 3376 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3377 break; 3378 case UHF_PORT_SUSPEND: 3379 3380 /* U3 -> U15 */ 3381 if (i == 3) { 3382 XWRITE4(sc, oper, port, v | 3383 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3384 } 3385 3386 /* wait 20ms for resume sequence to complete */ 3387 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 50); 3388 3389 /* U0 */ 3390 XWRITE4(sc, oper, port, v | 3391 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3392 break; 3393 default: 3394 err = USB_ERR_IOERROR; 3395 goto done; 3396 } 3397 break; 3398 3399 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3400 if ((value & 0xff) != 0) { 3401 err = USB_ERR_IOERROR; 3402 goto done; 3403 } 3404 3405 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3406 3407 sc->sc_hub_desc.hubd = xhci_hubd; 3408 3409 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3410 3411 if (XHCI_HCS0_PPC(v)) 3412 i = UHD_PWR_INDIVIDUAL; 3413 else 3414 i = UHD_PWR_GANGED; 3415 3416 if (XHCI_HCS0_PIND(v)) 3417 i |= UHD_PORT_IND; 3418 3419 i |= UHD_OC_INDIVIDUAL; 3420 3421 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3422 3423 /* see XHCI section 5.4.9: */ 3424 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3425 3426 for (j = 1; j <= sc->sc_noport; j++) { 3427 3428 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3429 if (v & XHCI_PS_DR) { 3430 sc->sc_hub_desc.hubd. 3431 DeviceRemovable[j / 8] |= 1U << (j % 8); 3432 } 3433 } 3434 len = sc->sc_hub_desc.hubd.bLength; 3435 break; 3436 3437 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3438 len = 16; 3439 memset(sc->sc_hub_desc.temp, 0, 16); 3440 break; 3441 3442 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3443 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3444 3445 if ((index < 1) || 3446 (index > sc->sc_noport)) { 3447 err = USB_ERR_IOERROR; 3448 goto done; 3449 } 3450 3451 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3452 3453 DPRINTFN(9, "port status=0x%08x\n", v); 3454 3455 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3456 3457 switch (XHCI_PS_SPEED_GET(v)) { 3458 case 3: 3459 i |= UPS_HIGH_SPEED; 3460 break; 3461 case 2: 3462 i |= UPS_LOW_SPEED; 3463 break; 3464 case 1: 3465 /* FULL speed */ 3466 break; 3467 default: 3468 i |= UPS_OTHER_SPEED; 3469 break; 3470 } 3471 3472 if (v & XHCI_PS_CCS) 3473 i |= UPS_CURRENT_CONNECT_STATUS; 3474 if (v & XHCI_PS_PED) 3475 i |= UPS_PORT_ENABLED; 3476 if (v & XHCI_PS_OCA) 3477 i |= UPS_OVERCURRENT_INDICATOR; 3478 if (v & XHCI_PS_PR) 3479 i |= UPS_RESET; 3480 if (v & XHCI_PS_PP) { 3481 /* 3482 * The USB 3.0 RH is using the 3483 * USB 2.0's power bit 3484 */ 3485 i |= UPS_PORT_POWER; 3486 } 3487 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3488 3489 i = 0; 3490 if (v & XHCI_PS_CSC) 3491 i |= UPS_C_CONNECT_STATUS; 3492 if (v & XHCI_PS_PEC) 3493 i |= UPS_C_PORT_ENABLED; 3494 if (v & XHCI_PS_OCC) 3495 i |= UPS_C_OVERCURRENT_INDICATOR; 3496 if (v & XHCI_PS_WRC) 3497 i |= UPS_C_BH_PORT_RESET; 3498 if (v & XHCI_PS_PRC) 3499 i |= UPS_C_PORT_RESET; 3500 if (v & XHCI_PS_PLC) 3501 i |= UPS_C_PORT_LINK_STATE; 3502 if (v & XHCI_PS_CEC) 3503 i |= UPS_C_PORT_CONFIG_ERROR; 3504 3505 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3506 len = sizeof(sc->sc_hub_desc.ps); 3507 break; 3508 3509 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3510 err = USB_ERR_IOERROR; 3511 goto done; 3512 3513 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3514 break; 3515 3516 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3517 3518 i = index >> 8; 3519 index &= 0x00FF; 3520 3521 if ((index < 1) || 3522 (index > sc->sc_noport)) { 3523 err = USB_ERR_IOERROR; 3524 goto done; 3525 } 3526 3527 port = XHCI_PORTSC(index); 3528 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3529 3530 switch (value) { 3531 case UHF_PORT_U1_TIMEOUT: 3532 if (XHCI_PS_SPEED_GET(v) != 4) { 3533 err = USB_ERR_IOERROR; 3534 goto done; 3535 } 3536 port = XHCI_PORTPMSC(index); 3537 v = XREAD4(sc, oper, port); 3538 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3539 v |= XHCI_PM3_U1TO_SET(i); 3540 XWRITE4(sc, oper, port, v); 3541 break; 3542 case UHF_PORT_U2_TIMEOUT: 3543 if (XHCI_PS_SPEED_GET(v) != 4) { 3544 err = USB_ERR_IOERROR; 3545 goto done; 3546 } 3547 port = XHCI_PORTPMSC(index); 3548 v = XREAD4(sc, oper, port); 3549 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3550 v |= XHCI_PM3_U2TO_SET(i); 3551 XWRITE4(sc, oper, port, v); 3552 break; 3553 case UHF_BH_PORT_RESET: 3554 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3555 break; 3556 case UHF_PORT_LINK_STATE: 3557 XWRITE4(sc, oper, port, v | 3558 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3559 /* 4ms settle time */ 3560 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 250); 3561 break; 3562 case UHF_PORT_ENABLE: 3563 DPRINTFN(3, "set port enable %d\n", index); 3564 break; 3565 case UHF_PORT_SUSPEND: 3566 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3567 j = XHCI_PS_SPEED_GET(v); 3568 if ((j < 1) || (j > 3)) { 3569 /* non-supported speed */ 3570 err = USB_ERR_IOERROR; 3571 goto done; 3572 } 3573 XWRITE4(sc, oper, port, v | 3574 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3575 break; 3576 case UHF_PORT_RESET: 3577 DPRINTFN(6, "reset port %d\n", index); 3578 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3579 break; 3580 case UHF_PORT_POWER: 3581 DPRINTFN(3, "set port power %d\n", index); 3582 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3583 break; 3584 case UHF_PORT_TEST: 3585 DPRINTFN(3, "set port test %d\n", index); 3586 break; 3587 case UHF_PORT_INDICATOR: 3588 DPRINTFN(3, "set port indicator %d\n", index); 3589 3590 v &= ~XHCI_PS_PIC_SET(3); 3591 v |= XHCI_PS_PIC_SET(1); 3592 3593 XWRITE4(sc, oper, port, v); 3594 break; 3595 default: 3596 err = USB_ERR_IOERROR; 3597 goto done; 3598 } 3599 break; 3600 3601 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3602 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3603 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3604 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3605 break; 3606 default: 3607 err = USB_ERR_IOERROR; 3608 goto done; 3609 } 3610 done: 3611 *plength = len; 3612 *pptr = ptr; 3613 return (err); 3614 } 3615 3616 static void 3617 xhci_xfer_setup(struct usb_setup_params *parm) 3618 { 3619 struct usb_page_search page_info; 3620 struct usb_page_cache *pc; 3621 struct xhci_softc *sc; 3622 struct usb_xfer *xfer; 3623 void *last_obj; 3624 uint32_t ntd; 3625 uint32_t n; 3626 3627 sc = XHCI_BUS2SC(parm->udev->bus); 3628 xfer = parm->curr_xfer; 3629 3630 /* 3631 * The proof for the "ntd" formula is illustrated like this: 3632 * 3633 * +------------------------------------+ 3634 * | | 3635 * | |remainder -> | 3636 * | +-----+---+ | 3637 * | | xxx | x | frm 0 | 3638 * | +-----+---++ | 3639 * | | xxx | xx | frm 1 | 3640 * | +-----+----+ | 3641 * | ... | 3642 * +------------------------------------+ 3643 * 3644 * "xxx" means a completely full USB transfer descriptor 3645 * 3646 * "x" and "xx" means a short USB packet 3647 * 3648 * For the remainder of an USB transfer modulo 3649 * "max_data_length" we need two USB transfer descriptors. 3650 * One to transfer the remaining data and one to finalise with 3651 * a zero length packet in case the "force_short_xfer" flag is 3652 * set. We only need two USB transfer descriptors in the case 3653 * where the transfer length of the first one is a factor of 3654 * "max_frame_size". The rest of the needed USB transfer 3655 * descriptors is given by the buffer size divided by the 3656 * maximum data payload. 3657 */ 3658 parm->hc_max_packet_size = 0x400; 3659 parm->hc_max_packet_count = 16 * 3; 3660 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3661 3662 xfer->flags_int.bdma_enable = 1; 3663 3664 usbd_transfer_setup_sub(parm); 3665 3666 if (xfer->flags_int.isochronous_xfr) { 3667 ntd = ((1 * xfer->nframes) 3668 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3669 } else if (xfer->flags_int.control_xfr) { 3670 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3671 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3672 } else { 3673 ntd = ((2 * xfer->nframes) 3674 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3675 } 3676 3677 alloc_dma_set: 3678 3679 if (parm->err) 3680 return; 3681 3682 /* 3683 * Allocate queue heads and transfer descriptors 3684 */ 3685 last_obj = NULL; 3686 3687 if (usbd_transfer_setup_sub_malloc( 3688 parm, &pc, sizeof(struct xhci_td), 3689 XHCI_TD_ALIGN, ntd)) { 3690 parm->err = USB_ERR_NOMEM; 3691 return; 3692 } 3693 if (parm->buf) { 3694 for (n = 0; n != ntd; n++) { 3695 struct xhci_td *td; 3696 3697 usbd_get_page(pc + n, 0, &page_info); 3698 3699 td = page_info.buffer; 3700 3701 /* init TD */ 3702 td->td_self = page_info.physaddr; 3703 td->obj_next = last_obj; 3704 td->page_cache = pc + n; 3705 3706 last_obj = td; 3707 3708 usb_pc_cpu_flush(pc + n); 3709 } 3710 } 3711 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3712 3713 if (!xfer->flags_int.curr_dma_set) { 3714 xfer->flags_int.curr_dma_set = 1; 3715 goto alloc_dma_set; 3716 } 3717 } 3718 3719 static usb_error_t 3720 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3721 { 3722 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3723 struct usb_page_search buf_inp; 3724 struct usb_device *udev; 3725 struct xhci_endpoint_ext *pepext; 3726 struct usb_endpoint_descriptor *edesc; 3727 struct usb_page_cache *pcinp; 3728 usb_error_t err; 3729 usb_stream_t stream_id; 3730 uint8_t index; 3731 uint8_t epno; 3732 3733 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3734 xfer->endpoint->edesc); 3735 3736 udev = xfer->xroot->udev; 3737 index = udev->controller_slot_id; 3738 3739 pcinp = &sc->sc_hw.devs[index].input_pc; 3740 3741 usbd_get_page(pcinp, 0, &buf_inp); 3742 3743 edesc = xfer->endpoint->edesc; 3744 3745 epno = edesc->bEndpointAddress; 3746 stream_id = xfer->stream_id; 3747 3748 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3749 epno |= UE_DIR_IN; 3750 3751 epno = XHCI_EPNO2EPID(epno); 3752 3753 if (epno == 0) 3754 return (USB_ERR_NO_PIPE); /* invalid */ 3755 3756 XHCI_CMD_LOCK(sc); 3757 3758 /* configure endpoint */ 3759 3760 err = xhci_configure_endpoint_by_xfer(xfer); 3761 3762 if (err != 0) { 3763 XHCI_CMD_UNLOCK(sc); 3764 return (err); 3765 } 3766 3767 /* 3768 * Get the endpoint into the stopped state according to the 3769 * endpoint context state diagram in the XHCI specification: 3770 */ 3771 3772 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3773 3774 if (err != 0) 3775 DPRINTF("Could not stop endpoint %u\n", epno); 3776 3777 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3778 3779 if (err != 0) 3780 DPRINTF("Could not reset endpoint %u\n", epno); 3781 3782 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3783 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3784 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3785 stream_id, epno, index); 3786 3787 if (err != 0) 3788 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3789 3790 /* 3791 * Get the endpoint into the running state according to the 3792 * endpoint context state diagram in the XHCI specification: 3793 */ 3794 3795 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3796 3797 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3798 3799 if (err != 0) 3800 DPRINTF("Could not configure endpoint %u\n", epno); 3801 3802 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3803 3804 if (err != 0) 3805 DPRINTF("Could not configure endpoint %u\n", epno); 3806 3807 XHCI_CMD_UNLOCK(sc); 3808 3809 return (0); 3810 } 3811 3812 static void 3813 xhci_xfer_unsetup(struct usb_xfer *xfer) 3814 { 3815 return; 3816 } 3817 3818 static void 3819 xhci_start_dma_delay(struct usb_xfer *xfer) 3820 { 3821 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3822 3823 /* put transfer on interrupt queue (again) */ 3824 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3825 3826 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3827 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3828 } 3829 3830 static void 3831 xhci_configure_msg(struct usb_proc_msg *pm) 3832 { 3833 struct xhci_softc *sc; 3834 struct xhci_endpoint_ext *pepext; 3835 struct usb_xfer *xfer; 3836 3837 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3838 3839 restart: 3840 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3841 3842 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3843 xfer->endpoint->edesc); 3844 3845 if ((pepext->trb_halted != 0) || 3846 (pepext->trb_running == 0)) { 3847 3848 uint16_t i; 3849 3850 /* clear halted and running */ 3851 pepext->trb_halted = 0; 3852 pepext->trb_running = 0; 3853 3854 /* nuke remaining buffered transfers */ 3855 3856 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3857 XHCI_MAX_STREAMS); i++) { 3858 /* 3859 * NOTE: We need to use the timeout 3860 * error code here else existing 3861 * isochronous clients can get 3862 * confused: 3863 */ 3864 if (pepext->xfer[i] != NULL) { 3865 xhci_device_done(pepext->xfer[i], 3866 USB_ERR_TIMEOUT); 3867 } 3868 } 3869 3870 /* 3871 * NOTE: The USB transfer cannot vanish in 3872 * this state! 3873 */ 3874 3875 USB_BUS_UNLOCK(&sc->sc_bus); 3876 3877 xhci_configure_reset_endpoint(xfer); 3878 3879 USB_BUS_LOCK(&sc->sc_bus); 3880 3881 /* check if halted is still cleared */ 3882 if (pepext->trb_halted == 0) { 3883 pepext->trb_running = 1; 3884 memset(pepext->trb_index, 0, 3885 sizeof(pepext->trb_index)); 3886 } 3887 goto restart; 3888 } 3889 3890 if (xfer->flags_int.did_dma_delay) { 3891 3892 /* remove transfer from interrupt queue (again) */ 3893 usbd_transfer_dequeue(xfer); 3894 3895 /* we are finally done */ 3896 usb_dma_delay_done_cb(xfer); 3897 3898 /* queue changed - restart */ 3899 goto restart; 3900 } 3901 } 3902 3903 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3904 3905 /* try to insert xfer on HW queue */ 3906 xhci_transfer_insert(xfer); 3907 3908 /* try to multi buffer */ 3909 xhci_device_generic_multi_enter(xfer->endpoint, 3910 xfer->stream_id, NULL); 3911 } 3912 } 3913 3914 static void 3915 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3916 struct usb_endpoint *ep) 3917 { 3918 struct xhci_endpoint_ext *pepext; 3919 3920 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3921 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3922 3923 if (udev->parent_hub == NULL) { 3924 /* root HUB has special endpoint handling */ 3925 return; 3926 } 3927 3928 ep->methods = &xhci_device_generic_methods; 3929 3930 pepext = xhci_get_endpoint_ext(udev, edesc); 3931 3932 USB_BUS_LOCK(udev->bus); 3933 pepext->trb_halted = 1; 3934 pepext->trb_running = 0; 3935 USB_BUS_UNLOCK(udev->bus); 3936 } 3937 3938 static void 3939 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3940 { 3941 3942 } 3943 3944 static void 3945 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3946 { 3947 struct xhci_endpoint_ext *pepext; 3948 3949 DPRINTF("\n"); 3950 3951 if (udev->flags.usb_mode != USB_MODE_HOST) { 3952 /* not supported */ 3953 return; 3954 } 3955 if (udev->parent_hub == NULL) { 3956 /* root HUB has special endpoint handling */ 3957 return; 3958 } 3959 3960 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3961 3962 USB_BUS_LOCK(udev->bus); 3963 pepext->trb_halted = 1; 3964 pepext->trb_running = 0; 3965 USB_BUS_UNLOCK(udev->bus); 3966 } 3967 3968 static usb_error_t 3969 xhci_device_init(struct usb_device *udev) 3970 { 3971 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3972 usb_error_t err; 3973 uint8_t temp; 3974 3975 /* no init for root HUB */ 3976 if (udev->parent_hub == NULL) 3977 return (0); 3978 3979 XHCI_CMD_LOCK(sc); 3980 3981 /* set invalid default */ 3982 3983 udev->controller_slot_id = sc->sc_noslot + 1; 3984 3985 /* try to get a new slot ID from the XHCI */ 3986 3987 err = xhci_cmd_enable_slot(sc, &temp); 3988 3989 if (err) { 3990 XHCI_CMD_UNLOCK(sc); 3991 return (err); 3992 } 3993 3994 if (temp > sc->sc_noslot) { 3995 XHCI_CMD_UNLOCK(sc); 3996 return (USB_ERR_BAD_ADDRESS); 3997 } 3998 3999 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4000 DPRINTF("slot %u already allocated.\n", temp); 4001 XHCI_CMD_UNLOCK(sc); 4002 return (USB_ERR_BAD_ADDRESS); 4003 } 4004 4005 /* store slot ID for later reference */ 4006 4007 udev->controller_slot_id = temp; 4008 4009 /* reset data structure */ 4010 4011 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4012 4013 /* set mark slot allocated */ 4014 4015 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4016 4017 err = xhci_alloc_device_ext(udev); 4018 4019 XHCI_CMD_UNLOCK(sc); 4020 4021 /* get device into default state */ 4022 4023 if (err == 0) 4024 err = xhci_set_address(udev, NULL, 0); 4025 4026 return (err); 4027 } 4028 4029 static void 4030 xhci_device_uninit(struct usb_device *udev) 4031 { 4032 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4033 uint8_t index; 4034 4035 /* no init for root HUB */ 4036 if (udev->parent_hub == NULL) 4037 return; 4038 4039 XHCI_CMD_LOCK(sc); 4040 4041 index = udev->controller_slot_id; 4042 4043 if (index <= sc->sc_noslot) { 4044 xhci_cmd_disable_slot(sc, index); 4045 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4046 4047 /* free device extension */ 4048 xhci_free_device_ext(udev); 4049 } 4050 4051 XHCI_CMD_UNLOCK(sc); 4052 } 4053 4054 static void 4055 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4056 { 4057 /* 4058 * Wait until the hardware has finished any possible use of 4059 * the transfer descriptor(s) 4060 */ 4061 *pus = 2048; /* microseconds */ 4062 } 4063 4064 static void 4065 xhci_device_resume(struct usb_device *udev) 4066 { 4067 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4068 uint8_t index; 4069 uint8_t n; 4070 uint8_t p; 4071 4072 DPRINTF("\n"); 4073 4074 /* check for root HUB */ 4075 if (udev->parent_hub == NULL) 4076 return; 4077 4078 index = udev->controller_slot_id; 4079 4080 XHCI_CMD_LOCK(sc); 4081 4082 /* blindly resume all endpoints */ 4083 4084 USB_BUS_LOCK(udev->bus); 4085 4086 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4087 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4088 XWRITE4(sc, door, XHCI_DOORBELL(index), 4089 n | XHCI_DB_SID_SET(p)); 4090 } 4091 } 4092 4093 USB_BUS_UNLOCK(udev->bus); 4094 4095 XHCI_CMD_UNLOCK(sc); 4096 } 4097 4098 static void 4099 xhci_device_suspend(struct usb_device *udev) 4100 { 4101 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4102 uint8_t index; 4103 uint8_t n; 4104 usb_error_t err; 4105 4106 DPRINTF("\n"); 4107 4108 /* check for root HUB */ 4109 if (udev->parent_hub == NULL) 4110 return; 4111 4112 index = udev->controller_slot_id; 4113 4114 XHCI_CMD_LOCK(sc); 4115 4116 /* blindly suspend all endpoints */ 4117 4118 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4119 err = xhci_cmd_stop_ep(sc, 1, n, index); 4120 if (err != 0) { 4121 DPRINTF("Failed to suspend endpoint " 4122 "%u on slot %u (ignored).\n", n, index); 4123 } 4124 } 4125 4126 XHCI_CMD_UNLOCK(sc); 4127 } 4128 4129 static void 4130 xhci_set_hw_power(struct usb_bus *bus) 4131 { 4132 DPRINTF("\n"); 4133 } 4134 4135 static void 4136 xhci_device_state_change(struct usb_device *udev) 4137 { 4138 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4139 struct usb_page_search buf_inp; 4140 usb_error_t err; 4141 uint8_t index; 4142 4143 /* check for root HUB */ 4144 if (udev->parent_hub == NULL) 4145 return; 4146 4147 index = udev->controller_slot_id; 4148 4149 DPRINTF("\n"); 4150 4151 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4152 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4153 &sc->sc_hw.devs[index].tt); 4154 if (err != 0) 4155 sc->sc_hw.devs[index].nports = 0; 4156 } 4157 4158 XHCI_CMD_LOCK(sc); 4159 4160 switch (usb_get_device_state(udev)) { 4161 case USB_STATE_POWERED: 4162 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4163 break; 4164 4165 /* set default state */ 4166 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4167 4168 /* reset number of contexts */ 4169 sc->sc_hw.devs[index].context_num = 0; 4170 4171 err = xhci_cmd_reset_dev(sc, index); 4172 4173 if (err != 0) { 4174 DPRINTF("Device reset failed " 4175 "for slot %u.\n", index); 4176 } 4177 break; 4178 4179 case USB_STATE_ADDRESSED: 4180 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4181 break; 4182 4183 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4184 4185 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4186 4187 if (err) { 4188 DPRINTF("Failed to deconfigure " 4189 "slot %u.\n", index); 4190 } 4191 break; 4192 4193 case USB_STATE_CONFIGURED: 4194 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4195 break; 4196 4197 /* set configured state */ 4198 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4199 4200 /* reset number of contexts */ 4201 sc->sc_hw.devs[index].context_num = 0; 4202 4203 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4204 4205 xhci_configure_mask(udev, 3, 0); 4206 4207 err = xhci_configure_device(udev); 4208 if (err != 0) { 4209 DPRINTF("Could not configure device " 4210 "at slot %u.\n", index); 4211 } 4212 4213 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4214 if (err != 0) { 4215 DPRINTF("Could not evaluate device " 4216 "context at slot %u.\n", index); 4217 } 4218 break; 4219 4220 default: 4221 break; 4222 } 4223 XHCI_CMD_UNLOCK(sc); 4224 } 4225 4226 static usb_error_t 4227 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4228 uint8_t ep_mode) 4229 { 4230 switch (ep_mode) { 4231 case USB_EP_MODE_DEFAULT: 4232 return (0); 4233 case USB_EP_MODE_STREAMS: 4234 if (xhcistreams == 0 || 4235 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4236 udev->speed != USB_SPEED_SUPER) 4237 return (USB_ERR_INVAL); 4238 return (0); 4239 default: 4240 return (USB_ERR_INVAL); 4241 } 4242 } 4243 4244 static const struct usb_bus_methods xhci_bus_methods = { 4245 .endpoint_init = xhci_ep_init, 4246 .endpoint_uninit = xhci_ep_uninit, 4247 .xfer_setup = xhci_xfer_setup, 4248 .xfer_unsetup = xhci_xfer_unsetup, 4249 .get_dma_delay = xhci_get_dma_delay, 4250 .device_init = xhci_device_init, 4251 .device_uninit = xhci_device_uninit, 4252 .device_resume = xhci_device_resume, 4253 .device_suspend = xhci_device_suspend, 4254 .set_hw_power = xhci_set_hw_power, 4255 .roothub_exec = xhci_roothub_exec, 4256 .xfer_poll = xhci_do_poll, 4257 .start_dma_delay = xhci_start_dma_delay, 4258 .set_address = xhci_set_address, 4259 .clear_stall = xhci_ep_clear_stall, 4260 .device_state_change = xhci_device_state_change, 4261 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4262 .set_endpoint_mode = xhci_set_endpoint_mode, 4263 }; 4264