1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _XHCI_H_ 29 #define _XHCI_H_ 30 31 #define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 32 #define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */ 33 #define XHCI_MAX_SCRATCHPADS 32 34 #define XHCI_MAX_EVENTS (16 * 13) 35 #define XHCI_MAX_COMMANDS (16 * 1) 36 #define XHCI_MAX_RSEG 1 37 #define XHCI_MAX_TRANSFERS 4 38 39 #define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */ 40 #define XHCI_DEV_CTX_ALIGN 64 /* bytes */ 41 #define XHCI_INPUT_CTX_ALIGN 64 /* bytes */ 42 #define XHCI_SLOT_CTX_ALIGN 32 /* bytes */ 43 #define XHCI_ENDP_CTX_ALIGN 32 /* bytes */ 44 #define XHCI_STREAM_CTX_ALIGN 16 /* bytes */ 45 #define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */ 46 #define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */ 47 #define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */ 48 #define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */ 49 #define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE 50 #define XHCI_TRB_ALIGN 16 /* bytes */ 51 #define XHCI_TD_ALIGN 64 /* bytes */ 52 #define XHCI_PAGE_SIZE 4096 /* bytes */ 53 54 struct xhci_dev_ctx_addr { 55 volatile uint64_t qwBaaDevCtxAddr[USB_MAX_DEVICES + 1]; 56 struct { 57 volatile uint64_t dummy; 58 } __aligned(64) padding; 59 volatile uint64_t qwSpBufPtr[XHCI_MAX_SCRATCHPADS]; 60 }; 61 62 #define XHCI_EPNO2EPID(x) \ 63 ((((x) & UE_DIR_IN) ? 1 : 0) | (2 * ((x) & UE_ADDR))) 64 65 struct xhci_slot_ctx { 66 volatile uint32_t dwSctx0; 67 #define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF) 68 #define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF) 69 #define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20) 70 #define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF) 71 #define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25) 72 #define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1) 73 #define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26) 74 #define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1) 75 #define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27) 76 #define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F) 77 volatile uint32_t dwSctx1; 78 #define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF) 79 #define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF) 80 #define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16) 81 #define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) 82 #define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24) 83 #define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) 84 volatile uint32_t dwSctx2; 85 #define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF) 86 #define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF) 87 #define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8) 88 #define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) 89 #define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16) 90 #define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3) 91 #define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22) 92 #define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF) 93 volatile uint32_t dwSctx3; 94 #define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF) 95 #define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF) 96 #define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27) 97 #define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) 98 volatile uint32_t dwSctx4; 99 volatile uint32_t dwSctx5; 100 volatile uint32_t dwSctx6; 101 volatile uint32_t dwSctx7; 102 }; 103 104 struct xhci_endp_ctx { 105 volatile uint32_t dwEpCtx0; 106 #define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7) 107 #define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7) 108 #define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8) 109 #define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3) 110 #define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10) 111 #define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F) 112 #define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15) 113 #define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1) 114 #define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16) 115 #define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF) 116 volatile uint32_t dwEpCtx1; 117 #define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1) 118 #define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3) 119 #define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3) 120 #define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) 121 #define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7) 122 #define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1) 123 #define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8) 124 #define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF) 125 #define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16) 126 #define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF) 127 volatile uint64_t qwEpCtx2; 128 #define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1) 129 #define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1) 130 #define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 131 volatile uint32_t dwEpCtx4; 132 #define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF) 133 #define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF) 134 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16) 135 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) 136 volatile uint32_t dwEpCtx5; 137 volatile uint32_t dwEpCtx6; 138 volatile uint32_t dwEpCtx7; 139 }; 140 141 struct xhci_input_ctx { 142 #define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU 143 volatile uint32_t dwInCtx0; 144 #define XHCI_INCTX_0_DROP_MASK(n) (1U << (n)) 145 volatile uint32_t dwInCtx1; 146 #define XHCI_INCTX_1_ADD_MASK(n) (1U << (n)) 147 volatile uint32_t dwInCtx2; 148 volatile uint32_t dwInCtx3; 149 volatile uint32_t dwInCtx4; 150 volatile uint32_t dwInCtx5; 151 volatile uint32_t dwInCtx6; 152 volatile uint32_t dwInCtx7; 153 }; 154 155 struct xhci_input_dev_ctx { 156 struct xhci_input_ctx ctx_input; 157 struct xhci_slot_ctx ctx_slot; 158 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 159 }; 160 161 struct xhci_dev_ctx { 162 struct xhci_slot_ctx ctx_slot; 163 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 164 } __aligned(XHCI_DEV_CTX_ALIGN); 165 166 struct xhci_stream_ctx { 167 volatile uint64_t qwSctx0; 168 #define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1) 169 #define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1) 170 #define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1) 171 #define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7) 172 #define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0 173 #define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1 174 #define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2 175 #define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3 176 #define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4 177 #define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5 178 #define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6 179 #define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7 180 #define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 181 volatile uint32_t dwSctx2; 182 volatile uint32_t dwSctx3; 183 }; 184 185 struct xhci_trb { 186 volatile uint64_t qwTrb0; 187 #define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48) 188 volatile uint32_t dwTrb2; 189 #define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF) 190 #define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24) 191 #define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F) 192 #define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17) 193 #define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF) 194 #define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF) 195 #define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) 196 #define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF) 197 #define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) 198 #define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22) 199 #define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF) 200 #define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16) 201 202 volatile uint32_t dwTrb3; 203 #define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) 204 #define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10) 205 #define XHCI_TRB_3_CYCLE_BIT (1U << 0) 206 #define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */ 207 #define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */ 208 #define XHCI_TRB_3_ISP_BIT (1U << 2) 209 #define XHCI_TRB_3_NSNOOP_BIT (1U << 3) 210 #define XHCI_TRB_3_CHAIN_BIT (1U << 4) 211 #define XHCI_TRB_3_IOC_BIT (1U << 5) 212 #define XHCI_TRB_3_IDT_BIT (1U << 6) 213 #define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3) 214 #define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7) 215 #define XHCI_TRB_3_BEI_BIT (1U << 9) 216 #define XHCI_TRB_3_DCEP_BIT (1U << 9) 217 #define XHCI_TRB_3_PRSV_BIT (1U << 9) 218 #define XHCI_TRB_3_BSR_BIT (1U << 9) 219 #define XHCI_TRB_3_TRT_MASK (3U << 16) 220 #define XHCI_TRB_3_TRT_NONE (0U << 16) 221 #define XHCI_TRB_3_TRT_OUT (2U << 16) 222 #define XHCI_TRB_3_TRT_IN (3U << 16) 223 #define XHCI_TRB_3_DIR_IN (1U << 16) 224 #define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF) 225 #define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16) 226 #define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F) 227 #define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16) 228 #define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF) 229 #define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20) 230 #define XHCI_TRB_3_ISO_SIA_BIT (1U << 31) 231 #define XHCI_TRB_3_SUSP_EP_BIT (1U << 23) 232 #define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF) 233 #define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24) 234 235 /* Commands */ 236 #define XHCI_TRB_TYPE_RESERVED 0x00 237 #define XHCI_TRB_TYPE_NORMAL 0x01 238 #define XHCI_TRB_TYPE_SETUP_STAGE 0x02 239 #define XHCI_TRB_TYPE_DATA_STAGE 0x03 240 #define XHCI_TRB_TYPE_STATUS_STAGE 0x04 241 #define XHCI_TRB_TYPE_ISOCH 0x05 242 #define XHCI_TRB_TYPE_LINK 0x06 243 #define XHCI_TRB_TYPE_EVENT_DATA 0x07 244 #define XHCI_TRB_TYPE_NOOP 0x08 245 #define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 246 #define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A 247 #define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B 248 #define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C 249 #define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D 250 #define XHCI_TRB_TYPE_RESET_EP 0x0E 251 #define XHCI_TRB_TYPE_STOP_EP 0x0F 252 #define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 253 #define XHCI_TRB_TYPE_RESET_DEVICE 0x11 254 #define XHCI_TRB_TYPE_FORCE_EVENT 0x12 255 #define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 256 #define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 257 #define XHCI_TRB_TYPE_GET_PORT_BW 0x15 258 #define XHCI_TRB_TYPE_FORCE_HEADER 0x16 259 #define XHCI_TRB_TYPE_NOOP_CMD 0x17 260 261 /* Events */ 262 #define XHCI_TRB_EVENT_TRANSFER 0x20 263 #define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 264 #define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 265 #define XHCI_TRB_EVENT_BW_REQUEST 0x23 266 #define XHCI_TRB_EVENT_DOORBELL 0x24 267 #define XHCI_TRB_EVENT_HOST_CTRL 0x25 268 #define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 269 #define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 270 271 /* Error codes */ 272 #define XHCI_TRB_ERROR_INVALID 0x00 273 #define XHCI_TRB_ERROR_SUCCESS 0x01 274 #define XHCI_TRB_ERROR_DATA_BUF 0x02 275 #define XHCI_TRB_ERROR_BABBLE 0x03 276 #define XHCI_TRB_ERROR_XACT 0x04 277 #define XHCI_TRB_ERROR_TRB 0x05 278 #define XHCI_TRB_ERROR_STALL 0x06 279 #define XHCI_TRB_ERROR_RESOURCE 0x07 280 #define XHCI_TRB_ERROR_BANDWIDTH 0x08 281 #define XHCI_TRB_ERROR_NO_SLOTS 0x09 282 #define XHCI_TRB_ERROR_STREAM_TYPE 0x0A 283 #define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B 284 #define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C 285 #define XHCI_TRB_ERROR_SHORT_PKT 0x0D 286 #define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E 287 #define XHCI_TRB_ERROR_RING_OVERRUN 0x0F 288 #define XHCI_TRB_ERROR_VF_RING_FULL 0x10 289 #define XHCI_TRB_ERROR_PARAMETER 0x11 290 #define XHCI_TRB_ERROR_BW_OVERRUN 0x12 291 #define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 292 #define XHCI_TRB_ERROR_NO_PING_RESP 0x14 293 #define XHCI_TRB_ERROR_EV_RING_FULL 0x15 294 #define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 295 #define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 296 #define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 297 #define XHCI_TRB_ERROR_CMD_ABORTED 0x19 298 #define XHCI_TRB_ERROR_STOPPED 0x1A 299 #define XHCI_TRB_ERROR_LENGTH 0x1B 300 #define XHCI_TRB_ERROR_BAD_MELAT 0x1D 301 #define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F 302 #define XHCI_TRB_ERROR_EVENT_LOST 0x20 303 #define XHCI_TRB_ERROR_UNDEFINED 0x21 304 #define XHCI_TRB_ERROR_INVALID_SID 0x22 305 #define XHCI_TRB_ERROR_SEC_BW 0x23 306 #define XHCI_TRB_ERROR_SPLIT_XACT 0x24 307 } __aligned(4); 308 309 struct xhci_dev_endpoint_trbs { 310 struct xhci_trb trb[XHCI_MAX_ENDPOINTS][XHCI_MAX_TRANSFERS]; 311 }; 312 313 #define XHCI_TD_PAGE_NBUF 17 /* units, room enough for 64Kbytes */ 314 #define XHCI_TD_PAGE_SIZE 4096 /* bytes */ 315 #define XHCI_TD_PAYLOAD_MAX (XHCI_TD_PAGE_SIZE * (XHCI_TD_PAGE_NBUF - 1)) 316 317 struct xhci_td { 318 struct xhci_trb td_trb[XHCI_TD_PAGE_NBUF + 1]; 319 320 /* 321 * Extra information needed: 322 */ 323 uint64_t td_self; 324 struct xhci_td *next; 325 struct xhci_td *alt_next; 326 struct xhci_td *obj_next; 327 struct usb_page_cache *page_cache; 328 uint32_t len; 329 uint32_t remainder; 330 uint8_t ntrb; 331 uint8_t status; 332 } __aligned(XHCI_TRB_ALIGN); 333 334 struct xhci_command { 335 struct xhci_trb trb; 336 TAILQ_ENTRY(xhci_command) entry; 337 }; 338 339 struct xhci_event_ring_seg { 340 volatile uint64_t qwEvrsTablePtr; 341 volatile uint32_t dwEvrsTableSize; 342 volatile uint32_t dwEvrsReserved; 343 }; 344 345 struct xhci_hw_root { 346 struct xhci_event_ring_seg hwr_ring_seg[XHCI_MAX_RSEG]; 347 struct { 348 volatile uint64_t dummy; 349 } __aligned(64) padding; 350 struct xhci_trb hwr_events[XHCI_MAX_EVENTS]; 351 struct xhci_trb hwr_commands[XHCI_MAX_COMMANDS]; 352 }; 353 354 struct xhci_endpoint_ext { 355 struct xhci_trb *trb; 356 struct usb_xfer *xfer[XHCI_MAX_TRANSFERS - 1]; 357 struct usb_page_cache *page_cache; 358 uint64_t physaddr; 359 uint8_t trb_used; 360 uint8_t trb_index; 361 uint8_t trb_halted; 362 uint8_t trb_running; 363 }; 364 365 enum { 366 XHCI_ST_DISABLED, 367 XHCI_ST_ENABLED, 368 XHCI_ST_DEFAULT, 369 XHCI_ST_ADDRESSED, 370 XHCI_ST_CONFIGURED, 371 XHCI_ST_MAX 372 }; 373 374 struct xhci_hw_dev { 375 struct usb_page_cache device_pc; 376 struct usb_page_cache input_pc; 377 struct usb_page_cache endpoint_pc; 378 379 struct usb_page device_pg; 380 struct usb_page input_pg; 381 struct usb_page endpoint_pg; 382 383 struct xhci_endpoint_ext endp[XHCI_MAX_ENDPOINTS]; 384 385 uint8_t state; 386 uint8_t nports; 387 uint8_t tt; 388 uint8_t reserved; 389 }; 390 391 struct xhci_hw_softc { 392 struct usb_page_cache root_pc; 393 struct usb_page_cache ctx_pc; 394 struct usb_page_cache scratch_pc[XHCI_MAX_SCRATCHPADS]; 395 396 struct usb_page root_pg; 397 struct usb_page ctx_pg; 398 struct usb_page scratch_pg[XHCI_MAX_SCRATCHPADS]; 399 400 struct xhci_hw_dev devs[XHCI_MAX_DEVICES + 1]; 401 }; 402 403 struct xhci_config_desc { 404 struct usb_config_descriptor confd; 405 struct usb_interface_descriptor ifcd; 406 struct usb_endpoint_descriptor endpd; 407 struct usb_endpoint_ss_comp_descriptor endpcd; 408 } __packed; 409 410 struct xhci_bos_desc { 411 struct usb_bos_descriptor bosd; 412 struct usb_devcap_usb2ext_descriptor usb2extd; 413 struct usb_devcap_ss_descriptor usbdcd; 414 struct usb_devcap_container_id_descriptor cidd; 415 } __packed; 416 417 union xhci_hub_desc { 418 struct usb_status stat; 419 struct usb_port_status ps; 420 struct usb_hub_ss_descriptor hubd; 421 uint8_t temp[128]; 422 }; 423 424 struct xhci_softc { 425 struct xhci_hw_softc sc_hw; 426 /* base device */ 427 struct usb_bus sc_bus; 428 /* configure process */ 429 struct usb_process sc_config_proc; 430 struct usb_bus_msg sc_config_msg[2]; 431 432 union xhci_hub_desc sc_hub_desc; 433 434 struct cv sc_cmd_cv; 435 struct lock sc_cmd_lock; 436 437 struct usb_device *sc_devices[XHCI_MAX_DEVICES]; 438 struct resource *sc_io_res; 439 struct resource *sc_irq_res; 440 441 void *sc_intr_hdl; 442 bus_size_t sc_io_size; 443 bus_space_tag_t sc_io_tag; 444 bus_space_handle_t sc_io_hdl; 445 /* last pending command address */ 446 uint64_t sc_cmd_addr; 447 /* result of command */ 448 uint32_t sc_cmd_result[2]; 449 /* copy of cmd register */ 450 uint32_t sc_cmd; 451 /* worst case exit latency */ 452 uint32_t sc_exit_lat_max; 453 454 /* offset to operational registers */ 455 uint32_t sc_oper_off; 456 /* offset to capability registers */ 457 uint32_t sc_capa_off; 458 /* offset to runtime registers */ 459 uint32_t sc_runt_off; 460 /* offset to doorbell registers */ 461 uint32_t sc_door_off; 462 463 /* chip specific */ 464 uint16_t sc_erst_max; 465 uint16_t sc_event_idx; 466 uint16_t sc_command_idx; 467 468 uint8_t sc_event_ccs; 469 uint8_t sc_command_ccs; 470 /* number of XHCI device slots */ 471 uint8_t sc_noslot; 472 /* number of ports on root HUB */ 473 uint8_t sc_noport; 474 /* number of scratch pages */ 475 uint8_t sc_noscratch; 476 /* root HUB device configuration */ 477 uint8_t sc_conf; 478 uint8_t sc_hub_idata[2]; 479 480 /* size of context */ 481 uint8_t sc_ctx_is_64_byte; 482 483 /* vendor string for root HUB */ 484 char sc_vendor[16]; 485 }; 486 487 #define XHCI_CMD_LOCK(sc) lockmgr(&(sc)->sc_cmd_lock, LK_EXCLUSIVE) 488 #define XHCI_CMD_UNLOCK(sc) lockmgr(&(sc)->sc_cmd_lock, LK_RELEASE) 489 #define XHCI_CMD_ASSERT_LOCKED(sc) KKASSERT(lockstatus(&(sc)->sc_cmd_lock, curthread) == LK_EXCLUSIVE) 490 491 /* prototypes */ 492 493 usb_error_t xhci_halt_controller(struct xhci_softc *); 494 usb_error_t xhci_init(struct xhci_softc *, device_t); 495 usb_error_t xhci_start_controller(struct xhci_softc *); 496 void xhci_interrupt(struct xhci_softc *); 497 void xhci_uninit(struct xhci_softc *); 498 499 #endif /* _XHCI_H_ */ 500