1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/stdint.h> 27 #include <sys/param.h> 28 #include <sys/queue.h> 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/bus.h> 33 #include <sys/module.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/condvar.h> 37 #include <sys/sysctl.h> 38 #include <sys/unistd.h> 39 #include <sys/callout.h> 40 #include <sys/malloc.h> 41 #include <sys/priv.h> 42 43 #include <bus/u4b/usb.h> 44 #include <bus/u4b/usbdi.h> 45 46 #include <bus/u4b/usb_core.h> 47 #include <bus/u4b/usb_busdma.h> 48 #include <bus/u4b/usb_process.h> 49 #include <bus/u4b/usb_util.h> 50 51 #include <bus/u4b/usb_controller.h> 52 #include <bus/u4b/usb_bus.h> 53 #include <bus/u4b/usb_pci.h> 54 #include <bus/u4b/controller/xhci.h> 55 #include <bus/u4b/controller/xhcireg.h> 56 #include "usb_if.h" 57 58 static device_probe_t xhci_pci_probe; 59 static device_attach_t xhci_pci_attach; 60 static device_detach_t xhci_pci_detach; 61 static usb_take_controller_t xhci_pci_take_controller; 62 63 static device_method_t xhci_device_methods[] = { 64 /* device interface */ 65 DEVMETHOD(device_probe, xhci_pci_probe), 66 DEVMETHOD(device_attach, xhci_pci_attach), 67 DEVMETHOD(device_detach, xhci_pci_detach), 68 DEVMETHOD(device_suspend, bus_generic_suspend), 69 DEVMETHOD(device_resume, bus_generic_resume), 70 DEVMETHOD(device_shutdown, bus_generic_shutdown), 71 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 72 73 DEVMETHOD_END 74 }; 75 76 static driver_t xhci_driver = { 77 .name = "xhci", 78 .methods = xhci_device_methods, 79 .size = sizeof(struct xhci_softc), 80 }; 81 82 static devclass_t xhci_devclass; 83 84 DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL); 85 MODULE_DEPEND(xhci, usb, 1, 1, 1); 86 87 88 static const char * 89 xhci_pci_match(device_t self) 90 { 91 uint32_t device_id = pci_get_devid(self); 92 93 switch (device_id) { 94 case 0x70231b6f: 95 return ("Etron EJ168 USB 3.0 Host Controller"); 96 case 0x01941033: 97 return ("NEC uPD720200 USB 3.0 controller"); 98 case 0x1e318086: 99 return ("Intel Panther Point USB 3.0 controller"); 100 case 0x8c318086: 101 return ("Intel Lynx Point USB 3.0 controller"); 102 default: 103 break; 104 } 105 if ((pci_get_class(self) == PCIC_SERIALBUS) 106 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 107 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 108 return ("XHCI (generic) USB 3.0 controller"); 109 } 110 return (NULL); /* dunno */ 111 } 112 113 static int 114 xhci_pci_probe(device_t self) 115 { 116 const char *desc = xhci_pci_match(self); 117 118 if (desc) { 119 device_set_desc(self, desc); 120 return (0); 121 } else { 122 return (ENXIO); 123 } 124 } 125 126 static int 127 xhci_pci_attach(device_t self) 128 { 129 struct xhci_softc *sc = device_get_softc(self); 130 int err; 131 int rid; 132 133 /* XXX check for 64-bit capability */ 134 135 if (xhci_init(sc, self)) { 136 device_printf(self, "Could not initialize softc\n"); 137 goto error; 138 } 139 140 pci_enable_busmaster(self); 141 142 rid = PCI_XHCI_CBMEM; 143 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 144 RF_ACTIVE); 145 if (!sc->sc_io_res) { 146 device_printf(self, "Could not map memory\n"); 147 goto error; 148 } 149 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 150 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 151 sc->sc_io_size = rman_get_size(sc->sc_io_res); 152 153 rid = 0; 154 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 155 RF_SHAREABLE | RF_ACTIVE); 156 if (sc->sc_irq_res == NULL) { 157 device_printf(self, "Could not allocate IRQ\n"); 158 goto error; 159 } 160 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 161 if (sc->sc_bus.bdev == NULL) { 162 device_printf(self, "Could not add USB device\n"); 163 goto error; 164 } 165 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 166 167 ksprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self)); 168 169 err = bus_setup_intr(self, sc->sc_irq_res, INTR_MPSAFE, 170 (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl, NULL); 171 172 if (err) { 173 device_printf(self, "Could not setup IRQ, err=%d\n", err); 174 sc->sc_intr_hdl = NULL; 175 goto error; 176 } 177 xhci_pci_take_controller(self); 178 179 err = xhci_halt_controller(sc); 180 181 if (err == 0) 182 err = xhci_start_controller(sc); 183 184 if (err == 0) 185 err = device_probe_and_attach(sc->sc_bus.bdev); 186 187 if (err) { 188 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err); 189 goto error; 190 } 191 return (0); 192 193 error: 194 xhci_pci_detach(self); 195 return (ENXIO); 196 } 197 198 static int 199 xhci_pci_detach(device_t self) 200 { 201 struct xhci_softc *sc = device_get_softc(self); 202 device_t bdev; 203 204 if (sc->sc_bus.bdev != NULL) { 205 bdev = sc->sc_bus.bdev; 206 device_detach(bdev); 207 device_delete_child(self, bdev); 208 } 209 /* during module unload there are lots of children leftover */ 210 device_delete_children(self); 211 212 pci_disable_busmaster(self); 213 214 if (sc->sc_irq_res && sc->sc_intr_hdl) { 215 216 xhci_halt_controller(sc); 217 218 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 219 sc->sc_intr_hdl = NULL; 220 } 221 if (sc->sc_irq_res) { 222 bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res); 223 sc->sc_irq_res = NULL; 224 } 225 if (sc->sc_io_res) { 226 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 227 sc->sc_io_res); 228 sc->sc_io_res = NULL; 229 } 230 231 xhci_uninit(sc); 232 233 return (0); 234 } 235 236 static int 237 xhci_pci_take_controller(device_t self) 238 { 239 struct xhci_softc *sc = device_get_softc(self); 240 uint32_t device_id = pci_get_devid(self); 241 uint32_t cparams; 242 uint32_t eecp; 243 uint32_t eec; 244 uint16_t to; 245 uint8_t bios_sem; 246 247 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 248 249 eec = -1; 250 251 /* Synchronise with the BIOS if it owns the controller. */ 252 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 253 eecp += XHCI_XECP_NEXT(eec) << 2) { 254 eec = XREAD4(sc, capa, eecp); 255 256 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 257 continue; 258 bios_sem = XREAD1(sc, capa, eecp + 259 XHCI_XECP_BIOS_SEM); 260 if (bios_sem == 0) 261 continue; 262 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 263 "to give up control\n"); 264 265 XWRITE1(sc, capa, eecp + 266 XHCI_XECP_OS_SEM, 1); 267 268 to = 500; 269 while (1) { 270 bios_sem = XREAD1(sc, capa, eecp + 271 XHCI_XECP_BIOS_SEM); 272 273 if (bios_sem == 0) 274 break; 275 276 if (--to == 0) { 277 device_printf(sc->sc_bus.bdev, 278 "timed out waiting for BIOS\n"); 279 break; 280 } 281 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */ 282 } 283 } 284 285 /* On Intel chipsets reroute ports from EHCI to XHCI controller. */ 286 if (device_id == 0x1e318086 /* Panther Point */ || 287 device_id == 0x8c318086 /* Lynx Point */) { 288 uint32_t temp = xhci_get_port_route(); 289 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp, 4); 290 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp, 4); 291 } 292 return (0); 293 } 294