1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* $FreeBSD: head/sys/dev/usb/controller/xhci_pci.c 276717 2015-01-05 20:22:18Z hselasky $ */ 27 28 #include <sys/stdint.h> 29 #include <sys/param.h> 30 #include <sys/queue.h> 31 #include <sys/types.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/module.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/condvar.h> 39 #include <sys/sysctl.h> 40 #include <sys/unistd.h> 41 #include <sys/callout.h> 42 #include <sys/malloc.h> 43 #include <sys/priv.h> 44 45 #include <bus/u4b/usb.h> 46 #include <bus/u4b/usbdi.h> 47 48 #include <bus/u4b/usb_core.h> 49 #include <bus/u4b/usb_busdma.h> 50 #include <bus/u4b/usb_process.h> 51 #include <bus/u4b/usb_util.h> 52 53 #include <bus/u4b/usb_controller.h> 54 #include <bus/u4b/usb_bus.h> 55 #include <bus/u4b/usb_pci.h> 56 #include <bus/u4b/controller/xhci.h> 57 #include <bus/u4b/controller/xhcireg.h> 58 #include "usb_if.h" 59 60 static device_probe_t xhci_pci_probe; 61 static device_attach_t xhci_pci_attach; 62 static device_detach_t xhci_pci_detach; 63 static usb_take_controller_t xhci_pci_take_controller; 64 65 static device_method_t xhci_device_methods[] = { 66 /* device interface */ 67 DEVMETHOD(device_probe, xhci_pci_probe), 68 DEVMETHOD(device_attach, xhci_pci_attach), 69 DEVMETHOD(device_detach, xhci_pci_detach), 70 DEVMETHOD(device_suspend, bus_generic_suspend), 71 DEVMETHOD(device_resume, bus_generic_resume), 72 DEVMETHOD(device_shutdown, bus_generic_shutdown), 73 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 74 75 DEVMETHOD_END 76 }; 77 78 static driver_t xhci_driver = { 79 .name = "xhci", 80 .methods = xhci_device_methods, 81 .size = sizeof(struct xhci_softc), 82 }; 83 84 static devclass_t xhci_devclass; 85 86 DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL); 87 MODULE_DEPEND(xhci, usb, 1, 1, 1); 88 89 static const char * 90 xhci_pci_match(device_t self) 91 { 92 uint32_t device_id = pci_get_devid(self); 93 94 switch (device_id) { 95 case 0x01941033: 96 return ("NEC uPD720200 USB 3.0 controller"); 97 98 case 0x10421b21: 99 return ("ASMedia ASM1042 USB 3.0 controller"); 100 101 case 0x0f358086: 102 return ("Intel BayTrail USB 3.0 controller"); 103 case 0x9c318086: 104 case 0x1e318086: 105 return ("Intel Panther Point USB 3.0 controller"); 106 case 0x8c318086: 107 return ("Intel Lynx Point USB 3.0 controller"); 108 case 0x8cb18086: 109 return ("Intel Wildcat Point USB 3.0 controller"); 110 case 0x8d318086: 111 return ("Intel Wellsburg USB 3.0 controller"); 112 case 0x9cb18086: 113 return ("Intel Wildcat Point-LP USB 3.0 controller"); 114 case 0x9d2f8086: 115 return ("Intel Sunrise Point-LP USB 3.0 controller"); 116 case 0xa12f8086: 117 return ("Intel Sunrise Point USB 3.0 controller"); 118 case 0xa1af8086: 119 return ("Intel Lewisburg USB 3.0 controller"); 120 case 0xa2af8086: 121 return ("Intel Union Point USB 3.0 controller"); 122 case 0xa01b177d: 123 return ("Cavium ThunderX USB 3.0 controller"); 124 default: 125 break; 126 } 127 128 if ((pci_get_class(self) == PCIC_SERIALBUS) 129 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 130 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 131 return ("XHCI (generic) USB 3.0 controller"); 132 } 133 return (NULL); /* dunno */ 134 } 135 136 static int 137 xhci_pci_probe(device_t self) 138 { 139 const char *desc = xhci_pci_match(self); 140 141 if (desc) { 142 device_set_desc(self, desc); 143 return (0); 144 } else { 145 return (ENXIO); 146 } 147 } 148 149 static int xhci_use_msi = 1; 150 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 151 152 static void 153 xhci_interrupt_poll(void *_sc) 154 { 155 struct xhci_softc *sc = _sc; 156 157 USB_BUS_UNLOCK(&sc->sc_bus); 158 xhci_interrupt(sc); 159 USB_BUS_LOCK(&sc->sc_bus); 160 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 161 } 162 163 static int 164 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 165 { 166 uint32_t temp; 167 uint32_t usb3_mask; 168 uint32_t usb2_mask; 169 170 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 171 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 172 173 temp |= set; 174 temp &= ~clear; 175 176 /* Don't set bits which the hardware doesn't support */ 177 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); 178 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); 179 180 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); 181 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); 182 183 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 184 185 return (0); 186 } 187 188 static int 189 xhci_pci_attach(device_t self) 190 { 191 struct xhci_softc *sc = device_get_softc(self); 192 int err, rid; 193 uint8_t usedma32; 194 #if defined(__DragonFly__) 195 int irq_flags; 196 #else 197 int count; 198 #endif 199 200 rid = PCI_XHCI_CBMEM; 201 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 202 RF_ACTIVE); 203 if (!sc->sc_io_res) { 204 device_printf(self, "Could not map memory\n"); 205 return (ENOMEM); 206 } 207 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 208 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 209 sc->sc_io_size = rman_get_size(sc->sc_io_res); 210 211 /* check for USB 3.0 controllers which don't support 64-bit DMA */ 212 switch (pci_get_devid(self)) { 213 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ 214 case 0x00141912: /* NEC uPD720201 USB 3.0 controller */ 215 case 0x78141022: /* AMD A10-7300, tested does not work w/64-bit DMA */ 216 usedma32 = 1; 217 break; 218 default: 219 usedma32 = 0; 220 break; 221 } 222 223 if (xhci_init(sc, self, usedma32)) { 224 device_printf(self, "Could not initialize softc\n"); 225 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 226 sc->sc_io_res); 227 return (ENXIO); 228 } 229 230 pci_enable_busmaster(self); 231 232 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_lock, 0); 233 USB_BUS_LOCK(&sc->sc_bus); 234 235 rid = 0; 236 #if defined(__DragonFly__) 237 pci_alloc_1intr(self, xhci_use_msi, &rid, &irq_flags); 238 sc->sc_irq_rid = rid; 239 #else 240 if (xhci_use_msi) { 241 count = pci_msi_count(self); 242 if (count >= 1) { 243 count = 1; 244 if (pci_alloc_msi(self, &rid, 1, count) == 0) { 245 if (bootverbose) 246 device_printf(self, "MSI enabled\n"); 247 sc->sc_irq_rid = 1; 248 } 249 } 250 } 251 #endif 252 253 /* 254 * hw.usb.xhci.use_polling=1 to force polling. 255 */ 256 if (xhci_use_polling() == 0) { 257 #if defined(__DragonFly__) 258 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, 259 &rid, irq_flags); 260 #else 261 sc->sc_irq_res = bus_alloc_resource_any( 262 self, SYS_RES_IRQ, 263 &sc->sc_irq_rid, 264 RF_SHAREABLE | RF_ACTIVE); 265 #endif 266 if (sc->sc_irq_res == NULL) { 267 pci_release_msi(self); 268 device_printf(self, "Could not allocate IRQ\n"); 269 /* goto error; FALLTHROUGH - use polling */ 270 } 271 } 272 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 273 if (sc->sc_bus.bdev == NULL) { 274 device_printf(self, "Could not add USB device\n"); 275 goto error; 276 } 277 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 278 279 ksprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self)); 280 281 if (sc->sc_irq_res != NULL) { 282 err = bus_setup_intr(self, sc->sc_irq_res, INTR_MPSAFE, 283 (driver_intr_t *)xhci_interrupt, sc, 284 &sc->sc_intr_hdl, NULL); 285 if (err != 0) { 286 bus_release_resource(self, SYS_RES_IRQ, 287 rman_get_rid(sc->sc_irq_res), 288 sc->sc_irq_res); 289 sc->sc_irq_res = NULL; 290 pci_release_msi(self); 291 device_printf(self, 292 "Could not setup IRQ, err=%d\n", 293 err); 294 sc->sc_intr_hdl = NULL; 295 } 296 } 297 298 /* On Intel chipsets reroute ports from EHCI to XHCI controller. */ 299 switch (pci_get_devid(self)) { 300 case 0x0f358086: /* BayTrail */ 301 case 0x9c318086: /* Panther Point */ 302 case 0x1e318086: /* Panther Point */ 303 case 0x8c318086: /* Lynx Point */ 304 case 0x8cb18086: /* Wildcat Point */ 305 case 0x9cb18086: /* Wildcat Point-LP */ 306 sc->sc_port_route = &xhci_pci_port_route; 307 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; 308 break; 309 default: 310 break; 311 } 312 313 xhci_pci_take_controller(self); 314 315 err = xhci_halt_controller(sc); 316 317 if (err == 0) 318 err = xhci_start_controller(sc); 319 320 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { 321 if (xhci_use_polling() != 0) { 322 device_printf(self, "Interrupt polling at %dHz\n", hz); 323 xhci_interrupt_poll(sc); 324 } else { 325 goto error; 326 } 327 } 328 USB_BUS_UNLOCK(&sc->sc_bus); 329 330 if (err == 0) { 331 err = device_probe_and_attach(sc->sc_bus.bdev); 332 } 333 334 if (err) { 335 device_printf(self, 336 "XHCI halt/start/probe failed err=%d\n", 337 err); 338 goto error; 339 } 340 return (0); 341 342 error: 343 USB_BUS_UNLOCK(&sc->sc_bus); 344 xhci_pci_detach(self); 345 return (ENXIO); 346 } 347 348 static int 349 xhci_pci_detach(device_t self) 350 { 351 struct xhci_softc *sc = device_get_softc(self); 352 device_t bdev; 353 354 if (sc->sc_bus.bdev != NULL) { 355 bdev = sc->sc_bus.bdev; 356 device_detach(bdev); 357 device_delete_child(self, bdev); 358 } 359 /* during module unload there are lots of children leftover */ 360 device_delete_children(self); 361 362 usb_callout_drain(&sc->sc_callout); 363 xhci_halt_controller(sc); 364 365 pci_disable_busmaster(self); 366 367 if (sc->sc_irq_res && sc->sc_intr_hdl) { 368 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 369 sc->sc_intr_hdl = NULL; 370 } 371 if (sc->sc_irq_res) { 372 bus_release_resource(self, SYS_RES_IRQ, 373 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 374 sc->sc_irq_res = NULL; 375 pci_release_msi(self); 376 } 377 if (sc->sc_io_res) { 378 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 379 sc->sc_io_res); 380 sc->sc_io_res = NULL; 381 } 382 383 xhci_uninit(sc); 384 385 return (0); 386 } 387 388 static int 389 xhci_pci_take_controller(device_t self) 390 { 391 struct xhci_softc *sc = device_get_softc(self); 392 uint32_t cparams; 393 uint32_t eecp; 394 uint32_t eec; 395 uint16_t to; 396 uint8_t bios_sem; 397 398 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 399 400 eec = -1; 401 402 /* Synchronise with the BIOS if it owns the controller. */ 403 for (eecp = XHCI_HCS0_XECP(cparams) << 2; 404 eecp != 0 && XHCI_XECP_NEXT(eec); 405 eecp += XHCI_XECP_NEXT(eec) << 2) { 406 eec = XREAD4(sc, capa, eecp); 407 408 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 409 continue; 410 bios_sem = XREAD1(sc, capa, eecp + XHCI_XECP_BIOS_SEM); 411 if (bios_sem == 0) 412 continue; 413 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 414 "to give up control\n"); 415 XWRITE1(sc, capa, eecp + XHCI_XECP_OS_SEM, 1); 416 to = 500; 417 while (1) { 418 bios_sem = XREAD1(sc, capa, eecp + XHCI_XECP_BIOS_SEM); 419 if (bios_sem == 0) 420 break; 421 422 if (--to == 0) { 423 device_printf(sc->sc_bus.bdev, 424 "timed out waiting for BIOS\n"); 425 break; 426 } 427 usb_pause_mtx(NULL, hz / 100 + 1); /* wait 10ms */ 428 } 429 } 430 return (0); 431 } 432