1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/stdint.h> 27 #include <sys/param.h> 28 #include <sys/queue.h> 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/bus.h> 33 #include <sys/module.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/condvar.h> 37 #include <sys/sysctl.h> 38 #include <sys/unistd.h> 39 #include <sys/callout.h> 40 #include <sys/malloc.h> 41 #include <sys/priv.h> 42 43 #include <bus/u4b/usb.h> 44 #include <bus/u4b/usbdi.h> 45 46 #include <bus/u4b/usb_core.h> 47 #include <bus/u4b/usb_busdma.h> 48 #include <bus/u4b/usb_process.h> 49 #include <bus/u4b/usb_util.h> 50 51 #include <bus/u4b/usb_controller.h> 52 #include <bus/u4b/usb_bus.h> 53 #include <bus/u4b/usb_pci.h> 54 #include <bus/u4b/controller/xhci.h> 55 #include <bus/u4b/controller/xhcireg.h> 56 #include "usb_if.h" 57 58 static device_probe_t xhci_pci_probe; 59 static device_attach_t xhci_pci_attach; 60 static device_detach_t xhci_pci_detach; 61 static usb_take_controller_t xhci_pci_take_controller; 62 63 static device_method_t xhci_device_methods[] = { 64 /* device interface */ 65 DEVMETHOD(device_probe, xhci_pci_probe), 66 DEVMETHOD(device_attach, xhci_pci_attach), 67 DEVMETHOD(device_detach, xhci_pci_detach), 68 DEVMETHOD(device_suspend, bus_generic_suspend), 69 DEVMETHOD(device_resume, bus_generic_resume), 70 DEVMETHOD(device_shutdown, bus_generic_shutdown), 71 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 72 73 DEVMETHOD_END 74 }; 75 76 static driver_t xhci_driver = { 77 .name = "xhci", 78 .methods = xhci_device_methods, 79 .size = sizeof(struct xhci_softc), 80 }; 81 82 static devclass_t xhci_devclass; 83 84 DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL); 85 MODULE_DEPEND(xhci, usb, 1, 1, 1); 86 87 88 static const char * 89 xhci_pci_match(device_t self) 90 { 91 uint32_t device_id = pci_get_devid(self); 92 93 switch (device_id) { 94 case 0x01941033: 95 return ("NEC uPD720200 USB 3.0 controller"); 96 97 case 0x10421b21: 98 return ("ASMedia ASM1042 USB 3.0 controller"); 99 100 case 0x1e318086: 101 return ("Intel Panther Point USB 3.0 controller"); 102 case 0x8c318086: 103 return ("Intel Lynx Point USB 3.0 controller"); 104 105 default: 106 break; 107 } 108 109 if ((pci_get_class(self) == PCIC_SERIALBUS) 110 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 111 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 112 return ("XHCI (generic) USB 3.0 controller"); 113 } 114 return (NULL); /* dunno */ 115 } 116 117 static int 118 xhci_pci_probe(device_t self) 119 { 120 const char *desc = xhci_pci_match(self); 121 122 if (desc) { 123 device_set_desc(self, desc); 124 return (0); 125 } else { 126 return (ENXIO); 127 } 128 } 129 130 static int xhci_use_msi = 1; 131 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 132 133 static void 134 xhci_interrupt_poll(void *_sc) 135 { 136 struct xhci_softc *sc = _sc; 137 USB_BUS_UNLOCK(&sc->sc_bus); 138 xhci_interrupt(sc); 139 USB_BUS_LOCK(&sc->sc_bus); 140 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 141 } 142 143 static int 144 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 145 { 146 uint32_t temp; 147 148 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 149 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 150 151 temp |= set; 152 temp &= ~clear; 153 154 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp, 4); 155 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp, 4); 156 157 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 158 159 return (0); 160 } 161 162 static int 163 xhci_pci_attach(device_t self) 164 { 165 struct xhci_softc *sc = device_get_softc(self); 166 int count, err, rid; 167 168 /* XXX check for 64-bit capability */ 169 170 if (xhci_init(sc, self)) { 171 device_printf(self, "Could not initialize softc\n"); 172 goto error; 173 } 174 175 pci_enable_busmaster(self); 176 177 rid = PCI_XHCI_CBMEM; 178 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 179 RF_ACTIVE); 180 if (!sc->sc_io_res) { 181 device_printf(self, "Could not map memory\n"); 182 goto error; 183 } 184 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 185 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 186 sc->sc_io_size = rman_get_size(sc->sc_io_res); 187 188 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_lock, 0); 189 190 sc->sc_irq_rid = 0; 191 if (xhci_use_msi) { 192 count = pci_msi_count(self); 193 if (count >= 1) { 194 count = 1; 195 if (pci_alloc_msi(self, &rid, 1, count) == 0) { 196 if (bootverbose) 197 device_printf(self, "MSI enabled\n"); 198 sc->sc_irq_rid = 1; 199 } 200 } 201 } 202 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, 203 &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 204 if (sc->sc_irq_res == NULL) { 205 device_printf(self, "Could not allocate IRQ\n"); 206 goto error; 207 } 208 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 209 if (sc->sc_bus.bdev == NULL) { 210 device_printf(self, "Could not add USB device\n"); 211 goto error; 212 } 213 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 214 215 ksprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self)); 216 217 if (sc->sc_irq_res != NULL) { 218 err = bus_setup_intr(self, sc->sc_irq_res, INTR_MPSAFE, 219 (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl, NULL); 220 if (err != 0) { 221 device_printf(self, "Could not setup IRQ, err=%d\n", err); 222 sc->sc_intr_hdl = NULL; 223 } 224 } 225 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL || 226 xhci_use_polling() != 0) { 227 device_printf(self, "Interrupt polling at %dHz\n", hz); 228 USB_BUS_LOCK(&sc->sc_bus); 229 xhci_interrupt_poll(sc); 230 USB_BUS_UNLOCK(&sc->sc_bus); 231 } 232 233 /* On Intel chipsets reroute ports from EHCI to XHCI controller. */ 234 switch (pci_get_devid(self)) { 235 case 0x1e318086: /* Panther Point */ 236 case 0x8c318086: /* Lynx Point */ 237 sc->sc_port_route = &xhci_pci_port_route; 238 break; 239 default: 240 break; 241 } 242 243 xhci_pci_take_controller(self); 244 245 err = xhci_halt_controller(sc); 246 247 if (err == 0) 248 err = xhci_start_controller(sc); 249 250 if (err == 0) 251 err = device_probe_and_attach(sc->sc_bus.bdev); 252 253 if (err) { 254 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err); 255 goto error; 256 } 257 return (0); 258 259 error: 260 xhci_pci_detach(self); 261 return (ENXIO); 262 } 263 264 static int 265 xhci_pci_detach(device_t self) 266 { 267 struct xhci_softc *sc = device_get_softc(self); 268 device_t bdev; 269 270 if (sc->sc_bus.bdev != NULL) { 271 bdev = sc->sc_bus.bdev; 272 device_detach(bdev); 273 device_delete_child(self, bdev); 274 } 275 /* during module unload there are lots of children leftover */ 276 device_delete_children(self); 277 278 if (sc->sc_io_res) { 279 usb_callout_drain(&sc->sc_callout); 280 xhci_halt_controller(sc); 281 } 282 283 pci_disable_busmaster(self); 284 285 if (sc->sc_irq_res && sc->sc_intr_hdl) { 286 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 287 sc->sc_intr_hdl = NULL; 288 } 289 if (sc->sc_irq_res) { 290 if (sc->sc_irq_rid == 1) 291 pci_release_msi(self); 292 bus_release_resource(self, SYS_RES_IRQ, sc->sc_irq_rid, 293 sc->sc_irq_res); 294 sc->sc_irq_res = NULL; 295 } 296 if (sc->sc_io_res) { 297 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 298 sc->sc_io_res); 299 sc->sc_io_res = NULL; 300 } 301 302 xhci_uninit(sc); 303 304 return (0); 305 } 306 307 static int 308 xhci_pci_take_controller(device_t self) 309 { 310 struct xhci_softc *sc = device_get_softc(self); 311 uint32_t cparams; 312 uint32_t eecp; 313 uint32_t eec; 314 uint16_t to; 315 uint8_t bios_sem; 316 317 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 318 319 eec = -1; 320 321 /* Synchronise with the BIOS if it owns the controller. */ 322 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 323 eecp += XHCI_XECP_NEXT(eec) << 2) { 324 eec = XREAD4(sc, capa, eecp); 325 326 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 327 continue; 328 bios_sem = XREAD1(sc, capa, eecp + 329 XHCI_XECP_BIOS_SEM); 330 if (bios_sem == 0) 331 continue; 332 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 333 "to give up control\n"); 334 XWRITE1(sc, capa, eecp + 335 XHCI_XECP_OS_SEM, 1); 336 to = 500; 337 while (1) { 338 bios_sem = XREAD1(sc, capa, eecp + 339 XHCI_XECP_BIOS_SEM); 340 if (bios_sem == 0) 341 break; 342 343 if (--to == 0) { 344 device_printf(sc->sc_bus.bdev, 345 "timed out waiting for BIOS\n"); 346 break; 347 } 348 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */ 349 } 350 } 351 return (0); 352 } 353