1 /*- 2 * Copyright (c) 2013-2014 Kevin Lo 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD: head/sys/dev/usb/net/if_axge.c 276701 2015-01-05 15:04:17Z hselasky $ */ 28 29 /* 30 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/condvar.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/module.h> 40 #include <sys/socket.h> 41 #include <sys/sysctl.h> 42 #include <sys/unistd.h> 43 44 #include <net/if.h> 45 #include <net/if_var.h> 46 #include <net/ifq_var.h> 47 48 #include <bus/u4b/usb.h> 49 #include <bus/u4b/usbdi.h> 50 #include <bus/u4b/usbdi_util.h> 51 #include "usbdevs.h" 52 53 #define USB_DEBUG_VAR axge_debug 54 #include <bus/u4b/usb_debug.h> 55 #include <bus/u4b/usb_process.h> 56 57 #include <bus/u4b/net/usb_ethernet.h> 58 #include <bus/u4b/net/if_axgereg.h> 59 60 /* 61 * Various supported device vendors/products. 62 */ 63 64 static const STRUCT_USB_HOST_ID axge_devs[] = { 65 #define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 66 AXGE_DEV(ASIX, AX88178A), 67 AXGE_DEV(ASIX, AX88179), 68 AXGE_DEV(DLINK, DUB1312), 69 AXGE_DEV(SITECOMEU, LN032), 70 #undef AXGE_DEV 71 }; 72 73 static const struct { 74 uint8_t ctrl; 75 uint8_t timer_l; 76 uint8_t timer_h; 77 uint8_t size; 78 uint8_t ifg; 79 } __packed axge_bulk_size[] = { 80 { 7, 0x4f, 0x00, 0x12, 0xff }, 81 { 7, 0x20, 0x03, 0x16, 0xff }, 82 { 7, 0xae, 0x07, 0x18, 0xff }, 83 { 7, 0xcc, 0x4c, 0x18, 0x08 } 84 }; 85 86 /* prototypes */ 87 88 static device_probe_t axge_probe; 89 static device_attach_t axge_attach; 90 static device_detach_t axge_detach; 91 92 static usb_callback_t axge_bulk_read_callback; 93 static usb_callback_t axge_bulk_write_callback; 94 95 static miibus_readreg_t axge_miibus_readreg; 96 static miibus_writereg_t axge_miibus_writereg; 97 static miibus_statchg_t axge_miibus_statchg; 98 99 static uether_fn_t axge_attach_post; 100 static uether_fn_t axge_init; 101 static uether_fn_t axge_stop; 102 static uether_fn_t axge_start; 103 static uether_fn_t axge_tick; 104 static uether_fn_t axge_setmulti; 105 static uether_fn_t axge_setpromisc; 106 107 static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t, 108 uint16_t, void *, int); 109 static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t, 110 uint16_t, void *, int); 111 static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t); 112 static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t, 113 uint16_t); 114 static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t, 115 uint8_t); 116 static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t, 117 uint16_t, uint16_t); 118 static void axge_chip_init(struct axge_softc *); 119 static void axge_reset(struct axge_softc *); 120 121 static int axge_attach_post_sub(struct usb_ether *); 122 static int axge_ifmedia_upd(struct ifnet *); 123 static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 124 static int axge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 125 static void axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 126 static void axge_rxeof(struct usb_ether *, struct usb_page_cache *, 127 unsigned int, unsigned int, uint32_t); 128 static void axge_csum_cfg(struct usb_ether *); 129 130 #define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 131 132 #ifdef USB_DEBUG 133 static int axge_debug = 0; 134 135 static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW, 0, "USB axge"); 136 SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RW, &axge_debug, 0, 137 "Debug level"); 138 #endif 139 140 static const struct usb_config axge_config[AXGE_N_TRANSFER] = { 141 [AXGE_BULK_DT_WR] = { 142 .type = UE_BULK, 143 .endpoint = UE_ADDR_ANY, 144 .direction = UE_DIR_OUT, 145 .frames = 16, 146 .bufsize = 16 * MCLBYTES, 147 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 148 .callback = axge_bulk_write_callback, 149 .timeout = 10000, /* 10 seconds */ 150 }, 151 [AXGE_BULK_DT_RD] = { 152 .type = UE_BULK, 153 .endpoint = UE_ADDR_ANY, 154 .direction = UE_DIR_IN, 155 .bufsize = 65536, 156 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 157 .callback = axge_bulk_read_callback, 158 .timeout = 0, /* no timeout */ 159 }, 160 }; 161 162 static device_method_t axge_methods[] = { 163 /* Device interface. */ 164 DEVMETHOD(device_probe, axge_probe), 165 DEVMETHOD(device_attach, axge_attach), 166 DEVMETHOD(device_detach, axge_detach), 167 168 /* MII interface. */ 169 DEVMETHOD(miibus_readreg, axge_miibus_readreg), 170 DEVMETHOD(miibus_writereg, axge_miibus_writereg), 171 DEVMETHOD(miibus_statchg, axge_miibus_statchg), 172 173 DEVMETHOD_END 174 }; 175 176 static driver_t axge_driver = { 177 .name = "axge", 178 .methods = axge_methods, 179 .size = sizeof(struct axge_softc), 180 }; 181 182 static devclass_t axge_devclass; 183 184 DRIVER_MODULE(axge, uhub, axge_driver, axge_devclass, NULL, NULL); 185 DRIVER_MODULE(miibus, axge, miibus_driver, miibus_devclass, NULL, NULL); 186 MODULE_DEPEND(axge, uether, 1, 1, 1); 187 MODULE_DEPEND(axge, usb, 1, 1, 1); 188 MODULE_DEPEND(axge, ether, 1, 1, 1); 189 MODULE_DEPEND(axge, miibus, 1, 1, 1); 190 MODULE_VERSION(axge, 1); 191 192 static const struct usb_ether_methods axge_ue_methods = { 193 .ue_attach_post = axge_attach_post, 194 .ue_attach_post_sub = axge_attach_post_sub, 195 .ue_start = axge_start, 196 .ue_init = axge_init, 197 .ue_stop = axge_stop, 198 .ue_tick = axge_tick, 199 .ue_setmulti = axge_setmulti, 200 .ue_setpromisc = axge_setpromisc, 201 .ue_mii_upd = axge_ifmedia_upd, 202 .ue_mii_sts = axge_ifmedia_sts, 203 }; 204 205 static int 206 axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, 207 uint16_t val, void *buf, int len) 208 { 209 struct usb_device_request req; 210 211 AXGE_LOCK_ASSERT(sc); 212 213 req.bmRequestType = UT_READ_VENDOR_DEVICE; 214 req.bRequest = cmd; 215 USETW(req.wValue, val); 216 USETW(req.wIndex, index); 217 USETW(req.wLength, len); 218 219 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 220 } 221 222 static void 223 axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, 224 uint16_t val, void *buf, int len) 225 { 226 struct usb_device_request req; 227 228 AXGE_LOCK_ASSERT(sc); 229 230 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 231 req.bRequest = cmd; 232 USETW(req.wValue, val); 233 USETW(req.wIndex, index); 234 USETW(req.wLength, len); 235 236 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) { 237 /* Error ignored. */ 238 } 239 } 240 241 static uint8_t 242 axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg) 243 { 244 uint8_t val; 245 246 axge_read_mem(sc, cmd, 1, reg, &val, 1); 247 return (val); 248 } 249 250 static uint16_t 251 axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, 252 uint16_t reg) 253 { 254 uint8_t val[2]; 255 256 axge_read_mem(sc, cmd, index, reg, &val, 2); 257 return (UGETW(val)); 258 } 259 260 static void 261 axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val) 262 { 263 axge_write_mem(sc, cmd, 1, reg, &val, 1); 264 } 265 266 static void 267 axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, 268 uint16_t reg, uint16_t val) 269 { 270 uint8_t temp[2]; 271 272 USETW(temp, val); 273 axge_write_mem(sc, cmd, index, reg, &temp, 2); 274 } 275 276 static int 277 axge_miibus_readreg(device_t dev, int phy, int reg) 278 { 279 struct axge_softc *sc; 280 uint16_t val; 281 int locked; 282 283 sc = device_get_softc(dev); 284 locked = lockowned(&sc->sc_lock); 285 if (!locked) 286 AXGE_LOCK(sc); 287 288 val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy); 289 290 if (!locked) 291 AXGE_UNLOCK(sc); 292 293 return (val); 294 } 295 296 static int 297 axge_miibus_writereg(device_t dev, int phy, int reg, int val) 298 { 299 struct axge_softc *sc; 300 int locked; 301 302 sc = device_get_softc(dev); 303 if (sc->sc_phyno != phy) 304 return (0); 305 locked = lockowned(&sc->sc_lock); 306 if (!locked) 307 AXGE_LOCK(sc); 308 309 axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val); 310 311 if (!locked) 312 AXGE_UNLOCK(sc); 313 314 return (0); 315 } 316 317 static void 318 axge_miibus_statchg(device_t dev) 319 { 320 struct axge_softc *sc; 321 struct mii_data *mii; 322 struct ifnet *ifp; 323 uint8_t link_status, tmp[5]; 324 uint16_t val; 325 int locked; 326 327 sc = device_get_softc(dev); 328 mii = GET_MII(sc); 329 locked = lockowned(&sc->sc_lock); 330 if (!locked) 331 AXGE_LOCK(sc); 332 333 ifp = uether_getifp(&sc->sc_ue); 334 if (mii == NULL || ifp == NULL || 335 (ifp->if_flags & IFF_RUNNING) == 0) 336 goto done; 337 338 sc->sc_flags &= ~AXGE_FLAG_LINK; 339 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 340 (IFM_ACTIVE | IFM_AVALID)) { 341 switch (IFM_SUBTYPE(mii->mii_media_active)) { 342 case IFM_10_T: 343 case IFM_100_TX: 344 case IFM_1000_T: 345 sc->sc_flags |= AXGE_FLAG_LINK; 346 break; 347 default: 348 break; 349 } 350 } 351 352 /* Lost link, do nothing. */ 353 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0) 354 goto done; 355 356 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR); 357 358 val = 0; 359 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 360 val |= MSR_FD; 361 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 362 val |= MSR_TFC; 363 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 364 val |= MSR_RFC; 365 } 366 val |= MSR_RE; 367 switch (IFM_SUBTYPE(mii->mii_media_active)) { 368 case IFM_1000_T: 369 val |= MSR_GM | MSR_EN_125MHZ; 370 if (link_status & PLSR_USB_SS) 371 memcpy(tmp, &axge_bulk_size[0], 5); 372 else if (link_status & PLSR_USB_HS) 373 memcpy(tmp, &axge_bulk_size[1], 5); 374 else 375 memcpy(tmp, &axge_bulk_size[3], 5); 376 break; 377 case IFM_100_TX: 378 val |= MSR_PS; 379 if (link_status & (PLSR_USB_SS | PLSR_USB_HS)) 380 memcpy(tmp, &axge_bulk_size[2], 5); 381 else 382 memcpy(tmp, &axge_bulk_size[3], 5); 383 break; 384 case IFM_10_T: 385 memcpy(tmp, &axge_bulk_size[3], 5); 386 break; 387 } 388 /* Rx bulk configuration. */ 389 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5); 390 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); 391 done: 392 if (!locked) 393 AXGE_UNLOCK(sc); 394 } 395 396 static void 397 axge_chip_init(struct axge_softc *sc) 398 { 399 /* Power up ethernet PHY. */ 400 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0); 401 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL); 402 uether_pause(&sc->sc_ue, hz / 4); 403 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 404 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS); 405 uether_pause(&sc->sc_ue, hz / 10); 406 } 407 408 static void 409 axge_reset(struct axge_softc *sc) 410 { 411 struct usb_config_descriptor *cd; 412 usb_error_t err; 413 414 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 415 416 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_lock, 417 cd->bConfigurationValue); 418 if (err) 419 DPRINTF("reset failed (ignored)\n"); 420 421 /* Wait a little while for the chip to get its brains in order. */ 422 uether_pause(&sc->sc_ue, hz / 100); 423 424 /* Reinitialize controller to achieve full reset. */ 425 axge_chip_init(sc); 426 } 427 428 static void 429 axge_attach_post(struct usb_ether *ue) 430 { 431 struct axge_softc *sc; 432 433 sc = uether_getsc(ue); 434 sc->sc_phyno = 3; 435 436 /* Initialize controller and get station address. */ 437 axge_chip_init(sc); 438 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, 439 ue->ue_eaddr, ETHER_ADDR_LEN); 440 } 441 442 static int 443 axge_attach_post_sub(struct usb_ether *ue) 444 { 445 struct axge_softc *sc; 446 struct ifnet *ifp; 447 int error; 448 449 sc = uether_getsc(ue); 450 ifp = uether_getifp(ue); 451 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 452 ifp->if_start = uether_start; 453 ifp->if_ioctl = axge_ioctl; 454 ifp->if_init = uether_init; 455 ifq_set_maxlen(&ifp->if_snd, ifqmaxlen); 456 ifq_set_ready(&ifp->if_snd); 457 458 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM; 459 ifp->if_hwassist = AXGE_CSUM_FEATURES; 460 ifp->if_capenable = ifp->if_capabilities; 461 462 /* 463 * NB: miibus assumes that the first member of the softc 464 * of it's parent is an arpcom structure 465 */ 466 error = mii_phy_probe(ue->ue_dev, &ue->ue_miibus, 467 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts); 468 469 return (error); 470 } 471 472 /* 473 * Set media options. 474 */ 475 static int 476 axge_ifmedia_upd(struct ifnet *ifp) 477 { 478 struct axge_softc *sc; 479 struct mii_data *mii; 480 struct mii_softc *miisc; 481 int error; 482 483 sc = ifp->if_softc; 484 mii = GET_MII(sc); 485 AXGE_LOCK_ASSERT(sc); 486 487 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 488 mii_phy_reset(miisc); 489 error = mii_mediachg(mii); 490 491 return (error); 492 } 493 494 /* 495 * Report current media status. 496 */ 497 static void 498 axge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 499 { 500 struct axge_softc *sc; 501 struct mii_data *mii; 502 503 sc = ifp->if_softc; 504 mii = GET_MII(sc); 505 AXGE_LOCK(sc); 506 mii_pollstat(mii); 507 ifmr->ifm_active = mii->mii_media_active; 508 ifmr->ifm_status = mii->mii_media_status; 509 AXGE_UNLOCK(sc); 510 } 511 512 /* 513 * Probe for a AX88179 chip. 514 */ 515 static int 516 axge_probe(device_t dev) 517 { 518 struct usb_attach_arg *uaa; 519 520 uaa = device_get_ivars(dev); 521 if (uaa->usb_mode != USB_MODE_HOST) 522 return (ENXIO); 523 if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX) 524 return (ENXIO); 525 if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX) 526 return (ENXIO); 527 528 return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa)); 529 } 530 531 /* 532 * Attach the interface. Allocate softc structures, do ifmedia 533 * setup and ethernet/BPF attach. 534 */ 535 static int 536 axge_attach(device_t dev) 537 { 538 struct usb_attach_arg *uaa; 539 struct axge_softc *sc; 540 struct usb_ether *ue; 541 uint8_t iface_index; 542 int error; 543 544 uaa = device_get_ivars(dev); 545 sc = device_get_softc(dev); 546 ue = &sc->sc_ue; 547 548 device_set_usb_desc(dev); 549 lockinit(&sc->sc_lock, device_get_nameunit(dev), 0, LK_CANRECURSE); 550 551 iface_index = AXGE_IFACE_IDX; 552 error = usbd_transfer_setup(uaa->device, &iface_index, 553 sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_lock); 554 if (error) { 555 device_printf(dev, "allocating USB transfers failed\n"); 556 goto detach; 557 } 558 559 ue->ue_sc = sc; 560 ue->ue_dev = dev; 561 ue->ue_udev = uaa->device; 562 ue->ue_lock = &sc->sc_lock; 563 ue->ue_methods = &axge_ue_methods; 564 565 error = uether_ifattach(ue); 566 if (error) { 567 device_printf(dev, "could not attach interface\n"); 568 goto detach; 569 } 570 return (0); /* success */ 571 572 detach: 573 axge_detach(dev); 574 return (ENXIO); /* failure */ 575 } 576 577 static int 578 axge_detach(device_t dev) 579 { 580 struct axge_softc *sc; 581 struct usb_ether *ue; 582 583 sc = device_get_softc(dev); 584 ue = &sc->sc_ue; 585 usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER); 586 uether_ifdetach(ue); 587 lockuninit(&sc->sc_lock); 588 589 return (0); 590 } 591 592 static void 593 axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 594 { 595 struct axge_softc *sc; 596 struct usb_ether *ue; 597 struct usb_page_cache *pc; 598 int actlen; 599 600 sc = usbd_xfer_softc(xfer); 601 ue = &sc->sc_ue; 602 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 603 604 switch (USB_GET_STATE(xfer)) { 605 case USB_ST_TRANSFERRED: 606 pc = usbd_xfer_get_frame(xfer, 0); 607 axge_rx_frame(ue, pc, actlen); 608 609 /* FALLTHROUGH */ 610 case USB_ST_SETUP: 611 tr_setup: 612 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 613 usbd_transfer_submit(xfer); 614 uether_rxflush(ue); 615 break; 616 617 default: 618 if (error != USB_ERR_CANCELLED) { 619 usbd_xfer_set_stall(xfer); 620 goto tr_setup; 621 } 622 break; 623 } 624 } 625 626 static void 627 axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 628 { 629 struct axge_softc *sc; 630 struct ifnet *ifp; 631 struct usb_page_cache *pc; 632 struct mbuf *m; 633 uint32_t txhdr; 634 int nframes, pos; 635 636 sc = usbd_xfer_softc(xfer); 637 ifp = uether_getifp(&sc->sc_ue); 638 639 switch (USB_GET_STATE(xfer)) { 640 case USB_ST_TRANSFERRED: 641 ifq_clr_oactive(&ifp->if_snd); 642 /* FALLTHROUGH */ 643 case USB_ST_SETUP: 644 tr_setup: 645 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 || 646 ifq_is_oactive(&ifp->if_snd)) { 647 /* 648 * Don't send anything if there is no link or 649 * controller is busy. 650 */ 651 return; 652 } 653 654 for (nframes = 0; nframes < 16 && 655 !ifq_is_empty(&ifp->if_snd); nframes++) { 656 m = ifq_dequeue(&ifp->if_snd); 657 if (m == NULL) 658 break; 659 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 660 nframes); 661 pos = 0; 662 pc = usbd_xfer_get_frame(xfer, nframes); 663 txhdr = htole32(m->m_pkthdr.len); 664 usbd_copy_in(pc, 0, &txhdr, sizeof(txhdr)); 665 txhdr = 0; 666 txhdr = htole32(txhdr); 667 usbd_copy_in(pc, 4, &txhdr, sizeof(txhdr)); 668 pos += 8; 669 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 670 pos += m->m_pkthdr.len; 671 if ((pos % usbd_xfer_max_framelen(xfer)) == 0) 672 txhdr |= 0x80008000; 673 674 /* 675 * XXX 676 * Update TX packet counter here. This is not 677 * correct way but it seems that there is no way 678 * to know how many packets are sent at the end 679 * of transfer because controller combines 680 * multiple writes into single one if there is 681 * room in TX buffer of controller. 682 */ 683 IFNET_STAT_INC(ifp, opackets, 1); 684 685 /* 686 * if there's a BPF listener, bounce a copy 687 * of this frame to him: 688 */ 689 BPF_MTAP(ifp, m); 690 691 m_freem(m); 692 693 /* Set frame length. */ 694 usbd_xfer_set_frame_len(xfer, nframes, pos); 695 } 696 if (nframes != 0) { 697 usbd_xfer_set_frames(xfer, nframes); 698 usbd_transfer_submit(xfer); 699 ifq_set_oactive(&ifp->if_snd); 700 } 701 return; 702 /* NOTREACHED */ 703 default: 704 IFNET_STAT_INC(ifp, oerrors, 1); 705 ifq_clr_oactive(&ifp->if_snd); 706 707 if (error != USB_ERR_CANCELLED) { 708 usbd_xfer_set_stall(xfer); 709 goto tr_setup; 710 } 711 return; 712 713 } 714 } 715 716 static void 717 axge_tick(struct usb_ether *ue) 718 { 719 struct axge_softc *sc; 720 struct mii_data *mii; 721 722 sc = uether_getsc(ue); 723 mii = GET_MII(sc); 724 AXGE_LOCK_ASSERT(sc); 725 726 mii_tick(mii); 727 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0) { 728 axge_miibus_statchg(ue->ue_dev); 729 if ((sc->sc_flags & AXGE_FLAG_LINK) != 0) 730 axge_start(ue); 731 } 732 } 733 734 static void 735 axge_setmulti(struct usb_ether *ue) 736 { 737 struct axge_softc *sc; 738 struct ifnet *ifp; 739 struct ifmultiaddr *ifma; 740 uint32_t h; 741 uint16_t rxmode; 742 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 743 744 sc = uether_getsc(ue); 745 ifp = uether_getifp(ue); 746 h = 0; 747 AXGE_LOCK_ASSERT(sc); 748 749 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR); 750 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 751 rxmode |= RCR_AMALL; 752 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); 753 return; 754 } 755 rxmode &= ~RCR_AMALL; 756 757 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 758 if (ifma->ifma_addr->sa_family != AF_LINK) 759 continue; 760 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 761 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 762 setbit(hashtbl, h); 763 } 764 765 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8); 766 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); 767 } 768 769 static void 770 axge_setpromisc(struct usb_ether *ue) 771 { 772 struct axge_softc *sc; 773 struct ifnet *ifp; 774 uint16_t rxmode; 775 776 sc = uether_getsc(ue); 777 ifp = uether_getifp(ue); 778 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR); 779 780 if (ifp->if_flags & IFF_PROMISC) 781 rxmode |= RCR_PRO; 782 else 783 rxmode &= ~RCR_PRO; 784 785 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); 786 axge_setmulti(ue); 787 } 788 789 static void 790 axge_start(struct usb_ether *ue) 791 { 792 struct axge_softc *sc; 793 794 sc = uether_getsc(ue); 795 /* 796 * Start the USB transfers, if not already started. 797 */ 798 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]); 799 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]); 800 } 801 802 static void 803 axge_init(struct usb_ether *ue) 804 { 805 struct axge_softc *sc; 806 struct ifnet *ifp; 807 uint16_t rxmode; 808 809 sc = uether_getsc(ue); 810 ifp = uether_getifp(ue); 811 AXGE_LOCK_ASSERT(sc); 812 813 if ((ifp->if_flags & IFF_RUNNING) != 0) 814 return; 815 816 /* 817 * Cancel pending I/O and free all RX/TX buffers. 818 */ 819 axge_stop(ue); 820 821 axge_reset(sc); 822 823 /* Set MAC address. */ 824 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, 825 IF_LLADDR(ifp), ETHER_ADDR_LEN); 826 827 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34); 828 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52); 829 830 /* Configure TX/RX checksum offloading. */ 831 axge_csum_cfg(ue); 832 833 /* Configure RX settings. */ 834 rxmode = (RCR_AM | RCR_SO | RCR_DROP_CRCE); 835 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 836 rxmode |= RCR_IPE; 837 838 /* If we want promiscuous mode, set the allframes bit. */ 839 if (ifp->if_flags & IFF_PROMISC) 840 rxmode |= RCR_PRO; 841 842 if (ifp->if_flags & IFF_BROADCAST) 843 rxmode |= RCR_AB; 844 845 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); 846 847 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 848 MMSR_PME_TYPE | MMSR_PME_POL | MMSR_RWMP); 849 850 /* Load the multicast filter. */ 851 axge_setmulti(ue); 852 853 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]); 854 855 ifp->if_flags |= IFF_RUNNING; 856 /* Switch to selected media. */ 857 axge_ifmedia_upd(ifp); 858 } 859 860 static void 861 axge_stop(struct usb_ether *ue) 862 { 863 struct axge_softc *sc; 864 struct ifnet *ifp; 865 866 sc = uether_getsc(ue); 867 ifp = uether_getifp(ue); 868 869 AXGE_LOCK_ASSERT(sc); 870 871 ifp->if_flags &= ~IFF_RUNNING; 872 ifq_clr_oactive(&ifp->if_snd); 873 sc->sc_flags &= ~AXGE_FLAG_LINK; 874 875 /* 876 * Stop all the transfers, if not already stopped: 877 */ 878 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]); 879 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]); 880 } 881 882 static int 883 axge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *uc) 884 { 885 struct usb_ether *ue; 886 struct axge_softc *sc; 887 struct ifreq *ifr; 888 int error, mask, reinit; 889 890 ue = ifp->if_softc; 891 sc = uether_getsc(ue); 892 ifr = (struct ifreq *)data; 893 error = 0; 894 reinit = 0; 895 if (cmd == SIOCSIFCAP) { 896 AXGE_LOCK(sc); 897 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 898 if ((mask & IFCAP_TXCSUM) != 0 && 899 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 900 ifp->if_capenable ^= IFCAP_TXCSUM; 901 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 902 ifp->if_hwassist |= AXGE_CSUM_FEATURES; 903 else 904 ifp->if_hwassist &= ~AXGE_CSUM_FEATURES; 905 reinit++; 906 } 907 if ((mask & IFCAP_RXCSUM) != 0 && 908 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 909 ifp->if_capenable ^= IFCAP_RXCSUM; 910 reinit++; 911 } 912 if (reinit > 0 && ifp->if_flags & IFF_RUNNING) 913 ifp->if_flags &= ~IFF_RUNNING; 914 else 915 reinit = 0; 916 AXGE_UNLOCK(sc); 917 if (reinit > 0) 918 uether_init(ue); 919 } else 920 error = uether_ioctl(ifp, cmd, data, uc); 921 922 return (error); 923 } 924 925 static void 926 axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 927 { 928 uint32_t pos; 929 uint32_t pkt_cnt; 930 uint32_t rxhdr; 931 uint32_t pkt_hdr; 932 uint32_t hdr_off; 933 uint32_t pktlen; 934 935 /* verify we have enough data */ 936 if (actlen < (int)sizeof(rxhdr)) 937 return; 938 939 pos = 0; 940 941 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr)); 942 rxhdr = le32toh(rxhdr); 943 944 pkt_cnt = (uint16_t)rxhdr; 945 hdr_off = (uint16_t)(rxhdr >> 16); 946 947 while (pkt_cnt--) { 948 /* verify the header offset */ 949 if ((int)(hdr_off + sizeof(pkt_hdr)) > actlen) { 950 DPRINTF("End of packet headers\n"); 951 break; 952 } 953 if ((int)pos >= actlen) { 954 DPRINTF("Data position reached end\n"); 955 break; 956 } 957 usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr)); 958 959 pkt_hdr = le32toh(pkt_hdr); 960 pktlen = (pkt_hdr >> 16) & 0x1fff; 961 if (pkt_hdr & (AXGE_RXHDR_CRC_ERR | AXGE_RXHDR_DROP_ERR)) { 962 DPRINTF("Dropped a packet\n"); 963 IFNET_STAT_INC(uether_getifp(ue), ierrors, 1); 964 } 965 if (pktlen >= 6 && (int)(pos + pktlen) <= actlen) { 966 axge_rxeof(ue, pc, pos + 2, pktlen - 6, pkt_hdr); 967 } else { 968 DPRINTF("Invalid packet pos=%d len=%d\n", 969 (int)pos, (int)pktlen); 970 } 971 pos += (pktlen + 7) & ~7; 972 hdr_off += sizeof(pkt_hdr); 973 } 974 } 975 976 static void 977 axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, 978 unsigned int offset, unsigned int len, uint32_t pkt_hdr) 979 { 980 struct ifnet *ifp; 981 struct mbuf *m; 982 983 ifp = uether_getifp(ue); 984 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 985 IFNET_STAT_INC(ifp, ierrors, 1); 986 return; 987 } 988 989 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 990 if (m == NULL) { 991 IFNET_STAT_INC(ifp, iqdrops, 1); 992 return; 993 } 994 m->m_pkthdr.rcvif = ifp; 995 m->m_len = m->m_pkthdr.len = len + ETHER_ALIGN; 996 m_adj(m, ETHER_ALIGN); 997 998 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 999 1000 IFNET_STAT_INC(ifp, ipackets, 1); 1001 1002 if ((pkt_hdr & (AXGE_RXHDR_L4CSUM_ERR | AXGE_RXHDR_L3CSUM_ERR)) == 0) { 1003 if ((pkt_hdr & AXGE_RXHDR_L4_TYPE_MASK) == 1004 AXGE_RXHDR_L4_TYPE_TCP || 1005 (pkt_hdr & AXGE_RXHDR_L4_TYPE_MASK) == 1006 AXGE_RXHDR_L4_TYPE_UDP) { 1007 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1008 CSUM_PSEUDO_HDR | CSUM_IP_CHECKED | CSUM_IP_VALID; 1009 m->m_pkthdr.csum_data = 0xffff; 1010 } 1011 } 1012 1013 IF_ENQUEUE(&ue->ue_rxq, m); 1014 } 1015 1016 static void 1017 axge_csum_cfg(struct usb_ether *ue) 1018 { 1019 struct axge_softc *sc; 1020 struct ifnet *ifp; 1021 uint8_t csum; 1022 1023 sc = uether_getsc(ue); 1024 AXGE_LOCK_ASSERT(sc); 1025 ifp = uether_getifp(ue); 1026 1027 csum = 0; 1028 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1029 csum |= CTCR_IP | CTCR_TCP | CTCR_UDP; 1030 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum); 1031 1032 csum = 0; 1033 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1034 csum |= CRCR_IP | CRCR_TCP | CRCR_UDP; 1035 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum); 1036 } 1037