1 /* $OpenBSD: rt2860reg.h,v 1.19 2009/05/18 19:25:07 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD: head/sys/dev/usb/wlan/if_runreg.h 288666 2015-10-04 13:39:00Z kevlo $ 20 */ 21 22 #ifndef _IF_RUNREG_H_ 23 #define _IF_RUNREG_H_ 24 25 #define RT2860_CONFIG_NO 1 26 #define RT2860_IFACE_INDEX 0 27 28 #define RT3070_OPT_14 0x0114 29 30 /* SCH/DMA registers */ 31 #define RT2860_INT_STATUS 0x0200 32 #define RT2860_INT_MASK 0x0204 33 #define RT2860_WPDMA_GLO_CFG 0x0208 34 #define RT2860_WPDMA_RST_IDX 0x020c 35 #define RT2860_DELAY_INT_CFG 0x0210 36 #define RT2860_WMM_AIFSN_CFG 0x0214 37 #define RT2860_WMM_CWMIN_CFG 0x0218 38 #define RT2860_WMM_CWMAX_CFG 0x021c 39 #define RT2860_WMM_TXOP0_CFG 0x0220 40 #define RT2860_WMM_TXOP1_CFG 0x0224 41 #define RT2860_GPIO_CTRL 0x0228 42 #define RT2860_MCU_CMD_REG 0x022c 43 #define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) 44 #define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) 45 #define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) 46 #define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) 47 #define RT2860_RX_BASE_PTR 0x0290 48 #define RT2860_RX_MAX_CNT 0x0294 49 #define RT2860_RX_CALC_IDX 0x0298 50 #define RT2860_FS_DRX_IDX 0x029c 51 #define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */ 52 #define RT2860_US_CYC_CNT 0x02a4 53 54 /* PBF registers */ 55 #define RT2860_SYS_CTRL 0x0400 56 #define RT2860_HOST_CMD 0x0404 57 #define RT2860_PBF_CFG 0x0408 58 #define RT2860_MAX_PCNT 0x040c 59 #define RT2860_BUF_CTRL 0x0410 60 #define RT2860_MCU_INT_STA 0x0414 61 #define RT2860_MCU_INT_ENA 0x0418 62 #define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) 63 #define RT2860_RX0Q_IO 0x0424 64 #define RT2860_BCN_OFFSET0 0x042c 65 #define RT2860_BCN_OFFSET1 0x0430 66 #define RT2860_TXRXQ_STA 0x0434 67 #define RT2860_TXRXQ_PCNT 0x0438 68 #define RT2860_PBF_DBG 0x043c 69 #define RT2860_CAP_CTRL 0x0440 70 71 /* RT3070 registers */ 72 #define RT3070_RF_CSR_CFG 0x0500 73 #define RT3070_EFUSE_CTRL 0x0580 74 #define RT3070_EFUSE_DATA0 0x0590 75 #define RT3070_EFUSE_DATA1 0x0594 76 #define RT3070_EFUSE_DATA2 0x0598 77 #define RT3070_EFUSE_DATA3 0x059c 78 #define RT3070_LDO_CFG0 0x05d4 79 #define RT3070_GPIO_SWITCH 0x05dc 80 81 /* RT5592 registers */ 82 #define RT5592_DEBUG_INDEX 0x05e8 83 84 /* MAC registers */ 85 #define RT2860_ASIC_VER_ID 0x1000 86 #define RT2860_MAC_SYS_CTRL 0x1004 87 #define RT2860_MAC_ADDR_DW0 0x1008 88 #define RT2860_MAC_ADDR_DW1 0x100c 89 #define RT2860_MAC_BSSID_DW0 0x1010 90 #define RT2860_MAC_BSSID_DW1 0x1014 91 #define RT2860_MAX_LEN_CFG 0x1018 92 #define RT2860_BBP_CSR_CFG 0x101c 93 #define RT2860_RF_CSR_CFG0 0x1020 94 #define RT2860_RF_CSR_CFG1 0x1024 95 #define RT2860_RF_CSR_CFG2 0x1028 96 #define RT2860_LED_CFG 0x102c 97 98 /* undocumented registers */ 99 #define RT2860_DEBUG 0x10f4 100 101 /* MAC Timing control registers */ 102 #define RT2860_XIFS_TIME_CFG 0x1100 103 #define RT2860_BKOFF_SLOT_CFG 0x1104 104 #define RT2860_NAV_TIME_CFG 0x1108 105 #define RT2860_CH_TIME_CFG 0x110c 106 #define RT2860_PBF_LIFE_TIMER 0x1110 107 #define RT2860_BCN_TIME_CFG 0x1114 108 #define RT2860_TBTT_SYNC_CFG 0x1118 109 #define RT2860_TSF_TIMER_DW0 0x111c 110 #define RT2860_TSF_TIMER_DW1 0x1120 111 #define RT2860_TBTT_TIMER 0x1124 112 #define RT2860_INT_TIMER_CFG 0x1128 113 #define RT2860_INT_TIMER_EN 0x112c 114 #define RT2860_CH_IDLE_TIME 0x1130 115 116 /* MAC Power Save configuration registers */ 117 #define RT2860_MAC_STATUS_REG 0x1200 118 #define RT2860_PWR_PIN_CFG 0x1204 119 #define RT2860_AUTO_WAKEUP_CFG 0x1208 120 121 /* MAC TX configuration registers */ 122 #define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) 123 #define RT2860_EDCA_TID_AC_MAP 0x1310 124 #define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) 125 #define RT2860_TX_PIN_CFG 0x1328 126 #define RT2860_TX_BAND_CFG 0x132c 127 #define RT2860_TX_SW_CFG0 0x1330 128 #define RT2860_TX_SW_CFG1 0x1334 129 #define RT2860_TX_SW_CFG2 0x1338 130 #define RT2860_TXOP_THRES_CFG 0x133c 131 #define RT2860_TXOP_CTRL_CFG 0x1340 132 #define RT2860_TX_RTS_CFG 0x1344 133 #define RT2860_TX_TIMEOUT_CFG 0x1348 134 #define RT2860_TX_RTY_CFG 0x134c 135 #define RT2860_TX_LINK_CFG 0x1350 136 #define RT2860_HT_FBK_CFG0 0x1354 137 #define RT2860_HT_FBK_CFG1 0x1358 138 #define RT2860_LG_FBK_CFG0 0x135c 139 #define RT2860_LG_FBK_CFG1 0x1360 140 #define RT2860_CCK_PROT_CFG 0x1364 141 #define RT2860_OFDM_PROT_CFG 0x1368 142 #define RT2860_MM20_PROT_CFG 0x136c 143 #define RT2860_MM40_PROT_CFG 0x1370 144 #define RT2860_GF20_PROT_CFG 0x1374 145 #define RT2860_GF40_PROT_CFG 0x1378 146 #define RT2860_EXP_CTS_TIME 0x137c 147 #define RT2860_EXP_ACK_TIME 0x1380 148 149 /* MAC RX configuration registers */ 150 #define RT2860_RX_FILTR_CFG 0x1400 151 #define RT2860_AUTO_RSP_CFG 0x1404 152 #define RT2860_LEGACY_BASIC_RATE 0x1408 153 #define RT2860_HT_BASIC_RATE 0x140c 154 #define RT2860_HT_CTRL_CFG 0x1410 155 #define RT2860_SIFS_COST_CFG 0x1414 156 #define RT2860_RX_PARSER_CFG 0x1418 157 158 /* MAC Security configuration registers */ 159 #define RT2860_TX_SEC_CNT0 0x1500 160 #define RT2860_RX_SEC_CNT0 0x1504 161 #define RT2860_CCMP_FC_MUTE 0x1508 162 163 /* MAC HCCA/PSMP configuration registers */ 164 #define RT2860_TXOP_HLDR_ADDR0 0x1600 165 #define RT2860_TXOP_HLDR_ADDR1 0x1604 166 #define RT2860_TXOP_HLDR_ET 0x1608 167 #define RT2860_QOS_CFPOLL_RA_DW0 0x160c 168 #define RT2860_QOS_CFPOLL_A1_DW1 0x1610 169 #define RT2860_QOS_CFPOLL_QC 0x1614 170 171 /* MAC Statistics Counters */ 172 #define RT2860_RX_STA_CNT0 0x1700 173 #define RT2860_RX_STA_CNT1 0x1704 174 #define RT2860_RX_STA_CNT2 0x1708 175 #define RT2860_TX_STA_CNT0 0x170c 176 #define RT2860_TX_STA_CNT1 0x1710 177 #define RT2860_TX_STA_CNT2 0x1714 178 #define RT2860_TX_STAT_FIFO 0x1718 179 180 /* RX WCID search table */ 181 #define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) 182 183 #define RT2860_FW_BASE 0x2000 184 #define RT2870_FW_BASE 0x3000 185 186 /* Pair-wise key table */ 187 #define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32) 188 189 /* IV/EIV table */ 190 #define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8) 191 192 /* WCID attribute table */ 193 #define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) 194 195 /* Shared Key Table */ 196 #define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32) 197 198 /* Shared Key Mode */ 199 #define RT2860_SKEY_MODE_0_7 0x7000 200 #define RT2860_SKEY_MODE_8_15 0x7004 201 #define RT2860_SKEY_MODE_16_23 0x7008 202 #define RT2860_SKEY_MODE_24_31 0x700c 203 204 /* Shared Memory between MCU and host */ 205 #define RT2860_H2M_MAILBOX 0x7010 206 #define RT2860_H2M_MAILBOX_CID 0x7014 207 #define RT2860_H2M_MAILBOX_STATUS 0x701c 208 #define RT2860_H2M_INTSRC 0x7024 209 #define RT2860_H2M_BBPAGENT 0x7028 210 #define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512) 211 212 213 /* possible flags for register RT2860_PCI_EECTRL */ 214 #define RT2860_C (1 << 0) 215 #define RT2860_S (1 << 1) 216 #define RT2860_D (1 << 2) 217 #define RT2860_SHIFT_D 2 218 #define RT2860_Q (1 << 3) 219 #define RT2860_SHIFT_Q 3 220 221 /* possible flags for registers INT_STATUS/INT_MASK */ 222 #define RT2860_TX_COHERENT (1 << 17) 223 #define RT2860_RX_COHERENT (1 << 16) 224 #define RT2860_MAC_INT_4 (1 << 15) 225 #define RT2860_MAC_INT_3 (1 << 14) 226 #define RT2860_MAC_INT_2 (1 << 13) 227 #define RT2860_MAC_INT_1 (1 << 12) 228 #define RT2860_MAC_INT_0 (1 << 11) 229 #define RT2860_TX_RX_COHERENT (1 << 10) 230 #define RT2860_MCU_CMD_INT (1 << 9) 231 #define RT2860_TX_DONE_INT5 (1 << 8) 232 #define RT2860_TX_DONE_INT4 (1 << 7) 233 #define RT2860_TX_DONE_INT3 (1 << 6) 234 #define RT2860_TX_DONE_INT2 (1 << 5) 235 #define RT2860_TX_DONE_INT1 (1 << 4) 236 #define RT2860_TX_DONE_INT0 (1 << 3) 237 #define RT2860_RX_DONE_INT (1 << 2) 238 #define RT2860_TX_DLY_INT (1 << 1) 239 #define RT2860_RX_DLY_INT (1 << 0) 240 241 /* possible flags for register WPDMA_GLO_CFG */ 242 #define RT2860_HDR_SEG_LEN_SHIFT 8 243 #define RT2860_BIG_ENDIAN (1 << 7) 244 #define RT2860_TX_WB_DDONE (1 << 6) 245 #define RT2860_WPDMA_BT_SIZE_SHIFT 4 246 #define RT2860_WPDMA_BT_SIZE16 0 247 #define RT2860_WPDMA_BT_SIZE32 1 248 #define RT2860_WPDMA_BT_SIZE64 2 249 #define RT2860_WPDMA_BT_SIZE128 3 250 #define RT2860_RX_DMA_BUSY (1 << 3) 251 #define RT2860_RX_DMA_EN (1 << 2) 252 #define RT2860_TX_DMA_BUSY (1 << 1) 253 #define RT2860_TX_DMA_EN (1 << 0) 254 255 /* possible flags for register DELAY_INT_CFG */ 256 #define RT2860_TXDLY_INT_EN (1U << 31) 257 #define RT2860_TXMAX_PINT_SHIFT 24 258 #define RT2860_TXMAX_PTIME_SHIFT 16 259 #define RT2860_RXDLY_INT_EN (1 << 15) 260 #define RT2860_RXMAX_PINT_SHIFT 8 261 #define RT2860_RXMAX_PTIME_SHIFT 0 262 263 /* possible flags for register GPIO_CTRL */ 264 #define RT2860_GPIO_D_SHIFT 8 265 #define RT2860_GPIO_O_SHIFT 0 266 267 /* possible flags for register USB_DMA_CFG */ 268 #define RT2860_USB_TX_BUSY (1U << 31) 269 #define RT2860_USB_RX_BUSY (1 << 30) 270 #define RT2860_USB_EPOUT_VLD_SHIFT 24 271 #define RT2860_USB_TX_EN (1 << 23) 272 #define RT2860_USB_RX_EN (1 << 22) 273 #define RT2860_USB_RX_AGG_EN (1 << 21) 274 #define RT2860_USB_TXOP_HALT (1 << 20) 275 #define RT2860_USB_TX_CLEAR (1 << 19) 276 #define RT2860_USB_PHY_WD_EN (1 << 16) 277 #define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ 278 #define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ 279 280 /* possible flags for register US_CYC_CNT */ 281 #define RT2860_TEST_EN (1 << 24) 282 #define RT2860_TEST_SEL_SHIFT 16 283 #define RT2860_BT_MODE_EN (1 << 8) 284 #define RT2860_US_CYC_CNT_SHIFT 0 285 286 /* possible flags for register SYS_CTRL */ 287 #define RT2860_HST_PM_SEL (1 << 16) 288 #define RT2860_CAP_MODE (1 << 14) 289 #define RT2860_PME_OEN (1 << 13) 290 #define RT2860_CLKSELECT (1 << 12) 291 #define RT2860_PBF_CLK_EN (1 << 11) 292 #define RT2860_MAC_CLK_EN (1 << 10) 293 #define RT2860_DMA_CLK_EN (1 << 9) 294 #define RT2860_MCU_READY (1 << 7) 295 #define RT2860_ASY_RESET (1 << 4) 296 #define RT2860_PBF_RESET (1 << 3) 297 #define RT2860_MAC_RESET (1 << 2) 298 #define RT2860_DMA_RESET (1 << 1) 299 #define RT2860_MCU_RESET (1 << 0) 300 301 /* possible values for register HOST_CMD */ 302 #define RT2860_MCU_CMD_SLEEP 0x30 303 #define RT2860_MCU_CMD_WAKEUP 0x31 304 #define RT2860_MCU_CMD_LEDS 0x50 305 #define RT2860_MCU_CMD_LED_RSSI 0x51 306 #define RT2860_MCU_CMD_LED1 0x52 307 #define RT2860_MCU_CMD_LED2 0x53 308 #define RT2860_MCU_CMD_LED3 0x54 309 #define RT2860_MCU_CMD_RFRESET 0x72 310 #define RT2860_MCU_CMD_ANTSEL 0x73 311 #define RT2860_MCU_CMD_BBP 0x80 312 #define RT2860_MCU_CMD_PSLEVEL 0x83 313 314 /* possible flags for register PBF_CFG */ 315 #define RT2860_TX1Q_NUM_SHIFT 21 316 #define RT2860_TX2Q_NUM_SHIFT 16 317 #define RT2860_NULL0_MODE (1 << 15) 318 #define RT2860_NULL1_MODE (1 << 14) 319 #define RT2860_RX_DROP_MODE (1 << 13) 320 #define RT2860_TX0Q_MANUAL (1 << 12) 321 #define RT2860_TX1Q_MANUAL (1 << 11) 322 #define RT2860_TX2Q_MANUAL (1 << 10) 323 #define RT2860_RX0Q_MANUAL (1 << 9) 324 #define RT2860_HCCA_EN (1 << 8) 325 #define RT2860_TX0Q_EN (1 << 4) 326 #define RT2860_TX1Q_EN (1 << 3) 327 #define RT2860_TX2Q_EN (1 << 2) 328 #define RT2860_RX0Q_EN (1 << 1) 329 330 /* possible flags for register BUF_CTRL */ 331 #define RT2860_WRITE_TXQ(qid) (1 << (11 - (qid))) 332 #define RT2860_NULL0_KICK (1 << 7) 333 #define RT2860_NULL1_KICK (1 << 6) 334 #define RT2860_BUF_RESET (1 << 5) 335 #define RT2860_READ_TXQ(qid) (1 << (3 - (qid)) 336 #define RT2860_READ_RX0Q (1 << 0) 337 338 /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */ 339 #define RT2860_MCU_MAC_INT_8 (1 << 24) 340 #define RT2860_MCU_MAC_INT_7 (1 << 23) 341 #define RT2860_MCU_MAC_INT_6 (1 << 22) 342 #define RT2860_MCU_MAC_INT_4 (1 << 20) 343 #define RT2860_MCU_MAC_INT_3 (1 << 19) 344 #define RT2860_MCU_MAC_INT_2 (1 << 18) 345 #define RT2860_MCU_MAC_INT_1 (1 << 17) 346 #define RT2860_MCU_MAC_INT_0 (1 << 16) 347 #define RT2860_DTX0_INT (1 << 11) 348 #define RT2860_DTX1_INT (1 << 10) 349 #define RT2860_DTX2_INT (1 << 9) 350 #define RT2860_DRX0_INT (1 << 8) 351 #define RT2860_HCMD_INT (1 << 7) 352 #define RT2860_N0TX_INT (1 << 6) 353 #define RT2860_N1TX_INT (1 << 5) 354 #define RT2860_BCNTX_INT (1 << 4) 355 #define RT2860_MTX0_INT (1 << 3) 356 #define RT2860_MTX1_INT (1 << 2) 357 #define RT2860_MTX2_INT (1 << 1) 358 #define RT2860_MRX0_INT (1 << 0) 359 360 /* possible flags for register TXRXQ_PCNT */ 361 #define RT2860_RX0Q_PCNT_MASK 0xff000000 362 #define RT2860_TX2Q_PCNT_MASK 0x00ff0000 363 #define RT2860_TX1Q_PCNT_MASK 0x0000ff00 364 #define RT2860_TX0Q_PCNT_MASK 0x000000ff 365 366 /* possible flags for register CAP_CTRL */ 367 #define RT2860_CAP_ADC_FEQ (1U << 31) 368 #define RT2860_CAP_START (1 << 30) 369 #define RT2860_MAN_TRIG (1 << 29) 370 #define RT2860_TRIG_OFFSET_SHIFT 16 371 #define RT2860_START_ADDR_SHIFT 0 372 373 /* possible flags for register RF_CSR_CFG */ 374 #define RT3070_RF_KICK (1 << 17) 375 #define RT3070_RF_WRITE (1 << 16) 376 377 /* possible flags for register EFUSE_CTRL */ 378 #define RT3070_SEL_EFUSE (1U << 31) 379 #define RT3070_EFSROM_KICK (1 << 30) 380 #define RT3070_EFSROM_AIN_MASK 0x03ff0000 381 #define RT3070_EFSROM_AIN_SHIFT 16 382 #define RT3070_EFSROM_MODE_MASK 0x000000c0 383 #define RT3070_EFUSE_AOUT_MASK 0x0000003f 384 385 /* possible flag for register DEBUG_INDEX */ 386 #define RT5592_SEL_XTAL (1U << 31) 387 388 /* possible flags for register MAC_SYS_CTRL */ 389 #define RT2860_RX_TS_EN (1 << 7) 390 #define RT2860_WLAN_HALT_EN (1 << 6) 391 #define RT2860_PBF_LOOP_EN (1 << 5) 392 #define RT2860_CONT_TX_TEST (1 << 4) 393 #define RT2860_MAC_RX_EN (1 << 3) 394 #define RT2860_MAC_TX_EN (1 << 2) 395 #define RT2860_BBP_HRST (1 << 1) 396 #define RT2860_MAC_SRST (1 << 0) 397 398 /* possible flags for register MAC_BSSID_DW1 */ 399 #define RT2860_MULTI_BCN_NUM_SHIFT 18 400 #define RT2860_MULTI_BSSID_MODE_SHIFT 16 401 402 /* possible flags for register MAX_LEN_CFG */ 403 #define RT2860_MIN_MPDU_LEN_SHIFT 16 404 #define RT2860_MAX_PSDU_LEN_SHIFT 12 405 #define RT2860_MAX_PSDU_LEN8K 0 406 #define RT2860_MAX_PSDU_LEN16K 1 407 #define RT2860_MAX_PSDU_LEN32K 2 408 #define RT2860_MAX_PSDU_LEN64K 3 409 #define RT2860_MAX_MPDU_LEN_SHIFT 0 410 411 /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */ 412 #define RT2860_BBP_RW_PARALLEL (1 << 19) 413 #define RT2860_BBP_PAR_DUR_112_5 (1 << 18) 414 #define RT2860_BBP_CSR_KICK (1 << 17) 415 #define RT2860_BBP_CSR_READ (1 << 16) 416 #define RT2860_BBP_ADDR_SHIFT 8 417 #define RT2860_BBP_DATA_SHIFT 0 418 419 /* possible flags for register RF_CSR_CFG0 */ 420 #define RT2860_RF_REG_CTRL (1U << 31) 421 #define RT2860_RF_LE_SEL1 (1 << 30) 422 #define RT2860_RF_LE_STBY (1 << 29) 423 #define RT2860_RF_REG_WIDTH_SHIFT 24 424 #define RT2860_RF_REG_0_SHIFT 0 425 426 /* possible flags for register RF_CSR_CFG1 */ 427 #define RT2860_RF_DUR_5 (1 << 24) 428 #define RT2860_RF_REG_1_SHIFT 0 429 430 /* possible flags for register LED_CFG */ 431 #define RT2860_LED_POL (1 << 30) 432 #define RT2860_Y_LED_MODE_SHIFT 28 433 #define RT2860_G_LED_MODE_SHIFT 26 434 #define RT2860_R_LED_MODE_SHIFT 24 435 #define RT2860_LED_MODE_OFF 0 436 #define RT2860_LED_MODE_BLINK_TX 1 437 #define RT2860_LED_MODE_SLOW_BLINK 2 438 #define RT2860_LED_MODE_ON 3 439 #define RT2860_SLOW_BLK_TIME_SHIFT 16 440 #define RT2860_LED_OFF_TIME_SHIFT 8 441 #define RT2860_LED_ON_TIME_SHIFT 0 442 443 /* possible flags for register XIFS_TIME_CFG */ 444 #define RT2860_BB_RXEND_EN (1 << 29) 445 #define RT2860_EIFS_TIME_SHIFT 20 446 #define RT2860_OFDM_XIFS_TIME_SHIFT 16 447 #define RT2860_OFDM_SIFS_TIME_SHIFT 8 448 #define RT2860_CCK_SIFS_TIME_SHIFT 0 449 450 /* possible flags for register BKOFF_SLOT_CFG */ 451 #define RT2860_CC_DELAY_TIME_SHIFT 8 452 #define RT2860_SLOT_TIME 0 453 454 /* possible flags for register NAV_TIME_CFG */ 455 #define RT2860_NAV_UPD (1U << 31) 456 #define RT2860_NAV_UPD_VAL_SHIFT 16 457 #define RT2860_NAV_CLR_EN (1 << 15) 458 #define RT2860_NAV_TIMER_SHIFT 0 459 460 /* possible flags for register CH_TIME_CFG */ 461 #define RT2860_EIFS_AS_CH_BUSY (1 << 4) 462 #define RT2860_NAV_AS_CH_BUSY (1 << 3) 463 #define RT2860_RX_AS_CH_BUSY (1 << 2) 464 #define RT2860_TX_AS_CH_BUSY (1 << 1) 465 #define RT2860_CH_STA_TIMER_EN (1 << 0) 466 467 /* possible values for register BCN_TIME_CFG */ 468 #define RT2860_TSF_INS_COMP_SHIFT 24 469 #define RT2860_BCN_TX_EN (1 << 20) 470 #define RT2860_TBTT_TIMER_EN (1 << 19) 471 #define RT2860_TSF_SYNC_MODE_SHIFT 17 472 #define RT2860_TSF_SYNC_MODE_DIS 0 473 #define RT2860_TSF_SYNC_MODE_STA 1 474 #define RT2860_TSF_SYNC_MODE_IBSS 2 475 #define RT2860_TSF_SYNC_MODE_HOSTAP 3 476 #define RT2860_TSF_TIMER_EN (1 << 16) 477 #define RT2860_BCN_INTVAL_SHIFT 0 478 479 /* possible flags for register TBTT_SYNC_CFG */ 480 #define RT2860_BCN_CWMIN_SHIFT 20 481 #define RT2860_BCN_AIFSN_SHIFT 16 482 #define RT2860_BCN_EXP_WIN_SHIFT 8 483 #define RT2860_TBTT_ADJUST_SHIFT 0 484 485 /* possible flags for register INT_TIMER_CFG */ 486 #define RT2860_GP_TIMER_SHIFT 16 487 #define RT2860_PRE_TBTT_TIMER_SHIFT 0 488 489 /* possible flags for register INT_TIMER_EN */ 490 #define RT2860_GP_TIMER_EN (1 << 1) 491 #define RT2860_PRE_TBTT_INT_EN (1 << 0) 492 493 /* possible flags for register MAC_STATUS_REG */ 494 #define RT2860_RX_STATUS_BUSY (1 << 1) 495 #define RT2860_TX_STATUS_BUSY (1 << 0) 496 497 /* possible flags for register PWR_PIN_CFG */ 498 #define RT2860_IO_ADDA_PD (1 << 3) 499 #define RT2860_IO_PLL_PD (1 << 2) 500 #define RT2860_IO_RA_PE (1 << 1) 501 #define RT2860_IO_RF_PE (1 << 0) 502 503 /* possible flags for register AUTO_WAKEUP_CFG */ 504 #define RT2860_AUTO_WAKEUP_EN (1 << 15) 505 #define RT2860_SLEEP_TBTT_NUM_SHIFT 8 506 #define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 507 508 /* possible flags for register TX_PIN_CFG */ 509 #define RT2860_TRSW_POL (1 << 19) 510 #define RT2860_TRSW_EN (1 << 18) 511 #define RT2860_RFTR_POL (1 << 17) 512 #define RT2860_RFTR_EN (1 << 16) 513 #define RT2860_LNA_PE_G1_POL (1 << 15) 514 #define RT2860_LNA_PE_A1_POL (1 << 14) 515 #define RT2860_LNA_PE_G0_POL (1 << 13) 516 #define RT2860_LNA_PE_A0_POL (1 << 12) 517 #define RT2860_LNA_PE_G1_EN (1 << 11) 518 #define RT2860_LNA_PE_A1_EN (1 << 10) 519 #define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) 520 #define RT2860_LNA_PE_G0_EN (1 << 9) 521 #define RT2860_LNA_PE_A0_EN (1 << 8) 522 #define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) 523 #define RT2860_PA_PE_G1_POL (1 << 7) 524 #define RT2860_PA_PE_A1_POL (1 << 6) 525 #define RT2860_PA_PE_G0_POL (1 << 5) 526 #define RT2860_PA_PE_A0_POL (1 << 4) 527 #define RT2860_PA_PE_G1_EN (1 << 3) 528 #define RT2860_PA_PE_A1_EN (1 << 2) 529 #define RT2860_PA_PE_G0_EN (1 << 1) 530 #define RT2860_PA_PE_A0_EN (1 << 0) 531 532 /* possible flags for register TX_BAND_CFG */ 533 #define RT2860_5G_BAND_SEL_N (1 << 2) 534 #define RT2860_5G_BAND_SEL_P (1 << 1) 535 #define RT2860_TX_BAND_SEL (1 << 0) 536 537 /* possible flags for register TX_SW_CFG0 */ 538 #define RT2860_DLY_RFTR_EN_SHIFT 24 539 #define RT2860_DLY_TRSW_EN_SHIFT 16 540 #define RT2860_DLY_PAPE_EN_SHIFT 8 541 #define RT2860_DLY_TXPE_EN_SHIFT 0 542 543 /* possible flags for register TX_SW_CFG1 */ 544 #define RT2860_DLY_RFTR_DIS_SHIFT 16 545 #define RT2860_DLY_TRSW_DIS_SHIFT 8 546 #define RT2860_DLY_PAPE_DIS SHIFT 0 547 548 /* possible flags for register TX_SW_CFG2 */ 549 #define RT2860_DLY_LNA_EN_SHIFT 24 550 #define RT2860_DLY_LNA_DIS_SHIFT 16 551 #define RT2860_DLY_DAC_EN_SHIFT 8 552 #define RT2860_DLY_DAC_DIS_SHIFT 0 553 554 /* possible flags for register TXOP_THRES_CFG */ 555 #define RT2860_TXOP_REM_THRES_SHIFT 24 556 #define RT2860_CF_END_THRES_SHIFT 16 557 #define RT2860_RDG_IN_THRES 8 558 #define RT2860_RDG_OUT_THRES 0 559 560 /* possible flags for register TXOP_CTRL_CFG */ 561 #define RT2860_EXT_CW_MIN_SHIFT 16 562 #define RT2860_EXT_CCA_DLY_SHIFT 8 563 #define RT2860_EXT_CCA_EN (1 << 7) 564 #define RT2860_LSIG_TXOP_EN (1 << 6) 565 #define RT2860_TXOP_TRUN_EN_MIMOPS (1 << 4) 566 #define RT2860_TXOP_TRUN_EN_TXOP (1 << 3) 567 #define RT2860_TXOP_TRUN_EN_RATE (1 << 2) 568 #define RT2860_TXOP_TRUN_EN_AC (1 << 1) 569 #define RT2860_TXOP_TRUN_EN_TIMEOUT (1 << 0) 570 571 /* possible flags for register TX_RTS_CFG */ 572 #define RT2860_RTS_FBK_EN (1 << 24) 573 #define RT2860_RTS_THRES_SHIFT 8 574 #define RT2860_RTS_RTY_LIMIT_SHIFT 0 575 576 /* possible flags for register TX_TIMEOUT_CFG */ 577 #define RT2860_TXOP_TIMEOUT_SHIFT 16 578 #define RT2860_RX_ACK_TIMEOUT_SHIFT 8 579 #define RT2860_MPDU_LIFE_TIME_SHIFT 4 580 581 /* possible flags for register TX_RTY_CFG */ 582 #define RT2860_TX_AUTOFB_EN (1 << 30) 583 #define RT2860_AGG_RTY_MODE_TIMER (1 << 29) 584 #define RT2860_NAG_RTY_MODE_TIMER (1 << 28) 585 #define RT2860_LONG_RTY_THRES_SHIFT 16 586 #define RT2860_LONG_RTY_LIMIT_SHIFT 8 587 #define RT2860_SHORT_RTY_LIMIT_SHIFT 0 588 589 /* possible flags for register TX_LINK_CFG */ 590 #define RT2860_REMOTE_MFS_SHIFT 24 591 #define RT2860_REMOTE_MFB_SHIFT 16 592 #define RT2860_TX_CFACK_EN (1 << 12) 593 #define RT2860_TX_RDG_EN (1 << 11) 594 #define RT2860_TX_MRQ_EN (1 << 10) 595 #define RT2860_REMOTE_UMFS_EN (1 << 9) 596 #define RT2860_TX_MFB_EN (1 << 8) 597 #define RT2860_REMOTE_MFB_LT_SHIFT 0 598 599 /* possible flags for registers *_PROT_CFG */ 600 #define RT2860_RTSTH_EN (1 << 26) 601 #define RT2860_TXOP_ALLOW_GF40 (1 << 25) 602 #define RT2860_TXOP_ALLOW_GF20 (1 << 24) 603 #define RT2860_TXOP_ALLOW_MM40 (1 << 23) 604 #define RT2860_TXOP_ALLOW_MM20 (1 << 22) 605 #define RT2860_TXOP_ALLOW_OFDM (1 << 21) 606 #define RT2860_TXOP_ALLOW_CCK (1 << 20) 607 #define RT2860_TXOP_ALLOW_ALL (0x3f << 20) 608 #define RT2860_PROT_NAV_SHORT (1 << 18) 609 #define RT2860_PROT_NAV_LONG (2 << 18) 610 #define RT2860_PROT_CTRL_RTS_CTS (1 << 16) 611 #define RT2860_PROT_CTRL_CTS (2 << 16) 612 613 /* possible flags for registers EXP_{CTS,ACK}_TIME */ 614 #define RT2860_EXP_OFDM_TIME_SHIFT 16 615 #define RT2860_EXP_CCK_TIME_SHIFT 0 616 617 /* possible flags for register RX_FILTR_CFG */ 618 #define RT2860_DROP_CTRL_RSV (1 << 16) 619 #define RT2860_DROP_BAR (1 << 15) 620 #define RT2860_DROP_BA (1 << 14) 621 #define RT2860_DROP_PSPOLL (1 << 13) 622 #define RT2860_DROP_RTS (1 << 12) 623 #define RT2860_DROP_CTS (1 << 11) 624 #define RT2860_DROP_ACK (1 << 10) 625 #define RT2860_DROP_CFEND (1 << 9) 626 #define RT2860_DROP_CFACK (1 << 8) 627 #define RT2860_DROP_DUPL (1 << 7) 628 #define RT2860_DROP_BC (1 << 6) 629 #define RT2860_DROP_MC (1 << 5) 630 #define RT2860_DROP_VER_ERR (1 << 4) 631 #define RT2860_DROP_NOT_MYBSS (1 << 3) 632 #define RT2860_DROP_UC_NOME (1 << 2) 633 #define RT2860_DROP_PHY_ERR (1 << 1) 634 #define RT2860_DROP_CRC_ERR (1 << 0) 635 636 /* possible flags for register AUTO_RSP_CFG */ 637 #define RT2860_CTRL_PWR_BIT (1 << 7) 638 #define RT2860_BAC_ACK_POLICY (1 << 6) 639 #define RT2860_CCK_SHORT_EN (1 << 4) 640 #define RT2860_CTS_40M_REF_EN (1 << 3) 641 #define RT2860_CTS_40M_MODE_EN (1 << 2) 642 #define RT2860_BAC_ACKPOLICY_EN (1 << 1) 643 #define RT2860_AUTO_RSP_EN (1 << 0) 644 645 /* possible flags for register SIFS_COST_CFG */ 646 #define RT2860_OFDM_SIFS_COST_SHIFT 8 647 #define RT2860_CCK_SIFS_COST_SHIFT 0 648 649 /* possible flags for register TXOP_HLDR_ET */ 650 #define RT2860_TXOP_ETM1_EN (1 << 25) 651 #define RT2860_TXOP_ETM0_EN (1 << 24) 652 #define RT2860_TXOP_ETM_THRES_SHIFT 16 653 #define RT2860_TXOP_ETO_EN (1 << 8) 654 #define RT2860_TXOP_ETO_THRES_SHIFT 1 655 #define RT2860_PER_RX_RST_EN (1 << 0) 656 657 /* possible flags for register TX_STAT_FIFO */ 658 #define RT2860_TXQ_MCS_SHIFT 16 659 #define RT2860_TXQ_WCID_SHIFT 8 660 #define RT2860_TXQ_ACKREQ (1 << 7) 661 #define RT2860_TXQ_AGG (1 << 6) 662 #define RT2860_TXQ_OK (1 << 5) 663 #define RT2860_TXQ_PID_SHIFT 1 664 #define RT2860_TXQ_VLD (1 << 0) 665 666 /* possible flags for register WCID_ATTR */ 667 #define RT2860_MODE_NOSEC 0 668 #define RT2860_MODE_WEP40 1 669 #define RT2860_MODE_WEP104 2 670 #define RT2860_MODE_TKIP 3 671 #define RT2860_MODE_AES_CCMP 4 672 #define RT2860_MODE_CKIP40 5 673 #define RT2860_MODE_CKIP104 6 674 #define RT2860_MODE_CKIP128 7 675 #define RT2860_RX_PKEY_EN (1 << 0) 676 677 /* possible flags for register H2M_MAILBOX */ 678 #define RT2860_H2M_BUSY (1 << 24) 679 #define RT2860_TOKEN_NO_INTR 0xff 680 681 /* possible flags for MCU command RT2860_MCU_CMD_LEDS */ 682 #define RT2860_LED_RADIO (1 << 13) 683 #define RT2860_LED_LINK_2GHZ (1 << 14) 684 #define RT2860_LED_LINK_5GHZ (1 << 15) 685 686 /* possible flags for RT3020 RF register 1 */ 687 #define RT3070_RF_BLOCK (1 << 0) 688 #define RT3070_PLL_PD (1 << 1) 689 #define RT3070_RX0_PD (1 << 2) 690 #define RT3070_TX0_PD (1 << 3) 691 #define RT3070_RX1_PD (1 << 4) 692 #define RT3070_TX1_PD (1 << 5) 693 #define RT3070_RX2_PD (1 << 6) 694 #define RT3070_TX2_PD (1 << 7) 695 696 /* possible flags for RT3020 RF register 15 */ 697 #define RT3070_TX_LO2 (1 << 3) 698 699 /* possible flags for RT3020 RF register 17 */ 700 #define RT3070_TX_LO1 (1 << 3) 701 702 /* possible flags for RT3020 RF register 20 */ 703 #define RT3070_RX_LO1 (1 << 3) 704 705 /* possible flags for RT3020 RF register 21 */ 706 #define RT3070_RX_LO2 (1 << 3) 707 708 /* possible flags for RT3053 RF register 18 */ 709 #define RT3593_AUTOTUNE_BYPASS (1 << 6) 710 711 /* possible flags for RT3053 RF register 50 */ 712 #define RT3593_TX_LO2 (1 << 4) 713 714 /* possible flags for RT3053 RF register 51 */ 715 #define RT3593_TX_LO1 (1 << 4) 716 717 /* Possible flags for RT5390 RF register 2. */ 718 #define RT5390_RESCAL (1 << 7) 719 720 /* Possible flags for RT5390 RF register 3. */ 721 #define RT5390_VCOCAL (1 << 7) 722 723 /* Possible flags for RT5390 RF register 38. */ 724 #define RT5390_RX_LO1 (1 << 5) 725 726 /* Possible flags for RT5390 RF register 39. */ 727 #define RT5390_RX_LO2 (1 << 7) 728 729 /* Possible flags for RT5390 BBP register 4. */ 730 #define RT5390_MAC_IF_CTRL (1 << 6) 731 732 /* Possible flags for RT5390 BBP register 105. */ 733 #define RT5390_MLD (1 << 2) 734 #define RT5390_EN_SIG_MODULATION (1 << 3) 735 736 /* RT2860 TX descriptor */ 737 struct rt2860_txd { 738 uint32_t sdp0; /* Segment Data Pointer 0 */ 739 uint16_t sdl1; /* Segment Data Length 1 */ 740 #define RT2860_TX_BURST (1 << 15) 741 #define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */ 742 743 uint16_t sdl0; /* Segment Data Length 0 */ 744 #define RT2860_TX_DDONE (1 << 15) 745 #define RT2860_TX_LS0 (1 << 14) /* SDP0 is the last segment */ 746 747 uint32_t sdp1; /* Segment Data Pointer 1 */ 748 uint8_t reserved[3]; 749 uint8_t flags; 750 #define RT2860_TX_QSEL_SHIFT 1 751 #define RT2860_TX_QSEL_MGMT (0 << 1) 752 #define RT2860_TX_QSEL_HCCA (1 << 1) 753 #define RT2860_TX_QSEL_EDCA (2 << 1) 754 #define RT2860_TX_WIV (1 << 0) 755 } __packed; 756 757 /* RT2870 TX descriptor */ 758 struct rt2870_txd { 759 uint16_t len; 760 uint8_t pad; 761 uint8_t flags; 762 } __packed; 763 764 /* TX Wireless Information */ 765 struct rt2860_txwi { 766 uint8_t flags; 767 #define RT2860_TX_MPDU_DSITY_SHIFT 5 768 #define RT2860_TX_AMPDU (1 << 4) 769 #define RT2860_TX_TS (1 << 3) 770 #define RT2860_TX_CFACK (1 << 2) 771 #define RT2860_TX_MMPS (1 << 1) 772 #define RT2860_TX_FRAG (1 << 0) 773 774 uint8_t txop; 775 #define RT2860_TX_TXOP_HT 0 776 #define RT2860_TX_TXOP_PIFS 1 777 #define RT2860_TX_TXOP_SIFS 2 778 #define RT2860_TX_TXOP_BACKOFF 3 779 780 uint16_t phy; 781 #define RT2860_PHY_MODE 0xc000 782 #define RT2860_PHY_CCK (0 << 14) 783 #define RT2860_PHY_OFDM (1 << 14) 784 #define RT2860_PHY_HT (2 << 14) 785 #define RT2860_PHY_HT_GF (3 << 14) 786 #define RT2860_PHY_SGI (1 << 8) 787 #define RT2860_PHY_BW40 (1 << 7) 788 #define RT2860_PHY_MCS 0x7f 789 #define RT2860_PHY_SHPRE (1 << 3) 790 791 uint8_t xflags; 792 #define RT2860_TX_BAWINSIZE_SHIFT 2 793 #define RT2860_TX_NSEQ (1 << 1) 794 #define RT2860_TX_ACK (1 << 0) 795 796 uint8_t wcid; /* Wireless Client ID */ 797 uint16_t len; 798 #define RT2860_TX_PID_SHIFT 12 799 800 uint32_t iv; 801 uint32_t eiv; 802 } __packed; 803 804 /* RT2860 RX descriptor */ 805 struct rt2860_rxd { 806 uint32_t sdp0; 807 uint16_t sdl1; /* unused */ 808 uint16_t sdl0; 809 #define RT2860_RX_DDONE (1 << 15) 810 #define RT2860_RX_LS0 (1 << 14) 811 812 uint32_t sdp1; /* unused */ 813 uint32_t flags; 814 #define RT2860_RX_DEC (1 << 16) 815 #define RT2860_RX_AMPDU (1 << 15) 816 #define RT2860_RX_L2PAD (1 << 14) 817 #define RT2860_RX_RSSI (1 << 13) 818 #define RT2860_RX_HTC (1 << 12) 819 #define RT2860_RX_AMSDU (1 << 11) 820 #define RT2860_RX_MICERR (1 << 10) 821 #define RT2860_RX_ICVERR (1 << 9) 822 #define RT2860_RX_CRCERR (1 << 8) 823 #define RT2860_RX_MYBSS (1 << 7) 824 #define RT2860_RX_BC (1 << 6) 825 #define RT2860_RX_MC (1 << 5) 826 #define RT2860_RX_UC2ME (1 << 4) 827 #define RT2860_RX_FRAG (1 << 3) 828 #define RT2860_RX_NULL (1 << 2) 829 #define RT2860_RX_DATA (1 << 1) 830 #define RT2860_RX_BA (1 << 0) 831 } __packed; 832 833 /* RT2870 RX descriptor */ 834 struct rt2870_rxd { 835 /* single 32-bit field */ 836 uint32_t flags; 837 } __packed; 838 839 /* RX Wireless Information */ 840 struct rt2860_rxwi { 841 uint8_t wcid; 842 uint8_t keyidx; 843 #define RT2860_RX_UDF_SHIFT 5 844 #define RT2860_RX_BSS_IDX_SHIFT 2 845 846 uint16_t len; 847 #define RT2860_RX_TID_SHIFT 12 848 849 uint16_t seq; 850 uint16_t phy; 851 uint8_t rssi[3]; 852 uint8_t reserved1; 853 uint8_t snr[2]; 854 uint16_t reserved2; 855 } __packed; 856 857 #define RT2860_RF_2820 0x0001 /* 2T3R */ 858 #define RT2860_RF_2850 0x0002 /* dual-band 2T3R */ 859 #define RT2860_RF_2720 0x0003 /* 1T2R */ 860 #define RT2860_RF_2750 0x0004 /* dual-band 1T2R */ 861 #define RT3070_RF_3020 0x0005 /* 1T1R */ 862 #define RT3070_RF_2020 0x0006 /* b/g */ 863 #define RT3070_RF_3021 0x0007 /* 1T2R */ 864 #define RT3070_RF_3022 0x0008 /* 2T2R */ 865 #define RT3070_RF_3052 0x0009 /* dual-band 2T2R */ 866 #define RT3593_RF_3053 0x000d /* dual-band 3T3R */ 867 #define RT5592_RF_5592 0x000f /* dual-band 2T2R */ 868 #define RT5390_RF_5370 0x5370 /* 1T1R */ 869 #define RT5390_RF_5372 0x5372 /* 2T2R */ 870 871 /* USB commands for RT2870 only */ 872 #define RT2870_RESET 1 873 #define RT2870_WRITE_2 2 874 #define RT2870_WRITE_REGION_1 6 875 #define RT2870_READ_REGION_1 7 876 #define RT2870_EEPROM_READ 9 877 878 #define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 879 880 #define RT2860_EEPROM_VERSION 0x01 881 #define RT2860_EEPROM_MAC01 0x02 882 #define RT2860_EEPROM_MAC23 0x03 883 #define RT2860_EEPROM_MAC45 0x04 884 #define RT2860_EEPROM_PCIE_PSLEVEL 0x11 885 #define RT2860_EEPROM_REV 0x12 886 #define RT2860_EEPROM_ANTENNA 0x1a 887 #define RT2860_EEPROM_CONFIG 0x1b 888 #define RT2860_EEPROM_COUNTRY 0x1c 889 #define RT2860_EEPROM_FREQ_LEDS 0x1d 890 #define RT2860_EEPROM_LED1 0x1e 891 #define RT2860_EEPROM_LED2 0x1f 892 #define RT2860_EEPROM_LED3 0x20 893 #define RT2860_EEPROM_LNA 0x22 894 #define RT2860_EEPROM_RSSI1_2GHZ 0x23 895 #define RT2860_EEPROM_RSSI2_2GHZ 0x24 896 #define RT2860_EEPROM_RSSI1_5GHZ 0x25 897 #define RT2860_EEPROM_RSSI2_5GHZ 0x26 898 #define RT2860_EEPROM_DELTAPWR 0x28 899 #define RT2860_EEPROM_PWR2GHZ_BASE1 0x29 900 #define RT2860_EEPROM_PWR2GHZ_BASE2 0x30 901 #define RT2860_EEPROM_TSSI1_2GHZ 0x37 902 #define RT2860_EEPROM_TSSI2_2GHZ 0x38 903 #define RT2860_EEPROM_TSSI3_2GHZ 0x39 904 #define RT2860_EEPROM_TSSI4_2GHZ 0x3a 905 #define RT2860_EEPROM_TSSI5_2GHZ 0x3b 906 #define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c 907 #define RT2860_EEPROM_PWR5GHZ_BASE2 0x53 908 #define RT2860_EEPROM_TSSI1_5GHZ 0x6a 909 #define RT2860_EEPROM_TSSI2_5GHZ 0x6b 910 #define RT2860_EEPROM_TSSI3_5GHZ 0x6c 911 #define RT2860_EEPROM_TSSI4_5GHZ 0x6d 912 #define RT2860_EEPROM_TSSI5_5GHZ 0x6e 913 #define RT2860_EEPROM_RPWR 0x6f 914 #define RT2860_EEPROM_BBP_BASE 0x78 915 #define RT3071_EEPROM_RF_BASE 0x82 916 917 /* EEPROM registers for RT3593. */ 918 #define RT3593_EEPROM_FREQ_LEDS 0x21 919 #define RT3593_EEPROM_FREQ 0x22 920 #define RT3593_EEPROM_LED1 0x22 921 #define RT3593_EEPROM_LED2 0x23 922 #define RT3593_EEPROM_LED3 0x24 923 #define RT3593_EEPROM_LNA 0x26 924 #define RT3593_EEPROM_LNA_5GHZ 0x27 925 #define RT3593_EEPROM_RSSI1_2GHZ 0x28 926 #define RT3593_EEPROM_RSSI2_2GHZ 0x29 927 #define RT3593_EEPROM_RSSI1_5GHZ 0x2a 928 #define RT3593_EEPROM_RSSI2_5GHZ 0x2b 929 #define RT3593_EEPROM_PWR2GHZ_BASE1 0x30 930 #define RT3593_EEPROM_PWR2GHZ_BASE2 0x37 931 #define RT3593_EEPROM_PWR2GHZ_BASE3 0x3e 932 #define RT3593_EEPROM_PWR5GHZ_BASE1 0x4b 933 #define RT3593_EEPROM_PWR5GHZ_BASE2 0x65 934 #define RT3593_EEPROM_PWR5GHZ_BASE3 0x7f 935 936 /* 937 * EEPROM IQ calibration. 938 */ 939 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ 0x130 940 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ 0x131 941 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ 0x133 942 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ 0x134 943 #define RT5390_EEPROM_RF_IQ_COMPENSATION_CTL 0x13c 944 #define RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL 0x13d 945 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ 0x144 946 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ 0x145 947 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ 0x146 948 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ 0x147 949 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ 0x148 950 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ 0x149 951 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ 0x14a 952 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ 0x14b 953 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ 0x14c 954 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ 0x14d 955 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ 0x14e 956 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ 0x14f 957 958 #define RT2860_RIDX_CCK1 0 959 #define RT2860_RIDX_CCK11 3 960 #define RT2860_RIDX_OFDM6 4 961 #define RT2860_RIDX_MAX 12 962 963 /* 964 * EEPROM access macro. 965 */ 966 #define RT2860_EEPROM_CTL(sc, val) do { \ 967 RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \ 968 RAL_BARRIER_READ_WRITE((sc)); \ 969 DELAY(RT2860_EEPROM_DELAY); \ 970 } while (/* CONSTCOND */0) 971 972 /* 973 * Default values for MAC registers; values taken from the reference driver. 974 */ 975 #define RT2870_DEF_MAC \ 976 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 977 { RT2860_BCN_OFFSET1, 0x6f77d0c8 }, \ 978 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 979 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 980 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 981 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 982 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 983 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 984 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 985 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 986 { RT2860_MAX_LEN_CFG, 0x00001f00 }, \ 987 { RT2860_LED_CFG, 0x7f031e46 }, \ 988 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 989 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 990 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 991 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 992 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 993 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 994 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 995 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 996 { RT2860_PBF_CFG, 0x00f40006 }, \ 997 { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \ 998 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 999 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 1000 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 1001 { RT2860_MM40_PROT_CFG, 0x03f44084 }, \ 1002 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 1003 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 1004 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 1005 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 1006 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 1007 { RT2860_PWR_PIN_CFG, 0x00000003 } 1008 1009 /* 1010 * Default values for BBP registers; values taken from the reference driver. 1011 */ 1012 #define RT2860_DEF_BBP \ 1013 { 65, 0x2c }, \ 1014 { 66, 0x38 }, \ 1015 { 68, 0x0b }, \ 1016 { 69, 0x12 }, \ 1017 { 70, 0x0a }, \ 1018 { 73, 0x10 }, \ 1019 { 81, 0x37 }, \ 1020 { 82, 0x62 }, \ 1021 { 83, 0x6a }, \ 1022 { 84, 0x99 }, \ 1023 { 86, 0x00 }, \ 1024 { 91, 0x04 }, \ 1025 { 92, 0x00 }, \ 1026 { 103, 0x00 }, \ 1027 { 105, 0x05 }, \ 1028 { 106, 0x35 } 1029 1030 #define RT5390_DEF_BBP \ 1031 { 31, 0x08 }, \ 1032 { 65, 0x2c }, \ 1033 { 66, 0x38 }, \ 1034 { 68, 0x0b }, \ 1035 { 69, 0x0d }, \ 1036 { 70, 0x06 }, \ 1037 { 73, 0x13 }, \ 1038 { 75, 0x46 }, \ 1039 { 76, 0x28 }, \ 1040 { 77, 0x59 }, \ 1041 { 81, 0x37 }, \ 1042 { 82, 0x62 }, \ 1043 { 83, 0x7a }, \ 1044 { 84, 0x9a }, \ 1045 { 86, 0x38 }, \ 1046 { 91, 0x04 }, \ 1047 { 92, 0x02 }, \ 1048 { 103, 0xc0 }, \ 1049 { 104, 0x92 }, \ 1050 { 105, 0x3c }, \ 1051 { 106, 0x03 }, \ 1052 { 128, 0x12 } 1053 1054 #define RT5592_DEF_BBP \ 1055 { 20, 0x06 }, \ 1056 { 31, 0x08 }, \ 1057 { 65, 0x2c }, \ 1058 { 66, 0x38 }, \ 1059 { 68, 0xdd }, \ 1060 { 69, 0x1a }, \ 1061 { 70, 0x05 }, \ 1062 { 73, 0x13 }, \ 1063 { 74, 0x0f }, \ 1064 { 75, 0x4f }, \ 1065 { 76, 0x28 }, \ 1066 { 77, 0x59 }, \ 1067 { 81, 0x37 }, \ 1068 { 82, 0x62 }, \ 1069 { 83, 0x6a }, \ 1070 { 84, 0x9a }, \ 1071 { 86, 0x38 }, \ 1072 { 88, 0x90 }, \ 1073 { 91, 0x04 }, \ 1074 { 92, 0x02 }, \ 1075 { 95, 0x9a }, \ 1076 { 98, 0x12 }, \ 1077 { 103, 0xc0 }, \ 1078 { 104, 0x92 }, \ 1079 { 105, 0x3c }, \ 1080 { 106, 0x35 }, \ 1081 { 128, 0x12 }, \ 1082 { 134, 0xd0 }, \ 1083 { 135, 0xf6 }, \ 1084 { 137, 0x0f } 1085 1086 /* 1087 * Default settings for RF registers; values derived from the reference driver. 1088 */ 1089 #define RT2860_RF2850 \ 1090 { 1, 0x98402ecc, 0x984c0786, 0x9816b455, 0x9800510b }, \ 1091 { 2, 0x98402ecc, 0x984c0786, 0x98168a55, 0x9800519f }, \ 1092 { 3, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800518b }, \ 1093 { 4, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800519f }, \ 1094 { 5, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800518b }, \ 1095 { 6, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800519f }, \ 1096 { 7, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800518b }, \ 1097 { 8, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800519f }, \ 1098 { 9, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800518b }, \ 1099 { 10, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800519f }, \ 1100 { 11, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800518b }, \ 1101 { 12, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800519f }, \ 1102 { 13, 0x98402ecc, 0x984c079e, 0x98168a55, 0x9800518b }, \ 1103 { 14, 0x98402ecc, 0x984c07a2, 0x98168a55, 0x98005193 }, \ 1104 { 36, 0x98402ecc, 0x984c099a, 0x98158a55, 0x980ed1a3 }, \ 1105 { 38, 0x98402ecc, 0x984c099e, 0x98158a55, 0x980ed193 }, \ 1106 { 40, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed183 }, \ 1107 { 44, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed1a3 }, \ 1108 { 46, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed18b }, \ 1109 { 48, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed19b }, \ 1110 { 52, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed193 }, \ 1111 { 54, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed1a3 }, \ 1112 { 56, 0x98402ec8, 0x984c068e, 0x98158a55, 0x980ed18b }, \ 1113 { 60, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed183 }, \ 1114 { 62, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed193 }, \ 1115 { 64, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed1a3 }, \ 1116 { 100, 0x98402ec8, 0x984c06b2, 0x98178a55, 0x980ed783 }, \ 1117 { 102, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed793 }, \ 1118 { 104, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed1a3 }, \ 1119 { 108, 0x98402ecc, 0x985c0a32, 0x98578a55, 0x980ed193 }, \ 1120 { 110, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed183 }, \ 1121 { 112, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed19b }, \ 1122 { 116, 0x98402ecc, 0x984c0a3a, 0x98178a55, 0x980ed1a3 }, \ 1123 { 118, 0x98402ecc, 0x984c0a3e, 0x98178a55, 0x980ed193 }, \ 1124 { 120, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed183 }, \ 1125 { 124, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed193 }, \ 1126 { 126, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed15b }, \ 1127 { 128, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed1a3 }, \ 1128 { 132, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed18b }, \ 1129 { 134, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed193 }, \ 1130 { 136, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed19b }, \ 1131 { 140, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed183 }, \ 1132 { 149, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed1a7 }, \ 1133 { 151, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed187 }, \ 1134 { 153, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed18f }, \ 1135 { 157, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed19f }, \ 1136 { 159, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed1a7 }, \ 1137 { 161, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed187 }, \ 1138 { 165, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed197 }, \ 1139 { 167, 0x98402ec4, 0x984c03d2, 0x98179855, 0x9815531f }, \ 1140 { 169, 0x98402ec4, 0x984c03d2, 0x98179855, 0x98155327 }, \ 1141 { 171, 0x98402ec4, 0x984c03d6, 0x98179855, 0x98155307 }, \ 1142 { 173, 0x98402ec4, 0x984c03d6, 0x98179855, 0x9815530f }, \ 1143 { 184, 0x95002ccc, 0x9500491e, 0x9509be55, 0x950c0a0b }, \ 1144 { 188, 0x95002ccc, 0x95004922, 0x9509be55, 0x950c0a13 }, \ 1145 { 192, 0x95002ccc, 0x95004926, 0x9509be55, 0x950c0a1b }, \ 1146 { 196, 0x95002ccc, 0x9500492a, 0x9509be55, 0x950c0a23 }, \ 1147 { 208, 0x95002ccc, 0x9500493a, 0x9509be55, 0x950c0a13 }, \ 1148 { 212, 0x95002ccc, 0x9500493e, 0x9509be55, 0x950c0a1b }, \ 1149 { 216, 0x95002ccc, 0x95004982, 0x9509be55, 0x950c0a23 } 1150 1151 #define RT3070_RF3052 \ 1152 { 0xf1, 2, 2 }, \ 1153 { 0xf1, 2, 7 }, \ 1154 { 0xf2, 2, 2 }, \ 1155 { 0xf2, 2, 7 }, \ 1156 { 0xf3, 2, 2 }, \ 1157 { 0xf3, 2, 7 }, \ 1158 { 0xf4, 2, 2 }, \ 1159 { 0xf4, 2, 7 }, \ 1160 { 0xf5, 2, 2 }, \ 1161 { 0xf5, 2, 7 }, \ 1162 { 0xf6, 2, 2 }, \ 1163 { 0xf6, 2, 7 }, \ 1164 { 0xf7, 2, 2 }, \ 1165 { 0xf8, 2, 4 }, \ 1166 { 0x56, 0, 4 }, \ 1167 { 0x56, 0, 6 }, \ 1168 { 0x56, 0, 8 }, \ 1169 { 0x57, 0, 0 }, \ 1170 { 0x57, 0, 2 }, \ 1171 { 0x57, 0, 4 }, \ 1172 { 0x57, 0, 8 }, \ 1173 { 0x57, 0, 10 }, \ 1174 { 0x58, 0, 0 }, \ 1175 { 0x58, 0, 4 }, \ 1176 { 0x58, 0, 6 }, \ 1177 { 0x58, 0, 8 }, \ 1178 { 0x5b, 0, 8 }, \ 1179 { 0x5b, 0, 10 }, \ 1180 { 0x5c, 0, 0 }, \ 1181 { 0x5c, 0, 4 }, \ 1182 { 0x5c, 0, 6 }, \ 1183 { 0x5c, 0, 8 }, \ 1184 { 0x5d, 0, 0 }, \ 1185 { 0x5d, 0, 2 }, \ 1186 { 0x5d, 0, 4 }, \ 1187 { 0x5d, 0, 8 }, \ 1188 { 0x5d, 0, 10 }, \ 1189 { 0x5e, 0, 0 }, \ 1190 { 0x5e, 0, 4 }, \ 1191 { 0x5e, 0, 6 }, \ 1192 { 0x5e, 0, 8 }, \ 1193 { 0x5f, 0, 0 }, \ 1194 { 0x5f, 0, 9 }, \ 1195 { 0x5f, 0, 11 }, \ 1196 { 0x60, 0, 1 }, \ 1197 { 0x60, 0, 5 }, \ 1198 { 0x60, 0, 7 }, \ 1199 { 0x60, 0, 9 }, \ 1200 { 0x61, 0, 1 }, \ 1201 { 0x61, 0, 3 }, \ 1202 { 0x61, 0, 5 }, \ 1203 { 0x61, 0, 7 }, \ 1204 { 0x61, 0, 9 } 1205 1206 #define RT5592_RF5592_20MHZ \ 1207 { 0x1e2, 4, 10, 3 }, \ 1208 { 0x1e3, 4, 10, 3 }, \ 1209 { 0x1e4, 4, 10, 3 }, \ 1210 { 0x1e5, 4, 10, 3 }, \ 1211 { 0x1e6, 4, 10, 3 }, \ 1212 { 0x1e7, 4, 10, 3 }, \ 1213 { 0x1e8, 4, 10, 3 }, \ 1214 { 0x1e9, 4, 10, 3 }, \ 1215 { 0x1ea, 4, 10, 3 }, \ 1216 { 0x1eb, 4, 10, 3 }, \ 1217 { 0x1ec, 4, 10, 3 }, \ 1218 { 0x1ed, 4, 10, 3 }, \ 1219 { 0x1ee, 4, 10, 3 }, \ 1220 { 0x1f0, 8, 10, 3 }, \ 1221 { 0xac, 8, 12, 1 }, \ 1222 { 0xad, 0, 12, 1 }, \ 1223 { 0xad, 4, 12, 1 }, \ 1224 { 0xae, 0, 12, 1 }, \ 1225 { 0xae, 4, 12, 1 }, \ 1226 { 0xae, 8, 12, 1 }, \ 1227 { 0xaf, 4, 12, 1 }, \ 1228 { 0xaf, 8, 12, 1 }, \ 1229 { 0xb0, 0, 12, 1 }, \ 1230 { 0xb0, 8, 12, 1 }, \ 1231 { 0xb1, 0, 12, 1 }, \ 1232 { 0xb1, 4, 12, 1 }, \ 1233 { 0xb7, 4, 12, 1 }, \ 1234 { 0xb7, 8, 12, 1 }, \ 1235 { 0xb8, 0, 12, 1 }, \ 1236 { 0xb8, 8, 12, 1 }, \ 1237 { 0xb9, 0, 12, 1 }, \ 1238 { 0xb9, 4, 12, 1 }, \ 1239 { 0xba, 0, 12, 1 }, \ 1240 { 0xba, 4, 12, 1 }, \ 1241 { 0xba, 8, 12, 1 }, \ 1242 { 0xbb, 4, 12, 1 }, \ 1243 { 0xbb, 8, 12, 1 }, \ 1244 { 0xbc, 0, 12, 1 }, \ 1245 { 0xbc, 8, 12, 1 }, \ 1246 { 0xbd, 0, 12, 1 }, \ 1247 { 0xbd, 4, 12, 1 }, \ 1248 { 0xbe, 0, 12, 1 }, \ 1249 { 0xbf, 6, 12, 1 }, \ 1250 { 0xbf, 10, 12, 1 }, \ 1251 { 0xc0, 2, 12, 1 }, \ 1252 { 0xc0, 10, 12, 1 }, \ 1253 { 0xc1, 2, 12, 1 }, \ 1254 { 0xc1, 6, 12, 1 }, \ 1255 { 0xc2, 2, 12, 1 }, \ 1256 { 0xa4, 0, 12, 1 }, \ 1257 { 0xa4, 4, 12, 1 }, \ 1258 { 0xa5, 8, 12, 1 }, \ 1259 { 0xa6, 0, 12, 1 } 1260 1261 #define RT5592_RF5592_40MHZ \ 1262 { 0xf1, 2, 10, 3 }, \ 1263 { 0xf1, 7, 10, 3 }, \ 1264 { 0xf2, 2, 10, 3 }, \ 1265 { 0xf2, 7, 10, 3 }, \ 1266 { 0xf3, 2, 10, 3 }, \ 1267 { 0xf3, 7, 10, 3 }, \ 1268 { 0xf4, 2, 10, 3 }, \ 1269 { 0xf4, 7, 10, 3 }, \ 1270 { 0xf5, 2, 10, 3 }, \ 1271 { 0xf5, 7, 10, 3 }, \ 1272 { 0xf6, 2, 10, 3 }, \ 1273 { 0xf6, 7, 10, 3 }, \ 1274 { 0xf7, 2, 10, 3 }, \ 1275 { 0xf8, 4, 10, 3 }, \ 1276 { 0x56, 4, 12, 1 }, \ 1277 { 0x56, 6, 12, 1 }, \ 1278 { 0x56, 8, 12, 1 }, \ 1279 { 0x57, 0, 12, 1 }, \ 1280 { 0x57, 2, 12, 1 }, \ 1281 { 0x57, 4, 12, 1 }, \ 1282 { 0x57, 8, 12, 1 }, \ 1283 { 0x57, 10, 12, 1 }, \ 1284 { 0x58, 0, 12, 1 }, \ 1285 { 0x58, 4, 12, 1 }, \ 1286 { 0x58, 6, 12, 1 }, \ 1287 { 0x58, 8, 12, 1 }, \ 1288 { 0x5b, 8, 12, 1 }, \ 1289 { 0x5b, 10, 12, 1 }, \ 1290 { 0x5c, 0, 12, 1 }, \ 1291 { 0x5c, 4, 12, 1 }, \ 1292 { 0x5c, 6, 12, 1 }, \ 1293 { 0x5c, 8, 12, 1 }, \ 1294 { 0x5d, 0, 12, 1 }, \ 1295 { 0x5d, 2, 12, 1 }, \ 1296 { 0x5d, 4, 12, 1 }, \ 1297 { 0x5d, 8, 12, 1 }, \ 1298 { 0x5d, 10, 12, 1 }, \ 1299 { 0x5e, 0, 12, 1 }, \ 1300 { 0x5e, 4, 12, 1 }, \ 1301 { 0x5e, 6, 12, 1 }, \ 1302 { 0x5e, 8, 12, 1 }, \ 1303 { 0x5f, 0, 12, 1 }, \ 1304 { 0x5f, 9, 12, 1 }, \ 1305 { 0x5f, 11, 12, 1 }, \ 1306 { 0x60, 1, 12, 1 }, \ 1307 { 0x60, 5, 12, 1 }, \ 1308 { 0x60, 7, 12, 1 }, \ 1309 { 0x60, 9, 12, 1 }, \ 1310 { 0x61, 1, 12, 1 }, \ 1311 { 0x52, 0, 12, 1 }, \ 1312 { 0x52, 4, 12, 1 }, \ 1313 { 0x52, 8, 12, 1 }, \ 1314 { 0x53, 0, 12, 1 } 1315 1316 #define RT3070_DEF_RF \ 1317 { 4, 0x40 }, \ 1318 { 5, 0x03 }, \ 1319 { 6, 0x02 }, \ 1320 { 7, 0x60 }, \ 1321 { 9, 0x0f }, \ 1322 { 10, 0x41 }, \ 1323 { 11, 0x21 }, \ 1324 { 12, 0x7b }, \ 1325 { 14, 0x90 }, \ 1326 { 15, 0x58 }, \ 1327 { 16, 0xb3 }, \ 1328 { 17, 0x92 }, \ 1329 { 18, 0x2c }, \ 1330 { 19, 0x02 }, \ 1331 { 20, 0xba }, \ 1332 { 21, 0xdb }, \ 1333 { 24, 0x16 }, \ 1334 { 25, 0x03 }, \ 1335 { 29, 0x1f } 1336 1337 #define RT3572_DEF_RF \ 1338 { 0, 0x70 }, \ 1339 { 1, 0x81 }, \ 1340 { 2, 0xf1 }, \ 1341 { 3, 0x02 }, \ 1342 { 4, 0x4c }, \ 1343 { 5, 0x05 }, \ 1344 { 6, 0x4a }, \ 1345 { 7, 0xd8 }, \ 1346 { 9, 0xc3 }, \ 1347 { 10, 0xf1 }, \ 1348 { 11, 0xb9 }, \ 1349 { 12, 0x70 }, \ 1350 { 13, 0x65 }, \ 1351 { 14, 0xa0 }, \ 1352 { 15, 0x53 }, \ 1353 { 16, 0x4c }, \ 1354 { 17, 0x23 }, \ 1355 { 18, 0xac }, \ 1356 { 19, 0x93 }, \ 1357 { 20, 0xb3 }, \ 1358 { 21, 0xd0 }, \ 1359 { 22, 0x00 }, \ 1360 { 23, 0x3c }, \ 1361 { 24, 0x16 }, \ 1362 { 25, 0x15 }, \ 1363 { 26, 0x85 }, \ 1364 { 27, 0x00 }, \ 1365 { 28, 0x00 }, \ 1366 { 29, 0x9b }, \ 1367 { 30, 0x09 }, \ 1368 { 31, 0x10 } 1369 1370 #define RT3593_DEF_RF \ 1371 { 1, 0x03 }, \ 1372 { 3, 0x80 }, \ 1373 { 5, 0x00 }, \ 1374 { 6, 0x40 }, \ 1375 { 8, 0xf1 }, \ 1376 { 9, 0x02 }, \ 1377 { 10, 0xd3 }, \ 1378 { 11, 0x40 }, \ 1379 { 12, 0x4e }, \ 1380 { 13, 0x12 }, \ 1381 { 18, 0x40 }, \ 1382 { 22, 0x20 }, \ 1383 { 30, 0x10 }, \ 1384 { 31, 0x80 }, \ 1385 { 32, 0x78 }, \ 1386 { 33, 0x3b }, \ 1387 { 34, 0x3c }, \ 1388 { 35, 0xe0 }, \ 1389 { 38, 0x86 }, \ 1390 { 39, 0x23 }, \ 1391 { 44, 0xd3 }, \ 1392 { 45, 0xbb }, \ 1393 { 46, 0x60 }, \ 1394 { 49, 0x81 }, \ 1395 { 50, 0x86 }, \ 1396 { 51, 0x75 }, \ 1397 { 52, 0x45 }, \ 1398 { 53, 0x18 }, \ 1399 { 54, 0x18 }, \ 1400 { 55, 0x18 }, \ 1401 { 56, 0xdb }, \ 1402 { 57, 0x6e } 1403 1404 #define RT5390_DEF_RF \ 1405 { 1, 0x0f }, \ 1406 { 2, 0x80 }, \ 1407 { 3, 0x88 }, \ 1408 { 5, 0x10 }, \ 1409 { 6, 0xa0 }, \ 1410 { 7, 0x00 }, \ 1411 { 10, 0x53 }, \ 1412 { 11, 0x4a }, \ 1413 { 12, 0x46 }, \ 1414 { 13, 0x9f }, \ 1415 { 14, 0x00 }, \ 1416 { 15, 0x00 }, \ 1417 { 16, 0x00 }, \ 1418 { 18, 0x03 }, \ 1419 { 19, 0x00 }, \ 1420 { 20, 0x00 }, \ 1421 { 21, 0x00 }, \ 1422 { 22, 0x20 }, \ 1423 { 23, 0x00 }, \ 1424 { 24, 0x00 }, \ 1425 { 25, 0xc0 }, \ 1426 { 26, 0x00 }, \ 1427 { 27, 0x09 }, \ 1428 { 28, 0x00 }, \ 1429 { 29, 0x10 }, \ 1430 { 30, 0x10 }, \ 1431 { 31, 0x80 }, \ 1432 { 32, 0x80 }, \ 1433 { 33, 0x00 }, \ 1434 { 34, 0x07 }, \ 1435 { 35, 0x12 }, \ 1436 { 36, 0x00 }, \ 1437 { 37, 0x08 }, \ 1438 { 38, 0x85 }, \ 1439 { 39, 0x1b }, \ 1440 { 40, 0x0b }, \ 1441 { 41, 0xbb }, \ 1442 { 42, 0xd2 }, \ 1443 { 43, 0x9a }, \ 1444 { 44, 0x0e }, \ 1445 { 45, 0xa2 }, \ 1446 { 46, 0x7b }, \ 1447 { 47, 0x00 }, \ 1448 { 48, 0x10 }, \ 1449 { 49, 0x94 }, \ 1450 { 52, 0x38 }, \ 1451 { 53, 0x84 }, \ 1452 { 54, 0x78 }, \ 1453 { 55, 0x44 }, \ 1454 { 56, 0x22 }, \ 1455 { 57, 0x80 }, \ 1456 { 58, 0x7f }, \ 1457 { 59, 0x8f }, \ 1458 { 60, 0x45 }, \ 1459 { 61, 0xdd }, \ 1460 { 62, 0x00 }, \ 1461 { 63, 0x00 } 1462 1463 #define RT5392_DEF_RF \ 1464 { 1, 0x17 }, \ 1465 { 3, 0x88 }, \ 1466 { 5, 0x10 }, \ 1467 { 6, 0xe0 }, \ 1468 { 7, 0x00 }, \ 1469 { 10, 0x53 }, \ 1470 { 11, 0x4a }, \ 1471 { 12, 0x46 }, \ 1472 { 13, 0x9f }, \ 1473 { 14, 0x00 }, \ 1474 { 15, 0x00 }, \ 1475 { 16, 0x00 }, \ 1476 { 18, 0x03 }, \ 1477 { 19, 0x4d }, \ 1478 { 20, 0x00 }, \ 1479 { 21, 0x8d }, \ 1480 { 22, 0x20 }, \ 1481 { 23, 0x0b }, \ 1482 { 24, 0x44 }, \ 1483 { 25, 0x80 }, \ 1484 { 26, 0x82 }, \ 1485 { 27, 0x09 }, \ 1486 { 28, 0x00 }, \ 1487 { 29, 0x10 }, \ 1488 { 30, 0x10 }, \ 1489 { 31, 0x80 }, \ 1490 { 32, 0x20 }, \ 1491 { 33, 0xc0 }, \ 1492 { 34, 0x07 }, \ 1493 { 35, 0x12 }, \ 1494 { 36, 0x00 }, \ 1495 { 37, 0x08 }, \ 1496 { 38, 0x89 }, \ 1497 { 39, 0x1b }, \ 1498 { 40, 0x0f }, \ 1499 { 41, 0xbb }, \ 1500 { 42, 0xd5 }, \ 1501 { 43, 0x9b }, \ 1502 { 44, 0x0e }, \ 1503 { 45, 0xa2 }, \ 1504 { 46, 0x73 }, \ 1505 { 47, 0x0c }, \ 1506 { 48, 0x10 }, \ 1507 { 49, 0x94 }, \ 1508 { 50, 0x94 }, \ 1509 { 51, 0x3a }, \ 1510 { 52, 0x48 }, \ 1511 { 53, 0x44 }, \ 1512 { 54, 0x38 }, \ 1513 { 55, 0x43 }, \ 1514 { 56, 0xa1 }, \ 1515 { 57, 0x00 }, \ 1516 { 58, 0x39 }, \ 1517 { 59, 0x07 }, \ 1518 { 60, 0x45 }, \ 1519 { 61, 0x91 }, \ 1520 { 62, 0x39 }, \ 1521 { 63, 0x07 } 1522 1523 #define RT5592_DEF_RF \ 1524 { 1, 0x3f }, \ 1525 { 3, 0x08 }, \ 1526 { 5, 0x10 }, \ 1527 { 6, 0xe4 }, \ 1528 { 7, 0x00 }, \ 1529 { 14, 0x00 }, \ 1530 { 15, 0x00 }, \ 1531 { 16, 0x00 }, \ 1532 { 18, 0x03 }, \ 1533 { 19, 0x4d }, \ 1534 { 20, 0x10 }, \ 1535 { 21, 0x8d }, \ 1536 { 26, 0x82 }, \ 1537 { 28, 0x00 }, \ 1538 { 29, 0x10 }, \ 1539 { 33, 0xc0 }, \ 1540 { 34, 0x07 }, \ 1541 { 35, 0x12 }, \ 1542 { 47, 0x0c }, \ 1543 { 53, 0x22 }, \ 1544 { 63, 0x07 } 1545 1546 #define RT5592_2GHZ_DEF_RF \ 1547 { 10, 0x90 }, \ 1548 { 11, 0x4a }, \ 1549 { 12, 0x52 }, \ 1550 { 13, 0x42 }, \ 1551 { 22, 0x40 }, \ 1552 { 24, 0x4a }, \ 1553 { 25, 0x80 }, \ 1554 { 27, 0x42 }, \ 1555 { 36, 0x80 }, \ 1556 { 37, 0x08 }, \ 1557 { 38, 0x89 }, \ 1558 { 39, 0x1b }, \ 1559 { 40, 0x0d }, \ 1560 { 41, 0x9b }, \ 1561 { 42, 0xd5 }, \ 1562 { 43, 0x72 }, \ 1563 { 44, 0x0e }, \ 1564 { 45, 0xa2 }, \ 1565 { 46, 0x6b }, \ 1566 { 48, 0x10 }, \ 1567 { 51, 0x3e }, \ 1568 { 52, 0x48 }, \ 1569 { 54, 0x38 }, \ 1570 { 56, 0xa1 }, \ 1571 { 57, 0x00 }, \ 1572 { 58, 0x39 }, \ 1573 { 60, 0x45 }, \ 1574 { 61, 0x91 }, \ 1575 { 62, 0x39 } 1576 1577 #define RT5592_5GHZ_DEF_RF \ 1578 { 10, 0x97 }, \ 1579 { 11, 0x40 }, \ 1580 { 25, 0xbf }, \ 1581 { 27, 0x42 }, \ 1582 { 36, 0x00 }, \ 1583 { 37, 0x04 }, \ 1584 { 38, 0x85 }, \ 1585 { 40, 0x42 }, \ 1586 { 41, 0xbb }, \ 1587 { 42, 0xd7 }, \ 1588 { 45, 0x41 }, \ 1589 { 48, 0x00 }, \ 1590 { 57, 0x77 }, \ 1591 { 60, 0x05 }, \ 1592 { 61, 0x01 } 1593 1594 #define RT5592_CHAN_5GHZ \ 1595 { 36, 64, 12, 0x2e }, \ 1596 { 100, 165, 12, 0x0e }, \ 1597 { 36, 64, 13, 0x22 }, \ 1598 { 100, 165, 13, 0x42 }, \ 1599 { 36, 64, 22, 0x60 }, \ 1600 { 100, 165, 22, 0x40 }, \ 1601 { 36, 64, 23, 0x7f }, \ 1602 { 100, 153, 23, 0x3c }, \ 1603 { 155, 165, 23, 0x38 }, \ 1604 { 36, 50, 24, 0x09 }, \ 1605 { 52, 64, 24, 0x07 }, \ 1606 { 100, 153, 24, 0x06 }, \ 1607 { 155, 165, 24, 0x05 }, \ 1608 { 36, 64, 39, 0x1c }, \ 1609 { 100, 138, 39, 0x1a }, \ 1610 { 140, 165, 39, 0x18 }, \ 1611 { 36, 64, 43, 0x5b }, \ 1612 { 100, 138, 43, 0x3b }, \ 1613 { 140, 165, 43, 0x1b }, \ 1614 { 36, 64, 44, 0x40 }, \ 1615 { 100, 138, 44, 0x20 }, \ 1616 { 140, 165, 44, 0x10 }, \ 1617 { 36, 64, 46, 0x00 }, \ 1618 { 100, 138, 46, 0x18 }, \ 1619 { 140, 165, 46, 0x08 }, \ 1620 { 36, 64, 51, 0xfe }, \ 1621 { 100, 124, 51, 0xfc }, \ 1622 { 126, 165, 51, 0xec }, \ 1623 { 36, 64, 52, 0x0c }, \ 1624 { 100, 138, 52, 0x06 }, \ 1625 { 140, 165, 52, 0x06 }, \ 1626 { 36, 64, 54, 0xf8 }, \ 1627 { 100, 165, 54, 0xeb }, \ 1628 { 36, 50, 55, 0x06 }, \ 1629 { 52, 64, 55, 0x04 }, \ 1630 { 100, 138, 55, 0x01 }, \ 1631 { 140, 165, 55, 0x00 }, \ 1632 { 36, 50, 56, 0xd3 }, \ 1633 { 52, 128, 56, 0xbb }, \ 1634 { 130, 165, 56, 0xab }, \ 1635 { 36, 64, 58, 0x15 }, \ 1636 { 100, 116, 58, 0x1d }, \ 1637 { 118, 165, 58, 0x15 }, \ 1638 { 36, 64, 59, 0x7f }, \ 1639 { 100, 138, 59, 0x3f }, \ 1640 { 140, 165, 59, 0x7c }, \ 1641 { 36, 64, 62, 0x15 }, \ 1642 { 100, 116, 62, 0x1d }, \ 1643 { 118, 165, 62, 0x15 } 1644 1645 union run_stats { 1646 uint32_t raw; 1647 struct { 1648 uint16_t fail; 1649 uint16_t pad; 1650 } error; 1651 struct { 1652 uint16_t success; 1653 uint16_t retry; 1654 } tx; 1655 } __aligned(4); 1656 1657 #endif /* _IF_RUNREG_H_ */ 1658